Low-Cost, 3.3V Zero Delay Buffer NRND – Not Recommend for New Designs DATASHEET The MPC962309 is a zero delay buffer designed to distribute high-speed clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin version of the MPC962309 which drives five outputs with one reference input. The -1H versions of these devices have higher drive than the -1 devices and can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs which lock to an input clock presented on the REF pin. The PLL feedback is on-chip and is obtained from the CLOCKOUT pad. Features • • • • • • • • • • • • • • • MPC962305 NRND 1:5 LVCMOS zero-delay buffer (MPC962305) 1:9 LVCMOS zero-delay buffer (MPC962309) Zero input-output propagation delay Multiple low-skew outputs 250 ps max output-output skew 700 ps max device-device skew Supports a clock I/O frequency range of 10 MHz to 133 MHz, compatible with CPU and PCI bus frequencies Low jitter, 200 ps max cycle-cycle, and compatible with Pentium® based systems Test Mode to bypass PLL (MPC962309 only. See Table 3) 8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin TSSOP package (MPC962309), all Pb-free Single 3.3 V supply Ambient temperature range: –40C to +85C Compatible with the CY2305, CY23S05, CY2309, CY23S09 Spread spectrum compatible Not Recommend for New Designs Use replacement part IDT2305 MPC962305 MPC962309 EF SUFFIX 8-LEAD SOIC PACKAGE Pb-FREE PACKAGE CASE 751-06 EJ SUFFIX 8-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 948J-01 EF SUFFIX 16-LEAD SOIC PACKAGE Pb-FREE PACKAGE CASE 751B-05 EJ SUFFIX 16-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 948F-01 • The MPC962309 has two banks of four outputs each, which can be controlled by the Select Inputs as shown in Table 3. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 A of current draw for the device. The PLL shuts down in one additional case as shown in Table 3. Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this situation, the difference between the output skews of two devices will be less than 700 ps. All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps. The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page. The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H, are available to provide faster rise and fall times of the base device. Pentium II is a trademark of Intel Corporation. MPC962305 REVISION 8 JANUARY 8, 2013 1 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr Block Diagram Pin Configuration CLKOUT PLL MUX REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 CLKA1 REF CLKA2 CLKA3 CLKA4 CLKB1 S2 CLKB2 Select Input Decoding S1 REF CLK2 CLK1 GND CLKB3 CLKB4 SOIC/TSSOP Top View 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 SOIC/TSSOP Top View 1 8 2 7 3 6 4 5 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1 CLKOUT CLK4 VDD CLK3 Table 1. Pin Description for MPC962309 Pin Signal Description 1 REF(1) 2 CLKA1(2) Buffered clock output, Bank A 3 (2) Buffered clock output, Bank A CLKA2 Input reference frequency, 5 V-tolerant input 4 VDD 3.3 V supply 5 GND Ground 6 CLKB1(2) Buffered clock output, Bank B 7 CLKB2(2) Buffered clock output, Bank B 8 S2(3) Select input, bit 2 9 (3) Select input, bit 1 S1 10 CLKB3(2) Buffered clock output, Bank B 11 CLKB4(2) Buffered clock output, Bank B 12 GND Ground 13 VDD 3.3 V supply 14 CLKA3 (2) Buffered clock output, Bank A 15 CLKA4(2) Buffered clock output, Bank A 16 CLKOUT(2) Buffered output, internal feedback on this pin 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. Table 2. Pin Description for MPC962305 Pin Signal 1 REF(1) Description Input reference frequency, 5 V-tolerant input 2 CLK2 (2) Buffered clock output 3 CLK1(2) Buffered clock output 4 GND 5 CLK3(2) 6 VDD 7 8 CLK4 (2) CLKOUT(2) Ground Buffered clock output 3.3 V supply Buffered clock output Buffered clock output, internal feedback on this pin 1. Weak pull-down. 2. Weak pull-down on all outputs. MPC962305 REVISION 8 JANUARY 8, 2013 2 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr Table 3. Select Input Decoding for MPC962309 S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT(1) Output Source PLL Shutdown 0 0 Three-State Three-State Driven PLL N 0 1 Driven Three-State Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. Table 4. Maximum Ratings Characteristics Value Unit 0.5 to +3.9 V 0.5 to VDD+0.5 V DC Input Voltage REF 0.5 to 5.5 V Storage Temperature 65 to +150 C 150 C >2000 V Supply Voltage to Ground Potential DC Input Voltage (Except Ref) Junction Temperature Static Discharge Voltage (per MIL-STD-883, Method 3015) Table 5. Operating Conditions for MPC962305-X and MPC962309-X Industrial Temperature Devices Parameter Min Max Unit Supply Voltage 3.0 3.6 V TA Operating Temperature (Ambient Temperature) 40 85 C CL Load Capacitance, below 100 MHz 30 pF CL Load Capacitance, from 100 MHz to 133 MHz 10 pF CIN Input Capacitance 7 pF VDD Description Table 6. Electrical Characteristics for MPC962305-X and MPC962309-X Industrial Temperature Devices(1) Parameter Description Test Conditions Min Max Unit 0.8 V VIL Input LOW VIH Input HIGH Voltage(2) IIL Input LOW Current VIN = 0 V 50.0 A IIH Input HIGH Current VIN = VDD 100.0 A 0.4 V VOL Voltage(2) Output LOW Voltage(3) 2.0 IOL = 8 mA (1) V IOH = 12 mA (1H) VOH Output HIGH Voltage(3) IOH = 8 mA (1) 2.4 V IOL = 12 mA (1H) IDD (PD mode) IDD Power Down Supply Current REF = 0 MHz 25.0 A Supply Current Unloaded outputs at 66.67 MHz, SEL inputs at VDD 35.0 mA 1. All parameters are specified with loaded outputs. 2. REF input has a threshold voltage of VPP/2. 3. Parameter is guaranteed by design and characterization. Not 100% tested in production. MPC962305 REVISION 8 JANUARY 8, 2013 3 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices(1) Parameter t1 Name Test Conditions Min Typ 10 10 Max Unit 100 133.33 MHz MHz 60.0 % Output Frequency 30-pF load 10-pF load Duty Cycle(2) = t2 t1 Measured at 1.4 V, FOUT = 66.67 MHz t3 Rise Time(2) Measured between 0.8 V and 2.0 V 2.50 ns t4 Fall Time(2) Measured between 0.8 V and 2.0 V 2.50 ns t5 Output to Output Skew(2) All outputs equally loaded 250 ps t6A Delay, REF Rising Edge to Measured at VDD/2 0 350 ps 5 8.7 ns 0 700 ps 40.0 50.0 CLKOUT Rising Edge(2) t6B Delay, REF Rising Edge to Measured at VDD/2. Measured in PLL Bypass Mode, CLKOUT Rising Edge(2) MPC962309 device only t7 Device to Device Skew(2) Measured at VDD/2 on the CLKOUT pins of devices tJ Cycle to Cycle Jitter(2) Measured at 66.67 MHz, loaded outputs 200 ps PLL Lock Time(2) Stable power supply, valid clock presented on REF pin 1.0 ms tLOCK 1 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices(1) Parameter Max Unit 100 133.33 MHz MHz 50.0 60.0 % 55.0 55.0 % Measured between 0.8 V and 2.0 V 1.50 ns Fall Time(2) Measured between 0.8 V and 2.0 V 1.50 ns t5 Output to Output Skew(2) All outputs equally loaded 250 ps t6A Delay, REF Rising Edge to Measured at VDD/2 0 350 ps 5 8.7 ns 0 700 ps t1 Name Test Conditions Min Output Frequency 30-pF load 10-pF load Duty Cycle(2) = t2 t1 Measured at 1.4 V, FOUT = 66.67 MHz 40.0 Duty Cycle(2) = t2 t1 Measured at 1.4 V, FOUT < 50 MHz 45.0 t3 Rise Time(2) t4 CLKOUT Rising t6B Edge(2) Delay, REF Rising Edge to CLKOUT Rising Typ 10 10 Edge(2) Measured at VDD/2. Measured in PLL Bypass Mode, 1 MPC962309 device only t7 Device to Device Skew(2) Measured at VDD/2 on the CLKOUT pins of devices t8 Output Slew Rate(2) Measured between 0.8 V and 2.0 V using Test Circuit #2 tJ Cycle to Cycle Jitter(2) Measured at 66.67 MHz, loaded outputs 200 ps PLL Lock Time(2) Stable power supply, valid clock presented on REF pin 1.0 ms tLOCK 1 V/ns 1. All parameters are specified with loaded outputs. 2. Parameter is guaranteed by design and characterization. Not 100% tested in production. MPC962305 REVISION 8 JANUARY 8, 2013 4 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr APPLICATIONS INFORMATION VCC 1.4 V VCC VCC 2 CCLK GND GND VCC VCC VCC 2 1.4 V FB_IN GND GND t5 t6 The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 1. Output-to-Output Skew tSK(O) Figure 2. Static Phase Offset Test Reference VCC 1.4 V VCC GND VCC 2 DEVICE 1 t2 GND t1 VCC VCC 2 DEVICE 2 DC = t2/t1 x 100% GND t7 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 3. Output Duty Cycle (DC) Figure 4. Device-to-Device Skew VCC = 3.3 V tN tN+1 2.0 tJ = |tN–tN+1| 0.8 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t4 Figure 5. Cycle-to-Cycle Jitter MPC962305 REVISION 8 JANUARY 8, 2013 t3 Figure 6. Output Transition Time Test Reference 5 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr Test Circuit #1 Test Circuit #2 VDD 0.1 F VDD OUTPUTS 1K 0.1 F CLKOUT OUTPUTS 1K CLOAD VDD 0.1 F GND CLKOUT 10 pF VDD GND 0.1 F Test Circuit for all parameters except t8 GND GND Test Circuit for t8, Output slew rate on –1H, –5 device Table 9. Ordering Information Ordering Code Package Type MPC962305D-1 8-pin 150-mil SOIC MPC962305D-1R2 8-pin 150-mil SOIC - Tape and Reel MPC962305EF-1 8-pin 150-mil SOIC (Pb-free) MPC962305EF-1R2 8-pin 150-mil SOIC (Pb-free) - Tape and Reel MPC962305D-1H 8-pin 150-mil SOIC MPC962305D-1HR2 8-pin 150-mil SOIC - Tape and Reel MPC962305EF-1H 8-pin 150-mil SOIC (Pb-free) MPC962305EF-1HR2 8-pin 150-mil SOIC (Pb-free) - Tape and Reel MPC962305DT-1H 8-pin 150-mil TSSOP MPC962305DT-1HR2 8-pin 150-mil TSSOP - Tape and Reel MPC962305EJ-1H 8-pin 150-mil TSSOP (Pb-free) MPC962305EJ-1HR2 8-pin 150-mil TSSOP (Pb-free) - Tape and Reel MPC962309D-1 16-pin 150-mil SOIC MPC962309D-1R2 16-pin 150-mil SOIC - Tape and Reel MPC962309EF-1 16-pin 150-mil SOIC (Pb-free) MPC962309EF-1R2 16-pin 150-mil SOIC (Pb-free) - Tape and Reel MPC962309D-1H 16-pin 150-mil SOIC MPC962309D-1HR2 16-pin 150-mil SOIC - Tape and Reel MPC962309EF-1H 16-pin 150-mil SOIC (Pb-free) MPC962309EF-1HR2 16-pin 150-mil SOIC (Pb-free) - Tape and Reel MPC962309DT-1H 16-pin 4.4-mm TSSOP MPC962309DT-1HR2 16-pin 4.4-mm TSSOP - Tape and Reel MPC962309EJ-1H 16-pin 4.4-mm TSSOP (Pb-free) MPC962309EJ-1HR2 16-pin 4.4-mm TSSOP (Pb-free) - Tape and Reel MPC962305 REVISION 8 JANUARY 8, 2013 6 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 1 OF 2 CASE 751-07 ISSUE U 8-LEAD SOIC PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 7 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 2 OF 2 PAGE 1 OF 3 CASE 751-07 ISSUE U 8-LEAD SOIC PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 8 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 1 OF 2 CASE 751B-05 ISSUE L 16-LEAD SOIC PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 9 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 2 OF 2 CASE 751B-05 ISSUE L 16-LEAD SOIC PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 10 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 1 OF 3 CASE 948F-01 ISSUE B 16-LEAD TSSOP PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 11 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 2 OF 3 CASE 948F-01 ISSUE B 16-LEAD TSSOP PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 12 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 3 OF 3 CASE 948F-01 ISSUE B 16-LEAD TSSOP PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 13 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 1 OF 3 CASE 948J-01 ISSUE B 8-LEAD TSSOP PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 14 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 2 OF 3 CASE 948J-01 ISSUE B 8-LEAD TSSOP PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 15 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr PACKAGE DIMENSIONS PAGE 3 OF 3 CASE 948J-01 ISSUE B 8-LEAD TSSOP PLASTIC PACKAGE MPC962305 REVISION 8 JANUARY 8, 2013 16 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr Revision History Sheet Rev 8 Table Page 1 Description of Change Date NRND – Not Recommend for New Designs 1/8/13 MPC962305 REVISION 8 JANUARY 8, 2013 17 ©2013 Integrated Device Technology, Inc. MPC962305 Data Sheet LOW-COST, 3.3V ZERO DELAY BUFFEr We’ve Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support [email protected] +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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