TI bq24617RGET Stand-alone synchronous switch-mode li-ion or li-polymer battery charger with system power selector and low iq Datasheet

bq24610
bq24617
www.ti.com
SLUS892 – DECEMBER 2009
Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer Battery Charger with System
Power Selector and Low Iq
Check for Samples: bq24610, bq24617
•
ACN
1
ACP
2
23
CE
4
5
TS
6
22
21
20
19
18 REGN
OAS
(bq24610)
OFB
(bq24617)
ACDRV 3
STAT1
LODRV
24
PH
PACKAGE AND PIN-OUT
17 GND
16 ACSET
15 ISET2
QFN-24
TOP VIEW
14 SRP
13 SRN
7
8
9
10
11
12
VFB
•
•
The bq24610/7 charges the battery in three phases:
preconditioning, constant current, and constant
voltage. Charge is terminated when the current
reaches a minimum user-selectable level. A
programmable charge timer provides a safety
backup. The bq24610/7 automatically restarts the
charge cycle if the battery voltage falls below an
internal threshold, and enters a low-quiescent current
sleep mode when the input voltage falls below the
battery voltage.
ISET1
•
The bq24610/7 is highly integrated Li-ion or
Li-polymer switch-mode battery charge controller. It
offers a constant-frequency synchronous switching
PWM controller with high accuracy charge current
and voltage regulation, charge preconditioning,
termination, adapter current regulation and charge
status monitoring.
BTST
•
DESCRIPTION
HIDRV
•
•
•
•
•
Netbook, Mobile Internet Device and
Ultra-Mobile PC
Personal Digital Assistants
Handheld Terminals
Industrial and Medical Equipment
Portable Equipment
VREF
•
•
•
STAT2
•
APPLICATIONS
BATDRV
•
VCC
•
600 kHz NMOS-NMOS Synchronous Buck
Converter
Stand-alone Charger Support for Li-Ion or
Li-Polymer
5V–28V VCC Input Operating Range and
Support 1-6 Battery Cells (bq24610)
5V–24V VCC Input Operating Range and
Support 1-5 Battery Cells (bq24617)
Up to 10A Charge Current and Adapter Current
High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
Integration
– Automatic System Power Selection from
Adapter or Battery
– Internal Loop Compensation
– Internal Soft Start
– Dynamic Power Management
Safety Protection
– Input Over-Voltage Protection
– Battery Thermistor Sense Hot/Cold Charge
Suspend
– Battery Detection
– Reverse Protection Input FET
– Programmable Safety Timer
– Charge Over-Current Protection
– Battery Short Protection
– Battery Over-Voltage Protection
– Thermal Shutdown
Status Outputs
– Adapter Present
– Charger Operation Status
Charge Enable Pin
6V Gate Drive for Synchronous Buck
Converter
30ns Driver Dead-time and 99.5% Max
Effective Duty Cycle
24-pin, 4×4-mm2 QFN package
Energy Star Low Quiescent Current Iq
– < 15 µA Off-State Battery Discharge current
– < 1.5 mA Off-State Input Quiescent Current
PG
•
•
•
TTC
FEATURES
1
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
bq24610
bq24617
SLUS892 – DECEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The bq24610/7 controls external switches to prevent battery discharge back to the input, connect the adapter to
the system, and to connect the battery to the system using 6-V gate drives for better system efficiency. The
bq24610/7 features Dynamic Power Management (DPM). These features reduce battery charge current when
the input power limit is reached to avoid overloading the AC adapter when supplying the load and the battery
charger simultaneously. A highly-accurate current-sense amplifier enables precise measurement of input current
from the AC adapter to monitor the overall system power.
TYPICAL APPLICATION
Q1 (ACFET)
SI7617DN
R17
10Ω
SYSTEM
P
ADAPTER-
P
R14
100 kW
C16
2.2μF
RAC
0.010 W
Q2 (ACFET)
SI7616DN
C14
0.1 mF
C15
0.1 µF
C3
0.1 µF
C2
0.1 µF
ACN
VCC
BATDRV
ACDRV
R5
100 kW
R18
1 kΩ
R7
100 kW
R6
10 kW
R15
100 kW
ISET1
PH
ISET2
BTST
R8
22.1 kW
VREF
REGN
bq24610
bq24617
Q4
SIS412DN
L1
C6
D1
0.1 µF
BAT54
C5
1 µF
RSR
0.010 W
C10
0.1 µF
GND
D2
R12 10 kW
D3
C12
C13
10 µF* 10 µF*
C11
0.1 µF
R13 10 kW
D4
VREF
Pack
Thermistor
Sense
103AT
R9
9.31 kW
R2
500 kΩ
Cff
22 pF
STAT1
SRP
ADAPTER +
PACK+
PACK-
CE
R11 10 kW
VBAT
6.8 µH*
Q5
SIS412DN
LODRV
C4
1 µF
P
Q3 (BATFET)
SI7617DN
R19
1 kΩ
HIDRV
ACSET
R4
32.4 kW
C7
1µF
ACP
VREF
R3
100 kW
C9
10 μF
C8
10 µF
N
R20
2Ω
N
ADAPTER+
R1
100 kW
SRN
STAT2
PG
VFB
R16
100 W
C1
0.1 μF
R10
430 kW
TS
TTC
PwrPad
CTTC
0.056 μF
VIN=19V, 3-cell, Iadapter_limit=4A, Icharge=3A, Ipre-charge= Iterm=0.3A, 5 hour saftey timer
Figure 1. Typical System Schematic
ORDERING INFORMATION
PART NUMBER
IC MARKING
bq24610
OAS
PACKAGE
24-PIN 4×4 mm2 QFN
bq24617
2
OFB
ODERING NUMBER
(Tape andReel)
QUANTITY
bq24610RGER
3000
bq24610RGET
250
bq24617RGER
3000
bq24617RGET
250
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Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24610 bq24617
bq24610
bq24617
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SLUS892 – DECEMBER 2009
PACKAGE THERMAL DATA
(1)
(2)
PACKAGE
θJP
θJA
TA = 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
QFN – RGE (1) (2)
4°C/W
43°C/W
2.3 W
0.023 W/°C
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2×2 via matrix. θJA has 5% improvement by 3x3 via matrix.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
VALUE
UNIT
–0.3 to 33
V
PH
–2 to 36
V
VFB
–0.3 to 16
V
REGN, LODRV, ACSET, TS, TTC
–0.3 to 7
V
BTST, HIDRV with respect to GND
–0.3 to 39
V
VREF, ISET1, ISET2
–0.3 to 3.6
V
ACP–ACN, SRP–SRN
–0.5 to 0.5
V
VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG
Voltage range
Maximum difference
voltage
TJ
Junction temperature range
–40 to 155
°C
Tstg
Storage temperature range
–55 to 155
°C
(1)
(2)
(3)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
Must have a series resistor between battery pack to VFB if Battery Pack voltage is expected to be greater than 16V. Usually the resistor
divider top resistor will take care of this.
RECOMMENDED OPERATING CONDITIONS
VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG
Voltage range
UNIT
–0.3 to 28
V
PH
–2 to 30
V
VFB
–0.3 to 14
V
REGN, LODRV, ACSET, TS, TTC
–0.3 to 6.5
V
BTST, HIDRV with respect to GND
–0.3 to 34
V
ISET1, ISET2
–0.3 to 3.3
V
VREF
Maximum difference
voltage
VALUE
ACP–ACN, SRP–SRN
3.3
V
–0.2 to 0.2
V
TJ
Junction temperature range
0 to 125
°C
Tstg
Storage temperature range
–55 to 155
°C
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bq24610
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SLUS892 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS
5.0V ≤ V(VCC) ≤ 28V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating range(610)
5.0
28.0
VCC input voltage operating range(617)
5.0
24.0
V
QUIESCENT CURRENTS
Total battery discharge current (sum of
currents into VCC, BTST, PH, ACP,
ACN, SRP, SRN, VFB), VFB ≤2.1 V
IBAT
Battery discharge current (sum of
currents into BTST, PH, SRP, SRN,
VFB), VFB ≤ 2.1 V
Adapter supply current (current into
VCC,ACP,ACN pin)
IAC
15
μA
VVCC > VSRN, VVCC > VUVLO CE = LOW
5
µA
VVCC > VSRN, VVCC > VVCCLOW CE = HIGH, Charge
done
5
µA
VVCC < VSRN, VVCC > VUVLO (SLEEP)
VVCC > VSRN, VVCC > VUVLO CE = LOW (IC quiescent
current)
1
1.5
VVCC > VSRN, VVCC >VVCCLOW, CE = HIGH, charge
done
2
5
VVCC > VSRN, VVCC >VVCCLOW, CE = HIGH, Charging,
Qg_total = 20 nC
mA
25
CHARGE VOLTAGE REGULATION
VFB
Feedback regulation voltage
2.1
Charge voltage regulation accuracy
IVFB
Leakage current into VFB pin
V
TJ = 0°C to 85°C
–0.5%
0.5%
TJ = -40°C to 125°C
–0.7%
0.7%
VFB = 2.1 V
100
100
nA
CURRENT REGULATION – FAST CHARGE
VISET1
ISET1 voltage range
VIREG_CHG
SRP-SRN current sense voltage range
VIREG_CHG = VSRP – VSRN
2
KISET1
Charge current set factor (amps of
charge current per volt on ISET1 pin)
RSENSE = 10 mΩ
Charge current regulation accuracy
IISET1
Leakage current into ISET1 pin
5
V
mV
A/V
VIREG_CHG = 40 mV
–3%
VIREG_CHG = 20 mV
–4%
3%
4%
VIREG_CHG = 5 mV
–25%
25%
VIREG_CHG = 1.5 mV (VSRN > 3.1V)
–40%
40%
VISET1 = 2 V
100
nA
2
V
CURRENT REGULATION – PRECHARGE
VISET2
ISET2 voltage range
KISET2
Precharge current set factor (amps of
RSENSE = 10 mΩ
precharge current per volt on ISET2 pin)
Precharge current regulation accuracy
IISET2
4
Leakage current into ISET2 pin
1
A/V
VIREG_PRECH = 20 mV
–4%
4%
VIREG_PRECH = 5 mV
–25%
25%
VIREG_PRECH = 1.5 mV (VSRN < 3.1V)
–55%
55%
VISET2 = 2V
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100
nA
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24610 bq24617
bq24610
bq24617
www.ti.com
SLUS892 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
5.0V ≤ V(VCC) ≤ 28V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE TERMINATION
Termination current set factor (Amps of
termination current per volt on ISET2
pin)
KTERM
Termination current accuracy
RSENSE = 10 mΩ
1
A/V
VITERM = 20 mV
–4%
4%
VITERM = 5 mV
–25%
25%
VITERM = 1.5 mV
–45%
Deglitch time for termination (both edge)
45%
100
tQUAL
Termination qualification time
VBAT>VRECH and ICHG<ITERM
IQUAL
Termination qualification current
Discharge current once termination is detected
ms
250
ms
2
mA
INPUT CURRENT REGULATION
VACSET
ACSET Voltage Range
VIREG_DPM
ACP-ACN Current Sense Voltage
Range
VIREG_DPM = VACP – VACN
KACSET
Input current set factor (amps of input
current per volt on ACSET pin)
RSENSE = 10 mΩ
IACSET
Input current regulation accuracy
leakage current in to ACSET pin
IISET1
2
Leakage current in to ACSET pin
100
5
V
mV
A/V
VIREG_DPM = 40 mV
–3%
VIREG_DPM = 20 mV
–4%
3%
4%
VIREG_DPM = 5 mV
–25%
25%
VACSET = 2 V
100
nA
INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)
VUVLO
AC Under-voltage rising threshold
VUVLO_HYS
AC Under-voltage hysteresis, falling
Measure on VCC
3.65
3.85
4
350
V
mV
VCC LOWV COMPARATOR
Falling threshold, disable charge
Measure on VCC
4.1
Rising threshold, resume charge
V
4.35
4.5
V
100
150
mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
_FALL
VSLEEP_HYS
SLEEP falling threshold
VVCC – VSRN to enter SLEEP
40
SLEEP hysteresis
500
mV
μs
SLEEP rising delay
VCC falling below SRN, Delay to turn off ACFET
1
SLEEP falling delay
VCC rising above SRN, Delay to turn on ACFET
30
μs
SLEEP rising shutdown deglitch
VCC falling below SRN, Delay to enter SLEEP mode
100
ms
SLEEP falling powerup deglitch
VCC rising above SRN, Delay to exit SLEEP mode
30
ms
ACN / SRN COMPARATOR
VACN-SRN_FALL
ACN to SRN falling threshold
VACN-SRN_HYS
ACN to SRN rising hysteresis
VACN – VSRN to turn on BATFET
100
200
310
mV
100
mV
ACN to SRN rising deglitch
VACN – VSRN > VACN-SRN_RISE
2
ms
ACN to SRN falling deglitch
VACN – VSRN < VACN-SRN_FALL
50
μs
BAT LOWV COMPARATOR
VLOWV
Precharge to fastcharge transition
(LOWV threshold)
VLOWV_HYS
LOWV hysteresis
Measured on VFB pin, Rising
1.534
1.55
1.566
V
100
mV
LOWV rising deglitch
VFB falling below VLOWV
25
ms
LOWV falling deglitch
VFB rising above VLOWV + VLOWV_HYS
25
ms
RECHARGE COMPARATOR
VRECHG
Recharge threshold (with-respect-to
VREG)
Measured on VFB pin, Falling
Recharge rising deglitch
VFB decreasing below VRECHG
10
ms
Recharge falling deglitch
VFB decreasing above VRECHG
10
ms
35
50
65
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mV
5
bq24610
bq24617
SLUS892 – DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
5.0V ≤ V(VCC) ≤ 28V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32.96
V
BAT OVER-VOLTAGE COMPARATOR
VOV_RISE
Over-voltage rising threshold
As percentage of VFB
104%
VOV_FALL
Over-voltage falling threshold
As percentage of VFB
102%
INPUT OVER-VOLTAGE COMPARATOR (ACOV)
VACOV
AC over-voltage rising threshold on
VCC (bq24610)
VACOV_HYS
AC over-voltage falling hysteresis
(bq24610)
VACOV
AC over-voltage rising threshold on
VCC (bq24617)
VACOV_HYS
AC over-voltage falling
hysteresis(bq24617)
31.04
32
1
25.22
26
V
26.78
V
820
mV
AC over-voltage deglitch (both edge)
Delay to changing the STAT pins
1
ms
AC over-voltage rising deglitch
Delay to disable charge
1
ms
AC over-voltage falling deglitch
Delay to resume charge
20
ms
Temperature increasing
145
°C
15
°C
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
TSHUT_HYS
Thermal shutdown hysteresis
Thermal shutdown rising deglitch
Temperature increasing
100
μs
Thermal shutdown falling deglitch
Temperature decreasing
10
ms
THERMISTOR COMPARATOR
VLTF
Cold temperature rising threshold
As Percentage to VVREF
72.5%
73.5%
VLTF_HYS
Rising hysteresis
As Percentage to VVREF
0.2%
0.4%
74.5%
0.6%
VHTF
Hot temperature rising threshold
As Percentage to VVREF
36.2%
37%
37.8%
VTCO
Cut-off temperature rising threshold
As Percentage to VVREF
33.7%
34.4%
35.1%
Deglitch time for temperature out of
range detection
VTS > VLTF, or VTS < VTCO, or VTS < VHTF
Deglitch time for temperature in valid
range detection
VTS < VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF
400
ms
20
ms
45.5
mV
CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
Charge over-current falling threshold
VOC
Current rising, in non-synchronous mode, mesure on
V(SRP-SRN), VSRP < 2 V
Current rising, as percentage of V(IREG_CHG), in
synchronous mode, VSRP > 2.2V
160%
Charge over-current threshold floor
Minimum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2V
50
mV
Charge over-current threshold ceiling
Maximum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2V
180
mV
CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET
Charge under-current falling threshold
Switch from SYNCH to NON-SYNCH, VSRP > 2.2V
1
5
9
mV
BATTERY SHORTED COMPARATOR (BATSHORT)
VBATSHT
BAT Short falling threshold, forced
non-syn mode
VBATSHT_HYS
BAT short rising hysteresis
VBATSHT_DEG
Deglitch on both edge
VSRP falling
2
V
200
mV
1
μs
1.25
mV
1.25
mV
1
μs
LOW CHARGE CURRENT COMPARATOR
VLC
Low charge current (average) falling
threshold to force into non-synchronous
mode
VLC_HYS
Low charge current rising hysteresis
VLC_DEG
Deglitch on both edge
Measure on V(SRP-SRN)
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VVCC > VUVLO, (0-35mA load)
IVREF_LIM
VREF current limit
VVREF = 0V, VVCC > VUVLO
6
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3.267
35
3.3
3.333
V
mA
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq24610 bq24617
bq24610
bq24617
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SLUS892 – DECEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
5.0V ≤ V(VCC) ≤ 28V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
6.0
6.3
UNIT
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VVCC > 10V, CE = HIGH, (0-40mA load)
5.7
IREGN_LIM
REGN current limit
VREGN = 0V, VVCC > VUVLO, CE = HIGH
40
V
mA
TTC INPUT AND SAFETY TIMER
TPRECHG
Precharge safety timer range (1)
Precharge time before fault occurs
TCHARGE
Fast charge saftey timer range, with +/10% accuracy (1)
Tchg = CTTC × KTTC
Fast charge timer accuracy (1)
0.01 μF ≤ CTTC ≤ 0.11 μF
KTTC
1440
1800
1
–10%
Timer multiplier
2160
sec
10
Hr
10%
5.6
VTTC below this threshold disables the safety timer and
termination
TTC low threshold
min/nF
0.4
TTC oscillator high threshold
1.5
TTC oscillator low threshold
V
1
TTC source/sink current
45
50
V
V
55
μA
BATTERY SWITCH (BATFET) DRIVER
RDS_BAT_OFF
BATFET turn-off resistance
VACN > 5V
150
Ω
RDS_BAT_ON
BATFET turn-on resistance
VACN > 5V
20
kΩ
VBATDRV_REG
BATFET drive voltage
VBATDRV_REG = VACN – VBATDRV when VACN > 5V and
BATFET is on
7
V
4.2
AC SWITCH (ACFET) DRIVER
RDS_AC_OFF
ACFET turn-off resistance
VVCC > 5V
30
Ω
RDS_AC_ON
ACFET turn-on resistance
VVCC > 5V
20
kΩ
VACDRV_REG
ACFET drive voltage
VACDRV_REG = VVCC – VACDRV when VVCC > 5V and
ACFET is on
7
V
4.2
AC / BAT MOSFET DRIVERS TIMING
Driver dead time
Dead time when switching between AC and BAT
μs
10
BATTERY DETECTION
tWAKE
Wake time
Max time charge is enabled
IWAKE
Wake current
RSENSE = 10mΩ
tDISCHARGE
Discharge time
Max time discharge current is applied
1
sec
IDISCHARGE
Discharge current
8
mA
IFAULT
Fault current after a timeout fault
2
mA
VWAKE
Wake threshold (with-respect-to VREG)
Voltage on VFB to detect battery absent during Wake
50
mV
Discharge threshold
Voltage on VFB to detect battery absent during
discharge
VDISCH
500
50
125
ms
200
1.55
mA
V
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON
High side driver (HSD) turn-on
resistance
VBTST – VPH = 5.5 V
3.3
6
Ω
RDS_HI_OFF
High side driver turn-off resistance
VBTST – VPH = 5.5 V
1
1.3
Ω
VBTST_REFRESH
Bootstrap refresh comparator threshold
voltage
VBTST – VPH when low side refresh pulse is requested
4.0
4.2
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
Low side driver (LSD) turn-on resistance
RDS_LO_OFF
Low side driver turn-off resistance
(1)
4.1
7
Ω
1
1.4
Ω
Verified by design
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SLUS892 – DECEMBER 2009
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ELECTRICAL CHARACTERISTICS (continued)
5.0V ≤ V(VCC) ≤ 28V, 0°C < TJ < +125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM DRIVERS TIMING
Driver dead time
Dead time when switching between LSD and HSD, no
load at LSD and HSD
PWM ramp height
As percentage of VCC
30
ns
PWM OSCILLATOR
VRAMP_HEIGHT
7
PWM switching frequency (2)
510
600
%
690
kHz
INTERNAL SOFT START (8 steps to regulation current ICHG)
Soft start steps
Soft start step time
8
step
1.6
ms
1.5
s
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power-up
Delay from CE=1 to charger is allowed to turn on
LOGIC IO PIN CHARACTERISTICS (CE, STAT1, STAT2, PG)
VIN_LO
CE input low threshold voltage
VIN_HI
CE input high threshold voltage
VBIAS_CE
CE input bias current
V = 3.3V (CE has internal 1MΩ pulldown resistor)
VOUT_LO
STAT1, STAT2, PG output low
saturation voltage
IOUT_HI
Leakage current
(2)
8
0.8
V
6
μA
Sink Current = 5 mA
0.5
V
V = 32 V
1.2
µA
2.1
Verified by design
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
Figure
Figure 2
Charge Enable
Figure 3
Current Soft-Start (CE=1)
Figure 4
Charge Disable
Figure 5
Continuous Conduction Mode Switching Waveforms
Figure 6
Cycle-by-Cycle Synchronous to Nonsynchronous
Figure 7
100% Duty and Refresh Pulse
Figure 8
Transient System Load (DPM)
Figure 9
Battery Insertion
Figure 10
Battery to Ground Short Protection
Figure 11
Battery to ground Short Transition
Figure 12
Efficiency vs Output Current
Figure 13
10 V/div
10 V/div
REF REGN and PG Power Up (CE=1)
PH
2 A/div
IBAT
REGN
5 V/div
CE
5 V/div
2 V/div
VREF
5 V/div
/PG
2 V/div
VCC
LODRV
t − Time = 200 ms/div
t − Time = 4 ms/div
Figure 3. Charge Enable
10 V/div
10 V/div
Figure 2. REF REGN and PG Power Up (CE=1)
CE
5 V/div
2 A/div
IBAT
PH
5 V/div 2 A/div
5 V/div
LODRV
5 V/div
PH
LODRV
IL
CE
t − Time = 2 μs/div
t − Time = 4 ms/div
Figure 4. Current Soft-Start (CE=1)
Figure 5. Charge Disable
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5 V/div
PH
HIDRV
LODRV
1 A/div 5 V/div
PH
2 A/div
5 V/div 20 V/div 20 V/div
SLUS892 – DECEMBER 2009
IL
LODRV
IL
t − Time = 100 ns/div
t − Time = 100 ns/div
10 V/div
2 A/div
IIN
PH
ISYS
LODRV
2 A/div
0.5 A/div 5 V/div
Figure 7. Cycle-by-Cycle Synchronous to Nonsynchronous
2 A/div
Figure 6. Continuous Conduction Mode Switching Waveform
IL
IBAT
t − Time = 200 μs/div
t − Time = 400 ns/div
Figure 9. Transient System Load (DPM)
10 V/div
10 V/div
Figure 8. 100% Duty and Refresh Pulse
PH
2 A/div
LODRV
IL
IL
20 V/div
2 A/div
5 V/div
5 V/div
PH
VBAT
VBAT
t − Time = 200 ms/div
Figure 10. Battery Insertion
10
t − Time = 4 ms/div
Figure 11. Battery to GND Short Protection
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10 V/div
98
96
94
Efficiency - %
92
LODRV
20 V/div
2 A/div
5 V/div
PH
90
20 Vin, 4 cell
88
12 Vin, 2 cell
86
20 Vin, 3 cell
IL
84
VBAT
12 Vin, 1 cell
82
t − Time = 10 μs/div
80
0
Figure 12. Battery to GND Short Transition
1
2
5
4
3
IBAT - Output Current - A
6
7
8
Figure 13. Efficiency vs Output Current
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Pin Functions – 24-Pin QFN
PIN
NO.
12
FUNCTION DESCRIPTION
NAME
1
ACN
Adapter current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode
filtering. An optional 0.1-μF ceramic capacitor is placed from ACN pin to GND for common-mode filtering.
2
ACP
Adapter current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode
filtering. A 0.1-μF ceramic capacitor is placed from ACP pin to GND for common-mode filtering.
3
ACDRV
AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power MOSFET
and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turn-off and
slow turn-on, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to
source of the ACFET is used to slow down the ON and OFF times.
4
CE
Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1MΩ pull-down resistor.
5
STAT1
Open-drain charge status pin to indicate various charger operation (See Table 3)
6
TS
Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold
temperature window with a resistor divider from VREF to TS to GND. (See Figure 18)
7
TTC
SafetyTimer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the timer
and termination are disabled. When this input is HIGH, the timer is disabled but termination is allowed.
8
PG
Open-drain power-good status output. Active LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active HIGH
when IC has an invalid VCC. PGcan be used to drive a LED or communicate with a host processor.
9
STAT2
Open-drain charge status pin to indicate various charger operation (See Table 3)
10
VREF
3.3V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for
programming of voltage and current regulation and for programming the TS threshold.
11
ISET1
Fast Charge current set input. The voltage of ISET1 pin programs the fast charge current regulation set-point.
12
VFB
Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to
adjust the output battery regulation voltage.
13
SRN
Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode
filtering. An optional 0.1-μF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.
14
SRP
Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode
filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.
15
ISET2
Pre-charge and termination current set input. The voltage of ISET2 pin programs the pre-charge current regulation set-point and
termination current trigger point.
16
ACSET
Adapter current set input. The voltage of ACSET pin programs the input current regulation set-point during Dynamic Power
Management (DPM)
17
GND
Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC.
18
REGN
PWM low side driver positive 6V supply output. Connect a 1-μF ceramic capacitor from REGN to GND pin, close to the IC. Use for
low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from REGN to BTST.
19
LODRV
PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
20
PH
PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side
power MOSFET source, and output inductor). Connect the 0.1-μF bootstrap capacitor from PH to BTST.
21
HIDRV
PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
22
BTST
PWM high side driver positive supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side
power MOSFET source, and output inductor). Connect the 0.1-μF bootstrap capacitor from SW to BTST.
23
BATDRV
Battery to system MOSFET driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system from
the battery to prevent current flow from the system to the battery, while allowing a low impedance path from battery to system.
Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the
system load voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical
to allow a quick turn-off and slow turn-on, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an
optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times.
24
VCC
IC power positive supply. Connect through a 10-Ω to the common-source (diode-OR) point: source of high-side P-channel MOSFET
and source of reverse-blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor from VCC to GND pin close to the IC.
PowerPAD
Exposed pad beneath the IC. Always solder PowerPAD to the board, and have vias on the PowerPAD plane star-connecting to GND
and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.
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BLOCK DIAGRAM
bq24610/17
VREF
VCC-6 V
ACN ACN-6 V ACN-6 V
LDO
INTERNAL
REFERENCE
VREF
3.3 V
LDO
VCC
-
SRN+100 mV
+
VCC
-
VUVLO
+
ACN
+
VCC
VCC
SLEEP
UVLO
VCC
VCC-6 V
LDO
SLEEP
SRN+200 mV
UVLO
ACN-SRN
-
ACDRV
SYSTEM
POWER
SELECTOR
LOGIC
VCC-6V
ACN
ACOV
CE
BATDRV
1M
ACN-6V
+
20X
-
V(ACP-ACN)
+
COMP
ERROR
AMPLIFIER
ACN
ACSET
+
1V
+
-
2.1 V
+
REGN
2 mA
LODRV
V(SRP-SRN)
160% X IBAT_REG
-
CHG_OCP
GND
TTC
Safety
Timer
IC Tj
+
145 degC
-
CHARGE
FAULT
STAT 1
STAT1
ISET1
IBAT_ REG
ISET2
+
LOWV
104% X VBAT_REG
-
-
BAT
+
ISET2
6 V LDO
REFRESH
4.2V
FAULT
+
ISET1
CE
+
+
-
PH
-
PH
VCC
PWM
CONTROL
LOGIC
BTST
20µA
8 mA
SYNCH
+
5 mV -
-
IBAT_ REG
SRN
CHARGE
OR
DISCHARGE
+
SRP-SRN
-
V(SRP-SRN)
HIDRV
BAT_OVP
20 µA
+
20X
-
LEVEL
SHIFTER
PWM
-
VFB
SRP
BTST
CE
+
ACP
TSHUT
STATE
MACHINE
LOGIC
BAT_OVP
STAT 2
STAT2
PG
PG
VFB
+
- 1.55V
TTC
-
0.4 V
+
VCC
+
DISABLE
TMR/TERM
BATTERY
DETECTION
LOGIC
ACOV
TTC
TTC
VREF
DISCHARGE
VACOV +-
LTF
+
VFB
-
TS
SUSPEND
RCHRG
HTF
+
+
-
2.05 V +-
RCHRG
V(SRP - SRN)
+
ISET2
-
TERM
TERM
TCO
+
-
TERMINATE CHARGE
Figure 14. Functional Block Diagram for bq24610/7
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OPERATIONAL FLOWCHART
POR
Turn on
BATDRV FET
SLEEP MODE
VCC > SRN
No
Indicate SLEEP
Yes
Enable VREF LDO &
Chip Bias
Indicate battery
absent
Turn off BATFET
Turn on ACFET
30ms delay
No
See Enabling and Disabling
Charge Section
Battery
present?
Initiate battery
detect algorithm
Yes
Conditions met
for charge?
Indicate NOT
CHARGING,
Suspend timers
No
No
Conditions met
for charge?
No
Yes
Yes
Regulate
precharge current
VFB < VLOWV
Start 30 minute
precharge timer
Yes
Indicate ChargeIn-Progress
Start Fastcharge
timer
No
VFB < VLOWV
Yes
No
Regulate
fastcharge current
Indicate NOT
CHARGING,
Suspend timers
No
Conditions met
for charge?
Yes
Precharge
timer expired?
Yes
Indicate ChargeIn-Progress
No
Turn off charge,
Enable IDISCHG for 1
second
Yes
Indicate Charge In
Progress
VFB > VRECH
&
ICHG < ITERM
FAULT
Enable IFAULT
No
Fastcharge
Timer Expired?
Charge Complete
VFB < VRECH
No
Yes
Indicate FAULT
No
VFB > VRECH
Yes
Indicate DONE
Battery Removed
Yes
Indicate BATTERY
ABSENT
Figure 15. Operational Flowchart
14
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DETAILED DESCRIPTION
Regulation Voltage
VRECH
Regulation Current
Precharge
Current
Regulation
Phase
Fastcharge Current
Regulation Phase
Fastcharge Voltage
Regulation Phase
Termination
Charge
Current
Charge
Voltage
VLOWV
IPRECH & I TERM
Precharge
Time
Fastcharge Safety Time
Figure 16. Typical Charging Profile
Battery Voltage Regulation
The bq24610/7 uses a high accuracy voltage bandgap and regulator for the high charging voltage accuaracy.
The charge voltage is programmed via a resistor divider from the battery to ground, with the midpoint tied to the
VFB pin. The voltage at the VFB pin is regulated to 2.1V, giving the following equation for the regulation voltage:
é R2 ù
V
= 2.1 V ´ ê1+
ú,
BAT
ë R1 û
(1)
where R2 is connected from VFB to the battery and R1 is connected from VFB to GND.
Battery Current Regulation
The ISET1 input sets the maximum fast charging current. Battery charge current is sensed by resistor RSR
connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100mV. Thus, for
a 10mΩ sense resistor, the maximum charging current is 10A. The equation for charge current is:
VISET1
ICHARGE =
20 ´ RSR
(2)
VISET1, the input voltage range of ISET1 is between 0V and 2V. The SRP and SRN pins are used to sense
voltage across RSR with default value of 10mΩ. However, resistors of other values can also be used. A larger
sense resistor will give a larger sense voltage, a higher regulation accuracy; but, at the expense of higher
conduction loss.
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Input Adapter Current Regulation
The total input from an AC adapter or other DC sources is a function of the system supply current and the battery
charging current. System current normally fluctuates as portions of the systems are powered up or down. Without
Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the
maximum charger input current simultaneously. By using DPM, the battery charger reduces the charging current
when the input current exceeds the input current limit set by ACSET. The current capability of the AC adaptor
can be lowered, reducing system cost.
Similar to setting battery regulation current, adaptor current is sensed by resistor RAC connected between ACP
and ACN. Its maximum value is set by ACSET using Equation 3:
VACSET
IDPM =
20 ´ RAC
(3)
VACSET, the input voltage range of ACSET is between 0 and 2V. The ACP and ACN pins are used to sense
voltage across RAC with default value of 10mΩ. However, resistors of other values can also be used. A larger the
sense resistor will give a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher
conduction loss.
Precharge
On power-up, if the battery voltage is below the VLOWV threshold, the bq24610/7 applies the precharge current to
the battery. This feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within
30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.
VISET2, the precharge current is determined by the voltage on the ISET2 pin according to Equation 4.
VISET2
IPRECHARGE =
100 ´ R SR
(4)
Charge Termination, Recharge, and Safety Timer
The bq24610/7 monitors the charging current during the voltage regulation phase. When VTTC is valid,
termination is detected while the voltage on the VFB pin is higher than the VRECH threshold AND the charge
current is less than the ITERM threshold, as calculated in Equation 5:
VISET2
ITERM =
100 ´ RSR
(5)
The input voltage of ISET2 is between 0 and 2V. The minimum precharge/termination current is clamped to be
around 125mA with default 10mΩ sensing resistor. As a safety backup, the bq24610/7 also provides a
programmable charge timer. The charge time is programmed by the capacitor connected between the TTC pin
and GND, and is given by Equation 6
tCHARGE = CTTC ´ K TTC
(6)
where CTTC (range from 0.01µF to 0.11 µF to give 1-10hr safety time) is the capacitor connected from TTC pin to
GND, and KTTC is the constant multiplier (5.6min/nF).
A
•
•
•
new charge cycle is initiated and safety timer is reset when one of the following conditions occur:
The battery voltage falls below the recharge threshold
A power-on-reset (POR) event occurs
CE is toggled
The TTC pin may be taken LOW to disable termination and to disable the safety timer. If TTC is pulled to VREF,
the bq24610/7 will continue to allow termination but disable the safety timer. TTC taken low will reset the safety
timer. When ACOV, VCCLOWV and SLEEP mode resume normal, the safety timer will be reset.
16
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Power Up
The bq24610/7 uses a SLEEP comparator to determine the source of power on the VCC pin, since VCC can be
supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, bq24610/7
will enable the ACFET and disable BATFET. If all other conditions are met for charging, bq24610/7 will then
attempt to charge the battery (See Enabling and Disabling Charging). If the SRN voltage is greater than VCC,
indicating that the battery is the power source, bq24610/7 enables the BATFET, and enters a low quiescent
current (<15μA) SLEEP mode to minimize current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled, ACFET turns off and BATFET turns on.
Enable and Disable Charging
The following conditions have to be valid before charge is enabled:
• CE is HIGH
• The device is not in Under-Voltage-Lockout (UVLO) and not in VCCLOWV mode
• The device is not in SLEEP mode
• The VCC voltage is lower than the AC over-voltage threshold (VCC < VACOV)
• 30ms delay is complete after initial power-up
• The REGN LDO and VREF LDO voltages are at the correct levels
• Thermal Shut (TSHUT) is not valid
• TS fault is not detected
One of the following conditions will stop on-going charging:
• CE is LOW;
• Adapter is removed, causing the device to enter UVLO, VCCLOWV or SLEEP mode;
• Adapter is over voltage;
• The REGN or VREF LDOs are overloaded;
• TSHUT IC temperature threshold is reached (145°C on rising-edge with 15°C hysteresis).
• TS voltage goes out of range indicating the battery temperature is too hot or too cold.
• TTC safety timer out
System Power Selector
The bq24610/7 automatically switches adapter or battery power to the system load. The battery is connected to
the system by default during power up or during SLEEP mode. The battery is disconnected from the system and
then the adapter is connected to the system 30ms after exiting SLEEP. An automatic break-before-make logic
prevents shoot-through currents when the selectors switch.
The ACDRV is used to drive a pair of back-to-back p-channel power MOSFETs between adapter and ACP with
sources connected together and to VCC. The FET connected to adapter prevents reverse discharge from the
battery to the adapter when turned off. The p-channel FET with the drain connected to the adapter input provides
reverse battery discharge protection when off; and also minimizes system power dissipation, with its low-RDSON,
compared to a Schottky diode. The other p-channel FET connected to ACP separates battery from adapter, and
provides a limited dI/dt when connecting the adapter to the system by controlling the FET turn-on time. The
BATDRV controls a p-channel power MOSFET placed between BAT and system.
When adapter is not detected, the ACDRV is pulled to VCC to keep ACFET off, disconnecting the adapter from
system. BATDRV stays at ACN-6V to connect battery to system.
Approximately 30ms after the device comes out of SLEEP mode, the system begins to switch from battery to
adapter. The break-before-make logic keeps both ACFET and BATFET off for 10us before ACFET turns on. This
prevents shoot-through current or any large discharging current from going into the battery. The BATDRV is
pulled up to ACN and the ACDRV pin is set to VCC-6V by an internal regulator to turn on p-channel ACFET,
connecting the adapter to the system.
When the adapter is removed, the system waits until VCC drops back to within 200mV above SRN to switch from
adapter back to battery. The break-before-make logic still keeps 10μs dead time. The ACDRV is pulled up to
VCC and the BATDRV pin is set to ACN-6V by an internal regulator to turn on p-channel BATFET, connecting
the battery to the system.
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Asymmetrical gate drive (fast turn-off and slow turn-on) for the ACDRV and BATDRV drivers provides fast
turn-off and slow turn-on of the ACFET and BATFET to help the break-before-make logic and to allow a soft-start
at turn-on of either FET. The soft-start time can be further increased, by putting a capacitor from gate to source
of the p-channel power MOSFETs.
Automatic Internal Soft-Start Charger Current
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current.
Each step lasts around 1.6ms, for a typical rise time of 12.8ms. No external components are needed for this
function.
Converter Operation
The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A
type III compensation network allows using ceramic capacitors at the output of the converter. The compensation
input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The
feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter is selected to give a resonant frequency of 12kHz–17kHz for bq24610/7, where
resonant frequency, fo, is given by:
1
fo =
2 p L o Co
(7)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop
compensation. The ramp is offset by 300mV in order to allow zero percent duty-cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100%
duty-cycle PWM request. Internal gate drive logic allows achieving 99.5% duty-cycle while ensuring the
N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below
4.2V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side
n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the
high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again
due to leakage current discharging the BTST capacitor below the 4.2 V, and the reset pulse is reissued.
The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region. Also see Application Information for how to select inductor, capacitor and MOSFET.
Synchronous and Non-Synchronous Operation
The charger operates in synchronous mode when the SRP-SRN voltage is above 5mV (0.5A inductor current for
a 10mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is
break-before-make complimentary switching to prevent shoot-through currents. During the 30ns dead time where
both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the
low-side FET turn-on keeps the power dissipation low, and allows safely charging at high currents. During
synchronous mode the inductor current is always flowing and converter operates in continuous conduction mode
(CCM), creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5mV (0.5A inductor
current for a 10mΩ sense resistor). The charger is forced into non-synchronous mode when battery voltage is
lower than 2V or when the average SRP-SRN voltage is lower than 1.25mV.
During non-synchronous operation, the body-diode of lower-side MOSFET can conduct the positive inductor
current after the high-side n-channel power MOSFET turns off. When the load current decreases and the
inductor current drops to zero, the body diode will be naturally turned off and the inductor current will become
discontinuous. This mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side n-channel
power MOSFET will turn-on for around 80ns when the bootstrap capacitor voltage drops below 4.2V, then the
low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side power
MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrap capacitor is
18
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always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for
battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and can
both source and sink current. The 80ns low-side pulse pulls the PH node (connection between high and low-side
MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80ns, the
low-side MOSFET is kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the 80ns recharge pulse. The charge should be low enough to be absorbed by the input
capacitance. Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on,
and the low-side MOSFET does not turn on (only 80ns recharge pulse) either, and there is almost no discharge
from the battery.
During the DCM mode the loop response automatically changes and has a single pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
Cycle-by-Cycle Charge Under Current Protection
If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the
switching cycle to prevent negative inductor current. During DCM, the low-side FET will only turn on for at around
80ns when the bootstrap capacitor voltage drops below 4.2V to provide refresh charge for the bootstrap
capacitor. This is important to prevent negative inductor current from causing a boost effect in which the input
voltage increases as power is transferred from the battery to the input capacitors and lead to an over-voltage
stress on the VCC node and potentially cause damage to the system.
Input Over Voltage Protection (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage
reaches the ACOV threshold, charge is disabled and the system is switched to battery instead of adapter.
Input Under Voltage Lock Out (UVLO)
The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from
either input adapter or battery, since a conduction path exists from the battery to VCC through the high side
NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC are disabled, and the gate
drive bias to ACFET and BATFET are disabled.
Battery Over-Voltage Protection
The converter will not allow the high-side FET to turn-on until the BAT voltage goes below 102% of the regulation
voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load is removed
or the battery is disconnected. An 8mA current sink from SRP to GND is on only during charge and allows
discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP will also
suspend the safety timer.
Cycle-by-Cycle Charge Over-Current Protection
The charger has a secondary cycle-to-cycle over-current protection. It monitors the charge current, and prevents
the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the
over-current is detected, and automatically resumes when the current falls below the over-current threshold.
Thermal Shutdown Protection
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C, then the charger will soft-start again if all other enable charge
conditions are valid. Thermal shutdown will also suspend the safety timer.
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Temperature Qualification
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the battery temperature must be within the V(LTF) to V(HTF) thresholds. If battery
temperature is outside of this range, the controller suspends charge and the safety timer and waits until the
battery temperature is within the V(LTF) to V(HTF) range. During the charge cycle the battery temperature must
be within the V(LTF) to V(TCO) thresholds. If battery temperature is outside of this range, the controller suspends
charge and waits until the battery temperature is within the V(LTF) to V(HTF) range. The controller suspends
charge by turning off the PWM charge FETs. Figure below summarizes the operation.
VREF
VREF
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTFH
VLTF
VLTFH
TEMPERATURE RANGE
TO INITIATE CHARGE
TEMPERATURE RANGE
DURING A CHARGE
CYCLE
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
GND
GND
Figure 17. TS pin, Thermistor Sense Thresholds
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 1, the value RT1 and RT2 can be
determined by using the following equations:
æ 1
1 ö
VVREF ´ RTHCOLD ´ RTHHO T ´ ç
÷
VHTF ø
è VLTF
RT2 =
æV
ö
æV
ö
RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷
V
V
è HTF
ø
è LTF
ø
VVREF
RT1 =
VLTF
(8)
-1
1
1
+
RT2 RTHCOLD
(9)
VREF
bq24610/7
RT1
TS
RT2
RTH
103AT
Figure 18. TS Resistor Network
20
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For example, 103AT NTC thermistors are used to monitor the battery pack temperature. Select TCOLD = 0ºC and
THOT = 40ºC then we get RT2 = 430kΩ, RT1 = 9.31kΩ and TCUT-OFF is around 45ºC. A small RC filter is suggested
to use for system-level ESD protection.
Timer Fault Recovery
The bq24610/7 provides a recovery method to deal with timer fault conditions. The following summarizes this
method:
Condition 1: The battery voltage is above the recharge threshold and a timeout fault occurs.
Recovery Method: The timer fault will clear when the battery voltage falls below the recharge threshold, and
battery detection will begin. Taking CE low or a POR condition will also clear the fault.
Condition 2: The battery voltage is below the recharge threshold and a timeout fault occurs.
Recovery Method: Under this scenario, the bq24610/7 applies the IFAULT current to the battery. This small
current is used to detect a battery removal condition and remains on as long as the battery voltage stays below
the recharge threshold. If the battery voltage goes above the recharge threshold, the bq24610/7 disables the
fault current and executes the recovery method described in Condition 1. Taking CE low or a POR condition will
also clear the fault.
PG Output
The open drain PG(power good) output indicates whether the VCC voltage is valid or not. The open drain FET
turns on whenever bq24610/7 has a valid VCC input ( not in UVLO or ACOV or SLEEP mode). The PGpin can
be used to drive an LED or communicate to the host processor.
CE (Charge Enable)
The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables
charge, provided all the other conditions for charge are met (see Enabling and Disabling Charge). A high to low
transition on this pin also resets all timers and fault conditions. There is an internal 1MΩ pulldown resistor on the
CE pin, so if CE is floated the charge will not turn on.
Inductor, Capacitor, and Sense Resistor Selection Guidelines
The bq24610/7 provides internal loop compensation. With this scheme, best stability occurs when the LC
resonant frequency, fo, is approximately 12kHz–17kHz for bq24610/7.
The following table provides a summary of typical LC components for various charge currents:
Table 2. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current for
bq24610/7 (600 kHz Switching Frequency)
CHARGE CURRENT
2A
4A
6A
8A
10A
Output Inductor Lo
6.8 μH
6.8 μH
4.7 μH
3.3 μH
3.3 μH
Output Capacitor Co
20 μF
20 μF
30 μF
40 μF
40 μF
Sense Resistor
10 mΩ
10 mΩ
10 mΩ
10 mΩ
10 mΩ
Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the table below.
These status pins can be used to drive LEDs or communicate with the host processor. Note that OFF indicates
that the open-drain transistor is turned off.
Table 3. STAT Pin Definition for bq24610/7
STAT1
STAT2
Charge in progress
CHARGE STATE
ON
OFF
Charge complete
OFF
ON
Charge suspend, timer fault, over-voltage, sleep mode, battery absent
OFF
OFF
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Battery Detection
For applications with removable battery packs, bq24610/7 provides a battery absent detection scheme to reliably
detect insertion or removal of battery packs.
POR or RECHARGE
The battery detection routine runs on
power up, or if VFB falls below VRECH
due to removing a battery or
discharging a battery
Apply 8mA discharge
current, start 1s timer
VFB < VLOWV
No
Yes
1s timer
expired
No
Yes
Battery Present,
Begin Charge
Disable 8mA
discharge current
Enable 125mA Charge,
Start 0.5s timer
VFB > VRECH
Yes
Disable 125mA
Charge
No
0.5s timer
expired
No
Yes
Battery Present,
Begin Charge
Battery Absent
Figure 19. Battery Detection Flowchart
Once the device has powered up, an 8mA discharge current will be applied to the SRN terminal. If the battery
voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is
turned on at low charge current (125mA). If the battery voltage gets up above the recharge threshold within
500ms, there is no battery present and the cycle restarts. If either the 500ms or 1 second timer time out before
the respective thresholds are hit, a battery is detected and a charge cycle is initiated.
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Battery not detected
VREG
VRECH
(VWAKE)
Battery
inserted
VLOWV
Battery detected
(VDISH)
tWAKE
tRECH_DEG
tLOWV_DEG
Figure 20. Battery Detect Timing Diagram
Care must be taken that the total output capacitance at the battery node is not so large that the discharge current
source cannot pull the voltage below the LOWV threshold during the 1 second discharge time. The maximum
output capacitance can be calculated as follows:
CMAX =
IDISCH ´ tDISCH
é R ù
0.5 ´ ê1+ 2 ú
ë R1 û
(10)
Where CMAX is the maximum output capacitance, IDISCH is the discharge current, tDISCH is the discharge time, and
R2 and R1 are the voltage feedback resistors from the battery to the VFB pin. The 0.5 factor is the difference
between the RECHARGE and the LOWV thresholds at the VFB pin.
Example
For a 3-cell Li+ charger, with R2 = 500k, R1 = 100k (giving 12.6V for voltage regulation), IDISCH = 8mA, tDISCH = 1
second,
8mA ´ 1sec
CMAX =
= 2.7 mF
é 500k ù
0.5 ´ ê1+
ú
ë 100k û
(11)
Based on these calculations, no more than 2.7 mF should be allowed on the battery node for proper operation of
the battery detection circuit.
Component List for Typical System Circuit of Figure 1
PART DESIGNATOR
QTY
DESCRIPTION
Q1, Q2, Q3
3
P-channel MOSFET, –30 V,–35 A, PowerPAK 1212-8, Vishay-Siliconix, Si7617DN
Q4, Q5
2
N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN
D1
1
Diode, Dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C
D2, D3, D4
3
LED Diode, Green, 2.1V, 20mA, LTST-C190GKT
RAC, RSR
2
Sense Resistor, 10 mΩ, 2010, Vishay-Dale, WSL2010R0100F
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PART DESIGNATOR
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QTY
DESCRIPTION
L1
1
Inductor, 6.8 µH, 5.5A, Vishay-Dale IHLP2525CZ
C8, C9, C12, C13
4
Capacitor, Ceramic, 10 µF, 35 V, 20%, X7R
C4, C5
2
Capacitor, Ceramic, 1 µF, 16 V, 10%, X7R
C1, C3, C6, C11
4
Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R
C2, C10
2
Capacitor, Ceramic, 0.1 µF, 50 V, 10%, X7R
C7
1
Capacitor, Ceramic, 1 µF, 50 V, 10%, X7R
C14, C15 (Optional)
2
Capacitor, Ceramic, 0.1 µF, 50 V, 10%, X7R
C16
1
Capacitor, Ceramic, 2.2 µF, 35V, 10%, X7R
Cff
1
Capacitor, Ceramic, 22 pF, 25V, 10%, X7R
CTTC
1
Capacitor, Ceramic, 0.056 µF, 16V, 5%, X7R
R1, R3, R5, R7
4
Resistor, Chip, 100 kΩ, 1/16W, 0.5%
R2
1
Resistor, Chip, 500 kΩ, 1/16W, 0.5%
R4
1
Resistor, Chip, 32.4 kΩ, 1/16W, 0.5%
R6
1
Resistor, Chip, 10 kΩ, 1/16W, 0.5%
R8
1
Resistor, Chip, 22.1 kΩ, 1/16W, 0.5%
R9
1
Resistor, Chip, 9.31 kΩ, 1/16W, 1%
R10
1
Resistor, Chip, 430 kΩ, 1/16W, 1%
R11, R12, R13, R18, R19
5
Resistor, Chip, 10 kΩ, 1/16W, 5%
R14, R15 (optional)
2
Resistor, Chip, 100 kΩ, 1/16W, 5%
R16
1
Resistor, Chip, 100 Ω, 1/16W, 5%
R17
1
Resistor, Chip, 10 Ω, 1/4W, 5%
R20
1
Resistor, Chip, 2 Ω, 1W, 5%
24
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APPLICATION INFORMATION
Inductor Selection
The bq24610/7 has 600kHz switching frequency to allow the use of small inductor and capacitor values. Inductor
saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(12)
The inductor ripple current depends on input voltage (VIN), duty cycle (D=VOUT/VIN), switching frequency (fs) and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fS ´ L
(13)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery charging
voltage range is from 9V to 12.6V for 3-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the
maximum inductor ripple current. Another example is 4-cell battery, the battery voltage range is from 12V to
16.8V, and 12V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between
inductor size and efficiency for a practical design.
The bq24610/7 has cycle-by-cycle charge under current protection (UCP) by monitoring charging current sensing
resistor to prevent negative inductor current. The Typical UCP threshold is 5mV falling edge corresponding to
0.5A falling edge for a 10mΩ charging current sensing resistor.
Input Capacitor
Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50%
and can be estimated by the following equation:
ICIN = ICHG ´
D ´ (1 - D)
(14)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be
placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage
rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred
for 20V input voltage. 10-20µF capacitance is suggested for typical of 3-4A charging current.
Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3
(15)
The output capacitor voltage ripple can be calculated as follows:
DVo =
1
8LCfs
2
2
æ
V
ç 1 - OUT
ç
VIN
è
ö
÷
÷
ø
(16)
At certain input/output voltage and switching frequenccy, the voltage ripple can be reduced by increasing the
output filter LC.
The bq24610/7 has internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor should be designed between 12 kHz and 17 kHz. The preferred ceramic capacitor
is 25V or higher rating, X7R or X5R for 4-cell application.
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Power MOSFETs Selection
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are
preferred for 20V input voltage and 40V or higher rating MOSFETs are prefered for 20-28V input voltage.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance,
RDS(ON), and the gate-to-drain charge, QGD. For bottom side MOSFET, FOM is defined as the product of the
MOSFET's on-resistance, RDS(ON), and the total gate charge, QG.
FOM top = RDS(on) ´ QG D
FOMbottom = RDS(on) ´ QG
(17)
The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle
(D=VOUT/VIN), charging current (ICHG), MOSFET's on-resistance RDS(ON)), input voltage (VIN), switching frequency
(F), turn on time (ton) and turn off time (ttoff):
1
Ptop = D ´ ICHG2 ´ RDS(on) +
´ VIN ´ ICHG ´ (t on + t off ) ´ fS
2
(18)
The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100ºC junction
temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn off times are
given by:
Q
Q
ton = SW , t off = SW
Ion
Ioff
(19)
where Qsw is the switching charge, Ion is the turn-on gate driving current and Ioff is the turn-off gate driving
current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge
(QGD) and gate-to-source charge (QGS):
1
QSW = QGD +
´ QGS
2
(20)
Gate driving current total can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total
turn-on gate resistance (Ron) and turn-off gate resistance Roff) of the gate driver:
VREG N - Vplt
Vplt
Ion =
, Ioff =
Ron
Roff
(21)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on)
(22)
If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The maximum
charging current in non-synchronous mode can be up to 0.9A (0.5A typ) for a 10mΩ charging current sensing
resistor considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body
diode capable of carrying the maximum non-synchronous mode charging current.
MOSFET gate driver power loss contributes to the domainant losses on controller IC, when the buck converter is
switching. Choosing the MOSFET with a small Qg_total will reduce the IC power loss to avoid thermal shutdown.
PICLoss_driver = VIN × Qg_total × fs
(23)
Where Qg_total is the total gate charge for both upper and lower MOSFET at 6V VREGN
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Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second
order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent over voltage event on VCC pin. ACP/ACN pin needs
to be placed after the input ACFET in order to avoid the over-voltage stress on these pins during hot-plug-in.
There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level.
However these two solutions may not have low cost or small size.
A cost effective and small size solution is shown in Figure 21. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used
for reverse voltage protection for VCC pin ( it can be the body diode of input ACFET). C2 is VCC pin decoupling
capacitor and it should be place to VCC pin as close as possible. The R2 and C2 form a damping RC network to
further protect the IC from high dv/dt and high voltage spike. C2 value should be less than C1 value so R1 can
dominant the equivalent ESR value to get enough damping effetc for hot plug-in. R1 and R2 package must be
sized enough to handle inrush current power loss according to resistor manufacturer’s datasheet. The filter
components value always need to be verified with real application and minor adjustments may need to fit in the
real application circuit.
D1
Adapter
connector
R1
2W
C1
2.2 mF
(2010)
R2 (1206)
4.7 -30W
VCC pin
C2
0.1-1 mF
Figure 21. Input Filter
PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 22) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use
shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on
different layers and using vias to make this connection.
2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal
traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching
MOSFETs.
3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area) and do not route the sense leads through a high-current path (see Figure 23 for Kelvin connection for
best current accuracy). Place decoupling capacitor on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route analog ground separately from power ground and use single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins
to reduce inductive and capacitive noise coupling. Connect analog ground to GND. Connect analog ground
and power ground together using PowerPAD as the single ground connection point. Or using a 0Ω resistor to
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tie analog ground to power ground (PowerPAD should tie to analog ground in this case). A star-connection
under PowerPAD is highly recommended.
8. It is critical that the exposed PowerPAD on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
10. All via size and number should be enough for a given current path.
SW
L1
V BAT
R1
High
Frequency
VIN
BAT
Current
C1
Path
PGND
C2
C3
Figure 22. High Frequency Current Path
Current Direction
R SNS
Current Sensing Direction
To SRP - SRN pin or ACP - ACN pin
Figure 23. Sensing Resistor PCB Layout
Refer to the EVM design (SLUU396) for the recommended component placement with trace and via locations.
For the QFN information, refer to SCBA017 and SLUA271.
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PACKAGE OPTION ADDENDUM
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1-Jan-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
BQ24610RGER
ACTIVE
VQFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24610RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
BQ24617RGER
PREVIEW
VQFN
RGE
24
3000
TBD
Call TI
Call TI
BQ24617RGET
PREVIEW
VQFN
RGE
24
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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