ON NCP9003SNT1G Compact backlight led boost driver Datasheet

NCP9003
Compact Backlight LED
Boost Driver
The NCP9003 is a high efficiency boost converter operating in
current loop, based on a PFM mode, to drive White LED. The current
mode regulation allows a uniform brightness of the LEDs. The chip
has been optimized for small ceramic capacitors, capable to supply
up to 1.0 W output power.
http://onsemi.com
MARKING
DIAGRAM
Features
• 2.7 to 5.5 V Input Voltage Range
• Vout to 24 V Output Compliance Allows up to 5 LEDs Drive in
•
•
•
•
•
•
•
•
•
•
•
•
Series
Built−in Overvoltage Protection
Full EMI Immunity
Inductor Based Converter brings up to 90% Efficiency
Constant Output Current Regulation
0.3 mA Standby Quiescent Current
Includes Dimming Function (PWM)
Enable Function Driven Directly from Low Battery Voltage Source
Automatic LEDs Current Matching
Thermal Shutdown Protection
All Pins are Fully ESD Protected
Low EMI Radiation
Pb−Free Package is Available
5
TSOP−5
SN SUFFIX
CASE 483
5
1
DBNAYWG
G
1
DBN = Specific Device Code
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Vout
1
GND
2
FB
3
Typical Applications
5
Vbat
4
EN
(Top View)
• LED Display Back Light Control
• Keyboard Back Light
• High Efficiency Step Up Converter
ORDERING INFORMATION
Device
Package
Shipping†
NCP9003SNT1G
TSOP−5
(Pb−Free)
3000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 1
1
Publication Order Number:
NCP9003/D
NCP9003
Vbat
Vbat
U1
4
EN
Vbat
C1
5
4.7 mF
L1
22 mH
2
GND
GND
3
Vout
FB
GND
D1
1
MBR0530
NCP9003
R1
GND
D6
C2
1.0 mF
D5
D4
D3
D2
15 W
LWT67C LWT67C LWT67C
LWT67C LWT67C
GND
Figure 1. Typical Application
Thermal Shutdown
Current Sense
Vbat
5 Vbat
CONTROLLER
Vsense
EN 4
100 k
GND
FB 3
300 k
1 Vout
Q1
−
+
2 GND
GND
+200 mV
Band Gap
Figure 2. Block Diagram
http://onsemi.com
2
NCP9003
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
Description
1
Vout
POWER
This pin is the power side of the external inductor and must be connected to the
external Schottky diode. It provides the output current to the load. Since the boost
converter operates in a current loop mode, the output voltage can range up to
+24 V but shall not extend this limit. However, if the voltage on this pin is higher
than the Over Voltage Protection threshold (OVP) the device comes back to
shutdown mode. To restart the chip, one must either send a Low to High
sequence on Pin EN, or switch off the Vbat supply. A capacitor must be used on
the output voltage to avoid false triggering of the OVP circuit. This capacitor
should be 1.0 mF minimum. Ceramic type, (ESR <100 mW), is mandatory to
achieve the high end efficiency. This capacitor limits the noise created by the fast
transients present in this circuitry. In order to limit the inrush current and to
operate with an acceptable start−up time, it is recommended to use any value
between 1.0 mF and 8.2 mF capacitor maximum. Care must be observed to avoid
EMI through the PCB copper tracks connected to this pin.
2
GND
POWER
This pin is the system ground for the NCP9003 and carries both the power and
the analog signals. High quality ground must be provided to avoid spikes and/or
uncontrolled operation. Care must be observed to avoid high−density current flow
in a limited PCB copper track. Ground plane technique is recommended.
3
FB
ANALOG INPUT
This pin provides the output current range adjustment by means of a sense
resistor connected to the analog control or with a PWM control. The dimming
function can be achieved by applying a PWM voltage technique to this pin (see
Figure 29). The current output tolerance depends upon the accuracy of this
resistor. Using a "5% metal film resistor or better, yields a good enough output
current accuracy.
Note: A built−in comparator switch OFF the DC/DC converter if the voltage
sensed across this pin and ground is higher than 700 mV (typical).
4
EN
DIGITAL INPUT
This is an Active−High logic input which enables the boost converter. The built−in
pull down resistor disables the device when the EN pin is left open. The LED
brightness can be controlled by applying a pulse width modulated signal to the
enable pin (see Figure 31).
5
Vbat
POWER
The external voltage supply is connected to this pin. A high quality reservoir
capacitor must be connected across Pin 1 and Ground to achieve the specified
output voltage parameters. A 4.7 mF/6.3 V, low ESR capacitor must be connected
as close as possible across Pin 5 and ground Pin 2. The X5R or X7R ceramic
MURATA types are recommended. The return side of the external inductor shall
be connected to this pin. Typical application will use a 22 mH, size 1008, to handle
the 1.0 to 100 mA max output current range. On the other hand, when the desired
output current is above 20 mA, the inductor shall have an ESR < 1.5 W to achieve
a good efficiency over the Vbat range.
http://onsemi.com
3
NCP9003
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply
Rating
Vbat
6.0
V
Output Power Supply Voltage Compliance
Vout
28
V
Digital Input Voltage
Digital Input Current
EN
−0.3 < Vin < Vbat + 0.3
1.0
V
mA
2.0
200
kV
V
PD
RqJA
160
250
mW
°C/W
Operating Ambient Temperature Range
TA
−25 to +85
°C
Operating Junction Temperature Range
TJ
−25 to +125
°C
TJmax
+150
°C
Tstg
−65 to +150
°C
ESD Capability (Note 1)
Human Body Model (HBM)
Machine Model (MM)
VESD
TSOP−5 Package
Power Dissipation @ TA = +85°C (Note 2)
Thermal Resistance, Junction−to−Air
Maximum Junction Temperature
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22−A114
Machine Model (MM) "200 V per JEDEC standard: JESD22−A115
2. The maximum package power dissipation limit must not be exceeded.
3. Latch−up current maximum rating: "100 mA per JEDEC standard: JESD78.
4. Moisture Sensivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
POWER SUPPLY SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −25°C to +85°C ambient
temperature, unless otherwise noted.)
Rating
Pin
Symbol
Min
Typ
Max
Unit
Power Supply
4
Vbat
2.7
−
5.5
V
Output Load Voltage Compliance
5
Vout
21
24
−
V
Continuous DC Current in the Load @ Vout = 3xLED, L = 22 mH,
ESR < 1.5 W, Vbat = 3.60 V
5
Iout
50
−
−
mA
Stand By Current, @ Iout = 0 mA, EN = L, Vbat = 3.6 V
4
Istdb
−
0.3
−
mA
Stand By Current, @ Iout = 0 mA, EN = L, Vbat = 5.5 V
4
Istdb
−
0.8
3.0
mA
Inductor Discharging Time @ Vbat = 3.6 V, L = 22 mH, 3xLED,
Iout = 10 mA
4
Toffmax
−
320
−
ns
Thermal Shutdown Protection
−
TSD
−
160
−
°C
Thermal Shutdown Protection Hysteresis
−
TSDH
−
30
−
°C
http://onsemi.com
4
NCP9003
ANALOG SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −25°C to +85°C ambient
temperature, unless otherwise noted.)
Pin
Symbol
Min
Typ
Max
Unit
High Level Input Voltage
Low Level Input Voltage
4
EN
1.3
−
−
−
−
0.4
V
V
EN Pull Down Resistor
4
REN
−
100
−
kW
Feedback Voltage Threshold
3
FB
185
200
225
mV
Output Current Stabilization Time Delay following a DC/DC Start−up,
@ Vbat = 3.60 V, L = 22 mH, Iout = 20 mA
1
Ioutdly
−
100
−
ms
Internal Switch ON Resistor @ Tamb = +25°C
1
QRDSON
−
1.7
−
W
Rating
5. The overall tolerance depends upon the accuracy of the external resistor.
ESD PROTECTION
The NCP9003 includes silicon devices to protect the pins
against the ESD spikes voltages. To cope with the different
ESD voltages developed in the applications, the built−in
structures have been designed to handle "2.0 kVin Human
Body Model (HBM) and "200 V in Machine Model (MM)
on each pin.
means of a current loop, the output voltage will varies
depending upon the dynamic impedance presented by the
load.
Considering high intensity LED, the output voltage can
range from a low 6.40 V (two LED in series biased with a
low current), up to 21 V, the voltage compliance the chip
can sustain continuously.
The basic DC/DC structure is depicted in Figure 3. With
a 28 V maximum rating voltage capability, the power
device can accommodate high voltage source without any
leakage current downgrading.
DC/DC OPERATION
The DC/DC converter is designed to supply a constant
current to the external load, the circuit being powered from
a standard battery supply. Since the regulation is made by
Vbat
L1
22 mH
Vdsense
POR
1
D1
Vds
C1
RESET
LOGIC
CONTROL
Vdsense
GND
+
−
R1
−
V(Ipeak)
D4
GND
D5
ZERO_CROSSING
1.0 mF
TIME_OUT
D3
D2
Q1
3
+
R2
xR
C2
Vref
GND
Figure 3. Basic DC/DC Converter Structure
http://onsemi.com
5
GND
Vs
NCP9003
Basically, the chip operates with two cycles:
Cycle #1: time t1, the energy is stored into the inductor
Cycle #2: time t2, the energy is dumped to the load
The POR signal sets the flip−flop and the first cycle takes
place. When the current hits the peak value, defined by the
First Start−Up
error amplifier associated to the loop regulation, the
flip−flop resets, the NMOS is deactivated and the current
is dumped into the load. Since the timings depend on the
environment, the internal timer limits the toff cycle to
320 ns (typical), making sure the system operates in a
continuous mode to maximize the energy transfer.
Normal Operation
Ipeak
IL
Iv
t1
0 mA
t2
t
Ids
0 mA
t
Io
0 mA
t
Figure 4. Basic DC−DC Operation
Based on the data sheet, the current flowing into the
inductor is bounded by two limits:
• Ipeak Value: Internally fixed to 350 mA typical
• Iv Value: Limited by the fixed Toff time built in the
chip (320 ns typical)
The system operates in a continuous mode as depicted in
Figure 4 and t1 and t2 times can be derived from basic
equations. (Note: The equations are for theoretical analysis
only, they do not include the losses.)
L + E * dI
dt
to avoid saturation of the core. On top of that, the ferrite
material shall be capable to operate at high frequency
(1.0 MHz) to minimize the Foucault’s losses developed
during the cycles.
The operating frequency can be derived from the
electrical parameters. Let V = Vo − Vbat, rearranging
Equation 1:
ton + dI * L
E
Since toff is nearly constant (according to the 320 ns
typical time), the dI is constant for a given load and
inductance value. Rearranging Equation 5 yields:
(eq. 1)
Let Vbat = E, then:
(Ip * Iv) * L
Vbat
(eq. 2)
(Ip * Iv) * L
t2 +
Vo * Vbat
(eq. 3)
t1 +
ton +
t2 * (Vo * Vbat)
L
V*dt
L
*L
E
(eq. 6)
Let E = Vbat, and Vopk = output peak voltage, then:
ton +
Since t2 = 320 ns typical and Vo = 21 V maximum, then
(assuming a typical Vbat = 3.0 V):
DI +
(eq. 5)
(Vopk * Vbat) * dt
Vbat
(eq. 7)
Finally, the operating frequency is:
f+
1
ton ) toff
(eq. 8)
The output power supplied by the NCP9003 is limited to
one watt: Figure 5 shows the maximum power that can be
delivered by the chip as a function of the output voltage.
(eq. 4)
320 ns * (21−3.0)
DImax +
+ 261 mA
22 mH
Of course, from a practical stand point, the inductor must
be sized to cope with the peak current present in the circuit
http://onsemi.com
6
NCP9003
Pout = f(Vbat) @ Rs = 2.0 W
Ipeak = f(Vbat) @ Lout = 22 mH
400
1200
3 LED
1000
350
2 LED
Ipeak (mA)
4 LED
5 LED
600
400
300
250
200
200
Pout = f(Vbat) @ Rsense = 2.0 W
0
2
3
4
Vbat (V)
5
150
6
2
3
4
Vbat (V)
5
6
Test conditions: L = 22 mH, Rsense = 10 W, Tamb = +20°C
Figure 5. Maximum Output Power as a Function of
the Battery Supply Voltage
Figure 6. Typical Inductor Peak Current as a
Function of Vbat Voltage
120
2 LED
100
3 LED
80
Iout (mA)
Pout (mW)
800
4 LED
60
5 LED
40
20
0
2.5
3.0
3.5
4.0
Vbat (V)
4.5
5.0
5.5
Test conditions: L = 22 mH, Rsense = 2.0 W, Tamb = +25°C
Figure 7. Maximum Output Current as a Function of Vbat
http://onsemi.com
7
NCP9003
Output Current Range Set−Up
The current regulation is achieved by means of an external sense resistor connected in series with the LED string.
Vbat
L1
22 mH
D1
FB
3
Load
Vout
1
Q1
CONTROLLER
GND
R1
xW
GND
Figure 8. Output Current Feedback
A standard 5% tolerance resistor, 22 W SMD device,
yields 9.09 mA, good enough to fulfill the back light
demand. The typical application schematic diagram is
provided in Figure 9.
The current flowing through the LED creates a voltage
drop across the sense resistor R1. The voltage drop is
constantly monitored internally, and maximum peak
current allowed in the inductor is set accordingly in order
to keep constant this voltage drop (and thus the current
flowing through the LED). For example, should one need
a 10 mA output current, the sense resistor should be sized
according to the following equation:
R1 + Feedback Threshold + 200 mV + 20 W
Iout
10 mA
(eq. 9)
Vbat
U1
4
Pulse
EN
Vbat
C1
5
4.7 mF
GND
L1
22 mH
GND
2
Vout
GND
FB
3
D1
1
MBR0530
NCP9003
GND
R1
22 W
D6
D5
D4
D3
D2
LWT67C LWT67C LWT67C LWT67C LWT67C
Figure 9. Basic Schematic Diagram
http://onsemi.com
8
C2
1.0 mF
GND
NCP9003
Output Load Drive
The Schottky diode D1, associated with capacitor C2
(see Figure 9), provides a rectification and filtering
function.
When a pulse−operating mode is acceptable:
• A PWM mode control can be used to adjust the output
current range by means of a resistor and a capacitor
connected across FB pin. On the other hand, the
Schottky diode can be removed and replaced by at
least one LED diode, keeping in mind such LED shall
sustain the large pulsed peak current during the
operation.
In order to optimize the built−in Boost capabilities, one
shall operate the NCP9003 in the continuous output current
mode. Such a mode is achieved by using and external
reservoir capacitor (see Table 1) across the LED.
At this point, the peak current flowing into the LED
diodes shall be within the maximum ratings specified for
these devices. Of course, pulsed operation can be achieved,
due to the EN signal Pin 4, to force high current into the
LED when necessary.
TYPICAL OPERATING CHARACTERISTICS
Yield = f(Vbat) @ Iout = 4.0 mA/Lout = 22 mH
100
4 LED/4 mA
90
3 LED/4 mA
70
2 LED/4 mA
YIELD (%)
YIELD (%)
80
5 LED/4 mA
60
50
40
20
10
10
90
3.50
4.00
4.50
5.00
0
2.50
5.50
4.00
4.50
5.00
5.50
Figure 10. Overall Efficiency vs. Power Supply @
Iout = 4.0 mA, L = 22 mH
Figure 11. Overall Efficiency vs. Power Supply @
Iout = 10 mA, L = 22 mH
Yield = f(Vbat) @ Iout = 15 mA/Lout = 22 mH
Yield = f(Vbat) @ Iout = 20 mA/Lout = 22 mH
100
3 LED/15 mA
3 LED/20 mA
90
80
70
5 LED/15 mA
2 LED/15 mA
4 LED/15 mA
YIELD (%)
YIELD (%)
3.50
Vbat (V)
70
50
3.00
Vbat (V)
80
60
3 LED/10 mA
40
20
3.00
5 LED/10 mA
50
30
0
2.50
2 LED/10 mA
60
30
100
4 LED/10 mA
90
80
70
Yield = f(Vbat) @ Iout = 10 mA/Lout = 22 mH
100
40
60
20
20
10
10
3.50
4.00
4.50
5.00
0
2.50
5.50
2 LED/20 mA
40
30
3.00
5 LED/20 mA
50
30
0
2.50
4 LED/20 mA
3.00
3.50
4.00
4.50
5.00
5.50
Vbat (V)
Vbat (V)
Figure 12. Overall Efficiency vs. Power Supply @
Iout = 15 mA, L = 22 mH
Figure 13. Overall Efficiency vs. Power Supply @
Iout = 20 mA, L = 22 mH
http://onsemi.com
9
NCP9003
Yield = f(Vbat) @ Iout = 40 mA/Lout = 22 mH
100
Feedback Variation vs. Temperature
205
2 LED/40 mA
204
FEEDBACK VOLTAGE (mV)
90
80
YIELD (%)
70
5 LED/40 mA
4 LED/40 mA
60
3 LED/40 mA
50
40
30
20
10
203
202
Vbat = 3.1 V thru 5.5 V
201
200
199
198
197
196
0
2.50
3.00
3.50
4.00
Vbat (V)
4.50
5.00
195
−40
5.50
0
−20
20
40
60
100
80
TEMPERATURE (°C)
All curve conditions: L = 22 mH, Cin = 4.7 mF, Cout = 1.0 mF,
Typical curve @ T° = +25°C
Figure 15. Feedback Voltage Stability
Figure 14. Overall Efficiency vs. Power Supply @
Iout = 40 mA, L = 22 mH
Feedback Variation vs. Nominal
(Vbat = 3.0 V, 6.0 V, T = 255C)
5
−40°C thru 125°C
1.2
3
2
1.0
1
Vbat = 3.1 V thru 5.5 V
IStby (mA)
FEEDBACK VARIATION (%)
4
0
−1
−2
0.8
0.6
0.4
−3
0.2
−4
−5
−40
−20
0
20
40
60
80
0.0
2.7
100
3.9
4.5
Vbat (V)
Figure 16. Feedback Voltage Variation
Figure 17. Standby Current
Frequency = f(Vbat) @ Iout = 20 mA−Lout = 22 mH
2 LED
2.0
1.5
3 LED
4 LED
1.0
5 LED
0.5
0
2.5
3.3
TEMPERATURE (°C)
3.0
3.5
4.0
4.5
5.0
5.1
5.5
OVP vs. Temperature
26
OVERVOLTAGE PROTECTION (V)
2.5
f (mHz)
Standby Current vs. Vbat
1.4
25
24
Vbat = 5.5 V
23
22
−40 −20
5.5
Vbat = 3.6 V
Vbat = 2.7 V
0
20
40
60
80
100
Vbat (V)
TEMPERATURE (°C)
Figure 18. Typical Operating Frequency
Figure 19. Overvoltage Protection
http://onsemi.com
10
120 130
NCP9003
TYPICAL OPERATING WAVEFORMS
Vout
Inductor
Current
Conditions: Vbat = 3.6 V, Lout = 22 mH, 5 LED, Iout = 15 mA
Figure 20. Typical Power Up Response
Vload
Inductor
Current
Conditions: Vbat = 3.6 V, Lout = 22 mH, 5 LED, Iout = 15 mA
Figure 21. Typical Start−Up Inductor Current and Output Voltage
http://onsemi.com
11
NCP9003
TYPICAL OPERATING WAVEFORMS
Inductor
Current
Conditions: Vbat = 3.6 V, Lout = 22 mH, 5 LED, Iout = 15 mA
Figure 22. Typical Inductor Current
Vload Ripple
50 mV/div
Inductor
Current
Conditions: Vbat = 3.6 V, Lout = 22 mH, 5 LED, Iout = 15 mA
Figure 23. Typical Output Load Voltage Ripple
http://onsemi.com
12
NCP9003
TYPICAL OPERATING WAVEFORMS
Output Voltage
Inductor Current
Test Conditions: L = 22 mH, Iout = 15 mA, Vbat = 3.6 V, Ambient Temperature
Figure 24. Typical Output Peak Voltage
92.00
EFFICIENCY (%)
90.00
ESR = 0.3 W
88.00
86.00
84.00
ESR = 1.3 W
82.00
80.00
78.00
3
3.5
4
4.5
5
5.5
Vbat (V)
NCP9003: Efficiency = f(ESR) @ 5 LED, ILed = 20 mA
Figure 25. Efficiency as a Function of Vbat and Inductor ESR
http://onsemi.com
13
NCP9003
NOISE (mV/SQR/Hz)
10.00
1.00
0.10
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 26. Noise Returned to the Battery
Test Conditions: Vbat = 3.6 V, Iout = 20 mA, string of 3 LED (OSRAM LWT67C)
Figure 27. Relative EMI Over 100 kHz − 30 MHz Bandwidth
http://onsemi.com
14
1000
NCP9003
TYPICAL APPLICATIONS CIRCUITS
Standard Feedback
The standard feedback provides a constant current to the
LED, independently of the Vbat supply and number of LED
associated in series. Figure 28 depicts a typical application
to supply 13 mA to the load.
Vbat
Vbat
U1
4
EN
Vbat
C1
5
4.7 mF
L1
22 mH
GND
2
3
GND
GND
D1
Vout 1
FB
MBR0530
NCP9003
R1
D6
C2
1.0 mF
D5
D4
D3
D2
GND
15 W
GND
LWT67C LWT67C LWT67C LWT67C LWT67C
Figure 28. Basic DC Current Mode Operation with Analog Feedback
PWM Operation
start and stop the converter, yielding high transients . These
transients might generate spikes difficult to filter out in the
rest of the application, a situation not recommended. The
output current depends upon the duty cycle of the signal
presented to the node Pin 3: this is very similar to the digital
control discussed in Figure 31.
The average mode yields a noise free operation since the
converter operates continuously, together with a very good
dimming function. The cost is an extra resistor and one
extra capacitor, both being low cost parts.
The analog feedback Pin 3 provides a way to dim the
LED by means of an external PWM signal as depicted in
Figure 29. By optimizing the internal high impedance
presented by the FB pin, one can set up a simple R/C
network to accommodate such a dimming function. Two
modes of operation can be considered:
• Pulsed mode, with no filtering
• Averaged mode with filtering capacitor
Although the pulsed mode will provide a good dimming
function, from a human eye standpoint, it will continuously
http://onsemi.com
15
NCP9003
Vbat
Vbat
U1
4
EN
Vbat
C1
5
4.7 mF
L1
22 mH
Average Network
PWM
R2
R3
150 k
10 k
C3
100 nF
2
GND
3
GND
D1
Vout 1
FB
GND
MBR0530
NCP9003
C2
1.0 mF
R4
5.6 k
GND
GND
R1
D6
D5
D4
D3
D2
GND
10 W
NOTE: RC filter R2 and C3 is optional (see text)
LWT67C LWT67C LWT67C LWT67C LWT67C
Sense Resistor
Figure 29. Basic DC Current Mode Operation with PWM Control
value, preferably well below 1.0 MW. Consequently, let R2 =
150 k, R3 = 10 k and R4 = 5.6 k. On the other hand, the
feedback delay to control the luminosity of the LED shall be
acceptable by the user, 10 ms or less being a good
compromise. The time constant can now be calculated based
on a 400 mV offset voltage at the C3/R2/R3 node to force
zero current to the LED. Assuming the PWM signal comes
from a standard gate powered by a 3.0 V supply, running at
10 kHz, then a full dimming of the LED can be achieved with
a 95% span of the Duty Cycle signal. Figure 30 depicts the
behavior under such PWM analog mode.
To implement such a function, let consider the feedback
input as an operational amplifier with a high impedance
input (reference schematic Figure 29). The analog loop
will keep going to balance the current flowing through the
sense resistor R1 until the feedback voltage is 200 mV. An
extra resistor (R4) isolates the FB node from low resistance
to ground, making possible to add an external voltage to
this pin.
The time constant R2/C3 generates the voltage across C3,
added to the node Pin 1, while R2/R3/R4/R1/C3 create the
discharge time constant. In order to minimize the pick up
noise at FB node, the resistors shall have relative medium
PWM
VFB
VPWM
Figure 30. Operation with Analog PWM, f = 10 kHz, DC = 25%
http://onsemi.com
16
NCP9003
Digital Control
Cycle, but care must be observed as the DC/DC converter
is continuously pulsed ON/OFF and noise are likely to be
generated.
Due to the EN pin, a digitally controlled luminosity can
be implemented by providing a PWM signal to this pin (see
Figure 31). The output current depends upon the Duty
Vbat
U1
4
Pulse
EN
Vbat
C1
5
L1
22 mH
GND
2
3
GND
4.7 mF
GND
D1
Vout 1
FB
Vload
MBR0530
NCP9003
R1
GND
22 W
D6
C2
1.0 mF
D5
D4
D3
D2
GND
LWT67C LWT67C LWT67C LWT67C LWT67C
NOTE: Pulse width and frequency depends upon the application constraints.
Figure 31. Typical Semi−Pulsed Mode of Operation
The PWM operation, using the EN pin as a digital
control, is depicted in Figures 32 and 33. The tests have
been carried out at room temperature with Vbat = 3.60 V,
L = 22 mH, five LEDs in series, RFB = 22 W.
PWM
Vload
VFB
VPWM
Figure 32. Operation @ PWM = 10 kHz, DC = 10%
http://onsemi.com
17
NCP9003
PWM
Vload
VFB
PWR CLK
Figure 33. Operation @ PWM = 10 kHz, DC = 25%
PWM
Vload
PWR CLK
Figure 34. Magnified View of Operation @ PWM = 10 kHz, DC = 25%
http://onsemi.com
18
NCP9003
NCP9003 Iout = f(PWM) @ f = 10 kHz
10.00
9.00
8.00
Digital EN
Iout (mA)
7.00
Analog PWM
6.00
5.00
4.00
3.00
2.00
1.00
0.00
0
20
40
60
80
100
120
DC (%)
Figure 35. Output Current as a Function of the Operating Condition
Table 1. Recommended Passive Parts
Part
Manufacturer
Description
Part Number
Ceramic Capacitor 1.0 mF/16 V
MURATA
GRM42 − X7R
GRM42−6X7R−105K16
Ceramic Capacitor 1.0 mF/25 V
MURATA
GRM42 – X5R
GRM
Ceramic Capacitor 4.7 mF/6.3 V
MURATA
GRM40 – X5R
GRM40−X5R−475K6.3
Inductor 22 mH
CoilCraft
1008PS − Shielded
1008PS−223MC
Inductor 22 mH
CoilCraft
Power Wafer
LPQ4812−223KXC
Inductor 22 mH
WURTH
Power Choke
744031220
Inductor 22 mH
TDK
Power Inductor
VLP4614T−220MR40
http://onsemi.com
19
NCP9003
Typical LEDs Load Mapping
Since the output power is voltage battery limited (see
Figure 5), one shall arrange the LED to cope with a specific
need. In particular, since the power cannot extend 600 mW
under realistic battery supply, powering ten LED can be
achieved by a series/parallel combination as depicted in
Figure 36.
50 mA
75 mA
D1
LED
D5
LED
D2
LED
D6
LED
D3
LED
D7
LED
D4
LED
D8
LED
7.0 V (Typ.)
Load
14 V (Typ.)
Load
D1
LED
D3
LED
D5
LED
D7
LED
D9
LED
D2
LED
D4
LED
D6
LED
D8
LED
D10
LED
Sense
Resistor
R1
2.7 W
GND
60 mA
Sense
Resistor
R1
3.9 W
Load
10.5 V (Typ.)
GND
Test conditions: Vbat = 3.6 V
Lout = 22 mH
Cout = 1.0 mF
D1
LED
D4
LED
D7
LED
D10
LED
D13
LED
D2
LED
D5
LED
D8
LED
D11
LED
D14
LED
D3
LED
D6
LED
D9
LED
D12
LED
D15
LED
Sense
Resistor
R1
3.3 W
GND
Figure 36. Examples of Possible LED Arrangements
http://onsemi.com
20
NCP9003
Vbat
J1
VBAT
C1
GND
J2
GROUND
1 mF/10 V
JP1
Isense
GND
C3
Vbat
GND
U1
EN
4
EN
2
GND
5
Vout
1
ENABLE
GND
TP2
FB
GND
FB
3
FB
TP3
Vout
D1
Vout
TP4
VSW
Z1
GND
GND
51R
GND
LW E67C
LW E67C
LW E67C
LW E67C
D2
D3
D4
D5
JP3
JUMP_6
Figure 37. NCP9003 Demo Board Schematic Diagram
http://onsemi.com
21
1
JP2
JUMP_6
2
1
2
Note: Use Jumper JP2 to JP3 to adjust the number of LED in the operating string
C2
MBR0530
NCP9003
R1
Iout
1 mF/25 V
Vbat
22 mH
3
2
1
1 mF/6.3 V
L1
S1
NCP9003
PACKAGE DIMENSIONS
TSOP−5
SN SUFFIX
CASE 483−02
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
D
S
5
4
1
2
L
A
3
B
J
C
0.05 (0.002)
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
2.90
3.10 0.1142 0.1220
B
1.30
1.70 0.0512 0.0669
C
0.90
1.10 0.0354 0.0433
D
0.25
0.50 0.0098 0.0197
G
0.85
1.05 0.0335 0.0413
H 0.013 0.100 0.0005 0.0040
J
0.10
0.26 0.0040 0.0102
K
0.20
0.60 0.0079 0.0236
L
1.25
1.55 0.0493 0.0610
M
0_
10 _
0_
10 _
S
2.50
3.00 0.0985 0.1181
G
H
M
K
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
22
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP9003/D