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NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
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ISL6532C
DATASHEET
FN9121
Rev 2.00
Jul 2004
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
The ISL6532C provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller
and integrated LDO to supply VDDQ with high current during
S0/S1 states and standby current during S3 state. During
S0/S1 state, a fully integrated sink-source regulator
generates an accurate (VDDQ/2) high current VTT voltage
without the need for a negative supply. A buffered version of
the VDDQ/2 reference is provided as VREF. An LDO
controller is also integrated for AGP core voltage regulation.
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltagemode control with fast transient response. Both the switching
regulator and standby LDO provide a maximum static
regulation tolerance of 2% over line, load, and temperature
ranges. The output is user-adjustable by means of external
resistors down to 0.8V.
Switching memory core output between the PWM regulator
and the standby LDO during state transitions is
accomplished smoothly via the internal ACPI control
circuitry. The NCH signal provides synchronized switching of
a backfeed blocking switch during the transitions eliminating
the need to route 5V Dual to the memory supply.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the PGOOD signal
indicates VTT is within spec and operational.
Features
• Generates 3 Regulated Voltages
- Synchronous Buck PWM Controller with Standby LDO
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference.
- Glitch-free Transitions During State Changes
- LDO Regulator for 1.5V Video and Core voltage
• ACPI compliant sleep state control
• Integrated VREF Buffer
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
- All Outputs: 2% Over Temperature
• 5V or 3.3V Down Conversion
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Over-voltage Monitoring on All Outputs
• OCP on the Switching Regulator and VTT
• Integrated Thermal Shutdown Protection
• QFN Package Option
- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad
Flat No Leads - Product Outline
- QFN Near Chip Scale Package Footprint; Improves
PCB Efficiency, Thinner in Profile
Each output is monitored for under and over-voltage events.
The switching regulator has over current protection. Thermal
shutdown is integrated.
• Pb-free available
Pinout
Applications
• Single and Dual Channel DDR Memory Power Systems in
ACPI compliant PCs
• Graphics cards - GPU and memory supplies
NCH
S3#
S5#
P12V
UGATE
LGATE
GNDP
ISL6532C (QFN) TOP VIEW
28 27 26 25 24 23 22
GNDP 1
21 PGOOD
• ASIC power supplies
5VSBY 2
20 PHASE
• Embedded processor and I/O supplies
GNDQ 3
19 DRIVE2
• DSP supplies
GNDQ 4
18 FB2
VTT 5
17 GNDA
VTT 6
16 COMP
VDDQ 7
15 FB
FN9121 Rev 2.00
Jul 2004
VREF_IN
VREF_OUT
OCSET
10 11 12 13 14
P5VSBY
VDDQ
9
VTTSNS
VDDQ
8
Ordering Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG. DWG. #
ISL6532CCR
0 to 70
28 Ld 6x6 QFN L28.6x6
ISL6532CCRZ
(See Note)
0 to 70
28 Ld 6x6 QFN L28.6x6
(Pb-free)
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which
is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
Page 1 of 16
P5VSBY
S3#
VDDQ S3
REGULATOR
+
-
S5#
ISL6532C
FN9121 Rev 2.00
Jul 2004
Block Diagram
5VSBY
VOLTAGE
REFERENCE
0.800V
0.680V (-15%)
VDDQ(3)
5V
0.920V (+15%)
12VCC
POR
VTTSNS
+
VTT
- REG
+
VTT(2)
S3
GNDQ
S0
DISABLE
{
S0/S3
SLEEP,
SOFT-START,
PGOOD,
AND FAULT
LOGIC
+
-
VREF_IN
{
RL
OSCILLATOR
+
FB2
UV/OV3
NCH
UV/OV
PWM ENABLE
12V
POR
PWM
P12V
PWM
LOGIC
UGATE
250kHz
+
+
-
Page 2 of 16
VREF_OUT
+
COMP
EA1
-
GNDA
DRIVE2
650 OUTPUT
IMPEDANCE
+
SOFT-START
RU
EA2
UV/OV1
PHASE
+
-
OC
COMP
20A
LGATE
UV/OV2
PGOOD
FB
COMP
OCSET
GNDP
ISL6532C
Simplified Power System Diagram
12V
5VSBY
5V
ISL6532C
NCH
SLEEP
STATE
LOGIC
SLP_S3
SLP_S5
Q1
VDDQ
PWM
CONTROLLER
+
Q2
5VSBY/3V3SBY
STANDBY
LDO
VDDQ
VREF
LINEAR
CONTROLLER
Q3
VTT
REGULATOR
VAGP
VTT
+
+
Typical Application - 5V or 3.3V Input
5VSBY
+12V
+3.3V
+5V or +3.3V
P12V
P5VSBY
5VSBY
CBP
RNCH
PGOOD
VDDQ
S3#
SLP_S3
NCH
Q4
S5#
SLP_S5
VREF_OUT
VREF
ROCSET
VREF_IN
UGATE
+
ISL6532C
LGATE
VTT
VDDQ
VDDQ
VDDQ
VTTSNS
GNDQ
GNDQ
+
VDDQ
Q3
CVTT_OUT
CIN
Q1
PHASE
VTT
VTT
+
OCSET
VDDQ
LOUT
2.5V
+
Q2
CVDDQ_OUT
DRIVE2
FB
COMP
VAGP
1.5V
FB2
+
GNDP
GNDA
COUT2
FN9121 Rev 2.00
Jul 2004
Page 3 of 16
ISL6532C
Typical Application - Input From 5V Dual
5VSBY
+12V
5V Dual
P12V
P5VSBY
CBP
5VSBY
+3.3V
PGOOD
VDDQ
S3#
SLP_S3
NCH
S5#
SLP_S5
VREF_OUT
VREF
+
OCSET
ROCSET
VREF_IN
UGATE
Q1
PHASE
VTT
VTT
ISL6532C
LGATE
VTT
+
VDDQ
VDDQ
VDDQ
CVTT_OUT
VDDQ
VDDQ
LOUT
2.5V
+
Q2
CVDDQ_OUT
GNDQ
GNDQ
VTTSNS
Q3
CIN
DRIVE2
FB
VAGP
COMP
1.5V
FB2
+
GNDP
GNDA
COUT2
FN9121 Rev 2.00
Jul 2004
Page 4 of 16
ISL6532C
Absolute Maximum Ratings
Thermal Information
5VSBY, P5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14V
UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Thermal Resistance (Typical, Notes 1, 2)
Recommended Operating Conditions
JA (oC/W) JC (oC/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
5
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V 10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V 10%
Supply Voltage on P5VSBY. . . . . . . . . . . . . . . . . . . . . . . +5V 10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current
ICC_S0
S3# & S5# HIGH, UGATE/LGATE Open
3.00
5.25
7.25
mA
ICC_S3
S3# LOW, S5# HIGH, UGATE/LGATE
Open
3.50
-
4.75
mA
ICC_S5
S5# LOW, S3# Don’t Care,
UGATE/LGATE Open
300
-
800
A
Rising 5VSBY POR Threshold
4.00
-
4.35
V
Falling 5VSBY POR Threshold
3.60
-
3.95
V
Rising P12V POR Threshold
10.0
-
10.5
V
Falling P12V POR Threshold
8.80
-
9.75
V
POWER-ON RESET
OSCILLATOR AND SOFT-START
PWM Frequency
fOSC
220
250
280
kHz
Ramp Amplitude
VOSC
-
1.5
-
V
Error Amp Reset Time
tRESET
Mechanical Off/S5 to S0
6.5
-
9.5
ms
tSS
Mechanical Off/S5 to S0
6.5
-
9.5
ms
-
0.800
-
V
-2.0
-
+2.0
%
-
80
-
dB
GBWP
15
-
-
MHz
SR
-
6
-
V/s
S3# Transition Level
VS3
-
1.5
-
V
S5# Transition Level
VS5
-
1.5
-
V
VDDQ Soft-Start Interval
REFERENCE VOLTAGE
Reference Voltage
VREF
System Accuracy
PWM CONTROLLER ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
Slew Rate
Guaranteed By Design
STATE LOGIC
FN9121 Rev 2.00
Jul 2004
Page 5 of 16
ISL6532C
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
IGATE
-
-0.8
-
A
UGATE and LGATE Sink
IGATE
-
0.8
-
A
-
-
6
mA
9.0
9.5
10.0
V
P5VSBY = 5.0V
-
-
650
mA
P5VSBY = 3.3V
-
-
550
mA
NCH BACKFEED CONTROL
NCH Current Sink
INCH
NCH Trip Level
VNCH
NCH = 0.8V
VDDQ STANDBY LDO
Output Drive Current
VTT REGULATOR
Upper Divider Impedance
RU
-
2.5
-
k
Lower Divider Impedance
RL
-
2.5
-
k
IVREF_OUT
-
-
2
mA
-3
-
3
A
-3.3
-
3.3
A
-
80
-
dB
GBWP
15
-
-
MHz
SR
-
6
-
V/s
DRIVE2 High Output Voltage
10.0
10.2
-
V
DRIVE2 Low Output Voltage
-
0.16
0.40
V
DRIVE2 High Output Source Current
-.5
-1.4
-
mA
DRIVE2 Low Output Sink Current
.85
1.3
-
mA
VREF_OUT Buffer Source Current
Maximum VTT Load Current
IVTT_MAX
Periodic load applied with 30% duty cycle
and 10ms period using ISL6532CEVAL1
evaluation board (see Application Note
AN1056)
VTT Over Current Trip
ITRIP_VTT
By Design
LINEAR REGULATOR
DC GAIN
Gain Bandwidth Product
Slew Rate
Guaranteed By Design
PGOOD
PGOOD Rising Threshold
VVTTSNS/VVDDQ S0
-
57.5
-
%
PGOOD Falling Threshold
VVTTSNS/VVDDQ S0
-
45.0
-
%
17
20
22
A
PROTECTION
OCSET Current Source
IOCSET
VDDQ OV Level
VFB/VREF
S0
-
115
-
%
VDDQ UV Level
VFB/VREF
S0
-
85
-
%
Linear Regulator OV Level
VFB2/VREF
S0
-
115
-
%
Linear Regulator UV Level
VFB2/VREF
S0
-
85
-
%
By Design
-
140
-
°C
Thermal Shutdown Limit
FN9121 Rev 2.00
Jul 2004
TSD
Page 6 of 16
ISL6532C
Functional Pin Description
5VSBY (Pin 2)
5VSBY is the bias supply of the ISL6532C. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6532C enters a reduced
power mode and draws less than 1mA (ICC_S5) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1F capacitor.
P12V (Pin 25)
P12V provides the gate drive to the switching MOSFETs of the
PWM power stage. The VTT regulation circuit and the Linear
Driver are also powered by P12V. P12V is not required except
during S0/S1/S2 operation. P12V is typically connected to the
+12V rail of an ATX power supply.
The FB pin is also monitored for under and over-voltage
events.
PHASE (Pin 20)
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET for
over-current protection.
OCSET (Pin 12)
Connect a resistor (ROCSET) from this pin to the drain of the
upper MOSFET. ROCSET, an internal 20A current source
(IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set
the converter over-current (OC) trip point according to the
following equation:
I OCSET xR OCSET
I PEAK = -----------------------------------------------r DS ON
5VSBY (Pin 11)
An over-current trip cycles the soft-start function.
This pin provides the VDDQ output power during S3 sleep
state. The regulator is capable of providing standby VDDQ
power from either the 5VSBY or 3.3VSBY rail. It is
recommended that the 5VSBY rail be used as the output
current handling capability of the standby LDO is higher than
with the 3.3VSBY rail.
VDDQ (Pins 7, 8, 9)
The VDDQ pins should be connected externally together to the
regulated VDDQ output. During S0/S1 states, the VDDQ pins
serve as inputs to the VTT regulator and to the VTT Reference
precision divider. During S3 state, the VDDQ pins serve as an
output from the integrated standby LDO.
GND, GNDA, GNDP, GNDQ (Pins 1, 3, 4, 17, 29)
VTT (Pins 5, 6)
The GND terminals of the ISL6532C provide the return path for
the VTT LDO, standby LDO and switching MOSFET gate
drivers. High ground currents are conducted directly through
the exposed paddle of the QFN package which must be
electrically connected to the ground plane through a path as
low in inductance as possible. GNDA is the Analog ground pin,
GNDQ is the return for the VTT regulator and GNDP is the
return for the upper and lower gate drives.
The VTT pins should be connect externally together. During
S0/S1 states, the VTT pins serve as the outputs of the VTT
linear regulator. During S3 state, the VTT regulator is disabled.
UGATE (Pin 26)
VREF_OUT (Pin 13)
UGATE drives the upper (control) FET of the VDDQ
synchronous buck switching regulator. UGATE is driven
between GND and P12V.
VREF_OUT is a buffered version of VTT and also acts as the
reference voltage for the VTT linear regulator. It is
recommended that a minimum capacitance of 0.1F is
connected between VDDQ and VREF_OUT and also between
VREF_OUT and ground for proper operation.
LGATE (Pin 27)
LGATE drives the lower (synchronous) FET of the VDDQ
synchronous buck switching regulator. LGATE is driven
between GND and P12V.
FB (Pin 15) and COMP (Pin 16)
The VDDQ switching regulator employs a single voltage control
loop. FB is the negative input to the voltage loop error
amplifier. The positive input of the error amplifier is connected
to a precision 0.8V reference and the output of the error
amplifier is connected to the COMP pin. The VDDQ output
voltage is set by an external resistor divider connected to FB.
With a properly selected divider, VDDQ can be set to any
voltage between the power rail (reduced by converter losses)
and the 0.8V reference. Loop compensation is achieved by
connecting an AC network across COMP and FB.
FN9121 Rev 2.00
Jul 2004
VTTSNS (Pin 10)
VTTSNS is used as the feedback for control of the VTT linear
regulator. Connect this pin to the VTT output at the physical
point of desired regulation.
VREF_IN (Pin 14)
A capacitor, CSS, connected between VREF_IN and ground is
required. This capacitor and the parallel combination of the
Upper and Lower Divider Impedance (RU||RL), sets the time
constant for the start up ramp when transitioning from S3 to
S0/S1/S2.
The minimum value for CSS can be found through the following
equation:
C VTTOUT V DDQ
C SS -----------------------------------------------10 2A R U R L
The calculated capacitance, CSS, will charge the output
capacitor bank on the VTT rail in a controlled manner without
reaching the current limit of the VTT LDO.
Page 7 of 16
ISL6532C
NCH (Pin 22)
NCH is an open-drain output that controls the MOSFET
blocking backfeed from VDDQ to the input rail during sleep
states. A 2k or larger resistor is to be tied between the 12V
rail and the NCH pin. Until the voltage on the NCH pin reaches
the NCH trip level, the PWM is disabled.
If NCH is not actively utilized, it still must be tied to the 12V rail
through a resistor. For systems using 5V dual as the input to
the switching regulator, a time constant, in the form of a
capacitor, can be added to the NCH pad to delay start of the
PWM switcher until the 5V dual has switched from 5VSBY to
5VATX.
PGOOD (Pin 21)
Power Good is an open-drain logic output that changes to a
logic low if any of the three regulators are out of regulation in
S0/S1/S2 state. PGOOD will always be low in any state other
than S0/S1/S2.
SLP_S5# (Pin 24)
This pin accepts the SLP_S5# sleep state signal.
SLP_S3# (Pin 23)
This pin accepts the SLP_S3# sleep state signal.
FB2 (Pin 18)
Connect the output of the external linear regulator to this pin
through a properly sized resistor divider. The voltage at this pin
is regulated to 0.8V. This pin is monitored for under and overvoltage events.
DRIVE2 (Pin 19)
Connect this pin to the gate terminal of an external N-Channel
MOSFET transistor. This pin provides the gate voltage for the
linear regulator pass transistor. It also provides a means of
compensating the error amplifier for applications requiring the
transient response of the linear regulator to be optimized.
Functional Description
Overview
The ISL6532C provides complete control, drive, protection and
ACPI compliance for a regulator powering DDR memory
systems. It is primarily designed for computer applications
powered from an ATX power supply. A 250kHz Synchronous
Buck Regulator with a precision 0.8V reference provides the
proper Core voltage to the system memory of the computer. An
internal LDO regulator with the ability to both sink and source
current and an externally available buffered reference that
tracks the VDDQ output by 50% provides the VTT termination
voltage. The ISL6532C also features an LDO regulator for
1.5V AGP Video and Core voltage.
ACPI compliance is realized through the SLP_S3 and SLP_S5
sleep signals and through monitoring of the 12V ATX bus.
Initialization
FN9121 Rev 2.00
Jul 2004
The ISL6532C automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors the
bias voltage at the 5VSBY and P12V pins. The POR function
initiates soft-start operation after the bias supply voltages
exceed their POR thresholds.
ACPI State Transitions
Cold Start (S4/S5 to S0 Transition)
At the onset of a mechanical start, the ISL6532C receives its
bias voltage from the 5V Standby bus (5VSBY). As soon as the
SLP_S3 and SLP_S5 have transitioned HIGH, the ISL6532C
starts an internal counter. Following a cold start or any
subsequent S4/S5 state, state transitions are ignored until the
system enters S0/S1. None of the regulators will begin the soft
start procedure until the 5V Standby bus has exceeded POR,
the 12V bus has exceeded POR and VNCH has exceeded the
trip level.
Once all of these conditions are met, the PWM error amplifier
will first be reset by internally shorting the COMP pin to the FB
pin. This reset lasts for 2048 clock cycles, which is typically
8.2ms (one clock cycle = 1/fOSC). The digital soft start
sequence will then begin.
The PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s). The
internal VTT LDO will also soft start through the reference that
tracks the output of the PWM regulator. The reference for the
AGP LDO controller will rise relative to the soft start reference.
The soft start lasts for 2048 clock cycles, which is typically
8.2ms. This method provides a rapid and controlled output
voltage rise.
S3
S5
12VATX 2V/DIV
5VSBY
1V/DIV
VDDQ
500mV/DIV
VAGP
500mV/DIV
VTT
500mV/DIV
PGOOD
5V/DIV
2048 CLOCK
CYCLES
12V POR
2048 CLOCK
CYCLES
SOFT START ENDS
SOFT START
INITIATES PGOOD COMPARATOR
ENABLED
FIGURE 1. TYPICAL COLD START
Page 8 of 16
ISL6532C
Figure 1 shows the soft start sequence for a typical cold start.
Due to the soft start capacitance, CSS, on the VREF_IN pin,
the S5 to S0 transition profile of the VTT rail will have a more
rounded features at the start and end of the soft start whereas
the VDDQ profile has distinct starting and ending points to the
ramp up.
By directly monitoring 12VATX and the SLP_S3 and SLP_S5
signals the ISL6532C can achieve PGOOD status significantly
faster than other devices that depend on
Latched_Backfeed_Cut for timing.
S3
S5
12VATX 2V/DIV
VAGP
500mV/DIV
VTT_FLOAT
VTT
500mV/DIV
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6532C will disable the VTT linear regulator and the AGP
LDO controller. The VDDQ standby regulator will be enabled
and the VDDQ switching regulator will be disabled. NCH is
pulled low to disable the backfeed blocking MOSFET. PGOOD
will also transition LOW. When VTT is disabled, the internal
reference for the VTT regulator is internally shorted to the VTT
rail. This allows the VTT rail to float. When floating, the voltage
on the VTT rail will depend on the leakage characteristics of the
memory and MCH I/O pins. It is important to note that the VTT
rail may not bleed down to 0V.
The VDDQ rail will be supported in the S3 state through the
standby VDDQ LDO. When S3 transitions LOW, the Standby
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut off
time will range between 4 and 8s. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail through
the P5VSBY pin. It is recommended that the 5V Standby rail
be used as the current delivery capability of the LDO is greater.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the ISL6532C
will enable the VDDQ switching regulator, disable the VDDQ
standby regulator, enable the VTT LDO and force the NCH pin
to a high impedance state turning on the blocking MOSFET.
The AGP LDO goes through a 2048 clock cycle soft-start. The
internal short between the VTT reference and the VTT rail is
released. Upon release of the short, the capacitor on VREF_IN
is then charged up through the internal resistor divider
network. The VTT output will follow this capacitor charge up,
and acting as the S3 to S0 transition soft start for the VTT rail.
The PGOOD comparator is enabled only after 2048 clock
cycles, or typically 8.2ms, have passed following the S3
transition to a HIGH state. Figure 2 illustrates a typical state
transition from S3 to S0. It should be noted that the soft start
profile of the VTT LDO output will vary according to the value of
the capacitor on the VREF_IN pin.
FN9121 Rev 2.00
Jul 2004
VDDQ
500mV/DIV
PGOOD
5V/DIV
2048 CLOCK
CYCLES
12V POR
PGOOD COMPARATOR
ENABLED
FIGURE 2. TYPICAL S3 TO S0 STATE TRANSITION
Active to Shutdown (S0 to S5 Transition)
When the system transitions from active, S0, state to shutdown,
S4/S5, state, the ISL6532C IC disables all regulators and forces
the PGOOD pin and the NCH pin LOW.
VDDQ Over Current Protection (S0 State)
The over-current function protects the switching converter from
a shorted output by using the upper MOSFET on-resistance,
rDS(ON), to monitor the current. This method enhances the
converter’s efficiency and reduces cost by eliminating a current
sensing resistor.
The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (ROCSET)
programs the over-current trip level (see Typical Application
diagrams on pages 3 and 4). An internal 20A (typical) current
sink develops a voltage across ROCSET that is referenced to
the converter input voltage. When the voltage across the upper
MOSFET (also referenced to the converter input voltage)
exceeds the voltage across ROCSET, the over-current function
initiates a soft-start sequence. The initiation of soft start will
affect all regulators. The VTT regulator is directly affected as it
receives it’s reference from VDDQ. The AGP LDO will also be
soft started, and as such, the AGP LDO voltage will be
disabled while the VDDQ regulator is disabled.
Figure 3 illustrates the protection feature responding to an over
current event. At time T0, an over current condition is sensed
across the upper MOSFET. As a result, the regulator is quickly
shutdown and the internal soft-start function begins producing
soft-start ramps. The delay interval seen by the output is
equivalent to three soft-start cycles. The fourth internal softstart cycle initiates a normal soft-start ramp of the output, at
time T1. The output is brought back into regulation by time T2,
as long as the over current event has cleared.
Page 9 of 16
ISL6532C
Had the cause of the over current still been present after the
delay interval, the over current condition would be sensed and
the regulator would be shut down again for another delay
interval of three soft start cycles. The resulting hiccup mode
style of protection would continue to repeat indefinitely.
The internal VTT LDO is protected from fault conditions
through a 3.3A current limit. This current limit protects the
ISL6532C if the LDO is sinking or sourcing current. During an
overcurrent event on the VTT LDO, only the VTT LDO is
disabled. Once the over current condition on the VTT rail is
removed, VTT will recover.
Over/Under Voltage Protection
VDDQ
All three regulators are protected from faults through internal
Over/Under voltage detection circuitry. If the any rail falls below
85% of the targeted voltage, then an undervoltage event is
tripped. An under voltage will disable all three regulators for a
period of 3 soft-start cycles, after which a normal soft-start is
initiated. If the output is still under 85% of target, the regulators
will continue to be disabled and soft-started in a hiccup mode
until the fault is cleared. This protection feature works much the
same as the VDDQ PWM over current protection works. See
Figure 3.
VAGP
VTT
500mV/DIV
INTERNAL SOFT-START FUNCTION
If the any rail exceeds 115% of the targeted voltage, then all
three outputs are immediately disabled. The ISL6532C will not
re-enable the outputs until either the bias voltage is toggled in
order to initiate a POR or the S5 signal is forced LOW and then
back to HIGH.
DELAY INTERVAL
Thermal Protection (S0/S3 State)
T0
TIME
T1
T2
FIGURE 3. VDDQ and VTT OVER CURRENT PROTECTION
AND VTT/VAGP LDO UNDER VOLTAGE
PROTECTION RESPONSES
The over-current function will trip at a peak inductor current
(IPEAK) determined by:
I OCSET x R OCSET
I PEAK = ---------------------------------------------------r DS ON
where IOCSET is the internal OCSET current source (20A
typical). The OC trip point varies mainly due to the MOSFET
rDS(ON) variations. To avoid over-current tripping in the normal
operating load range, find the ROCSET resistor from the
equation above with:
1. The maximum rDS(ON) at the highest junction temperature.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK for:
I
I PEAK > I OUT MAX + ---------- , whereI is
2
the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
ROCSET to smooth the voltage across ROCSET in the
presence of switching noise on the input voltage.
VTT Over Current Protection
FN9121 Rev 2.00
Jul 2004
If the ISL6532C IC junction temperature reaches a nominal
temperature of 140oC, all regulators will be disabled. The
ISL6532C will not re-enable the outputs until the junction
temperature drops below 110oC and either the bias voltage is
toggled in order to initiate a POR or the SLP_S5 signal is
forced LOW and then back to HIGH.
Shoot-Through Protection
A shoot-through condition occurs when both the upper and
lower MOSFETs are turned on simultaneously, effectively
shorting the input voltage to ground. To protect from a shootthrough condition, the ISL6532C incorporates specialized
circuitry which insures that complementary MOSFETs are not
ON simultaneously.
The adaptive shoot-through protection utilized by the VDDQ
regulator looks at the lower gate drive pin, LGATE, and the
upper gate drive pin, UGATE, to determine whether a
MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective MOSFET
is defined as being OFF and the other MOSFET is allowed to
turned ON. This method allows the VDDQ regulator to both
source and sink current.
Since the voltage of the MOSFET gates are being measured to
determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing such
measures. Doing so may interfere with the shoot-through
protection.
Application Guidelines
Page 10 of 16
ISL6532C
Layout is very important in high frequency switching converter
design. With power devices switching efficiently at 250kHz, the
resulting current transitions from one device to another cause
voltage spikes across the interconnecting impedances and
parasitic circuit elements. These voltage spikes can degrade
efficiency, radiate noise into the circuit, and lead to device
over-voltage stress. Careful component layout and printed
circuit board design minimizes these voltage spikes.
12VATX
NCH
5VSBY
GNDP
Q1 LOUT
UGATE
VDDQ
PHASE
LGATE
COMP
C2
C1
R2
R1
FB
C3 R3
R4
VDDQ(3)
VDDQ
VTT(2)
VTT
COUT2
VIN_AGP
Q3
DRIVE2
GND PAD
COUT1
Q2
R5
FB2
R6
VAGP
COUT3
LOAD
FN9121 Rev 2.00
Jul 2004
CIN
CBP
LOAD
The switching components should be placed close to the
ISL6532C first. Minimize the length of the connections
between the input capacitors, CIN, and the power switches by
placing them nearby. Position both the ceramic and bulk input
capacitors as close to the upper MOSFET drain as possible.
Position the output inductor and output capacitors between the
upper and lower MOSFETs and the load.
5VSBY
P5VSBY
There are two sets of critical components in the ISL6532C
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are the
small signal components which connect to sensitive nodes or
supply critical bypass current and signal coupling.
In order to dissipate heat generated by the internal VTT LDO,
the ground pad, pin 29, should be connected to the internal
ground plane through at least four vias. This allows the heat to
move away from the IC and also ties the pad to the ground
plane through a low impedance path.
VIN_DDR
ISL6532C
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
A multi-layer printed circuit board is recommended. Figure 4
shows the connections of the critical components in the
converter. Note that capacitors CIN and COUT could each
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections with
vias to this layer. Dedicate another solid layer as a power
plane and break this plane into smaller islands of common
voltage levels. Keep the metal runs from the PHASE terminals
to the output inductor short. The power plane should support
the input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the phase
nodes. Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the GATE pins to the MOSFET
gates should be kept short and wide enough to easily handle
the 1A of drive current.
CBP
P12V
GNDP
LOAD
Layout Considerations
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB pin
with vias tied straight to the ground plane as required.
Feedback Compensation - PWM Buck Converter
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the PHASE node.
The PWM wave is smoothed by the output filter (LO and CO).
Page 11 of 16
ISL6532C
PWM
COMPARATOR
7. Estimate Phase Margin - Repeat if Necessary.
LO
-
VOSC
6. Check Gain against Error Amplifier’s Open-Loop Gain.
VIN
DRIVER
OSC
DRIVER
+
VDDQ
PHASE
Compensation Break Frequency Equations
CO
ESR
(PARASITIC)
ZFB
VE/A
ZIN
ERROR
AMP
REFERENCE
DETAILED COMPENSATION COMPONENTS
ZFB
C1
C2
VDDQ
ZIN
C3
R2
R3
R1
COMP
FB
+
R4
ISL6532C
REFERENCE
R
V DDQ = 0.8 1 + ------1-
R 4
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at FLC and a zero at FESR . The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage VOSC .
Modulator Break Frequency Equations
1
F LC = ------------------------------------------2 x L O x C O
1
F ESR = -------------------------------------------2 x ESR x C O
The compensation network consists of the error amplifier
(internal to the ISL6532C) and the impedance networks ZIN
and ZFB. The goal of the compensation network is to provide a
closed loop transfer function with the highest 0dB crossing
frequency (f0dB) and adequate phase margin. Phase margin is
the difference between the closed loop phase at f0dB and 180
degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R1 , R2 ,
R3 , C1 , C2 , and C3) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
FN9121 Rev 2.00
Jul 2004
1
F P1 = -------------------------------------------------------- C 1 x C 2
2 x R 2 x ----------------------
C1 + C2
1
F Z2 = ------------------------------------------------------2 x R 1 + R 3 x C 3
1
F P2 = -----------------------------------2 x R 3 x C 3
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the graph of
Figure 6 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
FZ1 FZ2
FP1
FP2
80
OPEN LOOP
ERROR AMP GAIN
60
GAIN (dB)
-
+
1
F Z1 = -----------------------------------2 x R 2 x C 2
40
20
20LOG
(R2/R1)
20LOG
(VIN/VOSC)
0
COMPENSATION
GAIN
MODULATOR
GAIN
-20
-40
-60
CLOSED LOOP
GAIN
FLC
10
100
1K
FESR
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Feedback Compensation - AGP LDO Controller
Figure 7 shows the AGP LDO power and control stage. This
LDO, which uses a MOSFET as the linear pass element,
requires feedback compensation to insure stability of the
system. The LDO requires compensation because of the
output impedance of the error amplifier.
To properly compensate the LDO system, a 100k 1% resistor
and a 680pF X5R ceramic capacitor, represented as R10 and
C25 in Figure 7, are used. This compensation will insure a
Page 12 of 16
ISL6532C
Output Capacitor Selection - PWM Buck Converter
ISL6532C
VDDQ
0.8V
REFERENCE
650
+
-
OUTPUT
IMPEDANCE
DRIVE2
C25
VAGP
R10
FB2
R8
R9
ESR
R
V AGP = 0.8 1 + ------8-
R 9
COUT
RLOAD
+
FIGURE 7. COMPENSATION AND OUTPUT VOLTAGE
SELECTION OF THE LINEAR
stable system with any MOSFET given the following
conditions:
= C OUT ESR 10s
R FB = R 8 = 249
Maximum bandwidth will be realized at full load while minimum
bandwidth will be realized at no load. Bandwidth at no load will
be maximized as becomes closer to 10s.
Output Voltage Selection
The output voltage of the VDDQ PWM converter can be
programmed to any level between VIN and the internal
reference, 0.8V. An external resistor divider is used to scale
the output voltage relative to the reference voltage and feed it
back to the inverting input of the error amplifier, see Figure 5.
However, since the value of R1 affects the values of the rest of
the compensation components, it is advisable to keep its value
less than 5k. Depending on the value chosen for R1, R4 can
be calculated based on the following equation:
R1 0.8V
R4 = ----------------------------------V DDQ – 0.8V
If the output voltage desired is 0.8V, simply route VDDQ back
to the FB pin through R1, but do not populate R4.
The output voltage for the internal VTT linear regulator is set
internal to the ISL6532C to track the VDDQ voltage by 50%.
There is no need for external programming resistors.
As with the VDDQ PWM regulator, the AGP linear regulator
output voltage is set by means of an external resistor divider as
shown in Figure 7. For stability concerns described earlier, the
recommended value of the feedback resistor, R8, is 249. The
voltage programming resistor, R9 can be calculated based on
the following equation:
R 8 0.8V
R 9 = ---------------------------------V AGP – 0.8V
Component Selection Guidelines
FN9121 Rev 2.00
Jul 2004
An output capacitor is required to filter the inductor current and
supply the load transient current. The filtering requirements are
a function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew rate
(di/dt) and the magnitude of the transient load current. These
requirements are generally met with a mix of capacitors and
careful layout.
DDR memory systems are capable of producing transient load
rates above 1A/ns. High frequency capacitors initially supply
the transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (Effective Series Resistance) and
voltage rating requirements rather than actual capacitance
requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Capacitor Selection - LDO Regulators
The output capacitors used in LDO regulators are used to
provide dynamic load current. The amount of capacitance and
type of capacitor should be chosen with this criteria in mind.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function of
the ripple current. The ripple voltage and current are
approximated by the following equations:
I =
VIN - VOUT
Fs x L
x
VOUT
VIN
VOUT = I x ESR
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce the
converter’s response time to a load transient.
Page 13 of 16
ISL6532C
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6532C will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the application
of load and the removal of load. The following equations give
the approximate response time interval for application and
removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
VOUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case response
time can be either at the application or removal of load. Be
sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.
Input Capacitor Selection - PWM Buck Converter
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors
for high frequency decoupling and bulk capacitors to supply
the current needed each time the upper MOSFET turns on.
Place the small ceramic capacitors physically close to the
MOSFETs and between the drain of upper MOSFET and the
source of lower MOSFET.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be at
least 1.25 times greater than the maximum input voltage, while
a voltage rating of 1.5 times is a conservative guideline. For
most cases, the RMS current rating requirement for the input
capacitor of a buck regulator is approximately 1/2 the DC load
current.
The maximum RMS current required by the regulator may be
closely approximated through the following equation:
I RMS
MAX
=
V OUT
V IN – V OUT V OUT 2
2
1
-------------- I OUT
+ ------ ----------------------------- --------------
V IN
V IN
12 L f s
MAX
For a through hole design, several electrolytic capacitors may
be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These capacitors
must be capable of handling the surge-current at power-up.
FN9121 Rev 2.00
Jul 2004
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection - PWM Buck Converter
The ISL6532C requires 2 N-Channel power MOSFETs for
switching power and a third MOSFET to block backfeed from
VDDQ to the Input in S3 Mode. These should be selected
based upon rDS(ON) , gate supply requirements, and thermal
management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design factors.
The power dissipation includes two loss components; conduction
loss and switching loss. The conduction losses are the largest
component of power dissipation for both the upper and the lower
MOSFETs. These losses are distributed between the two
MOSFETs according to duty factor. The switching losses seen
when sourcing current will be different from the switching losses
seen when sinking current. When sourcing current, the upper
MOSFET realizes most of the switching losses. The lower switch
realizes most of the switching losses when the converter is sinking
current (see the equations below). These equations assume linear
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the upper and lower MOSFET’s
body diode. The gate-charge losses are dissipated in part by the
ISL6532C and do not significantly heat the MOSFETs. However,
large gate-charge increases the switching interval, tSW which
increases the MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at high
ambient temperature by calculating the temperature rise according
to package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Approximate Losses while Sourcing current
2
1
P UPPER = Io r DS ON D + --- Io V IN t SW f s
2
PLOWER = Io2 x rDS(ON) x (1 - D)
Approximate Losses while Sinking current
PUPPER = Io2 x rDS(ON) x D
2
1
P LOWER = Io r DS ON 1 – D + --- Io V IN t SW f s
2
Where: D is the duty cycle = VOUT / VIN ,
tSW is the combined switch ON and OFF time, and
fs is the switching frequency.
MOSFET Selection - AGP LDO
The main criteria for selection of the linear regulator pass
transistor is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.
Page 14 of 16
ISL6532C
The power dissipated in the linear regulator is:
ISL6532C Application Circuit
P LINEAR I O V IN – V OUT
Figure 8 shows an application circuit utilizing the ISL6532C.
Detailed information on the circuit, including a complete Bill-ofMaterials and circuit board description, can be found in
Application Note AN1056.
where IO is the maximum output current and VOUT is the
nominal output voltage of the linear regulator.
VCC5
5VSBY
VCC12
+3.3V
C17,18
1F
C26
0.1F
VREF
SLP_S5
S5#
SLP_S3
S3#
5VSBY
PGOOD
P12V
PGOOD
VDDQ
+
C21
220F
R10
C23
220F
R8
249
VDDQ
Q2,4
C6-8
1800F
C9-12
22F
R4
1.74k
GNDQ
GNDQ
DRIVE2
+
100k
FB
FB2
+
C1-3
2200F
2.5V 15AMAX
VDDQ
VDDQ
VDDQ
VTTSNS
C25 680pF
1.5V
+
Q1,3
LGATE
R9
287
GNDA
VAGP
8.87k
L2
2.1H
VTT
VTT
GNDP
Q4
C4,5
1F
ISL6532C
GNDP
VDDQ
R7
1000pF
PHASE
C20 +
220F
VTT
1.25V
C22
UGATE
C19
0.47F
VDDQ
C24
1F
VREF_IN
L1
2.1H
NCH
OCSET
VREF_OUT
C27
0.1F
Q5
C16
1F
P5VSBY
R2
10.0k
R1
4.99k
COMP
C15
1000pF
C14
6.8nF
R3
19.1k
C13
56nF
R5
22.6
R6
825
FIGURE 8. DDR SDRAM AND AGP VOLTAGE REGULATOR USING THE ISL6532C
© Copyright Intersil Americas LLC 2003-2004. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9121 Rev 2.00
Jul 2004
Page 15 of 16
ISL6532C
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L28.6x6
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
A3
b
0.23
D
0.28
9
0.35
5, 8
6.00 BSC
D1
D2
9
0.20 REF
-
5.75 BSC
3.95
4.10
9
4.25
7, 8
E
6.00 BSC
-
E1
5.75 BSC
9
E2
3.95
e
4.10
4.25
7, 8
0.65 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
28
2
Nd
7
3
Ne
7
3
P
-
-
0.60
9
-
-
12
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN9121 Rev 2.00
Jul 2004
Page 16 of 16