April 1997 NDS351AN N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. 1.2A, 30 V. RDS(ON) = 0.25 Ω @ VGS = 4.5 V RDS(ON) = 0.16 Ω @ VGS = 10 V. Industry standard outline SOT-23 surface mount package using proprietary SuperSOTTM-3 design for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. Compact industry standard SOT-23 surface mount _________________________________________________________________________________ D S G Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous ID Maximum Drain Current - Continuous PD Maximum Power Dissipation (Note 1a) - Pulsed Units 30 V 20 V ± 1.2 A ± 10 (Note 1a) (Note 1b) TJ,TSTG NDS351AN Operating and Storage Temperature Range 0.5 W 0.46 -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W © 1997 Fairchild Semiconductor Corporation NDS351AN Rev. C Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 30 V TJ =125°C 1 µA 10 µA IGSSF Gate - Body Leakage, Forward VGS = 20 VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA 2 V ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(ON) Static Drain-Source On-Resistance VGS = 4.5 V, ID = 1.2 A 0.8 TJ =125°C 0.5 TJ =125°C VGS = 10 V, ID = 1.4 A 1.7 1.3 1.5 0.19 0.25 0.28 0.37 0.125 0.16 3.5 Ω ID(ON) On-State Drain Current VGS = 4.5 V, VDS = 5 V gFS Forward Transconductance VDS = 5 V, ID= 1.2 A, 1.8 A S VDS = 10 V, VGS = 0 V, f = 1.0 MHz 125 pF 100 pF 90 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS td(on) Turn - On Delay Time tr Turn - On Rise Time td(off) tf Qg Total Gate Charge Q gs Gate-Source Charge Q gd Gate-Drain Charge (Note 2) VDD = 10 V, ID = 1 A, VGS = 10 V, RGEN = 50 Ω 6 15 ns 15 30 ns Turn - Off Delay Time 14 30 ns Turn - Off Fall Time 18 40 ns 1.9 2.7 nC VDS = 10 V, ID = 1.2 A, VGS = 4.5 V 0.5 nC 0.9 nC NDS351AN Rev. C Electrical Characteristics (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units 0.42 A 5 A 1.2 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Drain-Source Diode Forward Current ISM Maximum Pulsed Drain-Source Diode Forward Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.2 A (Note 2) 0.8 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. P D (t ) = T J− TA R θJA(t ) = TJ − TA R θJC+RθCA(t ) = I 2D (t ) × RDS(ON ) TJ Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper. b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper. 1a 1b Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS351AN Rev. C Typical Electrical Characteristics 1.8 5 6.0 5.0 R DS(on ) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D , DRAIN-SOURCE CURRENT (A) V GS =10V 4.5 4.0 4 3 3.5 2 3.0 1 1.6 VGS = 3.5V 1.4 1.2 4.0 4.5 1 5.0 6.0 0.8 7.0 10 0.6 0.4 0 0 1 V DS 2 0 3 1 Figure 1. On-Region Characteristics. 4 1.6 RDS(on) , NORMALIZED V GS = 4.5V 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 DRAIN-SOURCE ON-RESISTANCE 1.8 I D = 1.2A VGS = 4.5 V 1.6 1.2 25°C 1 -55°C 0.8 0.6 0.4 0 Figure 3. On-Resistance Variation with Temperature. 25°C 125°C 3 2 1 1 1.5 V 2 GS 2.5 3 3.5 2 I D, DRAIN CURRENT (A) 3 4 1.2 T = -55°C J 4 0 0.5 1 Figure 4. On-Resistance Variation with Drain Current and Temperature. 5 V DS = 5.0V TJ = 125°C 1.4 Vth , NORMALIZED GATE-SOURCE THRESHOLD VOLTAGE R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 3 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 I D , DRAIN CURRENT (A) 2 I D , DRAIN CURRENT (A) , DRAIN-SOURCE VOLTAGE (V) 4 , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 4.5 5 V DS= V GS I D = 250µA 1.1 1 0.9 0.8 0.7 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 150 Figure 6. Gate Threshold Variation with Temperature. NDS351AN Rev. C Typical Electrical Characteristics (continued) 5 I D = 250µA 1.08 1.04 1 1 TJ = 125°C 25°C 0.1 -55°C 0.01 0.001 S 0.96 0.92 -50 -25 0 T J 25 50 75 100 125 0.0001 150 0 0.2 0.4 0.6 0.8 1 V SD , BODY DIODE FORWARD VOLTAGE (V) , JUNCTION TEMPERATURE (°C) Figure 7. Breakdown Voltage Variation with Temperature. 1.2 Figure 8. Body Diode Forward Voltage Variation with Source Current and Temperature. 10 , GATE-SOURCE VOLTAGE (V) 400 300 200 150 C iss C oss 100 f = 1 MHz V GS = 0V C rss I D = 1.2A 10V VDS = 5V 8 15V 6 4 2 V 80 GS CAPACITANCE (pF) V GS = 0V I , REVERSE DRAIN CURRENT (A) BV DSS , NORMALIZED DRAIN-SOURCE BREAKDOWN VOLTAGE 1.12 50 0.1 0.2 0.5 V DS 1 2 5 10 20 0 30 0 1 t on VDD t d(on) t d(off) tf 90% 90% V OUT D VOUT R GEN 4 t off tr RL V IN 3 Figure 10. Gate Charge Characteristics. Figure 9. Capacitance Characteristics. VGS 2 Q g , GATE CHARGE (nC) , DRAIN TO SOURCE VOLTAGE (V) 10% 10% DUT G INVERTED 90% S V IN 50% 50% 10% PULSE WIDTH Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDS351AN Rev. C 5 20 VDS = 5.0V 1m s 10 4 25°C 3 125°C 2 5 3 I D , DRAIN CURRENT (A) T J = -55°C 1 N) S(O RD 1 0 1 2 3 I , DRAIN CURRENT (A) 4 0.1 0.2 0.5 V D s ms 10s DC DS 1 2 5 10 20 30 50 , DRAI N-SOURCE VOLTAGE (V) Figure 14. Maximum Safe Operating Area. 1.6 1 I , STEADY-STATE DRAIN CURRENT (A) 0.8 0.6 1a 1b 0.4 0.2 4.5"x5" FR-4 Board TA = 25 oC Still Air 0 0.1 0.2 0.3 2oz COPPER MOUNTING PAD AREA (in 2 ) 1.4 1.2 1a 1b 4.5"x5" FR-4 Board o 1 TA = 2 5 C Still Air VG S = 4 . 5 V D STEADY-STATE POWER DISSIPATION (W) Figure 13. Transconductance Variation with Drain Current and Temperature. 0 100 V GS = 4.5V SINGLE PULSE RθJA =See Note1b TA = 25°C 0.01 0.1 5 IT LIM 0.3 0.03 g 0 10m 1s FS , TRANSCONDUCTANCE (SIEMENS) Typical Electrical Characteristics (continued) 0.8 0 0.4 Figue 15. SuperSOTTM _ 3 Maximum Steady-State Power Dissipation versus Copper Mounting Pad Area. 0.1 0.2 0.3 2oz COPPER MOUNTING PAD AREA (in 2 ) 0.4 Figure 16. Maximum Steady-State Drain Current versus Copper Mounting Pad Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 1 0.5 D = 0.5 R θJA (t) = r(t) * R θJA R θJA = See Note 1b 0.2 0.2 0.1 0.1 0.05 0.05 0.02 0.01 0.005 P(pk) 0.02 t1 0.01 t2 TJ - TA = P * R θJA (t) Single Pulse Duty Cycle, D = t1 /t2 0.002 0.001 0.0001 0.001 0.01 0.1 t 1 , TIME (sec) 1 10 100 300 Figure 17. Transient Thermal Response Curve. Note : Characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. NDS351AN Rev. C