± SLLS576D − JULY 2003 − REVISED JANUARY 2004
D ESD Protection for RS-232 Bus Pins
D
D
D
D
D
D
D, DW, N, OR PW PACKAGE
(TOP VIEW)
− ±15-kV − Human-Body Model
Meets or Exceeds the Requirements of
TIA/EIA-232-F and ITU v.28 Standards
Operates at 5-V VCC Supply
Operates Up To 120 kbit/s
External Capacitors . . . 4 × 0.1 µF
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Applications
− Battery-Powered Systems, PDAs,
Notebooks, Laptops, Palmtop PCs, and
Hand-Held Equipment
C1+
V+
C1−
C2+
C2−
V−
DOUT2
RIN2
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
GND
DOUT1
RIN1
ROUT1
DIN1
DIN2
ROUT2
description/ordering information
The MAX202 device consists of two line drivers, two line receivers, and a dual charge-pump circuit with
±15-kV ESD protection pin to pin (serial-port connection pins, including GND). The device meets the
requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous communication
controller and the serial-port connector. The charge pump and four small external capacitors allow operation
from a single 5-V supply. The device operates at data signaling rates up to 120 kbit/s and a maximum of 30-V/µs
driver output slew rate.
ORDERING INFORMATION
PDIP (N)
SOIC (D)
0°C
0
C to 70
70°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC (DW)
TSSOP (PW)
PDIP (N)
SOIC (D)
−40°C
−40
C to 85
85°C
C
SOIC (DW)
TSSOP (PW)
Tube of 25
MAX202CN
Tube of 40
MAX202CD
Reel of 2500
MAX202CDR
Tube of 40
MAX202CDW
Reel of 2000
MAX202CDWR
Tube of 90
MAX202CPW
Reel of 2000
MAX202CPWR
Tube of 25
MAX202IN
Tube of 40
MAX202ID
Reel of 2500
MAX202IDR
Tube of 40
MAX202IDW
Reel of 2000
MAX202IDWR
Tube of 90
MAX202IPW
Reel of 2000
MAX202IPWR
TOP-SIDE
MARKING
MAX202C
MAX202C
MAX202C
MAX202C
MAX202I
MAX202I
MAX202I
MAX202I
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
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± SLLS576D − JULY 2003 − REVISED JANUARY 2004
Function Tables
EACH DRIVER
INPUT
DIN
OUTPUT
DOUT
L
H
H
L
H = high level, L = low
level
EACH RECEIVER
INPUT
RIN
OUTPUT
ROUT
L
H
H
L
Open
H
H = high level, L = low
level, Open = input
disconnected
or
connected driver off
logic diagram (positive logic)
11
14
DIN1
DOUT1
10
7
DIN2
DOUT2
12
13
ROUT1
RIN1
9
ROUT2
2
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Positive charge pump voltage range, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC − 0.3 V to 14 V
Negative charge pump voltage range, V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −14 V to 0.3 V
Input voltage range, VI: Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V+ + 0.3 V
Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Output voltage range, VO: Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V− − 0.3 V to V+ + 0.3 V
Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Short-circuit duration: DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to network GND.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4 and Figure 4)
Supply voltage
VIH
VIL
Driver high-level input voltage
DIN
Driver low-level input voltage
DIN
Driver input voltage
DIN
VI
Receiver input voltage
TA
Operating free-air temperature
MAX202C
MAX202I
MIN
NOM
MAX
4.5
5
5.5
2
UNIT
V
V
0.8
0
5.5
−30
30
0
70
−40
85
V
V
°C
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 4)
PARAMETER
TEST CONDITIONS
ICC
Supply current
‡ All typical values are at VCC = 5 V, and TA = 25°C.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V.
POST OFFICE BOX 655303
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VCC = 5 V
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MIN
TYP‡
MAX
8
15
UNIT
mA
3
± SLLS576D − JULY 2003 − REVISED JANUARY 2004
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 4)
PARAMETER
TEST CONDITIONS
MIN
TYP†
VOH
VOL
High-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = GND
5
9
Low-level output voltage
DOUT at RL = 3 kΩ to GND,
DIN = VCC
−5
−9
IIH
IIL
High-level input current
Low-level input current
VI = VCC
VI at 0 V
IOS‡
Short-circuit output current
VCC = 5.5 V,
VO = 0 V
MAX
UNIT
V
V
µA
15
200
−15
−200
µA
±10
±60
mA
ro
Output resistance
VCC, V+, and V− = 0 V,
VO = ±2 V
300
W
† All typical values are at VCC = 5 V, and TA = 25°C.
‡ Short-circuit durations should be controlled to prevent exceeding the device absolute power-dissipation ratings, and not more than one output
should be shorted at a time.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 4)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
Maximum data rate
CL = 50 to1000 pF,
One DOUT switching,
RL = 3 kΩ to 7 kΩ,
See Figure 1
tPLH (D)
Propagation delay time,
low- to high-level output
CL = 2500 pF,
All drivers loaded,
RL = 3 kΩ,
See Figure 1
2
µs
tPHL (D)
Propagation delay time,
high- to low-level output
CL = 2500 pF,
All drivers loaded,
RL = 3 kΩ,
See Figure 1
2
µs
tsk(p)
Pulse skew§
CL = 150 pF to 2500 pF,
RL = 3 kΩ to 7 kΩ,
See Figure 2
300
ns
SR(tr)
Slew rate, transition region
(see Figure 1)
CL = 50 pF to 1000 pF,
VCC = 5 V
RL = 3 kΩ to 7 kΩ,
120
3
kbit/s
6
30
V/µs
TYP
UNIT
±15
kV
† All typical values are at VCC = 5 V, and TA = 25°C.
§ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V.
ESD protection
PIN
DOUT, RIN
4
TEST CONDITIONS
Human-Body Model
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RECEIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 4)
PARAMETER
MIN
TYP†
3.5V
VCC−0.4 V
TEST CONDITIONS
VOH
VOL
High-level output voltage
IOH = −1 mA
IOL = 1.6 mA
VIT+
VIT−
Positive-going input threshold voltage
Vhys
ri
Input hysteresis (VIT+ − VIT−)
Low-level output voltage
VCC = 5 V,
VCC = 5 V,
Negative-going input threshold voltage
TA = 25°C
TA = 25°C
VI = ±3 V to ±25 V
Input resistance
MAX
UNIT
V
1.7
0.4
V
2.4
V
0.8
1.2
0.2
0.5
1
V
V
3
5
7
kW
† All typical values are at VCC = 5 V, and TA = 25°C.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 5 V ± 0.5 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 3)
PARAMETER
tPLH (R)
tPHL (R)
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
Propagation delay time, low- to high-level output
CL= 150 pF
0.5
10
µs
Propagation delay time, high- to low-level output
CL= 150 pF
0.5
10
µs
Pulse skew‡
tsk(p)
† All typical values are at VCC = 5 V, and TA = 25°C.
‡ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
NOTE 4: Test conditions are C1−C4 = 0.1 µF, at VCC = 5 V ± 0.5 V.
300
ns
PARAMETER MEASUREMENT INFORMATION
3V
Input
Generator
(see Note B)
1.5 V
RS-232
Output
50 Ω
RL
1.5 V
0V
tPHL (D)
CL
(see Note A)
Output
3V
−3 V
TEST CIRCUIT
SR(tr) +
t
PHL (D)
6V
or t
tPLH (D)
3V
−3 V
VOH
VOL
VOLTAGE WAVEFORMS
PLH (D)
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 1. Driver Slew Rate
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• DALLAS, TEXAS 75265
5
± SLLS576D − JULY 2003 − REVISED JANUARY 2004
PARAMETER MEASUREMENT INFORMATION
3V
Generator
(see Note B)
RS-232
Output
50 Ω
RL
Input
1.5 V
1.5 V
0V
CL
(see Note A)
tPHL (D)
tPLH (D)
VOH
50%
50%
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 120 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 2. Driver Pulse Skew
Input
3V
1.5 V
1.5 V
−3 V
Output
Generator
(see Note B)
50 Ω
CL
(see Note A)
tPHL (R)
tPLH (R)
VOH
50%
Output
50%
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.
Figure 3. Receiver Propagation Delay Times
6
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APPLICATION INFORMATION
1
C1 +
C3† +
0.1 µF,
−
0.1 µF,
6.3 V
−
16 V
VCC 16
C1+
+ CBYPASS
− = 0.1 µF
2
3
V+
GND
15
14
C1−
DOUT1
13
4
C2 +
0.1 µF,
16 V −
5 kΩ
5 C2−
12
C4 −
0.1 µF,
16 V +
DOUT2
RIN2
RIN1
C2+
6
11
V−
7
10
8
9
ROUT1
DIN1
DIN2
ROUT2
5 kΩ
† C3 can be connected to VCC or GND.
NOTES: A. Resistor values shown are nominal.
B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown.
Figure 4. Typical Operating Circuit and Capacitor Values
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± SLLS576D − JULY 2003 − REVISED JANUARY 2004
APPLICATION INFORMATION
capacitor selection
The capacitor type used for C1−C4 is not critical for proper operation. The MAX202 requires 0.1-µF capacitors,
although capacitors up to 10 µF can be used without harm. Ceramic dielectrics are suggested for the 0.1-µF
capacitors. When using the minimum recommended capacitor values, make sure the capacitance value does
not degrade excessively as the operating temperature varies. If in doubt, use capacitors with a larger (e.g., 2×)
nominal value. The capacitors’ effective series resistance (ESR), which usually rises at low temperatures,
influences the amount of ripple on V+ and V−.
Use larger capacitors (up to 10 µF) to reduce the output impedance at V+ and V−.
Bypass VCC to ground with at least 0.1 µF. In applications sensitive to power-supply noise generated by the
charge pumps, decouple VCC to ground with a capacitor the same size as (or larger than) the charge-pump
capacitors (C1−C4).
ESD protection
TI MAX202 devices have standard ESD protection structures incorporated on the pins to protect against
electrostatic discharges encountered during assembly and handling. In addition, the RS232 bus pins (driver
outputs and receiver inputs) of these devices have an extra level of ESD protection. Advanced ESD structures
were designed to successfully protect these bus pins against ESD discharge of ±15-kV when powered down.
ESD test conditions
Stringent ESD testing is performed by TI, based on various conditions and procedures. Please contact TI for
a reliability report that documents test setup, methodology, and results.
Human-Body Model (HBM)
The HBM of ESD testing is shown in Figure 5. Figure 6 shows the current waveform that is generated during
a discharge into a low impedance. The model consists of a 100-pF capacitor, charged to the ESD voltage of
concern, and subsequently discharged into the device under test (DUT) through a 1.5-kΩ resistor.
RD
1.5 kΩ
VHBM
+
−
CS
DUT
100 pF
Figure 5. HBM ESD Test Circuit
8
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± SLLS576D − JULY 2003 − REVISED JANUARY 2004
APPLICATION INFORMATION
1.5
VHBM = 2 kV
DUT = 10-V, 1-Ω Zener Diode
|
IDUT – A
1.0
0.5
0.0
0
50
100
150
200
Time – ns
Figure 6. Typical HBM Current Waveform
Machine Model (MM)
The MM ESD test applies to all pins using a 200-pF capacitor with no discharge resistance. The purpose of the
MM test is to simulate possible ESD conditions that can occur during the handling and assembly processes of
manufacturing. In this case, ESD protection is required for all pins, not just RS-232 pins. However, after PC
board assembly, the MM test no longer is as pertinent to the RS-232 pins.
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9
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
MAX202CD
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
MAX202CDR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
MAX202CDW
ACTIVE
SOIC
DW
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
MAX202CDWR
ACTIVE
SOIC
DW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
MAX202CPW
ACTIVE
TSSOP
PW
16
90
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
MAX202CPWR
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
MAX202ID
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
MAX202IDR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
MAX202IDW
ACTIVE
SOIC
DW
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
MAX202IDWR
ACTIVE
SOIC
DW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
MAX202IPW
ACTIVE
TSSOP
PW
16
90
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
MAX202IPWR
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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