BUK9Y14-40B N-channel TrenchMOS logic level FET Rev. 03 — 2 June 2008 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using NXP High Performance Automotive (HPA) TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for logic level gate drive sources Q101 compliant Suitable for thermally demanding environments due to 175 °C rating 1.3 Applications Air bag Automotive transmission control Fuel pump and injection Automotive ABS systems Diesel injection systems Motors, lamps and solenoids 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 40 V ID drain current VGS = 5 V; Tmb = 25 °C; see Figure 4 and 1 - - 56 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 85 W VGS = 5 V; ID = 10 A; VDS = 32 V; see Figure 14 - 9 - nC VGS = 5 V; ID = 20 A; Tj = 25 °C; see Figure 12 and 13 - 12 14 mΩ ID = 56 A; Vsup ≤ 40 V; RGS = 50 Ω; VGS = 5 V; Tj(init) = 25 °C; unclamped - - 89 mJ Dynamic characteristics QGD gate-drain charge Static characteristics RDSon drain-source on-state resistance Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning Pin Symbol Description 1, 2, 3 S source 4 G gate mb D mounting base; connected to drain Simplified outline Graphic symbol D mb G mbb076 S 1 2 3 4 SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number BUK9Y14-40B Package Name Description Version LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS drain-source voltage VGS gate-source voltage ID drain current Conditions Min Max Unit Tj ≥ 25 °C; Tj ≤ 175 °C - 40 V 15 15 V Tmb = 25 °C; VGS = 5 V; see Figure 4 and 1 - 56 A Tmb = 100 °C; VGS = 5 V; see Figure 1 - 40 A IDM peak drain current Tmb = 25 °C; tp ≤ 10 μs; pulsed; see Figure 4 - 226 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 85 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C - 89 mJ - - J Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy ID = 56 A; Vsup ≤ 40 V; RGS = 50 Ω; VGS = 5 V; Tj(init) = 25 °C; unclamped EDS(AL)R repetitive drain-source avalanche energy see Figure 3 [1][2] [3] Source-drain diode IS source current Tmb = 25 °C - 56 A ISM peak source current tp ≤ 10 μs; pulsed; Tmb = 25 °C - 226 A [1] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. [2] Repetitive avalanche rating limited by average junction temperature of 170 °C. [3] Refer to application note AN10273 for further information. BUK9Y14-40B_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 2 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 003aab217 60 03na19 120 ID (A) Pder (%) 40 80 20 40 0 0 0 50 100 150 Tmb (°C) 0 200 50 100 150 200 Tmb (°C) VGS 5V P der = Fig 1. Continuous drain current as a function of mounting base temperature P tot P tot (25°C ) × 100 % Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aab220 102 (1) IAL (A) 10 (2) (3) 1 10-1 10-3 10-2 10-1 1 t (ms) 10 AL (1) Singleípulse;T j = 25 °C. (2) Singleípulse;T j = 150 °C. (3) Repetitive. Fig 3. Single-shot and repetitive avalanche rating; avalanche current as a function of avalanche period BUK9Y14-40B_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 3 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 003aab218 103 Limit RDSon = VDS / ID ID (A) 102 tp = 10 μs 100 μs 10 1 ms DC 10 ms 1 100 ms 10−1 1 102 10 VDS (V) Tmb = 25 °C; IDM is single pulse Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 5 - - 1.8 K/W 03nm01 10 Zth (j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 δ= P 0.05 tp T 0.02 t tp 10-2 10-6 T single shot 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration BUK9Y14-40B_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 4 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit ID = 250 μA; VGS = 0 V; Tj = 25 °C 40 - - V ID = 250 μA; VGS = 0 V; Tj = -55 °C 36 - - V - - 2.3 V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 11 and 10 1.1 1.5 2 V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10 0.5 - - V μA Static characteristics V(BR)DSS VGS(th) drain-source breakdown voltage gate-source threshold ID = 1 mA; VDS = VGS; voltage Tj = -55 °C; see Figure 10 IDSS drain leakage current VDS = 40 V; VGS = 0 V; Tj = 175 °C - - 500 VDS = 40 V; VGS = 0 V; Tj = 25 °C - 0.02 1 μA IGSS gate leakage current VDS = 0 V; VGS = 20 V; Tj = 25 °C - 2 100 nA VDS = 0 V; VGS = -20 V; Tj = 25 °C - 2 100 nA VGS = 5 V; ID = 20 A; Tj = 175 °C; see Figure 12 - - 26 mΩ VGS = 4.5 V; ID = 20 A; Tj = 25 °C - - 16 mΩ VGS = 10 V; ID = 20 A; Tj = 25 °C - 9 11 mΩ VGS = 5 V; ID = 20 A; Tj = 25 °C; see Figure 12 and 13 - 12 14 mΩ IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 16 - 0.85 1.2 V - 50 - ns - 26 - nC - 21 - nC - 3.7 - nC - 9 - nC - 1360 1800 pF - 274 330 pF - 147 200 pF - 15 - ns RDSon drain-source on-state resistance Source-drain diode VSD source-drain voltage trr reverse recovery time IS = 20 A; dIS/dt = -100 A/μs; VGS = 0 V; VDS = 30 V recovered charge Qr Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGD gate-drain charge Ciss input capacitance Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time ID = 10 A; VDS = 32 V; VGS = 5 V; see Figure 14 VGS = 0 V; VDS = 25 V; f = 1 MHz; Tj = 25 °C; see Figure 15 VDS = 30 V; RL = 2.5 Ω; VGS = 5 V; RG(ext) = 10 Ω tr rise time - 34 - ns td(off) turn-off delay time - 68 - ns tf fall time - 42 - ns BUK9Y14-40B_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 5 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 003aab413 160 ID (A) 15 6 003aab415 15 RDSon (mΩ) 5 120 12 4 3.8 3.6 3.4 3.2 3 80 40 9 2.8 2.6 2.4 VGS (V) = 2.2 0 0 2 4 6 8 6 10 VDS (V) 3 7 11 15 VGS (V) T j = 25 °C T j = 25 °C; ID = 20 A Fig 6. Output characteristics: drain current as a function of drain-source voltage; typical values 003aab417 50 Fig 7. Drain-source on-state resistance as a function of gate-source voltage; typical values 003aab416 50 ID (A) gfs (S) 40 45 30 40 20 Tj = 175 °C 35 10 30 Tj = 25 °C 0 5 10 15 20 25 30 0 ID (A) 2 3 4 VGS (V) T j = 25 °C;VDS = 25V VDS = 25V Fig 8. Forward transconductance as a function of drain current; typical values Fig 9. Transfer characteristics: drain current as a function of gate-source voltage; typical values BUK9Y14-40B_3 Product data sheet 1 © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 6 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 03ng53 10−1 03ng52 2.5 ID (A) VGS(th) (V) 10−2 2.0 min typ max 10−3 1.5 10−4 1.0 10−5 0.5 10−6 0 1 max 2 3 VGS (V) typ min 0 −60 T j = 25 °C;VDS = VGS 0 60 120 180 Tj (°C) ID = 1 m A;VDS = VGS Fig 10. Sub-threshold drain current as a function of gate-source voltage 003aab851 2 Fig 11. Gate-source threshold voltage as a function of junction temperature 003aab414 30 a VGS (V) = 3 RDSon (mΩ) 3.4 3.8 4 5 1.5 20 1 10 15 10 0.5 0 −60 a= 0 60 120 180 Tj (°C) 0 0 60 90 120 150 ID (A) R DSon T j = 25 °C R DSon (25°C ) Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 13. Drain-source on-state resistance as a function of drain current; typical values BUK9Y14-40B_3 Product data sheet 30 © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 7 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 003aab412 5 003aab410 2500 VGS (V) C (pF) 4 2000 Ciss VDS = 14 V 3 1500 VDS = 32 V 2 1000 1 500 0 0 5 10 15 Coss Crss 0 10−1 20 25 QG (nC) 1 102 10 VDS (V) T j = 25 °C; ID = 10 A VGS = 0V ; f = 1 M H z Fig 14. Gate-source voltage as a function of gate charge; typical values Fig 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aab411 50 IS (A) 40 30 20 Tj = 175 °C Tj = 25 °C 10 0 0.0 0.2 0.4 0.6 0.8 1.0 VSD (V) VGS = 0V Fig 16. Source current as a function of source-drain voltage; typical values BUK9Y14-40B_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 8 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads A2 A E SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b 1/2 X c e A (A 3) A1 C θ L detail X y C 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 mm b3 b4 2.2 2.0 0.9 0.7 c D (1) c2 D1(1) E(1) E1(1) max 0.25 0.30 4.10 4.20 0.19 0.24 3.80 5.0 4.8 3.3 3.1 e H L L1 L2 w y θ 1.27 6.2 5.8 0.85 0.40 1.3 0.8 1.3 0.8 0.25 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 MO-235 Fig 17. Package outline SOT669 (LFPAK) BUK9Y14-40B_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 9 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status BUK9Y14-40B_3 20080602 Product data sheet Modifications: • Change notice Supersedes BUK9Y14-40B_2 Table 4 VDS temperature operating range corrected BUK9Y14-40B_2 20080523 Product data sheet - BUK9Y14-40B_1 BUK9Y14-40B_1 20070903 Product data sheet - - BUK9Y14-40B_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 10 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] BUK9Y14-40B_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 2 June 2008 11 of 12 BUK9Y14-40B NXP Semiconductors N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 June 2008 Document identifier: BUK9Y14-40B_3