HI2559, CXD2559 ® October 1997 Features NO C OM T RE DED ME N FO R IG DES NEW NS 1-Bit D/A Converter For Audio Application Description • Two-Channel D/A Converter and Oversampling Digital Filter Into a Single Chip • Distortion . . . . . . . . . . . . . . . . . . . . . . . . 0.012% or Less • S/N Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . .96dB or More • Master Clock . . . . . . . . . . . . . . . . . . . . . 384FS or 256FS Applications The HI2559, CXD2559 is a 1-bit stereo D/A converter featuring a 2nd-order ∆∑ system noise shaper. This good cost performance LSI has functions such as digital attenuator and digital de-emphasis and others. Ordering Information PART NUMBER • CD Player and CD-ROM Player, etc. Functions TEMP. RANGE ( oC) PACKAGE PKG. NO. HI2559JCQ -20 to 75 32 Ld MPQF Q32.7x7-S CXD2559Q -20 to 75 32 Ld MPQF Q32.7x7-S • Data Can Be Input at Rate of 1 x FS with a Built-In Digital Filter • The 24-/32-Slot Serial Data Interface Enables Independent Selection of Data Frontward Truncation/Rearward Truncation and MSB First/LSB First • Two Channels Can Be Attenuated Independently in 255 Steps • The Output From Two Channels (L/R/L + R/Mute) Can Be Selected Independently • Digital Emphasis Pinout AOUT2+ AVSS3 XVSS XTLI XTLO XVDD AVSS2 AOUT1+ HI2559, CXD2559 (MQFP) TOP VIEW 3231 30 29 28 27 26 25 1 24 2 23 3 22 4 21 5 20 6 19 18 7 17 8 9 10 11 12 13 14 15 16 AVDD1 AOUT1AVSS1 DVSS1 XCLK DASL0 DASL1 DVDD1 LRCK BCK SIN MLSL ATT SHIFT LATCH WO AVDD0 AOUT2AVSS0 DVDD0 TEST CLR MASL DVSS0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 4-1 File Number 4120.1 HI2559, CXD2559 Block Diagram XTLI XTLO XCLK CLOCK GENERATOR TIMING CIRCUIT AOUT1 (+) DAC1 LRCK AOUT1 (-) DIGITAL FILTER (OVER SAMPLING) BCK S SIN AOUT2 (+) P DAC2 MASL AOUT2 (-) MLSL ATT ROM HOST COMPUTER I/F SHIFT LATCH ATT1 ATT2 RAM Pin Descriptions PIN NO. SYMBOL I/O DESCRIPTION 1 AVDD0 - Analog power supply for Channel 2 output. 2 AOUT2(–) O Analog reversed phase output for Channel 2. 3 ADV SS0 - Analog GND for Channel 2 output. 4 DVDD0 - Digital power supply. 5 TEST I IC measurement. Fixed to Low. 6 CLR I System clear input. Cleared when low. Equipped with a pull-up resistor. 7 MASL I Selects whether 16-bit serial data is placed in the first 16-bit or the second 16-bit slot of the serial IN 32-bit slots. Frontward truncation when High; rearward truncation when low. Equipped with a pulldown resistor. 8 DV SS0 - Digital GND. 9 LRCK I Serial IN sampling frequency clock. Transfers Channel-1 data when High; Channel-2 data when low. 10 BCK I Serial bit transfer clock 48 FS or 64 FS in serial IN. The serial input data is retrieved at the rising edge. 11 SIN I Two channels per sampling serial data input. Data format is represented by 2’s complements, and consists of 24-bit or 32-bit slots. 12 MLSL I Selects whether 16-bit serial data SIN (Pin 15) of serial IN at LSB first or MSB first. MSBfirst when High; LSB-first when Low. Equipped with a pull-up resistor. 4-2 HI2559, CXD2559 Pin Descriptions (Continued) PIN NO. SYMBOL I/O DESCRIPTION 13 ATT I Data input of the microcomputer interface. Attenuation data, output selection setting value, and de-emphasis on/off data re-input in serial mode. 14 SHIFT I Shift clock input of the microcomputer interface. 15 LATCH I Latch input of the microcomputer interface. Latched at the rising edge. 16 WO I Synchronization window control. Window open when Low (forced synchronization). 17 DVDD1 - Digital power supply. 18 DASL1 I IC measurement. Fixed to Low. 19 DASL0 I IC measurement. Fixed High. 20 XCLK O Inversion output of the clock input from XTLI (Pin 1). 21 DV SS1 - Digital GND. 22 AV SS1 - Analog GND for Channel 1 output. 23 AOUT1 (-) O Analog reversed phase output for Channel 1. 24 AVDD1 I Analog power supply for Channel 1 output. 25 AOUT1 (+) O Analog positive phase output for Channel 1. 26 AV SS2 - Analog GND for Channel 1 output. 27 XVDD - Digital power supply for the master clock. 28 XTLO O Crystal oscillator output. Connects the master clock 256 FS or 384 FS crystal oscillator, which is identified automatically. 29 XTLI I Crystal oscillator input. Connects the master clock 256 FS or 384 FS crystal oscillator, which is identified automatically. External clock pulse is input at this pin. 30 XVSS - Digital GND for master clock 31 AV SS3 - Analog GND for Channel 2 output. 32 AOUT2 (+) O Analog positive phase output for Channel 2. 4-3 HI2559, CXD2559 Absolute Maximum Ratings TA = 25oC, VSS = 0V Operating Conditions Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . VSS -0.5V to 7.0V Input Voltage (V 1). . . . . . . . . . . . . . . . . . . . VSS -0.5V to V DD +0.5V Output Voltage (V 0) . . . . . . . . . . . . . . . . . . VSS- 0.5V to VDD +0.5V Operating Temperature (TOPR). . . . . . . . . . . . . . . . . -20oC to 75oC Storage Temperature (TSTG) . . . . . . . . . . . . . . . . . . -55oC to 150oC Supply Voltage (V DD) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V Operating Temperature (TA) . . . . . . . . . . . . . . . . . . . . 20oC to 75oC Sampling Frequency (FS) . . . . . . . . . . . . . . . . . . . . . 7kHz to 50kHz Input/Output Capacitance Input Pin (CIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9pF (Max.) Output Pin (COUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11pF (Max.) Measurement conditions: V DD = VI = 0V, f = 1MHz Electrical Specifications PARAMETER MIN TYP MAX UNITS APPLICABLE PIN VIH 0.7 VDD - - V Note 1 VIL - - 0.3 VDD VIH 2.2 - - V Note 2 V Note 3 V Note 4 V Note 5 SYMBOL TEST CONDITIONS DC Electrical Specifications Input Voltage V IL Output Voltage V OH IOH = -2mA VDD -0.8 - 0.4 VOL IOL = 4mA - - 0.4 VOH IOH = -1mA VDD /2 - - VOL IOL = 1mA - - VDD /2 V OH IOH = -4mA VDD -0.8 - - VOL IOL = 4mA 0 - - Input Leakage Current 1 IIL1 VIN = VSS or VDD -10 - 10 µA Note 6 Input Leakage Current 2 IIL2 VIN = VSS or VDD -40 - 40 µA Note 7 Input Leakage Current 3 IIL VIL = VSS -40 -100 -240 µA Note 8 Input Leakage Current 4 IIH VIH = VDD 40 100 240 µA Note 9 250k 1M 2.5M Ω Note 12 2 - 13 MHz 2 - 20 38 - 250 ns 25 - 250 ns Feedback Resistance RFB VIN = VSS or VDD NOTES: 1. Input pins except for *2t 2. ATT, SHIFT, LATCH 3. XCLK 4. XLO 5. AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-) 6. ATT, SHIFT, LATCH, LRCK, BCK, SINt 7. WO 8. CLR, MLSLt 9. MASL 10. XTLI VDD = 5.0 ±10%, TOPR = -20oC to 75oC AC Electrical Specifications PARAMETER Oscillation Frequency SYMBOL 256 FS fx 384 FS External Clock Pulse Input High Level Width 258 FS tCWH 384 FS 4-4 HI2559, CXD2559 VDD = 5.0 ±10%, TOPR = -20oC to 75oC AC Electrical Specifications PARAMETER SYMBOL External Clock Pulse Input Low Level Width 256 FS External Clock Pulse Input Pulse Cycle (Note 2) 256 FS tCWL 384 FS tCYC 384 FS 38 - 250 ns 25 - 250 ns 76 - 500 ns 50 - 500 ns Input BCK Frequency fBCK - - 3.1 MHz Input BCK Pulse Width tWIB 100 - - ns Input Data Setup Time tIDS 10 - - ns Input Data Hold Time tIDH 15 - - ns Input LRCK Setup Time tILRS 10 - - ns Input LRCK Hold Time tILRH 15 - - ns Program Input Basic Time tPR 100 - - ns Latch Input Pulse Width tWLT 200 - - ns ATT Setup Time tSET 5 - - ns ATT Hold Time tHOLD 100 - - ns ATT Interval tINT 300 - - ns NOTE: 11. Always input an external clock after turning the power on. ANALOG CHARACTERISTICS MEASUREMENT CONDITIONS TA = 25oC, VDD = 5.0V, FS = 44kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, Master Clock 384FS. S/N (EIAJ) *1 96 100 - dB THD + N (EIAJ) - 0.010 0.012 % Dynamic Range (EIAJ) *1, *2 91 93 - dB Channel Separation (EIAJ) - 90 - dB Output Level - 2.58 - V (ms) Gain Difference Between Channels - - 0.1 dB NOTES: 12. A-weighting filter used. 13. -60dB, 1kHz input. 4-5 HI2559, CXD2559 The analog characteristics are measured with the following circuit: Test Circuits 820P CXD2559Q 3.9K 130K + AOUT1 (-) 3.9K 47P 4.7K + 4.7K 0.015 4.7K 1800P 4.7K + 22 100 + 82P 12K OUTPUT 820P 4.7K 3.9K 130K + AOUT1 (+) 3.9K 4.7K 4.7K 47P FIGURE 1. ANALOG CHARACTERISTICS 384FS LRCK TEST DISC DATA CXD2500Q BCK DATA AOUT1 CXD2559Q AOUT2 ANALOG AUDIO ANALYZER (SHIBASOKU AM51A) ANALOG CIRCUIT FIGURE 2. Timing Diagrams tCYC EXTERNAL CLOCK INPUT tCWH tCWL XTLI tWIB tWIB AUDIO INPUT 50% BCK tIDS tIDH SIN tILRH tILAS LRCK PROGRAM INPUT ATT MSB tSET SHIFT LATCH tHOLD tPR tPR tPR FIGURE 3. TIMING CHART 4-6 tWLT tINT 15 4-7 FIGURE 4. SERIAL DATA INTERFACE 7 8 9 10 11 12 13 14 15 0 INVALID CH-2 1 2 3 4 5 6 15 14 13 12 11 10 9 MSB 0 INVALID 3 LSB 2 SIN 0 1 MLSL = “L” SIN MLSL = “H” LRCK BCK (24-BIT SLOT) 0 8 7 INVALID 4 3 2 1 LSB 7 8 5 MSB 0 9 10 11 12 13 14 15 6 1 0 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MSB INVALID 2 4 6 7 INVALID INVALID 3 8 MSB 1 2 3 4 5 6 15 14 13 12 11 10 9 0 INVALID 0 7 8 8 7 5 4 3 2 1 0 9 10 11 12 13 14 15 6 INVALID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CH-1 9 10 11 12 13 14 15 INVALID 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CH-1 LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SIN 4 INVALID LSB INVALID MSB LSB 15 0 0 LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MSB MLSL = “L”, MASL = “H” SIN INVALID 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MLSL = “L”, MASL = “L” SIN MLSL = “H”, MASL = “H” SIN CH-2 15 Timing Diagrams MLSL = “H”, MASL = “L” LRCK BCK (32-BIT SLOT) HI2559, CXD2559 (Continued) HI2559, CXD2559 Timing Diagrams (Continued) BYTE 0 BYTE 1 LSB ATT BYTE 2 MSB LSB MSB L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7 P0 P1 P2 P3 E A X X 19 20 21 22 23 24 SHIFT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 LATCH FIGURE 5. Description of Functions A. Crystal Oscillator Frequency Selection B. Serial Data Interface [Related pins] XTLI, XTLO, XCLK, BCK, SIN [Related pins] LRCK, BCK, SIN, MASL, MLSL Although the 384 FS or 256 VS crystal oscillator can be connected to XTLI and XTLO, the selection is determined depending on whether the input serial data is 24-bit or 32-bit slot. The frequency of the crystal oscillator is output from XCLK as it is. The serial data format consists of two channels per sampling serial data represented by 2’s complement. In each channel, the data is processed as a 24-bit slot when the crystal oscillator frequency is 384 FS, and as a 32-bit slot when the crystal oscillator frequency is 256 FS . 16 of these bits are used as data. SERIAL DATA INPUT BIT RATE CRYSTAL OSCILLATOR FREQUENCY XCLK OUTPUT 24-Bit Slot (48FS) 384FS 384FS 32-Bit Slot (64FS) 256FS 256FS MSL is used to select whether the serial data is arranged at LSB first or MSB first. Also, MASL is used to select whether the 16-bits of valid data is placed in the first or the second half of the 32-bit slot. MSL CXD2500BQ DA16 DA15 LRCK XTAI CXD2559Q 24-SLOT 48FS IFS 384FS SIN XTLI BCK 384FS LRCK XCLK XTLO H MSB First L LSB First MASL 24-BIT SLOT 32-BIT SLOT H Rearward Truncation Frontward Truncation L Rearward Truncation C. Control Mode CXD2507Q PCMD BCK LRCK XTAI CXD2559Q 24-SLOT SIN 48FS BCK IFS LRCK 384FS XCLK [Related pins] ATT, SHIFT, LATCH XTLI 384FS XTLO FIGURE 6. CONNECTION EXAMPLE FOR THE CD DSP The serial ports of ATT, SHIFT and LATCH are used to control functions such as the digital attenuator, output selection and digital de-emphasis. Data consists of 24-bits (3 bytes), which have the following meanings: 4-8 HI2559, CXD2559 CONTROL BIT CONTROL WHEN SYSTEM IS CLEARED L7 TO L0 The L channel attenuation data. FF (H) R7 to R0 The R channel attenuation data. FF (H) P3 to P0 Output selection. 9 (H) Stereo E De-emphasis (High = on, Low = off) OFF However, the time constant of the emphasis is γ 1 = 50µs and γ 2 = 15µs when FS = 44.1kHz. The de-emphasis function cannot be used when FS is not 44.1kHz. A Attenuate (Low = independent, High = common). However, the L channel Independent attenuation value is used when the L and R channels are commonly attenuated. X Don’t care. NOTE: When the data is more than three bytes are transferred to the ATT pin, only the three bytes transferred finally are effective. D. Digital Attenuator (FS = 44kHz for CD). [Related pins] ATT, SHIFT, LATCH 0dB The output data can be attenuated independently in the L and R channels, using the transfer data from the external microcomputer. A ATT1 The ATT data of the L and R channels consist of eight bits each, and the L and R channels can be attenuated commonly using the ATT control bit. (The L channel attenuation value is used when the L and R channels are commonly attenuated). (1) B ATT3 C ATT2 Command and Audio Output The attenuation data of the L and R channels consist of eight bits, it can be set 255 ways. The following table shows the relationship between the commands and the outputs. ATTENUATION DATA L7 TO L0/R7 TO R0 AUDIO OUTPUT FF (H) 0dB FE (H) ↓ 01 (H) -0.034dB ↓ -48.131dB 00 (H) -∞ FIGURE 7. METHOD OF OBTAINING AN ATTENUATION VALUE F. Output Selection [Related pins] ATT, SHIFT, LATCH The L and R channel outputs can be set in four combinations [L/RL + R/Mute] (16 ways in total) using the transfer data from the external microcomputer. The following table shows the relationship between the commands and the outputs. The attenuation values for 01 (H) to FE (H) can be obtained with the following equation: ATT = 20log [Input data/255] dB Ex. for attenuating data FA (H) ATT = 20log [250/255] db = 0.172dB E. Digital Attenuator Suppose that there are attenuation data ATT1, ATT2 and ATT3, and their relationship is ATT1>ATT3>ATT2. When ATT2 is transferred before the level reaches the value of ATT1 (point A in the figure), the level keeps approaching to the value of ATT2. Next, when ATT3 is transferred before the level reaches the value of ATT2 (point B or C in the figure), the level starts approaching to the value of ATT3 from its level at that time (point B or C in the figure). The transition (0 dB to → –∞) between the attenuation data is 1024/FS 4-9 HI2559, CXD2559 P0 P1 P2 P3 L CHANNEL OUTPUT R CHANNEL OUTPUT REMARKS 0 0 0 0 Mute Mute Mute 0 0 0 1 Mute R 0 0 1 0 Mute L 0 0 1 1 Mute L+R 0 1 0 0 R Mute 0 1 0 1 R R 0 1 1 0 R L 0 1 1 1 R L+R 1 0 0 0 L Mute 1 0 0 1 L R 1 0 1 0 L L 1 - 1 1 L L+R 1 1 0 0 L+R Mute 1 1 0 1 L+R R 1 1 1 0 L+R L 1 1 1 1 L+R L+R Reverse Stereo Mono NOTE: For L + R, the output data is (L + R)/2 to avoid overflow. When the power is turned on, it is necessary to set the rising edge of LRCK in the center of the window by performing the forced synchronization. G. I/O Sync Circuit [Related pins] LRCK and WO (1) Operation (When the WO Pin is “H”) After the system is cleared, the forced synchronization is performed by setting WO pin to Low at 2/F S or more. The forced synchronization is performed at the second rising edge of LRCK after the WO pin is turned to “Low.” The synchronization circuit has the window of eight clocks of the master clock and it monitors whether the rising edge of LRCK is in the window. If the rising edge of LRCK is out of the window, resynchronization is automatically performed. (2) Forced Synchronization by WO Pin Even if the rising edge of LRCK is within the window, it may not synchronize owing to the mixing of the external noises, etc. when the rising edge of LRCK is positioned near at both edges of the window. NOTE: WO pin must be “H” except the forced synchronization. H. System Clear When the Power is Turned ON. [Related Pins] CLR When the power is turned ON and the master clock more than 4 clocks is input to the XTLI pin, set the CLR pin from “L” to “H.” 4-10 +5V DIGITAL POWER SUPPLY D MICROCOMPUTER ATT SHIFT LATCH CLR WO MASL 0.01 WO LATCH CLR SHIFT ATT LRCK BCK SIN MLSL ATT SHIFT LATCH WO MLSL 12 13 14 15 16 10 11 9 B 17 18 19 20 21 22 23 24 A 3.9K 3.9K 3.9K 0.01 25 26 27 29 28 31 30 32 3.9K 3.9K AOUT2 (+) VSS VSS XTLI CXD2559Q XTLO VDD VSS AOUT 1 (+) DASL1 DASL0 CXD2500Q LRCK LRCK DA15 8CK XTAI DA16 SIN 1 0.01 3 2 C 4 8 7 6 5 4558 IS USED FOR OPERATIONAL AMPLIFIER DIGITAL GND VSS XCLK VSS VSS VSS 0.01 +5V POWER SUPPLY FOR AOUT2 TEST VDD D +5V POWER SUPPLY FOR AOUT1 C MASL CLR VDD VDD AOUT 2 (-) AOUT 1 (-) 4-11 VDD ANALOG GND +5V POWER SUPPLY FOR THE XTAL OSCILLATOR CIRCUIT A B 3 130K + 47P 2 5 47P + + 4 81 7 4 81 47K 4.7K 4.7K 47P 4.7K 0.01 0.01 4.7K 0.01 20p 7 47K 47P + 3 2 384FS OR 256FS 5 6 3.9K 6 130K 20p 3.9K 130K 3.9K 130K 0.01 + 7 4.7K 1800P 4.7K 4.7K 820P 6 5 820P 4.7K + 7 4.7K 1800P 4.7K + 82P 3 0.015 4.7K 2 + 82P 3 2 NOTE: Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 820P 5 6 4.7K 820P 22µ 0.01 22µ 0.01 0.01 -12V 1 1 4 8 4 8 0.01 +12V 12K 100 12K 100 CH1 OUT CH2 OUT Application Circuit