Intel DA28F016XS-15 16-mbit (1 mbit x 16, 2 mbit x 8) synchronous flash memory Datasheet

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28F016XS
16-MBIT (1 MBIT x 16, 2 MBIT x 8)
SYNCHRONOUS FLASH MEMORY
Effective Zero Wait-State Performance
up to 33 MHz
 Synchronous Pipelined Reads
SmartVoltage Technology
 User-Selectable 3.3V or 5V V CC
 User-Selectable 5V or 12V V PP
0.33 MB/sec Write Transfer Rate
Configurable x8 or x16 Operation
56-Lead TSOP and SSOP Type I
Package
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Backwards-Compatible with 28F008SA
Command-Set
2 µA Typical Deep Power-Down
1 mA Typical Active I CC Current in
Static Mode
16 Separately-Erasable/Lockable
128-Kbyte Blocks
1 Million Erase Cycles per Block
State-of-the-Art 0.6 µm ETOX™ IV Flash
Technology
Intel’s 28F016XS 16-Mbit flash memory is a revolutionary architecture which is the ideal choice for designing
truly revolutionary high-performance products. Combining very high read performance with the intrinsic
nonvolatility of flash memory, the 28F016XS eliminates the traditional redundant memory paradigm of
shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM, for
improved system performance. The innovative capabilities of the 28F016XS enable the design of directexecute code and mass storage data/file flash memory systems.
The 28F016XS is the highest performance high-density nonvolatile read/program flash memory solution
available today. Its synchronous pipelined read interface, flexible VCC and VPP voltages, extended cycling,
fast program and read performance, symmetrically-blocked architecture, and selective block locking provide a
highly flexible memory component suitable for resident flash component arrays on the system board or
SIMMs. The synchronous pipelined interface and x8/x16 architecture of the 28F016XS allow easy interface
with minimal glue logic to a wide range of processors/buses, providing effective zero wait-state read
performance up to 33 MHz. The 28F016XS’s dual read voltage allows the same component to operate at
either 3.3V or 5.0V VCC. Programming voltage at 5V VPP minimizes external circuitry in minimal-chip, space
critical designs, while the 12.0V VPP option maximizes program/erase performance. Its high read performance
combined with flexible block locking enable both storage and execution of operating systems/application
software and fast access to large data tables. The 28F016XS is manufactured on Intel’s 0.6 µm ETOX IV
process technology.
November 1996
Order Number: 290532-004
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F016XS may contain design defects or errors known as errata. Current characterized errata are available upon request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
COPYRIGHT © INTEL CORPORATION, 1996
CG-041493
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28F016XS FLASH MEMORY
CONTENTS
PAGE
PAGE
1.0 INTRODUCTION ............................................ 7
1.1 Product Overview ........................................ 7
5.0 ELECTRICAL SPECIFICATIONS ................. 24
5.1 Absolute Maximum Ratings ....................... 24
5.2 Capacitance............................................... 24
5.3 Transient Input/Output Reference
Waveforms............................................... 26
5.4 DC Characteristics (VCC = 3.3V) ................ 27
5.5 DC Characteristics (VCC = 5.0V) ................ 30
5.6 Timing Nomenclature ................................. 33
5.7 AC Characteristics—Read Only
Operations ................................................ 34
5.8 AC Characteristics for WE#—Controlled
Write Operations ....................................... 40
5.9 AC Characteristics for CE X#—Controlled
Write Operations ....................................... 44
5.10 Power-Up and Reset Timings .................. 48
5.11 Erase and Program Performance............. 49
2.0 DEVICE PINOUT........................................... 10
2.1 Lead Descriptions ...................................... 12
3.0 MEMORY MAPS ........................................... 14
3.1 Extended Status Register Memory Map..... 15
4.0 BUS OPERATIONS, COMMANDS AND
STATUS REGISTER DEFINITIONS............. 16
4.1 Bus Operations for Word-Wide Mode
(BYTE# = VIH)........................................... 16
4.2 Bus Operations for Byte-Wide Mode
(BYTE# = VIL) ........................................... 17
4.3 28F008SA—Compatible Mode Command
Bus Definitions.......................................... 18
4.4 28F016XS—Enhanced Command Bus
Definitions ................................................. 19
4.5 Compatible Status Register ....................... 20
4.6 Global Status Register ............................... 21
4.7 Block Status Register ................................ 22
4.8 Device Configuration Code ........................ 23
4.9 SFI Configuration Table ............................. 23
6.0 MECHANICAL SPECIFICATIONS ................ 51
APPENDIX A: Device Nomenclature and
Ordering Information .................................. 53
APPENDIX B: Additional Information............... 54
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28F016XS FLASH MEMORY
REVISION HISTORY
Number
Description
-001
Original Version
-002
Removed support of the following features:
• All page buffer operations (read, write, programming, Upload Device Information)
• Command queuing
• Software Sleep and Abort
• Erase all Unlocked Blocks and Two-Byte Write
• RY/BY# Configuration as part of the Device Configuration command
Changed definition of “NC.” Removed “No internal connection to die” from description.
Added “xx” to Upper Byte of Command (Data) Definition in Sections 4.3 and 4.4.
Modified parameters “V” and “I” of Section 5.1 to apply to “NC” pins.
Increased IPPR (VPP Read Current) for VPP > VCC to 200 µA at VCC = 3.3V/5.0V.
Changed VCC = 5.0V DC Characteristics (Section 5.5) marked with Note 1 to indicate
that these currents are specified for a CMOS rise/fall time (10% to 90%) of <5 ns
and a TTL rise/fall time of <10 ns.
Corrected tPHCH (RP# High to CLK) to be a “Min” specification at V CC = 3.3V/5.0V.
Corrected the graphical representation of tWHCH and tEHCH in Figures 15 and 16.
Increased Typical “Byte/Word Program Times” (tWHRH1A/tWHRH1B) for VPP = 5.0V (Sec.
5.13): tWHRH1A from 16.5 µs to 29.0 µs and t WHRH1B from 24.0 µs to 35.0 µs at V CC =
3.3V
tWHRH1A from 11.0 µs to 20.0 µs and t WHRH1B from 16.0 µs to 25.0 µs at V CC = 5.0V.
Increased Typical “Block Program Times” (tWHRH2/ tWHRH3) for VPP = 5.0V (Section 5.13):
tWHRH2 from 2.2 sec to 3.8 sec and t WHRH3 from 1.6 sec to 2.4 sec at V CC = 3.3V
tWHRH2 from 1.6 sec to 2.8 sec and t WHRH3 from 1.2 sec to 1.7 sec at V CC = 5.0V.
Changed “Time from Erase Suspend Command to WSM Ready” spec name to “Erase
Suspend Latency Time to Read;” Modified typical values and Added Min/Max values
at VCC =3.3/5.0V and VPP =5.0/12.0V (Section 5.13).
Minor cosmetic changes throughout document.
-003
4
Added 3/5# pin to Pinout Configuration (Figure 2), Product Overview (Section 1.1) and
Lead Descriptions (Section 2.1)
Modified Block Diagram (Figure 1): Removed Address Counter; Added 3/5# pin
Added 3/5# pin to Test Conditions of ICCS Specifications
Added 3/5# pin (Y) to Timing Nomenclature (Section 5.6)
Removed Note 7 of Section 5.7
Modified Device Configuration Code: Incorporated RY/BY# Configuration (Level Mode
support ONLY)
Modified Power-Up and Reset Timings (Section 5.10) to include 3/5# pin: Removed t5VPH
and t3VPH specifications; Added t PLYL, tPLYH, tYLPH, and tYHPH specifications
Added SSOP pinout (Figure 2) and Mechanical Specifications
Corrected TSOP Mechanical Specification A1 from 0.50 mm to 0.050 mm (Section 6.0)
Minor cosmetic changes throughout document.
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Number
-004
28F016XS FLASH MEMORY
REVISION HISTORY (Continued)
Description
Require all VCC Tolerences to be within 5% of Operational Voltage
IPPES Is Pushed to 200 µA from 50 Max
ICCD Is Pushed to 10 µA from 5 Max
Updated tAVAV at 3.3V
Updated tELEH at 3.3V and 5.0V
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1.0
28F016XS FLASH MEMORY
INTRODUCTION
The documentation of the Intel 28F016XS Flash
memory device includes this datasheet, a detailed
user’s manual, a number of application notes and
design tools, all of which are referenced in
Appendix B.
The datasheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The 16-Mbit Flash Product Family
User’s Manual provides complete descriptions of
the user modes, system interface examples and
detailed descriptions of all principles of operation. It
also contains the full list of software algorithm
flowcharts, and a brief section on compatibility with
the Intel 28F008SA.
Significant 28F016XS feature revisions occurred
between datasheet revisions 290532-001 and
290532-002. These revisions center around
removal of the following features:
•
All page buffer operations (read, write,
programming, Upload Device Information)
•
Command queuing
•
Software Sleep and Abort
•
Erase all Unlocked Blocks and Two-Byte Write
•
RY/BY# Configuration options
In addition, a significant 28F016XS change
occurred between datasheet revisions 290532-002
and 290532-003. This change centers around the
addition of a 3/5# pin to the device’s pinout
configuration. Figures 2 and 3 show the 3/5# pin
assignment for the TSOP and SSOP Type I
packages.
Intel recommends that all customers obtain the
latest revisions of 28F016XS documentation.
1.1
Product Overview
The 28F016XS is a high-performance, 16-Mbit
(16,777,216-bit) block erasable nonvolatile random
access memory organized as either 1 Mword x 16
or 2 Mbyte x 8, subdivided into even and odd
banks. Address A1 makes the bank selection. The
28F016XS includes sixteen 128-Kbyte (131,072
byte) blocks or sixteen 64-Kword (65,536 word)
blocks. Chip memory maps for x8 and x16 modes
are shown in Figures 4 and 5.
The implementation of a new architecture, with
many enhanced features, will improve the device
operating characteristics and result in greater
product reliability and ease-of-use as compared to
other flash memories. Significant features of the
28F016XS as compared to previous asynchronous
flash memories include:
•
Synchronous Pipelined Read Interface
•
Significantly Improved Read and Program
Performance
•
SmartVoltage Technology
 Selectable 3.3V or 5.0 VCC
 Selectable 5.0V or 12.0 VPP
•
Block Program/Erase Protection
The 28F016XS’s synchronous pipelined interface
dramatically raises read performance far beyond
previously attainable levels. Addresses are
synchronously latched and data is read from a
28F016XS bank every 30 ns (5V VCC, SFI
Configuration = 2). This capability translates to zero
wait-state reads at clock rates up to 33 MHz at 5V
VCC, after an initial address pipeline fill delay and
assuming even and odd banks within the flash
memory are alternately accessed. Data is latched
and driven valid 20 ns (tCHQV) after a rising CLK
edge. The 28F016XS is capable of operating up to
50 MHz (5V VCC); its programmable SFI
Configuration enables system design flexibility,
optimizing the 28F016XS to a specific system clock
frequency. See Section 4.9, SFI Configuration
Table, for specific SFI Configurations for given
operating frequencies.
The SFI Configuration optimizes the 28F016XS for
a wide range of system operating frequencies. The
default SFI Configuration is 4, which allows system
boot from the 28F016XS at any frequency up to
50 MHz at 5V VCC. After initiating an access, data
is latched and begins driving on the data outputs
after a CLK count corresponding to the SFI
Configuration has elapsed. The 28F016XS will hold
data valid until CE# or OE# is deactivated or a CLK
count corresponding to the SFI Configuration for a
subsequent access has elapsed.
The CLK and ADV# inputs, new to the 28F016XS in
comparison to previous flash memories, control
address latching and device synchronization during
read operations. The CLK input controls the device
latencies, times out the SFI Configuration counter
and synchronizes data outputs. ADV# indicates the
presence of a valid address on the 28F016XS
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28F016XS FLASH MEMORY
address inputs. During read operations, addresses
are latched and accesses are initiated on a rising
CLK edge in conjunction with ADV# low. Both CLK
and ADV# are ignored by the 28F016XS during
command/data write sequences.
The
28F016XS
incorporates
SmartVoltage
technology, providing VCC operation at both 3.3V
and 5.0V and program and erase capability at
VPP = 12.0V or 5.0V. Operating at VCC = 3.3V, the
28F016XS consumes less than one half the power
consumption at 5.0V VCC, while 5.0V VCC provides
highest read performance capability. VPP operation
at 5.0V eliminates the need for a separate 12.0V
converter, while the VPP = 12.0V option maximizes
program/erase performance. In addition to the
flexible program and erase voltages, the dedicated
VPP gives complete code protection with VPP ≤
VPPLK.
Block Erase Cycles by providing wear-leveling
algorithms and graceful block retirement. These
techniques have already been employed in many
flash file systems and hard disk drive designs.
All operations are started by a sequence of Write
commands to the device. Three Status Registers
(described in detail later in this datasheet) and a
RY/BY# output pin provide information on the
progress of the requested operation.
The following Status Registers are used to provide
device and WSM operation information to the user:
•
A 3/5# input pin configures the device’s internal
circuitry for optimal 3.3V or 5.0V read/program
operation.
A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory Status Register. The CSR, when used
alone, provides a straightforward upgrade
capability to the 28F016XS from a 28F008SAbased design.
•
A Command User Interface (CUI) serves as the
system interface between the microprocessor or
microcontroller and the internal memory operation.
A Global Status Register (GSR) which also
informs the system of overall Write State
Machine (WSM) status.
•
16 Block Status Registers (BSRs) which
provide block-specific status information such
as the block lock-bit status.
Internal Algorithm Automation allows program and
block erase operations to be executed using a TwoWrite command sequence to the CUI in the same
way as the 28F008SA 8-Mbit FlashFile™ memory.
Software locking of memory blocks is an added
feature of the 28F016XS as compared to the
28F008SA. The 28F016XS provides selectable
block locking to protect code or data such as directexecutable operating systems or application code.
Each block has an associated nonvolatile lock-bit
which determines the lock status of the block. In
addition, the 28F016XS has a master Write Protect
pin (WP#) which prevents any modifications to
memory blocks whose lock-bits are set.
Writing of memory data is performed in either byte
or word increments, typically within 6 µs at 12.0V
VPP, which is a 33% improvement over the
28F008SA. A block erase operation erases one of
the 16 blocks in typically 1.2 sec, independent of
the other blocks.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve one million
8
The GSR and BSR memory maps for Byte-Wide
and Word-Wide modes are shown in Figures 5
and 6.
The 28F016XS incorporates an open drain RY/BY#
output pin. This feature allows the user to OR-tie
many RY/BY# pins together in a multiple memory
configuration such as a Resident Flash Array.
The 28F016XS also incorporates a dual chipenable function with two input pins, CE0# and CE1#.
These pins have exactly the same functionality as
the regular chip-enable pin, CE#, on the 28F008SA.
For minimum chip designs, CE1# may be tied to
ground and system logic may use CE0# as the chip
enable input. The 28F016XS uses the logical
combination of these two signals to enable or
disable the entire chip. Both CE0# and CE1# must
be active low to enable the device. If either one
becomes inactive, the chip will be disabled. This
feature, along with the open drain RY/BY# pin,
allows the system designer to reduce the number of
control pins used in a large array of 16-Mbit
devices.
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28F016XS FLASH MEMORY
DQ
DQ
8-15
Output
Buffer
0-7
Output
Buffer
Input
Buffer
Input
Buffer
3/5#
I/O Logic
BYTE#
Data
Register
Output Multiplexer
ID
Register
CLK
ADV#
CSR
CE0#
ESRs
CE1 #
CUI
0-20
OE#
A
Data
Comparator
Input
Buffer
WP#
Y
Decoder
Y Gating/Sensing
Even Bank
X
Decoder
Y
Decoder
128-Kbyte
128-Kbyte
Block 14
Block 15
RY/BY#
WSM
128-Kbyte
Block 1
128-Kbyte
X
Decoder
Block 0
Even Address Latch
RP#
Odd Address Latch
Address
Register
WE#
Program/Erase
Voltage Switch
Odd Bank
VPP
3/5#
VCC
GND
Y Gating/Sensing
0532_01
Figure 1. 28F016XS Block Diagram
Architectural Evolution Includes Synchronous Pipelined Read Interface,
SmartVoltage Technology, and Extended Status Registers
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28F016XS FLASH MEMORY
The BYTE# pin allows either x8 or x16
read/programs to the 28F016XS. BYTE# at logic
low selects 8-bit mode with address A0 selecting
between low byte and high byte. On the other hand,
BYTE# at logic high enables 16-bit operation with
address A1 becoming the lowest order address and
address A0 is not used (don’t care). A device block
diagram is shown in Figure 1.
The 28F016XS incorporates an Automatic Power
Saving (APS) feature, which substantially reduces
the active current when the device is in static mode
of operation (addresses not switching). In APS
mode, the typical ICC current is 1 mA at 5.0V (3 mA
at 3.3V).
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA) pin
transitions low. This mode brings the device power
consumption to less than 2.0 µA, typically, and
provides additional write protection by acting as a
device reset pin during power transitions. A reset
time of 300 ns (5V VCC) is required from RP#
switching high before latching an address into the
28F016XS. In the deep power-down state, the
WSM is reset (any current operation will abort) and
the CSR, GSR and BSR registers are cleared.
A CMOS standby mode of operation is enabled
when either CE0# or CE1# transitions high and RP#
stays high with all input control pins at CMOS
levels. In this mode, the device typically draws an
ICC standby current of 70 µA at 5V V CC.
The 28F016XS is available in 56-Lead, 1.2 mm
thick, 14 mm x 20 mm TSOP and 1.8 mm thick, 16
mm x 23.7 mm SSOP Type I packages. The form
factor and pinout of these two packages allow for
very high board layout densities.
2.0
DEVICE PINOUT
The 28F016XS is pinout compatible with the
28F016SA/SV 16-Mbit FlashFile memory components, providing a performance upgrade path to
the 28F016XS. The 28F016XS 56-Lead TSOP and
SSOP pinout configurations are shown in Figures 2
and 3.
28F016SA/SV
28F016SA/SV
3/5#
CE1 #
NC
A 20
A 19
A 18
A 17
A 16
V CC
A 15
A 14
A 13
A 12
CE0 #
V PP
RP#
A 11
A 10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
3/5#
CE 1 #
NC
A 20
A 19
A 18
A 17
A 16
V CC
A 15
A 14
A 13
A 12
CE 0 #
V PP
RP#
A 11
A 10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
E28F016XS
56-LEAD TSOP PINOUT
14 mm x 20 mm
TOP VIEW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WP#
WE#
OE#
RY/BY#
DQ15
DQ 7
DQ 14
DQ 6
GND
DQ 13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ 3
DQ 10
DQ 2
VCC
DQ 9
DQ 1
DQ 8
DQ 0
A0
BYTE#
ADV#
CLK
WP#
WE#
OE#
RY/BY#
DQ15
DQ 7
DQ 14
DQ 6
GND
DQ 13
DQ5
DQ12
DQ4
VCC
GND
DQ11
DQ 3
DQ 10
DQ 2
VCC
DQ 9
DQ1
DQ8
DQ0
A0
BYTE#
NC
NC
0532_02
Figure 2. 28F016XS 56-Lead TSOP Pinout Configuration Shows Compatibility with
the 28F016SA/SV, Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs
10
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28F016SA/SV
CE0 #
A 12
A 13
A 14
28F016XS FLASH MEMORY
28F016SA/SV
CE0 #
1
A12
A13
A 14
2
3
4
A 15
3/5#
A 15
3/5#
5
CE1 #
NC
A 20
A 19
A 18
CE1 #
NC
A 20
A 19
A 18
7
8
9
A 17
6
10
11
DA28F016XS
56-LEAD SSOP
STANDARD PINOUT
56
55
54
53
52
51
50
VPP
RP#
A11
A10
A9
A1
A2
VPP
RP#
A11
A10
A9
A1
A2
49
48
A3
A4
A3
A4
47
46
A5
A6
A5
45
A7
A7
44
43
42
GND
A8
VCC
GND
A8
41
DQ 9
DQ 9
A6
A 17
12
A 16
A 16
13
VCC
VCC
14
GND
DQ 6
DQ 14
GND
DQ 6
DQ 14
15
DQ 7
18
40
39
DQ 1
DQ 8
DQ 1
DQ 7
DQ 15
DQ 15
19
38
DQ 0
DQ 0
RY/BY#
20
21
37
A0
36
BYTE#
BYTE#
NC
NC
RY/BY#
16 mm x 23.7 mm
TOP VIEW
16
17
VCC
DQ 8
A0
OE#
OE#
WE#
WP#
DQ13
WE#
WP#
DQ13
22
23
35
34
ADV#
CLK
24
33
DQ5
DQ5
25
32
DQ2
DQ 10
DQ12
DQ12
26
31
DQ 3
DQ 10
DQ 3
DQ4
DQ4
27
30
DQ 11
DQ 11
VCC
VCC
28
29
GND
GND
DQ2
XS_SSOP
Figure 3. 28F016XS 56-Lead SSOP Pinout Configuration Shows Compatibility with the 28F016SA/SV,
Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs
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INTEL CONFIDENTIAL
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28F016XS FLASH MEMORY
2.1
Lead Descriptions
Symbol
Type
Name and Function
A0
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when device is
in x8 mode. This address is latched in x8 data programs and ignored in x16
mode (i.e., the A0 input buffer is turned off when BYTE# is high).
A1
INPUT
BANK-SELECT ADDRESS: Selects an even or odd bank in a selected block.
A 128-Kbyte block is subdivided into an even and odd bank. A 1 = 0 selects the
even bank and A1 = 1 selects the odd bank, in both byte-wide mode and wordwide mode device configurations.
A2–A16
INPUT
WORD-SELECT ADDRESSES: Select a word within one 128-Kbyte block.
Address A1 and A7–16 select 1 of 2048 rows, and A2–6 select 16 of 512
columns. These addresses are latched during both data reads and programs.
A17–A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 16 erase blocks. These
addresses are latched during data programs, erase and lock-block operations.
DQ0–DQ7
INPUT/
OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, identifier or status data in the appropriate read mode. Floated
when the chip is de-selected or the outputs are disabled.
DQ8–DQ15
INPUT/
OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 data program operations.
Outputs array or identifier data in the appropriate read mode; not used for
Status Register reads. Outputs floated when the chip is de-selected, the
outputs are disabled (OE# = VIH) or BYTE# is driven active.
CE0#, CE1#
INPUT
CHIP ENABLE INPUTS: Activate the device’s control logic, input buffers,
decoders and sense amplifiers. With either CE0# or CE1# high, the device is
de-selected and power consumption reduces to standby levels upon
completion of any current data program or erase operations. Both CE0# and
CE1# must be low to select the device.
All timing specifications are the same for both signals. Device Selection occurs
with the latter falling edge of CE0# or CE1#. The first rising edge of CE0# or
CE1# disables the device.
RP#
INPUT
RESET/POWER-DOWN: RP# low places the device in a deep power-down
state. All circuits that consume static power, even those circuits enabled in
standby mode, are turned off. When returning from deep power-down, a
recovery time of t PHCH is required to allow these circuits to power-up.
When RP# goes low, the current WSM operation is terminated, and the device
is reset. All Status Registers return to ready, clearing all status flags. Exit from
deep power-down places the device in read array mode.
OE#
INPUT
OUTPUT ENABLE: Drives device data through the output buffers when low.
The outputs float to tri-state off when OE# is high. CE x# overrides OE#, and
OE# overrides WE#.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Data Register and Address
Latch. WE# is active low, and latches both address and data (command or
array) on its rising edge.
12
E
2.1
28F016XS FLASH MEMORY
Lead Descriptions (Continued)
Symbol
Type
Name and Function
CLK
INPUT
CLOCK: Provides the fundamental timing and internal operating frequency.
CLK latches input addresses in conjunction with ADV#, times out the desired
output SFI Configuration as a function of the CLK period, and synchronizes
device outputs. CLK can be slowed or stopped with no loss of data or
synchronization. CLK is ignored during program operations.
ADV#
INPUT
ADDRESS VALID: Indicates that a valid address is present on the address
inputs. ADV# low at the rising edge of CLK latches the address on the address
inputs into the flash memory and initiates a read access to the even or odd
bank depending on the state of A1. ADV# is ignored during program operations.
OPEN
DRAIN
OUTPUT
READY/BUSY: Indicates status of the internal WSM. When low, it indicates
that the WSM is busy performing an operation. RY/BY# high indicates that the
WSM is ready for new operations, erase is suspended, or the device is in deep
power-down mode. This output is always active (i.e., not floated to tri-state off
when OE# or CE0#, CE1# are high).
WP#
INPUT
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit
for each block. When WP# is low, those locked blocks as reflected by the
Block-Lock Status bits (BSR.6), are protected from inadvertent data programs
or erases. When WP# is high, all blocks can be written or erased regardless of
the state of the lock-bits. The WP# input buffer is disabled when RP#
transitions low (deep power-down mode).
BYTE#
INPUT
BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or
output on DQ0–7, and DQ8–15 float. Address A 0 selects between the high and
low byte. BYTE# high places the device in x16 mode, and turns off the A 0 input
buffer. Address A1 then becomes the lowest order address.
3/5#
INPUT
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V
operation. 3/5# low configures internal circuits for 5.0V operation.
NOTE:
Reading the array with 3/5# high in a 5.0V system could damage the device.
Reference the power-up and reset timings (Section 5.10) for 3/5# switching
delay to valid data.
VPP
SUPPLY
RY/BY#
PROGRAM/ERASE POWER SUPPLY (12.0V ± 0.6V, 5.0V ± 0.5V) :
For erasing memory array blocks or writing words/bytes into the flash array.
VPP = 5.0V ± 0.5V eliminates the need for a 12.0V converter, while the 12.0V ±
0.6V option maximizes program/erase performance.
Successful completion of program and erase attempts is inhibited with V PP at
or below 1.5V. Program and erase attempts with VPP between 1.5V and 4.5V,
between 5.5V and 11.4V, and above 12.6V produce spurious results and
should not be attempted.
VCC
SUPPLY
DEVICE POWER SUPPLY (3.3V ± 5%, 5.0V ± 5%):
To switch 3.3V to 5.0V (or vice versa), first ramp V CC down to GND, and then
power to the new VCC voltage. Do not leave any power pins floating.
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E
28F016XS FLASH MEMORY
2.1
Lead Descriptions (Continued)
Symbol
GND
Type
SUPPLY
NO CONNECT:
Lead may be driven or left floating.
NC
3.0
Name and Function
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
MEMORY MAPS
x8 Mode
x16 Mode
A 20-0
1FFFFF
128-Kbyte Block 15
FFFFF
64-Kword Block 15
1E0000
1DFFFF
128-Kbyte Block 14
128-Kbyte Block 13
128-Kbyte Block 12
128-Kbyte Block 11
128-Kbyte Block 10
128-Kbyte Block 9
128-Kbyte Block 8
128-Kbyte Block 7
128-Kbyte Block 6
128-Kbyte Block 5
128-Kbyte Block 4
128-Kbyte Block 3
128-Kbyte Block 2
128-Kbyte Block 1
128-Kbyte Block 0
A 20-1
64-Kword Block 14
1C0000
1BFFFF
64-Kword Block 13
1A0000
19FFFF
64-Kword Block 12
180000
17FFFF
64-Kword Block 11
160000
15FFFF
64-Kword Block 10
140000
13FFFF
64-Kword Block 9
120000
11FFFF
64-Kword Block 8
100000
0FFFFF
64-Kword Block 7
0E0000
0DFFFF
64-Kword Block 6
0C0000
0BFFFF
64-Kword Block 5
0A0000
09FFFF
64-Kword Block 4
080000
07FFFF
64-Kword Block 3
060000
05FFFF
64-Kword Block 2
040000
03FFFF
64-Kword Block 1
020000
01FFFF
64-Kword Block 0
000000
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
0532_03
Figure 4. 28F016XS Memory Map
(Byte-Wide Mode)
14
0532_04
Figure 5. 28F016XS Memory Map
(Word-Wide Mode)
E
3.1
28F016XS FLASH MEMORY
Extended Status Register Memory Map
x8 Mode
x16 Mode
A 20-0
A 20-1
FFFFFH
1FFFFFH
RESERVED
RESERVED
RESERVED
F0003H
1E0006H
RESERVED
1E0005H
GSR
RESERVED
GSR
1E0004H
RESERVED
F0002H
1E0003H
BSR 15
BSR 15
RESERVED
RESERVED
.
.
.
F0001H
1E0002H
RESERVED
1E0001H
RESERVED
1E0000H
.
.
.
01FFFFH
F0000H
0FFFFH
RESERVED
RESERVED
000006H
00003H
RESERVED
RESERVED
000005H
GSR
GSR
000004H
00002H
RESERVED
RESERVED
000003H
BSR 0
BSR 0
RESERVED
RESERVED
000002H
RESERVED
000001H
RESERVED
000000H
0532_05
Figure 6. Extended Status Register Memory
Map (Byte-Wide Mode)
00001H
00000H
0532_06
Figure 7. Extended Status Register Memory
Map (Word-Wide Mode)
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E
28F016XS FLASH MEMORY
4.0
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1
Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode
Notes
RP#
CE0–1#
OE#
WE#
ADV#
CLK
A1
DQ0–15
RY/BY#
1,9,10
VIH
VIL
X
VIH
VIL
↑
X
X
X
1,9
VIH
VIL
X
VIH
VIH
↑
X
X
X
Read
1,2,7,9
VIH
VIL
VIL
VIH
X
↑
X
DOUT
X
Output
Disable
1,6,7,9
VIH
VIL
VIH
VIH
X
X
X
High Z
X
Standby
1,6,7,9
VIH
VIL
X
X
X
X
X
High Z
X
Deep
Power-Down
1,3
VIL
X
X
X
X
X
X
High Z
VOH
Manufacturer
ID
1,4,9
VIH
VIL
VIL
VIH
X
↑
VIL
0089H
VOH
Device ID
1,4,8,9
VIH
VIL
VIL
VIH
X
↑
VIH
66A8H
VOH
Write
1,5,6,9
VIH
VIL
VIH
VIL
X
X
X
DIN
X
Latch Read
Address
Inhibit
Latching
Read Address
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for data
pins depending on whether or not OE# is active.
2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended, or the device is in deep power-down mode,
RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation
is in progress.
3. RP# at GND ± 0.2V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID
codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for erase, data program, or lock-block operations can only be completed successfully when VPP = VPPH1 or
VPP = VPPH2.
6. While the WSM is running, RY/BY# stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is
not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a
write operation).
8. The 28F016XS shares an identical device identifier with the 28F016XD.
9. CE0–1# at VIL is defined as both CE0# and CE1# low, and CE0–1# at VIH is defined as either CE0# or CE1# high.
10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address A1 = 0 selects the even bank and
A1 = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
16
E
4.2
28F016XS FLASH MEMORY
Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Mode
Notes
RP#
CE0–1#
OE#
WE#
ADV#
CLK
A0
DQ0–7
RY/BY#
1,9,10
VIH
VIL
X
VIH
VIL
↑
X
X
X
1,9
VIH
VIL
X
VIH
VIH
↑
X
X
X
Read
1,2,7,9
VIH
VIL
VIL
VIH
X
↑
X
DOUT
X
Output
Disable
1,6,7,9
VIH
VIL
VIH
VIH
X
X
X
High Z
X
Standby
1,6,7,9
VIH
VIH
X
X
X
X
X
High Z
X
Deep
Power-Down
1,3
VIL
X
X
X
X
X
X
High Z
VOH
Manufacturer
ID
1,4,9
VIH
VIL
VIL
VIH
X
↑
VIL
89H
VOH
Device ID
1,4,8,9
VIH
VIL
VIL
VIH
X
↑
VIH
A8H
VOH
Write
1,5,6,9
VIH
VIL
VIH
VIL
X
X
X
DIN
X
Latch Read
Address
Inhibit
Latching
Read Address
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for data
pins depending on whether or not OE# is active.
2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended, or the device is in deep power-down mode,
RY/BY# will be at VOH if it is tied to VCC through a resistor. RY/BY# at VOH is independent of OE# while a WSM operation
is in progress.
3. RP# at GND ± 0.2V ensures the lowest deep power-down current.
4. A0 and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. A0 and A1 at VIH provide device ID
codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for erase, data program, or lock-block operations can only be completed successfully when VPP = VPPH1 or
VPP = VPPH2.
6. While the WSM is running, RY/BY# stays at VOL until all operations are complete. RY/BY# goes to VOH when the WSM is
not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations (for example, a Status Register read during a
program operation).
8. The 28F016XS shares an identical device identifier with the 28F016XD.
9. CE0–1# at VIL is defined as both CE0# and CE1# low, and CE0–1# at VIH is defined as either CE0# or CE1# high.
10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address A1 = 0 selects the even bank and
A1 = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
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28F016XS FLASH MEMORY
4.3
28F008SA—Compatible Mode Command Bus Definitions
First Bus Cycle
Command
Notes
Read Array
E
Second Bus Cycle
(4)
Oper
Addr
Data
Oper
Addr
Data(4)
Write
X
xxFFH
Read
AA
AD
Intelligent Identifier
1
Write
X
xx90H
Read
IA
ID
Read Compatible Status Register
2
Write
X
xx70H
Read
X
CSRD
Clear Status Register
3
Write
X
xx50H
Program
Write
X
xx40H
Write
PA
PD
Alternate Program
Write
X
xx10H
Write
PA
PD
Block Erase/Confirm
Write
X
xx20H
Write
BA
xxD0H
Erase Suspend/Resume
Write
X
xxB0H
Write
X
xxD0H
ADDRESS
DATA
AA = Array Address
AD = Array Data
BA = Block Address
CSRD = CSR Data
IA = Identifier Address
ID = Identifier Data
PA = Program Address
PD = Program Data
X = Don’t Care
NOTES:
1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters data program, erase, or suspend operations.
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register
definitions.
4. The upper byte of the data bus (D8–15) during command writes is a “Don’t Care” in x16 operation of the device.
18
E
4.4
28F016XS FLASH MEMORY
28F016XS—Enhanced Command Bus Definitions
First Bus Cycle
Command
Read Extended Status Register
Second Bus Cycle
Notes
Oper
Addr
Data
Oper
Addr
Data(4)
1
Write
X
xx71H
Read
RA
GSRD
BSRD
Write
X
xx77H
Write
BA
xxD0H
Lock Block/Confirm
(4)
Upload Status Bits/Confirm
2
Write
X
xx97H
Write
X
xxD0H
Device Configuration
3
Write
X
xx96H
Write
X
DCCD
ADDRESS
DATA
BA = Block Address
AD = Array Data
RA = Extended Register Address
BSRD = BSR Data
PA = Program Address
GSRD = GSR Data
X = Don’t Care
DCCD = Device Configuration Code Data
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register memory maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. This command sets the SFI Configuration allowing the device to be optimized for the specific sytem operating frequency.
4. The upper byte of the Data bus (D8–15) during command writes is a “Don’t Care” in x16 operation of the device.
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E
28F016XS FLASH MEMORY
4.5
Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
R
R
7
6
5
4
3
2
1
0
NOTES:
CSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
RY/BY# output or WSMS bit must be checked to
determine completion of an operation (erase,
erase suspend, or data program) before the
appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
0 = Erase In Progress/Completed
CSR.5 = ERASE STATUS
1 = Error In Block Erasure
0 = Successful Block Erase
If DWS and ES are set to “1” during an erase
attempt, an improper command sequence was
entered. Clear the CSR and attempt the
operation again.
CSR.4 = DATA WRITE STATUS
1 = Error in Data Program
0 = Data Program Successful
CSR.3 = VPP STATUS
1 = VPP Error Detect, Operation Abort
0 = VPP OK
The VPPS bit, unlike an A/D converter, does not
provide continuous indication of VPP level. The
WSM interrogates VPP’s level only after the Data
Program or Erase command sequences have
been entered, and informs the system if V PP has
not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPLK(max)
and VPPH1(min), between VPPH1(max) and
VPPH2(min), and above VPPH2(max).
CSR.2–0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
20
E
4.6
28F016XS FLASH MEMORY
Global Status Register
WSMS
OSS
DOS
R
R
R
R
R
7
6
5
4
3
2
1
0
NOTES:
GSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
RY/BY# output or WSMS bit must be checked to
determine completion of an operation (block lock,
suspend, Upload Status Bits, erase or data
program) before the appropriate Status bit (OSS
or DOS) is checked for success.
GSR.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
0 = Operation in Progress/Completed
GSR.5 = DEVICE OPERATION STATUS
1 = Operation Unsuccessful
0 = Operation Successful or Currently
Running
GSR.4–0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the GSR.
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E
28F016XS FLASH MEMORY
4.7
Block Status Register
BS
BLS
BOS
R
R
VPPS
VPPL
R
7
6
5
4
3
2
1
0
NOTES:
BSR.7 = BLOCK STATUS
1 = Ready
0 = Busy
RY/BY# output or BS bit must be checked to
determine completion of an operation (block lock,
suspend, erase or data program) before the
appropriate Status bits (BOS, BLS) is checked
for success.
BSR.6 = BLOCK LOCK STATUS
1 = Block Unlocked for Program/Erase
0 = Block Locked for Program/Erase
BSR.5 = BLOCK OPERATION STATUS
1 = Operation Unsuccessful
0 = Operation Successful or
Currently Running
BSR.2 = VPP STATUS
1 = VPP Error Detect, Operation Abort
0 = VPP OK
BSR.1 = VPP LEVEL
1 = VPP Detected at 5.0V ± 10%
0 = VPP Detected at 12.0V ± 5%
BSR.1 is not guaranteed to report accurate
feedback between the VPPH1 and VPPH2 voltage
ranges. Programs and erases with VPP between
VPPLK(max) and VPPH1 (min), between
VPPH1(max) and VPPH2(min), and above
VPPH2(max) produce spurious results and should
not be attempted.
BSR.4,3,0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the BSRs.
22
E
4.8
28F016XS FLASH MEMORY
Device Configuration Code
R
R
SFI2
SFI1
SFI0
R
R
RB
7
6
5
4
3
2
1
0
NOTES:
DCC.5–DCC.3 = SFI CONFIGURATION
(SFI2-SFI0)
001 = SFI Configuration 1
010 = SFI Configuration 2
011 = SFI Configuration 3
100 = SFI Configuration 4
(Default)
Default SFI Configuration on power-up or return
from deep power-down mode is 4, allowing
system boot from the 28F016XS at any
frequency up to the device's maximum
frequency. Undocumented combinations of
SFI2-SFI0 are reserved by Intel Corporation for
future implementations and should not be used.
DCC.0 = RY/BY# CONFIGURATION
(RB)
1 = Level Mode (Default)
Undocumented combinations of RB are reserved
by Intel Corporation for future implementations
and should not be used.
DCC.7–DCC.6, DCC.2–DCC.1 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use. Set these bits to “0” when modifying the Device Configuration
Code.
4.9
SFI Configuration Table
SFI
Configuration
Notes
28F016XS-15
Frequency (MHz)
28F016XS-20
Frequency (MHz)
28F016XS-25
Frequency (MHz)
4
1
50 (and below)
50 (and below)
40 (and below)
3
50 (and below)
37.5 (and below)
30 (and below)
2
33 (and below)
25 (and below)
20 (and below)
1
16.7 (and below)
12.5 (and below)
10 (and below)
NOTE:
1. Default SFI Configuration after power-up or return from deep power-down mode via RP# low.
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E
28F016XS FLASH MEMORY
5.0
ELECTRICAL SPECIFICATIONS
5.1
Absolute Maximum Ratings*
Temperature Under Bias ....................0°C to +80°C
Storage Temperature ................... –65°C to +125°C
NOTICE: This is a production datasheet. The
specifications are subject to change without notice. Verify
with your local Intel Sales office that you have the latest
datasheet before finalizing a design.
*WARNING: Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the
“Operating Conditions” is not recommended and
extended exposure beyond the "Operating Conditions"
may affect device reliability.
VCC = 3.3V ± 5% Systems
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
Ambient Temperature
TA
Operating Temperature, Commercial
1
0
70
°C
VCC
VCC with Respect to GND
2
–0.2
7.0
V
VPP
VPP Supply Voltage with Respect to GND
2,3
–0.2
14.0
V
–0.5
VCC
+ 0.5
V
V
Voltage on any Pin (except VCC,VPP) with
Respect to GND
2,5
I
Current into any Non-Supply Pin
5
± 30
mA
IOUT
Output Short Circuit Current
4
100
mA
VCC = 5.0V ± 5% Systems
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
Ambient Temperature
TA
Operating Temperature, Commercial
1
0
70
°C
VCC
VCC with Respect to GND
2
–0.2
7.0
V
VPP
VPP Supply Voltage with Respect to GND
2,3
–0.2
14.0
V
V
Voltage on any Pin (except VCC,VPP) with
Respect to GND
2,5
–2.0
7.0
V
I
Current into any Non-Supply Pin
5
± 30
mA
IOUT
Output Short Circuit Current
4
100
mA
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to –2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is VCC +0.5V which may overshoot to VCC +2.0V for periods <20 ns.
3. Maximum DC voltage on VPP may overshoot to +14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. This specification also applies to pins marked “NC.”
24
E
5.2
28F016XS FLASH MEMORY
Capacitance
For a 3.3V ± 5% System:
Symbol
Parameter
Notes
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
6
8
pF
TA = +25°C, f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA = +25°C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
50
pF
For the 28F016XS-20
and 28F016XS-25
1, 2
For 5.0V ± 5% System:
Symbol
Parameter
Notes
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
6
8
pF
TA = +25°C, f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA = +25°C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
100
pF
For the 28F016XS-20
30
pF
For the 28F016XS-15
1, 2
NOTE:
1. Sampled, not 100% tested. Guaranteed by design.
2. To obtain iBIS models for the 28F016XS, please contact your local Intel/Distribution Sales Office.
25
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E
28F016XS FLASH MEMORY
5.3
Transient Input/Output Reference Waveforms
2.4
2.0
INPUT
2.0
OUTPUT
TEST POINTS
0.8
0.45
0.8
0532_07
AC test inputs are driven at VOH (2.4 VTTL) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins at VIH
(2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 8. Transient Input/Output Reference Waveform (VCC = 5.0V ± 5%)
for Standard Testing Configuration(1)
3.0
INPUT
1.5
TEST POINTS
1.5
OUTPUT
0.0
0532_08
AC test inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0.” Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
Figure 9. Transient Input/Output Reference Waveform (VCC = 3.3V ± 5%)
High Speed Reference Waveform(2) (VCC = 5.0V ± 5%)
NOTES:
1. Testing characteristics for 28F016XS-20 at 5V VCC.
2. Testing characteristics for 28F016XS-15 at 5V VCC and 28F016XS-20/28F016XS-25 at 3.3V VCC.
26
E
5.4
28F016XS FLASH MEMORY
DC Characteristics
VCC = 3.3V ± 5%, T A = 0°C to +70°C
3/5# = Pin Set High for 3.3V Operations
Parameter
Notes
Max
Units
ILI
Symbol
Input Load Current
1
Min
Typ
±1
µA
VCC = VCC Max
VIN = VCC or GND
ILO
Output Leakage
Current
1
± 10
µA
VCC = VCC Max
VOUT = VCC or GND
ICCS
VCC Standby
Current
70
130
µA
1
4
mA
VCC = VCC Max
CE0#, CE1#, RP# = VCC ±
0.2V
BYTE#, WP#, 3/5# = V CC ±
0.2V or GND ± 0.2V
VCC = VCC Max
CE0#, CE1#, RP# = VIH
BYTE#, WP#, 3/5# = V IH or
VIL
1
2
5
µA
1,5
ICCD
VCC Deep
Power-Down
Current
ICCR1
VCC Word/Byte
Read Current
1,4,5
65
85
mA
ICCR2
VCC Word/Byte
Read Current
1,4,
5,6
60
75
mA
Test Conditions
RP# = GND ± 0.2V
BYTE# = VCC ± 0.2V or
GND ± 0.2V
VCC = VCC Max
CMOS: CE0# ,CE1# = GND
± 0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V,
Inputs = GND ± 0.2V or
VCC ± 0.2V
4-Location Access
Sequence: 3-1-1-1
(clocks)
f = 25 MHz, I OUT = 0 mA
VCC = VCC Max
CMOS: CE0#, CE1# = GND
± 0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V,
Inputs = GND ± 0.2V or
VCC ± 0.2V
4-Location Access
Sequence: 3-1-1-1
(clocks)
f = 16 MHz, I OUT = 0 mA
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E
28F016XS FLASH MEMORY
5.4
DC Characteristics (Continued)
VCC = 3.3V ± 5%, T A = 0°C to +70°C
3/5# = Pin Set High for 3.3V Operations
Symbol
ICCW
Parameter
VCC Program
Current
Notes
Min
1,6
Typ
Max
Units
8
12
mA
VPP = 12.0V ± 5%
Test Conditions
8
17
mA
VPP = 5.0V ± 10%
6
12
mA
Program in Progress
Program in Progress
ICCE
VCC Block Erase
Current
1,6
VPP = 12.0V ± 5%
Block Erase in Progress
9
17
mA
VPP = 5.0V ± 10%
Block Erase in Progress
ICCES
VCC Erase
Suspend Current
1,2
3
6
mA
CE0#, CE1# = VIH
Block Erase Suspended
IPPS
VPP Standby/Read
1
±1
± 10
µA
VPP ≤ VCC
IPPR
Current
30
200
µA
VPP > VCC
IPPD
VPP Deep PowerDown Current
VPP Program
Current
1
0.2
5
µA
RP# = GND ± 0.2V
1,6
10
15
mA
1,6
15
4
25
10
mA
mA
14
20
mA
30
200
µA
VPP = 12.0V ± 5%
Program in Progress
Program in Progress
VPP = 12.0V ± 5%
Block Erase in Progress
VPP = 5.0V ± 10%
Block Erase in Progress
VPP = VPPH1 or VPPH2
Block Erase Suspended
IPPW
IPPE
VPP Erase Current
IPPES
VPP Erase
Suspend Current
1
VIL
Input Low Voltage
6
–0.3
0.8
V
VIH
Input High Voltage
6
2.0
V
VOL
Output Low
Voltage
6
VCC
+0.3
0.4
VOH1
Output High
Voltage
6
VOH2
28
V
VCC = VCC Min
IOL = 4 mA
2.4
V
VCC = VCC Min
IOH = –2.0 mA
VCC
–0.2
V
VCC = VCC Min
IOH = –100 µA
E
5.4
28F016XS FLASH MEMORY
DC Characteristics (Continued)
VCC = 3.3V ± 5%, T A = 0°C to +70°C
3/5# = Pin Set High for 3.3V Operations
Symbol
VPPLK
VPPH1
VPPH2
VLKO
Parameter
VPP
Erase/Program
Lock Voltage
VPP during
Program/Erase
Operations
VPP during
Program/Erase
Operations
VCC
Erase/Program
Lock Voltage
Notes
Min
3,6
0.0
3
4.5
3
11.4
Typ
Max
Units
1.5
V
5.0
5.5
V
12.0
12.6
V
2.0
Test Conditions
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V or 5.0V, T = +25°C. These
currents are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICCES and ICCR.
3. Block erases, programs and lock block operations are inhibited when VPP ≤ VPPLK and not guaranteed in the ranges
between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max).
4. Automatic Power Savings (APS) reduces ICCR to 3 mA typical in static operation.
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
6. Sampled, but not 100% tested. Guaranteed by design.
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28F016XS FLASH MEMORY
5.5
DC Characteristics
VCC = 5.0V ± 5%, T A = 0°C to +70°C
3/5# = Pin Set Low for 5.0V Operations
Parameter
Notes
ILI
Input Load Current
ILO
Output Leakage
Current
ICCS
VCC Standby
Current
Symbol
Max
Units
1
±1
µA
VCC = VCC Max
VIN = VCC or GND
1
± 10
µA
VCC = VCC Max
VOUT = VCC or GND
70
130
µA
2
4
mA
VCC = VCC Max
CE0#, CE1#, RP# = VCC ±
0.2V
BYTE#, WP#, 3/5# = V CC ±
0.2V or GND ± 0.2V
VCC = VCC Max
CE0#, CE1#, RP# = VIH
BYTE#, WP#, 3/5# = VIH or
VIL
1,5
Min
Typ
ICCD
VCC Deep PowerDown Current
1
2
5
µA
ICCR1
VCC Read Current
1,4,5
120
175
mA
ICCR2
VCC Read Current
1,4,
5,6
105
150
mA
30
Test Conditions
RP# = GND ± 0.2V
BYTE# = VCC ± 0.2V or
GND ± 0.2V
VCC = VCC Max
CMOS: CE0# ,CE1# = GND
± 0.2V, BYTE# = GND ±
0.2V or VCC ± 0.2V,
Inputs = GND ± 0.2V or
VCC ± 0.2V
4-Location Access
Sequence: 3-1-1-1
(clocks)
f = 33 MHz, I OUT = 0 mA
VCC = VCC Max
CMOS: CE0#, CE1# = GND
± 0.2V, BYTE# = GND ±
0.2V, or VCC ± 0.2V,
Inputs = GND ± 0.2V or
VCC ± 0.2V
4-Location Access
Sequence: 3-1-1-1
(clocks)
f = 20 MHz, I OUT = 0 mA
E
5.5
28F016XS FLASH MEMORY
DC Characteristics (Continued)
VCC = 5.0V ± 5%, T A = 0°C to +70°C
3/5# = Pin Set Low for 5.0V Operations
Symbol
ICCW
Parameter
VCC Program
Current
Notes
Min
Typ
Max
Units
25
35
mA
1,6
Test Conditions
VPP = 12.0V ± 5%
Program in Progress
25
40
mA
VPP = 5.0V ± 10%
Program in Progress
ICCE
VCC Erase
Suspend Current
1,6
18
25
mA
VPP = 12.0V ± 5%
Block Erase in Progress
20
30
mA
VPP = 5.0V ± 10%
Block Erase in Progress
ICCES
VCC Block Erase
Current
IPPS
VPP Standby/Read
IPPR
Current
IPPD
VPP Deep PowerDown Current
VPP Program
Current
IPPW
IPPE
VPP Block Erase
Current
1,2
5
10
mA
CE0#, CE1# = VIH
Block Erase Suspended
1
±1
± 10
µA
VPP ≤ VCC
30
200
µA
VPP > VCC
1
0.2
5
µA
RP# = GND ± 0.2V
1,6
7
12
mA
17
22
mA
5
10
mA
16
20
mA
30
200
µA
VPP = 12.0V ± 5%
Program in Progress
VPP = 5.0V ± 10%
Program in Progress
VPP = 12.0V ± 5%
Block Erase in Progress
VPP = 5.0V ± 10%
Block Erase in Progress
VPP = VPPH1 or VPPH2
Block Erase Suspended
1,6
IPPES
VPP Erase
Suspend Current
VIL
Input Low Voltage
6
–0.5
0.8
V
VIH
Input High Voltage
6
2.0
V
VOL
Output Low
Voltage
6
VCC
+0.5
0.45
VOH1
Output High
Voltage
6
VOH2
1
0.85
VCC
VCC
–0.4
V
VCC = VCC Min
IOL = 5.8 mA
V
VCC = VCC Min
IOH = –2.5 mA
VCC = VCC Min
IOH = –100 µA
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E
28F016XS FLASH MEMORY
5.5
DC Characteristics (Continued)
VCC = 5.0V ± 5%, TA = 0°C to +70°C
3/5# = Pin Set Low for 5.0V Operations
Symbol
VPPLK
VPPH1
VPPH2
VLKO
Parameter
VPP
Program/Erase
Lock Voltage
VPP during
Program/Erase
Operations
VPP during
Program/Erase
Operations
VCC
Program/Erase
Lock Voltage
Notes
Min
3,6
0.0
Typ
Max
Units
1.5
V
4.5
5.0
5.5
V
11.4
12.0
12.6
V
2.0
Test Conditions
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V or 5.0V, T = +25°C. These
currents are valid for all product versions (package and speeds) and are specified for a CMOS rise/fall time (10% to 90%) of
<5 ns and a TTL rise/fall time of <10 ns.
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum of
ICCES and ICCR.
3. Block erases, programs and lock block operations are inhibited when VPP ≤ VPPLK and not guaranteed in the ranges
between VPPLK(max) and VPPH1(min), between VPPH1 (max) and VPPH2(min) and above VPPH2(max).
4. Automatic Power Saving (APS) reduces ICCR to 1 mA typical in static operation.
5. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
6. Sampled, but not 100% tested. Guaranteed by design.
32
E
5.6
28F016XS FLASH MEMORY
Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems, use the standard JEDEC cross point definitions (standard testing) or from where signals
cross 1.5V (high speed testing).
Each timing parameter consists of five characters. Some common examples are defined below:
tELCH time(t) from CE# (E) going low (L) to CLK (C) going high (H)
tAVCH time(t) from address (A) valid (V) to CLK (C) going high (H)
tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)
Pin Characters
Pin States
A
Address Inputs
H
High
C
CLK (Clock)
L
Low
D
Data Inputs
V
Valid
Q
Data Outputs
X
Driven, but Not Necessarily Valid
E
CE# (Chip Enable)
Z
High Impedance
F
BYTE# (Byte Enable)
L
Latched
G
OE# (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY/BY# (Ready Busy)
V
ADV# (Address Valid)
Y
3/5# Pin
5V
VCC at 4.5V Minimum
3V
VCC at 3.0V Minimum
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E
28F016XS FLASH MEMORY
5.7
AC Characteristics—Read Only Operations(1)
VCC = 3.3V ± 5%, T A = 0°C to +70°C
Versions(3)
Symbol
Parameter
Notes
28F016XS-20
28F016XS-25
Min
Min
Max
50
Max
Units
40
MHz
fCLK
CLK Frequency
tCLK
CLK Period
20
25
ns
tCH
CLK High Time
6
8.5
ns
tCL
CLK Low Time
6
8.5
ns
tCLCH
CLK Rise Time
4
4
ns
tCHCL
CLK Fall Time
4
4
ns
tELCH
CEX# Setup to CLK
tVLCH
6
25
35
ns
ADV# Setup to CLK
20
25
ns
tAVCH
Address Valid to CLK
20
25
ns
tCHAX
Address Hold from CLK
0
0
ns
tCHVH
ADV# Hold from CLK
0
0
ns
tGLCH
OE# Setup to CLK
20
25
ns
tCHQV
CLK to Data Delay
tPHCH
RP# High to CLK
tCHQX
Output Hold from CLK
tELQX
30
35
ns
480
480
ns
2
6
6
ns
CEX# to Output Low Z
2,6
0
0
ns
tEHQZ
CEX# High to Output High Z
2,6
tGLQX
OE# to Output Low Z
2
tGHQZ
OE# High to Output High Z
2
tOH
Output Hold from CEX# or OE#
Change, Whichever Occurs First
6
34
30
0
30
0
30
0
ns
30
0
ns
ns
ns
E
5.7
28F016XS FLASH MEMORY
AC Characteristics—Read Only Operations(1) (Continued)
VCC = 5.0V ± 5%, T A = 0°C to +70°C
Versions(3)
Symbol
28F016XS-15(4)
Parameter
Notes
Min
Max
28F016XS-20(5)
Min
66
Max
Units
50
MHz
fCLK
CLK Frequency
tCLK
CLK Period
15
20
ns
tCH
CLK High Time
3.5
6
ns
tCL
CLK Low Time
3.5
6
ns
tCLCH
CLK Rise Time
4
4
ns
tCHCL
CLK Fall Time
4
4
ns
tELCH
CEX# Setup to CLK
tVLCH
6
25
30
ns
ADV# Setup to CLK
15
20
ns
tAVCH
Address Valid to CLK
15
20
ns
tCHAX
Address Hold from CLK
0
0
ns
tCHVH
ADV# Hold from CLK
0
0
ns
tGLCH
OE# Setup to CLK
15
20
ns
tCHQV
CLK to Data Delay
tPHCH
RP# High to CLK
tCHQX
Output Hold from CLK
tELQX
20
30
ns
300
300
ns
2
5
5
ns
CEX# to Output Low Z
2,6
0
0
ns
tEHQZ
CEX# High to Output High Z
2,6
tGLQX
OE# to Output Low Z
2
tGHQZ
OE# High to Output High Z
2
tOH
Output Hold from CEX# or OE#
Change, Whichever Occurs First
6
30
0
30
0
30
0
ns
30
0
ns
ns
ns
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements.
2. Sampled, not 100% tested. Guaranteed by design.
3. Device speeds are defined as:
15 ns at VCC = 5.0V equivalent to 20 ns at VCC = 3.3V
20 ns at VCC = 5.0V equivalent to 25 ns at VCC = 3.3V
4. See the high speed AC Input/Output Reference Waveforms.
5. See the standard AC Input/Output Reference Waveforms.
6. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
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E
28F016XS FLASH MEMORY
t
CH
t CL
t
t CHCL
CLCH
t CLK
0532_09
Figure 10. CLK Waveform
CLK
ADDR
t CHAX
A1
1 CLK Periods
t AVCH
ADV#
t EHQZ
t VLCH
CEx#
t CHVH
t GHQZ
t ELCH
t ELQX
OE#
t GLCH
t GLQX
t OH
Even
Odd
Even
Odd
DATA
t CHQX
t CHQV
0532_10
NOTE:
1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank
accesses; the length of the burst access is dictated by the control CPU or bus architecture.
Figure 11. Read Timing Waveform(1)
(SFI Configuration = 1, Alternate-Bank Accesses)
36
E
28F016XS FLASH MEMORY
CLK
ADDR
t CHAX
A1
2 CLK Periods
t AVCH
ADV#
t EHQZ
t VLCH
CEx#
t CHVH
t GHQZ
t ELCH
t ELQX
OE#
t GLCH
t GLQX Even
t OH
Odd
Even
Odd
DATA
t CHQX
t CHQV
0532_11
NOTE:
1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank
accesses; the length of the burst access is dictated by the control CPU or bus architecture.
Figure 12. Read Timing Waveform(1)
(SFI Configuration = 2, Alternate-Bank Accesses)
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28F016XS FLASH MEMORY
CLK
ADDR
tCHAX
A1
3 CLK Periods
tAVCH
ADV#
t EHQZ
tVLCH
CEx#
t CHVH
tGHQZ
tELCH
tELQX
OE#
tGLCH
Even
tGLQX
tOH
Odd
Note 2
Even
Odd
Note 2
DATA
tCHQX
tCHQV
0532_12
NOTES:
1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank
accesses; the length of the burst access is dictated by the control CPU or bus architecture.
2. Depending on the actual operation frequency, a consecutive alternating bank access can be initiated one clock period
earlier. See AP-398 Designing with the 28F016XS for further information.
Figure 13. Read Timing Waveform(1)
(SFI Configuration = 3, Alternate-Bank Accesses)
38
E
28F016XS FLASH MEMORY
CLK
ADDR
tCHAX
A1
4 CLK Periods
tAVCH
ADV#
tEHQZ
tVLCH
tCHVH
CEx#
tGHQZ
tELCH
tELQX
OE#
tGLCH
Even
tGLQX
tOH
Odd
Even
Odd
DATA
tPHCH
tCHQX
tCHQV
RP#
0532_13
NOTE:
1. The 28F016XS can sustain an optimized burst access throughout the 28F016XS array assuming alternating bank
accesses; the length of the burst access is dictated by the control CPU or bus architecture.
Figure 14. Read Timing Waveform(1)
(SFI Configuration = 4, Alternating Bank Accesses)
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28F016XS FLASH MEMORY
5.8
AC Characteristics for WE#—Controlled Write Operations(1)
E
VCC = 3.3V ± 5%, T A = 0°C to +70°C
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
tVPWH1,2
VPP Setup to WE# Going
High
tPHEL
28F016XS-20
Notes
Min
Typ
Max
28F016XS-25
Min
Typ
Max
Unit
75
75
ns
3
100
100
ns
RP# Setup to CEX# Going
Low
3,7
480
480
ns
tELWL
CEX# Setup to WE# Going
Low
3,7
0
0
ns
tAVWH
Address Setup to WE#
Going High
2,6
60
60
ns
tDVWH
Data Setup to WE# Going
High
2,6
60
60
ns
tWLWH
WE# Pulse Width
60
60
ns
tWHDX
Data Hold from WE# High
2
5
5
ns
tWHAX
Address Hold from WE#
High
2
5
5
ns
tWHEH
CEX# hold from WE# High
3,7
5
5
ns
tWHWL
WE# Pulse Width High
15
15
ns
tGHWL
Read Recovery before
Write
3
0
0
ns
tWHRL
WE# High to RY/BY#
Going Low
3
tRHPL
RP# Hold from Valid
Status Register (CSR,
GSR, BSR) data and
RY/BY# High
3
0
0
ns
tPHWL
RP# High Recovery to
WE# Going Low
3
480
480
ns
tWHCH
Write Recovery before
Read
20
20
ns
tQVVL1,2
VPP Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY/BY# High
3
0
0
µs
tWHQV1
Duration of Program
Operation
3,4,
5,8
5
9
TBD
5
9
TBD
µs
tWHQV2
Duration of Block Erase
Operation
3,4
0.6
1.6
20
0.6
1.6
20
sec
40
100
100
ns
E
5.8
28F016XS FLASH MEMORY
AC Characteristics for WE#—Controlled Write Operations(1) (Continued)
VCC = 5.0V ± 5%, T A = 0°C to +70°C
Versions
Symbol
28F016XS-15
Parameter
Notes
tAVAV
Write Cycle Time
tVPWH1,2
VPP Setup to WE# Going
High
tPHEL
Min
Typ
Max
28F016XS-20
Min
Typ
Max
Unit
65
65
ns
3
100
100
ns
RP# Setup to CEX# Going
Low
3,7
300
300
ns
tELWL
CEX# Setup to WE# Going
Low
3,7
0
0
ns
tAVWH
Address Setup to WE#
Going High
2,6
50
50
ns
tDVWH
Data Setup to WE# Going
High
2,6
50
50
ns
tWLWH
WE# Pulse Width
50
50
ns
tWHDX
Data Hold from WE# High
2
0
0
ns
tWHAX
Address Hold from WE#
High
2
5
5
ns
tWHEH
CEX# hold from WE# High
3,7
5
5
ns
tWHWL
WE# Pulse Width High
15
15
ns
tGHWL
Read Recovery before
Write
3
0
0
ns
tWHRL
WE# High to RY/BY#
Going Low
3
tRHPL
RP# Hold from Valid
Status Register (CSR,
GSR, BSR) data and
RY/BY# High
3
0
0
ns
tPHWL
RP# High Recovery to
WE# Going Low
3
300
300
ns
tWHCH
Write Recovery before
Read
20
20
ns
tQVVL1,2
VPP Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY/BY# High
3
0
0
µs
tWHQV1
Duration of Program
Operation
3,4,
5,8
4.5
6
TBD
4.5
6
TBD
µs
tWHQV2
Duration of Block Erase
Operation
3,4
0.6
1.2
20
0.6
1.2
20
sec
100
100
ns
41
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INTEL CONFIDENTIAL
(until publication date)
28F016XS FLASH MEMORY
NOTES:
1. Read timings during program and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested. Guaranteed by design.
4. Program/erase durations are measured to valid Status Register (CSR) Data.
5. Program operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE# for all command program operations.
7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
8. Please contact Intel’s Application Hotline or your local sales office for current TBD information.
42
E
E
28F016XS FLASH MEMORY
CLK
NOTE 6
DEEP
POWER-DOWN
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY
WRITE READ EXTENDED
REGISTER COMMAND
READ EXTENDED
STATUS REGISTER DATA
V
IH
ADDRESSES (A)
V
IL
NOTE 1
A
t
A=RA
IN
t
AVAV
t
V
IH
ADDRESSES (A)
V
IL
NOTE 2
READ COMPATIBLE
STATUS REGISTER DATA
WHAX
AVWH
NOTE 3
A
t
t
AVAV
IN
t
AVWH
WHAX
ADV#
NOTE 6
V
IH
CEx # (E)
V
NOTE 4
IL
t
V
OE# (G)
V
t
ELWL
WHCH
IL
t
V
t
WHEH
IH
t
WHWL
t
WHQV1,2
GHWL
IH
WE# (W)
V
IL
t
t
V
IH
DATA (D/Q)
V
IL
WLWH
t
DVWH
HIGH Z
t
D
IN
WHDX
D
D
IN
t
V
RY/BY# (R)
V
D
IN
D
OUT
IN
PHWL
WHRL
OH
OL
t
V
RHPL
IH
NOTE 5
RP# (P)
V
IL
t
V
V
PP
(V)
V
V
V
t
VPWH2
QVVL2
PPH2
PPH1
t
PPLK
VPWH1
NOTE 7
t
QVVL1
IL
NOTE 8
0532_14
NOTES:
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/erase operations.
4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
5. RP# low transition is only to show tRHPL; not valid for above read and program cycles.
6. Data program/erase cycles are asynchronous; CLK and ADV# are ignored.
7. VPP voltage during data program/erase operations valid at both 12.0V and 5.0V.
8. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 15. AC Waveforms for WE#—Command Write Operations,
Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read
43
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INTEL CONFIDENTIAL
(until publication date)
28F016XS FLASH MEMORY
5.9
AC Characteristics for CEX#—Controlled Write Operations(1)
E
VCC = 3.3V ± 5%, T A = 0°C to +70°C
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
tVPEH1,2
VPP Setup to CEX# Going
High
tPHWL
28F016XS-20
Notes
Min
Typ
Max
28F016XS-25
Min
Typ
Max
Unit
80
75
ns
3,7
100
100
ns
RP# Setup to WE# Going
Low
3
480
480
ns
tWLEL
WE# Setup to CEX# Going
Low
3,7
0
0
ns
tAVEH
Address Setup to CEX#
Going High
2,6,7
60
60
ns
tDVEH
Data Setup to CEX# Going
High
2,6,7
60
60
ns
tELEH
CEX# Pulse Width
7
65
60
ns
tEHDX
Data Hold from CEX# High
2,7
10
10
ns
tEHAX
Address Hold from CEX#
High
2,7
10
10
ns
tEHWH
WE hold from CEX# High
3,7
5
5
ns
tEHEL
CEX# Pulse Width High
7
15
15
ns
tGHEL
Read Recovery before
Write
3
0
0
ns
tEHRL
CEX# High to RY/BY#
Going Low
3,7
tRHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY/BY# High
tPHEL
RP# High Recovery to
CEX# Going Low
tEHCH
Write Recovery before
Read
tQVVL1,2
VPP Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY/BY# High
tEHQV1
Duration of Program
Operation
tEHQV2
Duration of Block Erase
Operation
44
100
100
ns
3
0
0
ns
3,7
480
480
ns
20
20
ns
3
0
0
µs
3,4,5,8
5
9
TBD
5
9
TBD
µs
3,4
0.6
1.6
20
0.6
1.6
20
sec
E
5.9
28F016XS FLASH MEMORY
AC Characteristics for CEX#—Controlled Write Operations(1) (Continued)
VCC = 5.0V ± 5%, T A = 0°C to +70°C
Versions
Symbol
28F016XS-15
Parameter
Notes
tAVAV
Write Cycle Time
tVPEH1,2
VPP Setup to CEX# Going
High
tPHWL
Min
Typ
Max
28F016XS-20
Min
Typ
Max
Unit
60
60
ns
3,7
100
100
ns
RP# Setup to WE# Going
Low
3
300
300
ns
tWLEL
WE# Setup to CEX# Going
Low
3,7
0
0
ns
tAVEH
Address Setup to CEX#
Going High
2,6,7
45
45
ns
tDVEH
Data Setup to CEX# Going
High
2,6,7
45
45
ns
tELEH
CEX# Pulse Width
7
50
50
ns
tEHDX
Data Hold from CEX# High
2,7
0
0
ns
tEHAX
Address Hold from CEX#
High
2,7
5
5
ns
tEHWH
WE hold from CEX# High
3,7
5
5
ns
tEHEL
CEX# Pulse Width High
7
15
15
ns
tGHEL
Read Recovery before
Write
3
0
0
ns
tEHRL
CEX# High to RY/BY#
Going Low
3,7
tRHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY/BY# High
tPHEL
RP# High Recovery to
CEX# Going Low
tEHCH
Write Recovery before
Read
tQVVL1,2
VPP Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY/BY# High
tEHQV1
Duration of Program
Operation
tEHQV2
Duration of Block Erase
Operation
100
100
ns
3
0
0
ns
3,7
300
300
ns
20
20
ns
3
0
0
µs
3,4,5,8
4.5
6
TBD
4.5
6
TBD
µs
3,4
0.6
1.2
20
0.6
1.2
20
sec
45
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9053204.DOC
INTEL CONFIDENTIAL
(until publication date)
28F016XS FLASH MEMORY
NOTES:
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested. Guaranteed by design.
4. Program/erase durations are measured to valid Status Register (CSR) Data.
5. Program operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE# for all command write operations.
7. CEX# is defined as the latter of CE0# or CE1# going low, or the first of CE0# or CE1# going high.
8. Please contact Intel’s Application Hotline or your local sales office for current TBD information.
46
E
E
28F016XS FLASH MEMORY
CLK
NOTE 6
DEEP
POWER-DOWN
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY
WRITE READ EXTENDED
REGISTER COMMAND
READ EXTENDED
STATUS REGISTER DATA
V
IH
ADDRESSES (A)
V
IL
NOTE 1
A
t
A=RA
IN
t
AVAV
t
READ COMPATIBLE
STATUS REGISTER DATA
EHAX
AVEH
NOTE 3
V
IH
ADDRESSES (A)
V
NOTE 2
IL
A
t
t
AVAV
IN
t
AVEH
EHAX
ADV#
NOTE 6
V
IH
WE# (W)
V
IL
t
t
WLEL
EHWH
t
V
OE# (G)
V
IL
t
V
CEx#(E)
V
NOTE 4
IH
DATA (D/Q)
GHEL
IL
ELEH
DVEH
HIGH Z
t
t
D
IN
EHDX
D
D
IN
D
IN
D
OUT
IN
PHEL
t
V
RY/BY# (R)
V
t
EHQV1,2
IL
t
V
t
EHEL
IH
t
V
EHCH
IH
EHRL
OH
OL
t
V
RHPL
IH
NOTE 5
RP# (P)
V
IL
t
V
V
V
(V)
PP
V
V
t
VPEH2
QVVL2
PPH1
PPH2
t
PPLK
VPEH1
NOTE 7
t
QVVL1
IL
NOTE 8
0532_15
NOTES:
1. This address string depicts data program/erase cycles with corresponding verification via ESRD.
2. This address string depicts data program/erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during data program/erase operations.
4. CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
5. RP# low transition is only to show tRHPL; not valid for above read and program cycles.
6. Data program/erase cycles are asynchronous; CLK and ADV# are ignored.
7. VPP voltage during data program/erase operations valid at both 12.0V and 5.0V.
8. VPP voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 16. AC Waveforms for CEX#—Controlled Write Operations,
Illustrating a Two Command Write Sequence Followed by an Extended Status Register Read
47
4/15/97 9:41 AM
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INTEL CONFIDENTIAL
(until publication date)
E
28F016XS FLASH MEMORY
5.10
Power-Up and Reset Timings
VCC POWER-UP
RP#
(P)
t YHPH
t YLPH
3/5#
5.0V
(Y)
t PLYL
4.5V
3.3V
VCC
0V
(3V,5V)
t PL5V
0532_18
NOTE:
For read timings following reset see Section 5.7.
Figure 17. VCC Power-Up and RP# Reset Waveforms
Symbol
tPLYL
Parameter
Notes
Min
Max
Unit
RP# Low to 3/5# Low (High)
0
µs
3/5# Low (High) to RP# High
0
µs
0
µs
tPLYH
tYLPH
tYHPH
tPL5V
RP# Low to VCC at 4.5V (Minimum)
tPL3V
RP# Low to VCC at 3V (Min) or 3.6V (Max)
2
NOTES:
1. The tYLPH and/or tYHPH times must be strictly followed to guarantee all other read and program specifications for the
28F016XS.
2. The power supply may start to switch concurrently with RP# going low.
48
E
5.11
28F016XS FLASH MEMORY
Erase and Program Performance(3,4)
VCC = 3.3V ± 5%, V PP = 5.0V ± 5%, TA = 0°C to +70°C
Symbol
Parameter
Notes
Min
Typ(1)
Max
Units
tWHRH1A
Byte Program Time
2,5
TBD
29
TBD
µs
tWHRH1B
Word Program Time
2,5
TBD
35
TBD
µs
tWHRH2
Block Program Time
2,5
TBD
3.8
TBD
sec
Byte Program
Mode
tWHRH3
Block Program Time
2,5
TBD
2.4
TBD
sec
Word Program
Mode
Block Erase Time
2,5
TBD
2.8
TBD
sec
1.0
12
75
µs
Erase Suspend
Latency Time to Read
Test Conditions
VCC = 3.3V ± 5%, V PP = 12.0V ± 0.6V, T A = 0°C to +70°C
Symbol
Parameter
Notes
Min
Typ(1)
Max
Units
tWHRH1
Program Time
2,5
5
9
TBD
µs
tWHRH2
Block Program Time
2,5
TBD
1.2
4.2
sec
Byte Program
Mode
tWHRH3
Block Program Time
2,5
TBD
0.6
2.0
sec
Word Program
Mode
2
0.6
1.6
20
sec
1.0
9
55
µs
Block Erase Time
Erase Suspend
Latency Time to Read
Test Conditions
49
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INTEL CONFIDENTIAL
(until publication date)
E
28F016XS FLASH MEMORY
5.11
Erase and Program Performance(3,4) (Continued)
VCC = 5.0V ± 5%, VPP = 5.0V ± 5%, TA = 0°C to +70°C
Symbol
Parameter
Notes
Min
Typ(1)
Max
Units
tWHRH1A
Byte Program Time
2,5
TBD
20
TBD
µs
tWHRH1B
Word Program Time
2,5
TBD
25
TBD
µs
tWHRH2
Block Program Time
2,5
TBD
2.8
TBD
sec
Byte Program
Mode
tWHRH3
Block Program Time
2,5
TBD
1.7
TBD
sec
Word Program
Mode
Block Erase Time
2,5
TBD
2.0
TBD
sec
1.0
9
55
µs
Erase Suspend
Latency Time to Read
Test Conditions
VCC = 5.0V ± 5%, VPP = 12.0V ± 0.6V, T A = 0°C to +70°C
Symbol
Parameter
Notes
Min
Typ(1)
Max
Units
tWHRH1
Program Time
2,5
4.5
6
TBD
µs
tWHRH2
Block Program Time
2,5
TBD
0.8
4.2
sec
Byte Program
Mode
tWHRH3
Block Program Time
2,5
TBD
0.4
2.0
sec
Word Program
Mode
2
0.6
1.2
20
sec
1.0
7
40
µs
Block Erase Time
Erase Suspend
Latency Time to Read
NOTES:
1. +25°C, and nominal voltages.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled, but not 100% tested. Guaranteed by design.
5. Please contact Intel’s Application Hotline or your local sales office for current TBD information.
50
Test Conditions
E
6.0
28F016XS FLASH MEMORY
MECHANICAL SPECIFICATIONS
048928.eps
Figure 18. Mechanical Specifications of the 28F016XS 56-Lead TSOP Type I Package
Family: Thin Small Out-Line Package
Symbol
Millimeters
Minimum
Nominal
Notes
Maximum
A
1.20
A1
0.050
A2
0.965
0.995
1.025
b
0.100
0.150
0.200
c
0.115
0.125
0.135
D1
18.20
18.40
18.60
E
13.80
14.00
14.20
e
0.50
D
19.80
20.00
20.20
L
0.500
0.600
0.700
N
∅
56
0°
3°
5°
0.150
0.250
0.350
Y
Z
0.100
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INTEL CONFIDENTIAL
(until publication date)
E
28F016XS FLASH MEMORY
a
He
E
R1
A2
b
R2
L1
Detail A
D
A
B
e
1
Y
C A1
See Detail A
0528_20
Figure 19. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package
Family: Shrink Small Out-Line Package
Symbol
Millimeters
Minimum
A
Nominal
Maximum
1.80
1.90
A1
0.47
0.52
0.57
A2
1.18
1.28
1.38
B
0.25
0.30
0.40
C
0.13
0.15
0.20
D
23.40
23.70
24.00
E
13.10
13.30
13.50
e1
He
0.80
15.70
N
L1
16.00
16.30
56
0.45
0.50
Y
52
Notes
0.55
0.10
a
2°
3°
4°
b
3°
4°
5°
R1
0.15
0.20
0.25
R2
0.15
0.20
0.25
E
28F016XS FLASH MEMORY
APPENDIX A
DEVICE NOMENCLATURE AND ORDERING
INFORMATION
Product line designator for all Intel Flash products
DA2 8 F 0 1 6 XS - 1 5
Package
DA = SSOP
E = TSOP
Period of Maximum CLK
Input Frequency (ns)
Device Density
016 = 16 Mbit
Device Type
S = Synchronous Pipelined
Interface
Product Family
X = Fast Flash
0532_20
Valid Combinations
Option
Order Code
VCC = 3.3V ± 5%,
50 pF load,
1.5V I/O Levels(1)
1
E28F016XS15
28F016XS-20
2
E28F016XS20
28F016XS-25
3
DA28F016XS15
28F016XS-20
4
DA28F016XS20
28F016XS-25
VCC = 5.0V ± 5%,
100 pF load
TTL I/O Levels(1)
VCC = 5.0V ± 5%,
30 pF load
1.5V I/O Levels(1)
28F016XS-15
28F016XS-20
28F016XS-15
28F016XS-20
NOTE:
1. See Section 5.3 for Transient Input/Output Reference Waveforms.
53
4/15/97 9:41 AM
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INTEL CONFIDENTIAL
(until publication date)
28F016XS FLASH MEMORY
APPENDIX B
ADDITIONAL INFORMATION(1,2)
Order Number
E
Document/Tool
297372
16-Mbit Flash Product Family User’s Manual
292147
AP-398 Designing with the 28F016XS
292146
AP-600 Performance Benefits and Power/Energy Savings of 28F016XSBased System Designs
292163
AP-610 Flash Memory In-System Code and Data Update Techniques
292165
AB-62 Compiled Code Optimizations for Flash Memories
297500
Interfacing the 28F016XS to the i960 Microprocessor Family
297504
Interfacing the 28F016XS to the Intel486™ Microprocessor Family
294016
ER-33 ETOX™ Flash Memory Technology—Insight to Intel’s Fourth
Generation Process Innovation
297508
FLASHBuilder Utility
Contact Intel/Distribution
Sales Office
28F016XS Benchmark Utility
Contact Intel/Distribution
Sales Office
Flash Cycling Utility
Contact Intel/Distribution
Sales Office
28F016XS iBIS Model
Contact Intel/Distribution
Sales Office
28F016XS VHDL Model
Contact Intel/Distribution
Sales Office
28F016XS TimingDesigner* Library Files
Contact Intel/Distribution
Sales Office
28F016XS Orcad/Viewlogic Schematic Symbols
NOTE:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should
contact their local Intel or distribution sales office.
2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.
54