AD ADV7312 Multiformat 11-bit hdtv video encoder Datasheet

Multiformat 11-Bit
HDTV Video Encoder
ADV7312
FEATURES
High Definition Input Formats
8-, 16-, 24-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:
SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3ⴛ8-Bit 4:4:4 Input Format
HDTV RGB Supported:
RGB, RGBHV
Other High Definition Formats Using Async
Timing Mode
High Definition Output Formats
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-, 16-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Programmable DAC Gain Control
Sync Outputs in All Modes
On-Board Voltage Reference
Six 11-Bit Precision Video DACs
Purchase of licensed I2C components of Analog Devices or one of its
sublicensed Associated Companies conveys a license for the purchaser under
the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as
defined by Philips.
2-Wire Serial I2C ® Interface
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product
APPLICATIONS
Enhanced Versatile Disk (EVD) Players
SD/PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
STANDARD DEFINITION
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE FILTERS
SD TEST PATTERN
Y7–Y0
C7–C0
S7–S0
D
E
M
U
X
PROGRAMMABLE
RGB MATRIX
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
HSYNC
VSYNC
BLANK
CLKIN_A
CLKIN_B
TIMING
GENERATOR
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
ADV7312
11-BIT
DAC
O
V
E
R
S
A
M
P
L
I
N
G
11-BIT
DAC
11-BIT
DAC
11-BIT
DAC
11-BIT
DAC
11-BIT
DAC
I2C
INTERFACE
GENERAL DESCRIPTION
The ADV®7312 is a high speed, digital-to-analog encoder on
a single monolithic chip. It includes six high speed video D/A
converters with TTL compatible inputs.
The ADV7312 has separate 8-, 16-bit input ports that accept
data in high definition and/or standard definition video format.
For all standards, external horizontal, vertical, and blanking
signals or EAV/SAV timing codes control the insertion of
appropriate synchronization signals into the digital data stream
and therefore the output signal.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADV7312
DETAILED FEATURES
High Definition Programmable Features (720p 1080i)
2 Oversampling (148.5 MHz)
Internal Test Pattern Generator
(Color Hatch, Black Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)
High Definition Programmable Features (525p/625p)
8 Oversampling
Internal Test Pattern Generator
(Color Hatch, Black Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)
Standard Definition Programmable Features
16 Oversampling
Internal Test Pattern Generator (Color Bars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction
Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable
Gain/Attenuation
PrPb SSAF™
Separate Pedestal Control on Component and
Composite/S-Video Output
VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1
CGMS/WSS
Closed Captioning
Standards Directly Supported
Resolution
Frame
Rate (Hz)
Clk
Input (MHz)
Standard
720 480
720 576
720 483
720 480
720 576
1280 720
1920 1080
1920 1080
29.97
25
59.94
59.94
50
60
30
25
27
27
27
27
27
74.25
74.25
74.25
ITU-R BT.656
ITU-R BT.656
SMPTE 293M
BTA T-1004
ITU-R BT.1362
SMPTE 296M
SMPTE 274M
SMPTE 274M*
Other standards are supported in Async Timing Mode.
*SMPTE 274M-1998: System no. 6
DETAILED FUNCTIONAL BLOCK DIAGRAM
HD PIXEL
INPUT
CLKIN_B
Y
DEINTER- CR
LEAVE
CB
TEST
PATTERN
SHARPNESS
AND
ADAPTIVE
FILTER
CONTROL
Y COLOR
CR COLOR
CB COLOR
DAC
PS 8
HDTV 2
4:2:2
TO
4:4:4
DAC
P_HSYNC
P_VSYNC
P_BLANK
TIMING
GENERATOR
CLOCK
CONTROL
AND PLL
DAC
U
UV SSAF
S_HSYNC
S_VSYNC
S_BLANK
V
TIMING
GENERATOR
RGB
MATRIX
DAC
SD 16
DAC
CLKIN_A
CB
SD PIXEL
INPUT
DEINTER- CR
LEAVE
Y
TEST
PATTERN
DNR
GAMMA
COLOR
CONTROL
LUMA
AND
CHROMA
FILTERS
SYNC
INSERTION
2 OVERSAMPLING
FSC
MODULATION
CGMS
WSS
DAC
HDTV
SD
Standard Definition Video, conforming to
ITU-R BT.601/ITU-R BT.656.
High Definition Television Video, conforming to
SMPTE 274M or SMPTE 296M.
YCrCb
SD, PS, or HD Component Digital Video.
HD
High Definition Video, i.e., Progressive Scan or HDTV.
YPrPb
SD, PS, or HD Component Analog Video.
PS
Progressive Scan Video, conforming to SMPTE 293M,
ITU-R BT.1358, BTAT-1004EDTV2, or BTA1362.
TERMINOLOGY
–2–
REV. 0
ADV7312
CONTENTS
PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . .
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD SHARPNESS FILTER CONTROL AND ADAPTIVE
FILTER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . .
HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . .
HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . .
HD Sharpness Filter and Adaptive Filter Application
Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SD Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . .
Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . .
DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . .
SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . .
BOARD DESIGN AND LAYOUT CONSIDERATIONS .
DAC Termination and Layout Considerations . . . . . . . .
Video Output Buffer and Optional Output Filter . . . . . . .
PCB Board Layout Considerations . . . . . . . . . . . . . . . . .
Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 1—COPY GENERATION MANAGEMENT
SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PS CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . .
SD CGMS Data Registers 2–0 . . . . . . . . . . . . . . . . . . . . .
HD/PS CGMS [Address 12h, Bit 6] . . . . . . . . . . . . . . . .
Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . .
CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 2—SD WIDE SCREEN SIGNALING . . . . . .
APPENDIX 3—SD CLOSED CAPTIONING . . . . . . . . . .
APPENDIX 4—TEST PATTERNS . . . . . . . . . . . . . . . . . .
APPENDIX 5—SD TIMING MODES . . . . . . . . . . . . . . .
Mode 0 (CCIR-656)—Slave Option . . . . . . . . . . . . . . . .
Mode 0 (CCIR-656)—Master Option . . . . . . . . . . . . . . .
Mode 1—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1—Master Option . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2—Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2—Master Option . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3—Master/Slave Option . . . . . . . . . . . . . . . . . . . . .
APPENDIX 6—HD TIMING . . . . . . . . . . . . . . . . . . . . . .
APPENDIX 7—VIDEO OUTPUT LEVELS . . . . . . . . . . .
HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . .
RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YPrPb Levels—SMPTE/EBU N10 . . . . . . . . . . . . . . . . .
APPENDIX 8—VIDEO STANDARDS . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 14
THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 14
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 15
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 16
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Subaddress Register (SR7–SR0) . . . . . . . . . . . . . . . . . . . 17
INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 30
Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . . 30
Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . . 30
Simultaneous Standard Definition and Progressive Scan
or HDTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz . . . 31
OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 33
TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 34
HD TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SD Real-Time Control, Subcarrier Reset,
and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 38
Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . . 38
Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 40
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 41
COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 45
HD Y Level, HD Cr Level, HD Cb Level . . . . . . . . . . . . 45
HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 45
SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 45
SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
REV. 0
–3–
47
48
49
49
49
50
52
53
53
53
53
53
53
53
53
54
54
55
55
55
57
57
57
57
59
59
59
59
59
59
61
62
63
66
66
67
68
69
70
71
72
73
74
74
75
76
80
82
ADV7312–SPECIFICATIONS
(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375–3.6 V, VREF = 1.235 V,
RSET = 3040 ⍀, RLOAD = 300 ⍀. All specifications TMIN to TMAX (0ⴗC to 70ⴗC), unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions
1
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity2, +ve
Differential Nonlinearity2, –ve
DIGITAL OUTPUTS
Output Low Voltage, VOL
Output High Voltage, VOH
Three-State Leakage Current
Three-State Output Capacitance
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current
Input Capacitance, CIN
ANALOG OUTPUTS
Full-Scale Output Current
Output Current Range
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Capacitance, COUT
VOLTAGE REFERENCE
Internal Reference Range, VREF
External Reference Range, VREF
VREF Current4
POWER REQUIREMENTS
Normal Power Mode
IDD5
11
1.5
0.5
1.0
Bits
LSB
LSB
LSB
0.4 [0.4]3
2.4[2.0]
3
± 1.0
2
2
0.8
3
2
4.1
4.1
0
1.15
1.15
4.33
4.33
1.0
1.0
7
1.235
1.235
± 10
4.6
4.6
1.4
1.3
1.3
V
V
µA
pF
V
V
µA
pF
V
V
µA
IDD_IO
IAA7, 8
Sleep Mode
IDD
IAA
IDD_IO
200
10
250
µA
µA
µA
0.01
%/%
POWER SUPPLY REJECTION RATIO
45
VIN = 2.4 V
mA
mA
%
V
pF
170
110
95
172
1.0
39
1906
ISINK = 3.2 mA
ISOURCE = 400 µA
VIN = 0.4 V, 2.4 V
mA
mA
mA
mA
mA
mA
SD Only [16⫻]
PS Only [8⫻]
HDTV Only [2⫻]
SD[16⫻, 8-bit] + PS[8⫻, 16-bit]
NOTES
1
Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.
2
DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL,
the actual step value lies below the ideal step value.
3
Value in brackets for V DD_IO = 2.375 V–2.75 V.
4
External current required to overdrive internal V REF.
5
IDD, the circuit current, is the continuous current required to drive the digital core.
6
Guaranteed maximum by characterization.
7
IAA is the total current required to supply all DACs including the V REF circuitry and the PLL circuitry.
8
All DACs on.
Specifications subject to change without notice.
–4–
REV. 0
ADV7312
DYNAMIC SPECIFICATIONS
(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V, VREF = 1.235 V,
RSET = 3040 , RLOAD = 300 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted.)
Parameter
PROGRESSIVE SCAN MODE
Luma Bandwidth
Chroma Bandwidth
SNR
HDTV MODE
Luma Bandwidth
Chroma Bandwidth
STANDARD DEFINITION MODE
Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma/Luma Intermodulation
Chroma/Luma Gain Inequality
Chroma/Luma Delay Inequality
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
Differential Gain
Differential Phase
SNR
Min
Typ
Unit
Test Conditions
12.5
5.8
65.6
72
MHz
MHz
dB
dB
Luma ramp unweighted
Flat field full bandwidth
30
13.75
MHz
MHz
0.4
0.4
1.2
–0.2
0
97.0
–1.1
0.5
84
75.2
0.20
0.15
59.1
77.1
°
Specifications subject to change without notice.
REV. 0
–5–
Max
%
±%
±°
±%
±%
ns
±%
dB
dB
%
°
dB
dB
Referenced to 40 IRE
NTSC
NTSC
Luma ramp
Flat field full bandwidth
ADV7312
TIMING SPECIFICATIONS
(VAA = 2.375 V–2.625 V, VDD = 2.375 V–2.625 V; VDD_IO = 2.375 V–3.6 V, VREF = 1.235 V, RSET = 3040 ,
RLOAD = 300 . All specifications TMIN to TMAX (0C to 70C), unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
ns
Test Conditions
1
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
0
0.6
1.3
0.6
0.6
100
300
300
0.6
100
ANALOG OUTPUTS
Analog Output Delay2
Output Skew
CLOCK CONTROL AND PIXEL PORT3
fCLK
fCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t111
Data Hold Time, t121
SD Output Access Time, t13
SD Output Hold Time, t14
HD Output Access Time, t13
HD Output Hold Time, t14
PIPELINE DELAY4
7
1
First clock generated after this period
relevant for repeated start condition
ns
ns
27
81
40
40
2.0
2.0
15
5.0
14
5.0
63
76
35
41
36
MHz
MHz
% of one clk cycle
% of one clk cycle
ns
ns
ns
ns
ns
ns
Progressive scan mode
HDTV mode/async mode
clk cycles
clk cycles
clk cycles
clk cycles
clk cycles
SD [2, 16]
SD component mode [16]
PS [1]
PS [8]
HD [2, 1]
NOTES
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: C[7:0]; Y[7:0], S[7:0]
Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.
4
SD, PS = 27 MHz, HD = 74.25 MHz.
Specifications subject to change without notice.
–6–
REV. 0
ADV7312
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
t13
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 1. HD Only 4:2:2 Input Mode [Input Mode 010]; PS Only 4:2:2 Input Mode [Input Mode 001]
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7–C0
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
t11
S7–S0
Cr0
Cr1
t13
Cr2
Cr3
Cr4
Cr5
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001]
REV. 0
–7–
ADV7312
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
G0
G1
G2
G3
G4
G5
C7–C0
B0
B1
B2
B3
B4
B5
t11
R0
S7–S0
t13
R1
R2
R3
R4
R5
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
t13 = OUTPUT ACCESS TIME
t14 = OUTPUT HOLD TIME
Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010]
CLKIN_B*
t9
CONTROL
INPUTS
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
Cb0
Y0
Cr0
Y1
t12
Crxxx
Yxxx
t12
t11
t11
t13
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
*CLKIN_B MUST BE USED IN THIS PS MODE.
Figure 4. PS 4:2:2 8-Bit Interleaved at 27 MHz HSYNC/VSYNC Input Mode [Input Mode 100]
–8–
REV. 0
ADV7312
CLKIN_A
t9
CONTROL
INPUTS
t10
P_VSYNC,
P_HSYNC,
P_BLANK
Y7–Y0
Cb0
Y0
Cr0
Y1
Yxxx
t13
t12
t11
Crxxx
t14
CONTROL
OUTPUTS
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
Figure 5. PS 4:2:2 1 8-Bit Interleaved at 54 MHz HSYNC/ VSYNC Input Mode [Input Mode 111]
CLKIN_B*
t9
3FF
Y7–Y0
t10
00
00
XY
t12
Cb0
Y0
Cr0
Y1
t12
t11
t11
t13
CONTROL
OUTPUTS
t14
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
*CLKIN_B USED IN THIS PS ONLY MODE.
Figure 6. PS Only 4:2:2 1 8-Bit Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100]
CLKIN_A
t9
Y7–Y0
3FF
t11
t10
00
00
XY
Cb0
Y0
Cr0
Y1
t13
t12
t14
CONTROL
OUTPUTS
t9 = CLOCK HIGH TIME
t10 = CLOCK LOW TIME
t11 = DATA SETUP TIME
t12 = DATA HOLD TIME
NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0 01 BIT-1
Figure 7. PS Only 4:2:2 1 8-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]
REV. 0
–9–
ADV7312
CLKIN_B
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
HD INPUT
t11
CLKIN_A
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
S7–S0
t9
t12
t10
SD INPUT
Cb0
Y0
Y1
Cr0
Cb1
Y2
t11
Figure 8. HD 4:2:2 and SD (8-Bit) Simultaneous Input Mode [Input Mode 101: SD Oversampled]
[Input Mode 110: HD Oversampled]
CLKIN_B
t9
CONTROL
INPUTS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C7–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
PS INPUT
t11
CLKIN_A
CONTROL
INPUTS
S_HSYNC,
S_VSYNC,
S_BLANK
S7–S0
t9
t12
t10
SD INPUT
Cb0
Y0
Y1
Cr0
Cb1
Y2
t11
Figure 9. PS (4:2:2) and SD (8-Bit) Simultaneous Input Mode [Input Mode 011]
–10–
REV. 0
ADV7312
CLKIN_B
t10
t9
CONTROL
INPUTS
P_HSYNC,
P_VSYNC,
P_BLANK
Y7–Y0
PS INPUT
Cb0
t11
Y0
Cr0
Crxxx
Y1
t12
Yxxx
t12
t11
CLKIN_A
CONTROL
INPUTS
t9
S_HSYNC,
S_VSYNC,
S_BLANK
t12
t10
SD INPUT
S7–S0
Cb0
Y0
Cr0
Cb1
Y1
Y2
t11
Figure 10. PS (8-Bit) and SD (8-Bit) Simultaneous Input Mode [Input Mode 100]
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC,
S_BLANK
S7–S0/Y7–Y0*
IN SLAVE MODE
Cb0
Cr0
Cb2
Cr2
Cb4
t11
Cr4
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 11. 8-Bit SD Only Pixel Input Mode [Input Mode 000]
REV. 0
–11–
ADV7312
CLKIN_A
t9
CONTROL
INPUTS
t12
t10
S_HSYNC,
S_VSYNC,
S_BLANK
IN SLAVE MODE
Y0
S7–S0/Y7–Y0*
Cb0
C7–C0
Y1
Y2
Y3
Cr0
Cb2
Cr2
t11
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 12. 16-Bit SD Only Pixel Input Mode [Input Mode 000]
P_HSYNC
P_VSYNC
a
P_BLANK
Y7–Y0
Y0
Y1
Y2
Y3
C7–C0
Cb0
Cr0
Cr1
Cb1
b
a = 16 CLKCYCLES FOR 525p
a = 12 CLKCYCLES FOR 626p
a = 44 CLKCYCLES FOR 1080i @ 30Hz, 25Hz
a = 70 CLKCYCLES FOR 720p
AS RECOMMENDED BY STANDARD
b(MIN) = 122 CLKCYCLES FOR 525p
b(MIN) = 132 CLKCYCLES FOR 625p
b(MIN) = 236 CLKCYCLES FOR 1080i @ 30Hz, 25Hz
b(MIN) = 300 CLKCYCLES FOR 720p
Figure 13. HD 4:2:2 Input Timing Diagram
–12–
REV. 0
ADV7312
P_HSYNC
P_VSYNC
a
P_BLANK
Y7–Y0
Cb
Cr
Y
Y
b
a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p
Figure 14. PS 4:2:2 1 8-Bit Interleaved Input Timing Diagram
S_HSYNC
S_VSYNC
PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES
S_BLANK
S7–S0/Y7–Y0*
Cb
PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 15. SD Timing Input for Timing Mode 1
t3
t5
t3
SDA
t1
t6
SCLK
t2
t4
t7
Figure 16. MPU Port Timing Diagram
REV. 0
Y
–13–
t8
Cr
Y
ADV7312
The ADV7312 is a Pb-free environmentally friendly product.
It is manufactured using the most up-to-date materials and
processes. The coating on the leads of each device is 100%
pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to
255°C (± 5°C).
ABSOLUTE MAXIMUM RATINGS*
VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V
VDD_IO to IO_GND . . . . . . . . . . . . –0.3 V to VDD_IO to +0.3 V
Ambient Operating Temperature (TA) . . . . . . . . . 0°C to 70°C
Storage Temperature (TS) . . . . . . . . . . . . . . . –65°C to +150°C
Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . . 260°C
In addition it is backward compatible with conventional SnPb
soldering processes. This means that the electroplated Sn coating
can be soldered with Sn/Pb solder pastes at conventional reflow
temperatures of 220°C to 235°C.
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE*
THERMAL CHARACTERISTICS
θJC = 11°C/W
θJA = 47°C/W
Package
Description
Model
ADV7312KST
Plastic Quad Flat Package
EVAL-ADV7312EB Evaluation Board
Package
Option
ST-64-2
*Analog output short circuit to any power supply or common can be of an
indefinite duration.
S_VSYNC
S_HSYNC
DGND
DGND
S0
S1
VDD
S2
DGND
S3
S4
S5
S6
S7
CLKIN_B
GND_IO
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 S_BLANK
VDD_IO 1
DGND 2
PIN 1
IDENTIFIER
47 RSET1
46 VREF
DGND 3
Y0 4
45 COMP1
Y1 5
44 DAC A
Y2 6
43 DAC B
Y3 7
ADV7312
42 DAC C
Y4 8
TOP VIEW
(Not to Scale)
41 VAA
40 AGND
Y5 9
VDD 10
DGND 11
39 DAC D
Y6 12
37 DAC F
Y7 13
36 COMP2
DGND 14
35 RSET2
34 EXT_LF
38 DAC E
DGND 15
33 RESET
C0 16
CLKIN_A
RTC_SCR_TR
C7
C6
C5
C4
C3
P_VSYNC
P_BLANK
P_HSYNC
SCLK
SDA
I2C
ALSB
C2
C1
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7312 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–14–
REV. 0
ADV7312
PIN FUNCTION DESCRIPTIONS
Mnemonic
Input/Output
Function
DGND
G
Digital Ground.
AGND
G
Analog Ground.
CLKIN_A
I
Pixel Clock Input for HD Only (74.25 MHz), PS Only (27 MHz), SD Only (27 MHz).
CLKIN_B
I
Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz
(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.
COMP1,2
O
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to VAA.
DAC A
O
CVBS/Green/Y/Y Analog Output.
DAC B
O
Chroma/Blue/U/Pb Analog Output.
DAC C
O
Luma/Red/V/Pr Analog Output.
DAC D
O
In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Y/Green [HD] Analog Output.
DAC E
O
In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Pr/Red Analog Output.
DAC F
O
In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Pb/Blue [HD] Analog Output.
P_HSYNC
I
Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
P_VSYNC
I
Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
P_BLANK
I
Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.
S_BLANK
I/O
Video Blanking Control Signal for SD Only.
S_HSYNC
I/O
Video Horizontal Sync Control Signal for SD Only.
S_VSYNC
I/O
Video Vertical Sync Control Signal for SD Only.
Y7–Y0
I
SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan
data. The LSB is set up on Pin Y0.
C7–C0
I
Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data.
The LSB is set up on Pin C0.
S7–S0
I
SD or Progressive Scan/HDTV Input Port for Cr[Red/V] data in 4:4:4 input mode. LSB is set up
on Pin S0.
RESET
I
This input resets the on-chip timing generator and sets the ADV7312 into default register setting.
RESET is an active low signal.
RSET1,2
I
A 3040 Ω resistor must be connected from this pin to AGND and is used to control the amplitudes
of the DAC outputs.
SCLK
I
I2C Port Serial Interface Clock Input.
SDA
I/O
I2C Port Serial Data Input/Output.
ALSB
I
TTL Address Input. This signal sets up the LSB of the I2C address. When this pin is tied low,
the I2C filter is activated, which reduces noise on the I2C interface.
VDD_IO
P
Power Supply for Digital Inputs and Outputs.
VDD
P
Digital Power Supply.
VAA
P
Analog Power Supply.
VREF
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
EXT_LF
I
External Loop Filter for the Internal PLL.
RTC_SCR_TR I
2
IC
GND_IO
REV. 0
I
Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input.
This input pin must be tied high (VDD_IO) for the ADV7312 to interface over the I2C port.
Digital Input/Output Ground.
–15–
ADV7312
MPU PORT DESCRIPTION
The ADV7312 support a 2-wire serial (I2C compatible) microprocessor bus driving multiple peripherals. Two inputs, serial data
(SDA) and serial clock (SCL), carry information between any
device connected to the bus and the ADV7312. Each slave
device is recognized by a unique address. The ADV7312 have
four possible slave addresses for both read and write operations.
These are unique addresses for each device and are illustrated
in Figure 17. The LSB sets either a read or write operation.
Logic 1 corresponds to a read operation, while Logic 0 corresponds to
a write operation. A1 is set by setting the ALSB pin of the
ADV7312 to Logic 0 or Logic 1. When ALSB is set to 1,
there is greater input bandwidth on the I2C lines, which allows
high speed data transfers on this bus. When ALSB is set to 0,
there is reduced input bandwidth on the I2C lines, which means
that pulses of less than 50 ns will not pass into the I2C internal
controller. This mode is recommended for noisy systems.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
READ/WRITE
CONTROL
WRITE
READ
Figure 17. Slave Address = D4h
To control the various devices on the bus, the following protocol
must be followed. First the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted address.
The R/W bit determines the direction of the data.
A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then they cause an
immediate jump to the idle condition. During a given SCL high
period, the user should only issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7312 will not issue an acknowledge and will return to the idle
condition. If in auto-increment mode the user exceeds the highest
subaddress, the following action will be taken:
1. In read mode, the highest subaddress register contents
will continue to be output until the master device issues
a no-acknowledge. This indicates the end of a read.
A no-acknowledge condition is when the SDA line is not
pulled low on the ninth pulse.
SET UP BY
ALSB
0
1
The ADV7312 acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long, supporting the 7-bit addresses
plus the R/W bit. It interprets the first byte as the device address
and the second byte as the starting subaddress. There is a
subaddress auto-increment facility. This allows data to be
written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.
2. In write mode, the data for the invalid byte will not be loaded
into any subaddress register, a no-acknowledge will be issued
by the ADV7312, and the part will return to the idle condition.
Before writing to the subcarrier frequency registers, it is a
requirement that the ADV7312 has been reset at least once
after power-up.
The four subcarrier frequency registers must be updated, starting
with subcarrier frequency register 0 through subcarrier frequency
register 3. The subcarrier frequency will not update until the last
subcarrier frequency register byte has been received by the
ADV7312.
Figure 18 illustrates an example of data transfer for a write
sequence and the start and stop conditions. Figure 19 shows
bus write and read sequences.
SDATA
SCLOCK
S
1–7
8
9
START ADRR R/W ACK
1–7
8
9
SUBADDRESS ACK
1–7
DATA
8
9
P
ACK
STOP
Figure 18. Bus Data Transfer
–16–
REV. 0
ADV7312
WRITE
SEQUENCE
S
SLAVE ADDR
A(S)
SUBADDR
A(S)
DATA
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
DATA
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
A(S)
SUBADDR
A(S) S SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M)
P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
Figure 19. Read and Write Sequence
REGISTER ACCESSES
Register Programming
The MPU can write to or read from all of the registers of the
ADV7312 except the subaddress registers, which are write only
registers. The subaddress register determines which register the
next read or write operation accesses. All communications with
the part through the bus start with an access to the subaddress
register. A read/write operation is then performed from/to the
target address, which increments to the next address until a stop
command is performed on the bus.
The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless otherwise stated.
REV. 0
Subaddress Register (SR7–SR0)
The communications register is an 8-bit write only register. After
the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.
–17–
ADV7312
SR7–
SR0 Register
00h
Power Mode
Register
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Sleep Mode. With this
control enabled, the
current consumption is
reduced to µA level. All
DACs and the internal
2
PLL cct are disabled. I C
registers can be read from
and written to in Sleep
Mode.
PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the over-sampling to be
switched off.
DAC F: Power On/Off
DAC E: Power On/Off
DAC D: Power On/Off
DAC C: Power On/Off
DAC B: Power On/Off
DAC A: Power On/Off
Bit 0
Register Setting
Register Reset Values
(Shaded)
0
Sleep Mode off
FCh
1
Sleep Mode on
0
PLL on
1
PLL off
0
DAC F off
1
DAC F on
0
DAC E off
1
DAC E on
0
DAC D off
1
DAC D on
0
DAC D off
1
DAC C on
0
DAC B off
1
DAC B on
0
DAC A off
1
01h
Mode Select
Register
DAC A on
BTA T-1004 or BT.1362
Compatibility
Clock Edge
Reserved
Disabled
1
Enabled
0
Cb clocked on rising edge
1
Y clocked on rising edge
Only for PS dual edge clk mode
Only for PS interleaved input at
27 MHz
0
Clock Align
0
1
Input Mode
Y/S Bus Swap
0
Only if two input clocks are used
Must be set if the phase
delay between the two input
clocks is <9.25 ns or
>27.75 ns.
0
0
0
SD input only
0
0
1
PS input only
0
1
0
HDTV input only
0
1
1
SD and PS [16-bit]
1
0
0
SD and PS [8-bit]
1
0
1
SD and HDTV [SD
oversampled]
1
1
0
SD and HDTV [HDTV
oversampled]
1
1
1
PS only [at 54 MHz]
0
8-bit data on S bus
1
8-bit data on Y bus
–18–
38h
SD Only Mode 8-bit/16-bit
Modes
REV. 0
ADV7312
SR7–
SR0
Register
Bit Description
02h
Mode Register 0
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Test Pattern Black Bar
Bit 2
Bit 1
Bit 0
Register Setting
0
0
Zero must be written to
these bits
Disabled
Enabled
0
1
RGB Matrix
0
Sync on RGB
0
1
RGB/YUV Output
1
YUV component outputs
No Sync output
0
1
HD Sync
03h
04h
0x11h, Bit 2
must also be
enabled
Sync on all RGB outputs
RGB component outputs
0
SD Sync
20h
Disable Programmable
RGB matrix
Enable Programmable RGB
matrix
No Sync
1
1
Reset
Values
Output SD Syncs on
HSYNC output, VSYNC
output, BLANK output
0
1
No Sync output
Output HD Syncs on
HSYNC output, VSYNC
output, BLANK output
RGB Matrix 0
RGB Matrix 1
x
x
x
x
x
x
x
x
x
x
LSB for GY
LSB for RV
03h
F0h
LSB for BU
LSB for GV
LSB for GU
05h
06h
RGB Matrix 2
RGB Matrix 3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit 9–2 for GY
Bit 9–2 for GU
4Eh
0Eh
07h
08h
RGB Matrix 4
RGB Matrix 5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bit 9–2 for GV
Bit 9–2 for BU
24h
92h
09h
0Ah
RGB Matrix 6
DAC A, B, C
Output Level2
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
Bit 9–2 for RV
0%
7Ch
00h
0
0
0
0
0
0
0
1
+0.018%
0
0
0
0
0
0
1
0
…
0.036%
……
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
+7.382%
+7.5%
1
1
0
0
0
0
0
0
–7.5%
1
1
0
0
0
0
0
1
–7.382%
1
0
0
0
0
0
1
0
…
–7.364%
…….
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
–0.018%
0%
0
0
0
0
0
0
0
1
+0.018%
0
0
0
0
0
0
1
0
…
0.036%
……
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
+7.382%
+7.5%
1
1
0
0
0
0
0
0
–7.5%
1
1
0
0
0
0
0
1
–7.382%
1
0
0
0
0
0
1
0
…
–7.364%
…….
1
1
1
1
1
1
1
1
–0.018%
Positive Gain to DAC Output
Voltage
Negative Gain to DAC Output
Voltage
0Bh
DAC D, E, F
Output Level
Positive Gain to DAC Output
Voltage
Negative Gain to DAC Output
Voltage
00h
0Ch
Reserved
00h
0Dh
0Eh
Reserved
Reserved
00h
00h
0Fh
Reserved
00h
NOTES
1
For more detail, refer to Appendix 7.
2
For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.
REV. 0
–19–
ADV7312
SR7–
SR0
10h
Register
Bit Description
HD Mode
Register 1
HD Output Standard
Bit 7
Bit 6
Bit 5
Bit 4
HD Input Control Signals
HD 720p
HD Mode
Register 2
0
0
0
1
1
0
1
1
Bit 1
Bit 0
0
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
HD Test Pattern Hatch/Field
1
HD VBI Open
HD Mode
Register 3
0
0
0
1
1
1
0
1
0
1
HD Y Delay with Respect to
Falling Edge of HSYNC
0
0
0
0
0
0
1
1
1
0
0
HD CGMS
1
HD CGMS CRC
Reserved
HSYNC, VSYNC,
BLANK
EAV/SAV codes
0
1
0
1
0
1
0
Pixel data valid off
Pixel data valid on
Reserved
HD test pattern off
HD test pattern on
Hatch
00h
Field/frame
Disabled
Enabled
Disabled
–11 IRE
–6 IRE
–1.5 IRE
Disabled
Enabled
0
1
HD Color Delay with Respect
to Falling Edge of HSYNC
00h
BLANK active high
BLANK active low
Macrovision off
Macrovision on
HD Test Pattern Enable
12h
EIA770.2 output
EIA770.1 output
Output levels for full
input range
1080i
720p
HD Pixel Data Valid
HD Sharpness Filter
Reset
Values
525p
625p
0
1
HD Undershoot Limiter
Register Setting
Async Timing Mode
Reserved
0
1
HD BLANK Polarity
11h
Bit 2
0
1
HD 625p
HD Macrovision for
525p/625p
Bit 3
0
0
0
0 clk cycles
0
0
0
1
1
0
0
1
1
0
1
0
1 clk cycles
2 clk cycles
3 clk cycles
4 clk cycles
0 clk cycles
00h
1 clk cycle
2 clk cycles
3 clk cycles
4 clk cycles
Disabled
Enabled
Disabled
Enabled
–20–
REV. 0
ADV7312
SR7–
SR0 Register
13h
HD Mode
Register 4
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
HD Cr/Cb Sequence
Bit 0
Register Setting
0
Cb after falling edge of
HSYNC
Cr after falling edge of
HSYNC
0 must be written to this
bit
1
Reserved
0
HD Input Format
0
Sinc Filter on DAC D, E, F
Reserved
Disabled
1
Enabled
0 must be written to this
bit
0
Disabled
Enabled
4:4:4
4:2:2
1
0
1
HD Chroma Input
HD Double Buffering
14h
HD Mode
Register 5
0
1
Disabled
Enabled
x
HD Timing Reset
1080i Frame Rate
Reserved
0
HD VSYNC/Field Input
Lines/Frame 1
15h
HD Mode
Register 6
0
0
0
0
1
0
0
0 = Field Input
1
1 = VSYNC Input
Update field/line counter
Field/line counter free
running
0
Reserved
0
HD RGB Input
1
0
HD Sync on PrPb
1
HD Color DAC Swap
0
1
HD Gamma Curve A/B
0
1
HD Gamma Curve Enable
0
1
2
00h
0 must be written to this
bit
00h
Disabled
Enabled
Disabled
Enabled
DAC E = Pb;
DAC F = Pr
DAC E = Pr;
DAC F = Pb
Gamma Curve A
Gamma Curve B
Disabled
Enabled
Mode A
0
1
HD Adaptive Filter Enable
A low-high-low transition
resets the internal HD
timing counters
30 Hz/2200 total
samples/lines
25 Hz/2640 total
samples/lines
0 must be written to these
bits
0
1
HD Adaptive Filter Mode2
4Ch
0 must be written here.
0
0
HD Chroma SSAF
Reset
Values
0
Mode B
Disabled
1
Enabled
NOTES
1
When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are
free running and wrap around when external sync signals indicate so.
2
Adaptive Filter mode is not available in PS only @ 54 MHz input mode.
REV. 0
–21–
ADV7312
SR7–
SR0 Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
Setting
Reset
Values
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Y level value
Cr level value
A0h
80h
x
x
x
x
x
x
x
x
Cb level value
Reserved
80h
00h
1Ah
1Bh
Reserved
Reserved
00h
00h
1Ch
1Dh
Reserved
Reserved
00h
00h
1Eh
1Fh
Reserved
Reserved
00h
00h
16h
17h
HD Y Level*
HD Cr Level*
18h
19h
HD Cb Level*
20h
HD Sharpness Filter
Gain
Bit Description
HD Sharpness Filter Gain Value A
HD Sharpness Filter Gain Value B
0
0
0
0
0
0
0
1
Gain A = 0
Gain A = +1
..
0
..
1
..
1
..
1
……
Gain A = +7
1
..
0
..
0
..
0
..
Gain A = –8
……
1
1
1
1
0
0
0
0
Gain A = –1
Gain B = 0
0
..
0
..
0
..
1
..
Gain B = +1
…….
0
1
1
0
1
0
1
0
Gain B = +7
Gain B = –8
..
1
..
1
..
1
..
1
……..
Gain B = –1
00h
21h
22h
HD CGMS Data 0
HD CGMS Data 1
HD CGMS Data Bits
HD CGMS Data Bits
0
C15
0
C14
0
C13
0
C12
C19
C11
C18
C10
C17
C9
C16
C8
CGMS 19–16
CGMS 15–8
00h
00h
23h
24h
HD CGMS Data 2
HD Gamma A
HD CGMS Data Bits
HD Gamma Curve A Data Points
C7
x
C6
x
C5
x
C4
x
C3
x
C2
x
C1
x
C0
x
CGMS 7–0
A0
00h
00h
25h
HD Gamma A
HD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
A1
00h
26h
27h
HD Gamma A
HD Gamma A
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A2
A3
00h
00h
28h
29h
HD Gamma A
HD Gamma A
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A4
A5
00h
00h
2Ah
2Bh
HD Gamma A
HD Gamma A
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A6
A7
00h
00h
2Ch
2Dh
HD Gamma A
HD Gamma A
HD Gamma Curve A Data Points
HD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A8
A9
00h
00h
2Eh
2Fh
HD Gamma B
HD Gamma B
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B0
B1
00h
00h
30h
31h
HD Gamma B
HD Gamma B
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B2
B3
00h
00h
32h
33h
HD Gamma B
HD Gamma B
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B4
B5
00h
00h
34h
35h
HD Gamma B
HD Gamma B
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B6
B7
00h
00h
36h
37h
HD Gamma B
HD Gamma B
HD Gamma Curve B Data Points
HD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B8
B9
00h
00h
NOTES
Programmable gamma correction is not available in PS only @ 54 MHz input mode.
*For use with internal test pattern only.
–22–
REV. 0
ADV7312
SR7–
SR0 Register
Bit Description
38h
HD Adaptive Filter Gain 1 Value A
HD Adaptive Filter
Gain 1
HD Adaptive Filter Gain 1 Value B
39h
HD Adaptive Filter
Gain 2
HD Adaptive Filter
Gain 3
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Register
Setting
Reset
Values
0
0
..
0
0
0
..
1
0
0
..
1
0
1
..
1
Gain A = 0
Gain A = +1
……
Gain A = +7
00h
1
..
0
..
0
..
0
..
Gain A = –8
……
1
1
1
1
0
0
0
Gain A = –1
Gain B = 0
0
..
0
..
0
..
1
..
Gain B = +1
…….
0
1
1
0
1
0
1
0
Gain B = +7
Gain B = –8
..
1
..
1
..
1
..
1
……..
Gain B = –1
0
0
0
0
0
0
0
1
Gain A = 0
Gain A = +1
..
0
..
1
..
1
..
1
……
Gain A = +7
1
..
0
..
0
..
0
..
Gain A = –8
……
1
1
1
1
0
0
0
0
Gain A = –1
Gain B = 0
0
..
0
..
0
..
1
..
Gain B = +1
…….
0
1
1
0
1
0
1
0
Gain B = +7
Gain B = –8
..
1
..
1
..
1
..
1
……..
Gain B = –1
HD Adaptive Filter Gain 3 Value A
HD Adaptive Filter Gain 3 Value B
Bit 3
0
HD Adaptive Filter Gain 2 Value A
HD Adaptive Filter Gain 2 Value B
3Ah
Bit 7
0
0
0
0
0
0
0
1
Gain A = 0
Gain A = +1
..
0
..
1
..
1
..
1
……
Gain A = +7
1
..
0
..
0
..
0
..
Gain A = –8
……
1
1
1
1
0
0
0
0
Gain A = –1
Gain B = 0
0
0
0
1
Gain B = +1
..
0
..
1
..
1
..
1
…….
Gain B = +7
1
..
0
..
0
..
0
..
Gain B = –8
……..
00h
00h
3Bh
HD Adaptive Filter
Threshold A
HD Adaptive Filter Threshold A Value
1
x
1
x
1
x
1
x
x
x
x
x
Gain B = –1
Threshold A
00h
3Ch
HD Adaptive Filter
Threshold B
HD Adaptive Filter Threshold B Value
x
x
x
x
x
x
x
x
Threshold B
00h
3Dh
HD Adaptive Filter
Threshold C
HD Adaptive Filter Threshold C Value
x
x
x
x
x
x
x
x
Threshold C
00h
REV. 0
–23–
ADV7312
SR7–
SR0 Register
Bit Description
3Eh
3Fh
Reserved
Reserved
40h
SD Mode Register 0
Bit 7
Bit 6
Bit 5
Bit 2
SD Standard
SD Chroma Filter
SD Mode Register 1
Bit 3
Bit 1
Bit 0
0
0
0
1
NTSC
PAL B, D, G, H, I
1
1
0
1
PAL M
PAL N
0
0
0
0
0
1
LPF NTSC
LPF PAL
0
0
1
1
0
1
Notch NTSC
Notch PAL
1
1
0
0
0
1
SSAF Luma
Luma CIF
1
1
1
1
0
1
Luma QCIF
Reserved
0
0
0
0
0
1
1.3 MHz
0.65 MHz
0
0
1
1
0
1
1.0 MHz
2.0 MHz
1
1
0
0
0
1
Reserved
Chroma CIF
1
1
1
1
0
1
Chroma QCIF
3.0 MHz
Reserved
SD PrPb SSAF
SD DAC Output 1
0
Disabled
1
Enabled
Refer to output configuration
section
0
1
SD DAC Output 2
0
1
SD Pedestal
SD Mode Register 2
Disabled
Enabled
0
1
Disabled
Enabled
0
1
Disabled
Enabled
SD Pedestal YPrPb Output
0
1
SD Output Levels Y
0
1
SD Output Levels PrPb
SD VBI Open
SD CC Field Control
Reserved
00h
08h
Disabled
Enabled
0
1
SD Pixel Data Valid
00h
Disabled
Enabled
0
1
SD VCR FF/RW Sync
43h
Reset
Values
Refer to output configuration
section
0
1
SD Square Pixel
SD SAV/EAV Step Edge
Control
Register Setting
00h
00h
SD Luma Filter
41h
42h
Bit 4
No pedestal on YUV
7.5 IRE pedestal on YUV
Y = 700 mV/300 mV
Y = 714 mV/286 mV
0
0
700 mV p-p[PAL];
1000 mV p-p[NTSC]
0
1
1
0
700 mV p-p
1000 mV p-p
1
1
0
648 mV p-p
Disabled
1
Enabled
0
0
0
1
CC disabled
CC on odd field only
1
1
0
1
CC on odd field only
CC on both fields
1
00h
Reserved
–24–
REV. 0
ADV7312
SR7–
SR0 Register
44h
SD Mode
Register 3
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SD VSYNC-3H
Bit 0
0
1
SD RTC/TR/SCR
0
1
Subcarrier Reset
1
1
0
1
Timing Reset
RTC enabled
720 pixels
710 [NTSC]/702[PAL]
Chroma enabled
1
Chroma disabled
Enabled
1
Disabled
Disabled
0
SD Color Bars
1
SD DAC Swap
Enabled
DAC A = Luma, DAC B =
Chroma
0
1
45h
46h
Reserved
Reserved
47h
SD Mode
Register 4
DAC A = Chroma, DAC B =
Luma
00h
00h
SD PrPb Scale
SD Y Scale
0
Disabled
1
Enabled
Disabled
0
1
SD Hue Adjust
1
Enabled
Disabled
0
1
SD Luma SSAF Gain
Enabled
Disabled
0
1
Reserved
Reserved
Reserved
SD Mode
Register 5
Enabled
0 must be written to this bit
0
0
0 must be written to this bit
0 must be written to this bit
0
Reserved
Reserved
0
SD Double Buffering
0
1
SD Input Format
SD Gamma Curve
49h
SD Mode
Register 6
0
0
0
1
Enabled
8-bit Input
16-bit Input
1
1
0
1
0 must be written here
0
1
SD Gamma Control
Disabled
Enabled
0
1
Disabled
Enabled
0
1
Gamma Curve A
Gamma Curve B
SD Undershoot Limiter
SD Chroma Delay
Reserved
REV. 0
0
1
0
1
1
Disabled
– 11 IRE
– 6 IRE
0
1
Enabled
0
SD Black Burst Output on DAC
Luma
0
0
1
– 1.5 IRE
0 must be written to this bit
Disabled
Reserved
Reserved
00h
0 must be written to this bit
Disabled
0
SD Digital Noise Reduction
00h
Enabled
Disabled
0
SD Brightness
48h
00h
0
0
SD Burst
Disabled
0
0
SD Chroma
Reset
Values
VSYNC = 2.5 lines [PAL]
VSYNC = 3 lines [NTSC]
Genlock disabled
0
1
SD Active Video Length
Register Setting
0
0
0
1
Disabled
4 clk cycles
1
1
0
1
8 clk cycles
Reserved
0
0 must be written to this bit
0 must be written to this bit
0
–25–
00h
ADV7312
SR7–
SR0 Register
Bit Description
4Ah
SD Slave/Master Mode
SD Timing
Register 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SD Timing Mode
SD BLANK Input
Bit 2
Bit 1
0
0
0
1
1
1
0
1
Bit 0
Register Setting
0
1
Slave Mode
Master Mode
Mode 0
1
SD Timing Reset
4Bh
SD Timing
Register 1
0
0
Disabled
No delay
0
1
1
1
0
1
2 clk cycles
4 clk cycles
6 clk cycles
0
1
SD Min. Luma Value
x
0
–40 IRE
0
0
SD HSYNC to VSYNC Delay
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
0
1
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
–7.5 IRE
A low-high-low transition will reset
the internal SD timing counters
0
0
Ta = 1 clk cycle
0
1
1
0
Ta = 4 clk cycles
Ta = 16 clk cycles
1
1
00h
Ta = 128 clk cycles
Tb = 0 clk cycle
Tb = 4 clk cycles
Tb = 8 clk cycles
Tb = 18 clk cycles
Tc = Tb
Tc = Tb + 32 s
1 clk cycle
4 clk cycles
16 clk cycles
128 clk cycles
0
1
0
1
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Subcarrier Phase Bit 9–2
F0h
21h
00h
Extended Data on Even Fields
x
x
x
x
x
x
x
x
Extended Data Bit 7–0
00h
Extended Data on Even Fields
x
x
x
x
x
x
x
x
Extended Data Bit 15–8
00h
Data on Odd Fields
x
x
x
x
x
x
x
x
Data Bit 7–0
00h
Data on Odd Fields
x
x
x
x
x
x
x
x
Data Bit 15–8
00h
Pedestal on Odd Fields
17
16
15
14
13
12
11
10
Setting any of these bits to 1 will
disable pedestal on the line number
indicated by the bit settings
00h
SD FSC Register 2
SD FSC Register 3
SD Closed
Captioning
SD Closed
Captioning
SD Closed
Captioning
SD Pedestal
Register 0
x
x
0
0
0
0
1
SD FSC Register 0
SD FSC Register 1
SD FSC Phase
SD Closed
Captioning
0
0
HSYNC to Pixel Data Adjust
4Ch
0
SD HSYNC Width
SD HSYNC to VSYNC Rising
Edge Delay [Mode 1 Only]
VSYNC Width [Mode 2 Only]
08h
Mode 1
Mode 2
Mode 3
Enabled
0
SD Luma Delay
Reset
Values
0 clk cycles
1 clk cycle
2 clk cycles
3 clk cycles
Subcarrier Frequency Bit 7–0
Subcarrier Frequency Bit 15–8
Subcarrier Frequency Bit 23–16
Subcarrier Frequency Bit 31–24
16h
7Ch
56h
SD Pedestal
Register 1
Pedestal on Odd Fields
25
24
23
22
21
20
19
18
57h
SD Pedestal
Register 2
Pedestal on Even Fields
17
16
15
14
13
12
11
10
00h
58h
SD Pedestal
Register 3
Pedestal on Even Fields
25
24
23
22
21
20
19
18
00h
LINE 1
HSYNC
LINE 313
00h
LINE 314
tA
tC
tB
VSYNC
Figure 20. Timing Register 1 in PAL Mode
–26–
REV. 0
ADV7312
SR7–
SR0 Register
59h
SD CGMS/WSS 0
Bit Description
Bit 7
Bit 6
Bit 5
SD CGMS Data
SD CGMS CRC
5Ah
SD CGMS/WSS 1
SD CGMS/WSS Data
5Bh
SD CGMS/WSS 2
SD CGMS/WSS Data
5Ch
SD LSB Register
SD LSB for Y Scale Value
SD LSB for U Scale Value
SD LSB for V Scale Value
SD LSB for FSC Phase
5Dh
5Eh
SD Y Scale Register
SD V Scale Register
SD Y Scale Value
SD V Scale Value
5Fh
60h
SD U Scale Register
SD Hue Register
SD U Scale Value
SD Hue Adjust Value
61h
SD Brightness/WSS
63h
SD Luma SSAF
SD DNR 0
64h
SD DNR 1
19
18
17
16
14
7
6
00h
Disabled
Enabled
13
12
11
10
9
8
CGMS data bits C13–C8 or WSS
data bits C13–C8
CGMS data bits C15–C14
00h
5
4
3
2
1
x
0
x
CGMS/WSS data bits C7–C0
00h
00h
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
CGMS data bits C19–C16
Disabled
Enabled
x
x
SD Luma SSAF
Gain/Attenuation
Reset
Values
Disabled
Enabled
x
x
0
1
Register Setting
Disabled
Enabled
15
0
0
0
SD Y Scale Bit 1–0
SD U Scale Bit 1–0
SD V Scale Bit 1–0
0
0
0
0
0
0
SD Y Scale Bit 7–2
SD V Scale Bit 7–2
00h
00h
SD U Scale Bit 7–2
SD Hue Adjust Bit 7–0
00h
00h
SD Brightness Bit 6–0
00h
Disabled
Enabled
Line 23
0
0
1
0
1
1
0
1
0
0
0
0
–4 dB
0 B
+4 B
00h
0
0
0
0
No gain
00h
0
0
0
0
0
0
0
1
1
1
0
1
+1/16 [–1/8]
+2/16 [–2/8]
+3/16 [–3/8]
0
0
1
1
0
0
0
1
+4/16 [–4/8]
+5/16 [–5/8]
In DNR
mode, the
values in
brackets
apply.
0
0
1
1
1
1
0
1
+6/16 [–6/8]
+7/16 [–7/8]
1
0
0
0
+8/16 [–1]
d
d
0
0
0
0
0
0
0
0
1
0
1
0
No gain
+1/16 [–1/8]
+2/16 [–2/8]
0
0
0
1
1
0
1
0
+3/16 [–3/8]
+4/16 [–4/8]
0
0
1
1
0
1
1
0
+5/16 [–5/8]
+6/16 [–6/8]
0
1
1
0
1
0
1
0
+7/16 [–7/8]
+8/16 [–1]
0
0
0
0
0
0
0
0
0
0
0
1
0
1
…
1
…
1
…
1
…
1
…
1
…
0
…
62
1
1
1
1
1
1
0
63
2 pixels
1
4 pixels
DNR Threshold
00h
Subcarrier Phase Bits 1–0
Coring Gain Border
Border Area
REV. 0
Bit 0
0
1
SD Brightness Value
Block Size Control
Bit 1
0
1
SD Blank WSS Data
Coring Gain Data
Bit 2
0
1
SD CGMS on Even Fields
SD WSS
Bit 3
0
1
SD CGMS on Odd Fields
62h
Bit 4
0
1
8 pixels
16 pixels
–27–
00h
ADV7312
SR7–
SR0 Register
Bit Description
65h
DNR Input Select
SD DNR 2
Bit 7
Bit 6
Bit 5
DNR Mode
DNR Block Offset
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
0
0
0
1
1
0
Filter A
Filter B
0
1
1
0
1
0
Filter C
Filter D
0
1
DNR mode
DNR sharpness mode
0
0
0
0
0
0
0
1
0 pixel offset
1 pixel offset
…
1
…
1
…
1
…
0
…
14 pixel offset
Reset
Values
00h
66h
SD Gamma A
SD Gamma Curve A Data Points
1
x
1
x
1
x
1
x
x
x
x
x
15 pixel offset
A0
00h
67h
68h
SD Gamma A
SD Gamma A
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A1
A2
00h
00h
69h
6Ah
SD Gamma A
SD Gamma A
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A3
A4
00h
00h
6Bh
6Ch
SD Gamma A
SD Gamma A
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A5
A6
00h
00h
6Dh
SD Gamma A
SD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
A7
00h
6Eh
6Fh
SD Gamma A
SD Gamma A
SD Gamma Curve A Data Points
SD Gamma Curve A Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
A8
A9
00h
00h
70h
71h
SD Gamma B
SD Gamma B
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B0
B1
00h
00h
72h
73h
SD Gamma B
SD Gamma B
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B2
B3
00h
00h
74h
75h
SD Gamma B
SD Gamma B
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B4
B5
00h
00h
76h
77h
SD Gamma B
SD Gamma B
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B6
B7
00h
00h
78h
79h
SD Gamma B
SD Gamma B
SD Gamma Curve B Data Points
SD Gamma Curve B Data Points
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
B8
B9
00h
00h
7Ah
SD Brightness
Detect
SD Brightness Value
x
x
x
x
x
x
x
x
Read only
7Bh
Field Count
Register
Field Count
x
x
x
Reserved
Reserved
Reserved
Revision Code
7Ch
Bit 1 = 0
0
0
0
x
x
0
0
0
Read only
0 must be written to this bit
0 must be written to this bit
0 must be written to this bit
Read only
0
–28–
0
0
0
0
0 must be written to these bits
00h
REV. 0
ADV7312
SR7SR0
Register
7Dh
7Eh
Reserved
Reserved
7Fh
80h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Macrovision
MV Control Bits
x
x
x
x
x
x
x
x
00h
81h
82h
Macrovision
Macrovision
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
83h
84h
Macrovision
Macrovision
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
85h
86h
Macrovision
Macrovision
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
87h
88h
Macrovision
Macrovision
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
89h
8Ah
Macrovision
Macrovision
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
8Bh
8Ch
Macrovision
Macrovision
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
8Dh
8Eh
Macrovision
Macrovision
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
8Fh
90h
Macrovision
Macrovision
MV Control Bits
MV Control Bits
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
00h
00h
91h
Macrovision
MV Control Bit
0
0
0
0
0
0
0
REV. 0
Register Setting
Reset
Values
Bit Description
x
–29–
00h
0 must be written to these bits
ADV7312
INPUT CONFIGURATION
Simultaneous Standard Definition and
Progressive Scan or HDTV
Address[01h] : Input Mode 011(SD 8-Bit, PS 16-Bit) or
101(SD and HD, SD Oversampled), 110(SD and HD, HD
Oversampled), Respectively
Note that the ADV7312 defaults to simultaneous standard
definition and progressive scan on power-up.
Address[01h] : Input Mode = 011
Standard Definition Only
Address[01h] : Input Mode = 000
YCrCb, PS, HDTV, or any other HD data must be input in
4:2:2 format. In 4:2:2 input mode the HD Y data is input on
Pins Y7–Y0 and the HD CrCb data on C7–C0. If PS 4:2:2 data
is interleaved onto a single 8-bit bus, Y7–Y0 are used for the
input port. The input data is to be input at 27 MHz, with the
data being clocked on the rising and falling edge of the input
clock. The input mode register at Address 01h is set accordingly. If the YCrCb data does not conform to SMPTE 293M
(525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i],
SMPTE 296M[720p], or BTA-T1004, the async timing mode
must be used.
The 8-bit multiplexed input data is input on Pins S7–S0 (or
Y7–Y0, depending on Register Address 01h, Bit 7), with S0 being
the LSB in 8-bit input mode. Input standards supported are
ITU-R BT.601/656. In 16-bit input mode, the Y pixel data is
input on Pins S7–S2 and CrCb data on Pins Y7–Y0.
16-Bit Mode Operation
With Reg 01h Bit 7 = 0
CrCb data is input on Y Bus
Y data is input on S Bus
With Reg 01h Bit 7 = 1
The 8-bit standard definition data must be compliant with
ITU-R BT.601/656 in 4:2:2 format. Standard definition data is
input on Pins S7–S0, with S0 being the LSB. Using 8-bit input
format, the data is input on Pins S7–S2. The clock input for SD
must be input on CLKIN_A and the clock input for HD must
be input on CLKIN_B. Synchronization signals are optional. SD
syncs are input on Pins S_VSYNC, S_HSYNC, and S_BLANK.
HD syncs on Pins P_VSYNC, P_HSYNC, and P_BLANK.
CrCb data is input on C Bus
Y data is input on Y Bus
The 27 MHz clock input must be input on Pin CLKIN_A.
Input sync signals are optional and are input on the S_VSYNC,
S_HSYNC, and S_BLANK pins.
S_VSYNC
S_HSYNC
S_BLANK
3
MPEG2
DECODER
27MHz
3
MPEG2
DECODER
ADV7312
27MHz
CLKIN_A
YCrCb
8
YCrCb
8
CLKIN_A
S[7:0]
S[7:0] OR Y[7:0]*
ADV7312
*SELECTED BY ADDRESS 0x01 BIT 7
CrCb
8
INTERLACED TO
Y
PROGRESSIVE
Figure 21. SD Only Input Mode
8
Progressive Scan Only or HDTV Only
Address[01h] Input Mode 001 or 010, Respectively
3
YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data
is input on Pins Y7–Y0 and the CrCb data on Pins C7–C0. In
4:4:4 input mode, Y data is input on Pins Y7–Y0, Cb data on
Pins C7–C0, and Cr data on Pins S7–S0. If the YCrCb data
does not conform to SMPTE 293M (525p), ITU-R BT.1358M
(625p), SMPTE 274M[1080i], SMPTE 296M[720p], or
BTA-T1004/1362, the async timing mode must be used. RGB
data can only be input in 4:4:4 format in PS input mode only or
HDTV input mode only when HD RGB input is enabled. G data
is input on Pins Y7–Y0, R data on S7–S0, and B data on C7–C0.
The clock signal must be input on Pin CLKIN_A.
27MHz
27MHz
YCrCb
ADV7312
Cb
8
Cr
8
Y
8
3
Y[7:0]
P_VSYNC
P_HSYNC
P_BLANK
Figure 23. Simultaneous PS and SD Input
3
SDTV
DECODER
HDTV
DECODER
1080i
OR
720p
27MHz
YCrCb
8
CrCb
8
Y
8
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S[7:0]
ADV7312
74.25MHz
CLKIN_A
C[7:0]
CLKIN_B
3
MPEG2
DECODER
INTERLACED TO
PROGRESSIVE
S_VSYNC
S_HSYNC
S_BLANK
C[7:0]
Y[7:0]
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
Figure 24. Simultaneous HD and SD Input
C[7:0]
S[7:0]
Y[7:0]
P_VSYNC
P_HSYNC
P_BLANK
Figure 22. Progressive Scan Input Mode
–30–
REV. 0
ADV7312
If in simultaneous SD/HD input mode the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
ALIGN bit [Address 01h Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
CLKIN_B
Y7–Y0
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
Figure 26b. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
CLKIN_A
CLKIN_B
CLKIN
tDELAY 9.25ns OR
tDELAY 27.75ns
PIXEL INPUT
DATA
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
Figure 25. Clock Phase with Two Input Clocks
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address[01h] : Input Mode 100 or 111, Respectively
WITH A 54 MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
Figure 26c. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 8-bit bus and is input
on Pins Y7–Y0. When a 27 MHz clock is supplied, the data is
clocked in on the rising and falling edge of the input clock and
CLOCK EDGE [Address 0x01, Bit 1] must be set accordingly.
MPEG2
DECODER
The following figures show the possible conditions: (a) Cb data
on the rising edge and (b) Y data on the rising edge.
YCrCb
27MHz OR 54MHz
CLKIN_A
ADV7312
INTERLACED
TO
PROGRESSIVE
CLKIN_B
Y7–Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y[7:0]
P_VSYNC
P_HSYNC
P_BLANK
Figure 27. 1 8-Bit PS at 27 MHz or 54 MHz
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
REV. 0
8
3
Y1
Figure 26a. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
YCrCb
Table I provides an overview of all possible input configurations.
–31–
ADV7312
Table I. Input Configurations
Input Format
Total Bits
Input Video
Input Pins
Subaddress
Register Setting
ITU-R BT.656
8
4:2:2
YCrCb
S7–S0 [MSB = S7]
16
4:2:2
Y
S7–S0 [MSB = S7]
01h
48h
01h
00h
00h
00h
8
4:2:2
CrCb
YCrCb
Y7–Y0 [MSB = Y7]
Y7–Y0 [MSB = Y7]
8 [27 MHz clock]
4:2:2
YCrCb
Y7–Y0 [MSB = Y7]
48h
01h
48h
01h
13h
08h
80h
00h
10h
40h
8 [54 MHz clock]
4:2:2
YCrCb
Y7–Y0 [MSB = Y7]
01h
13h
70h
40h
16
4:2:2
Y
CrCb
Y7–Y0 [MSB = Y7]
C7–C0 [MSB = C7]
01h
13h
10h
40h
24
4:4:4
Y
Cb
Y7–Y0 [MSB = Y7]
C7–C0 [MSB = C7]
01h
13h
10h
00h
16
4:2:2
Cr
Y
S7–S0 [MSB = S7]
Y7–Y0 [MSB = Y7]
01h
20h
24
4:4:4
24
4:4:4
PS Only
HDTV Only
HD RGB
CrCb
C7–C0 [MSB = C7]
13h
40h
Y
Cb
Y7–Y0 [MSB = Y7]
C7–C0 [MSB = C7]
01h
13h
20h
00h
Cr
G
S7–S0 [MSB = S7]
Y7–Y0 [MSB = Y7]
01h
10h or 20h
B
C7–C0 [MSB = C7]
13h
00h
S7–S0 [MSB = S7]
S7–S0 [MSB = S9]
15h
01h
02h
40h
ITU-R BT.656 and PS
8
4:2:2
R
YCrCb
ITU-R BT.656 and PS or HDTV
8
4:2:2
YCrCb
YCrCb
Y7–Y0 [MSB = Y9]
S7–S0 [MSB = S7]
13h
01h
40h
30h or 50h or 60h
16
4:2:2
Y
CrCb
Y7–Y0 [MSB = Y7]
C7–C0 [MSB = C7]
13h
48h
40h
00h
–32–
REV. 0
ADV7312
OUTPUT CONFIGURATION
The tables below demonstrate what output signals are assigned to the DACs when the control bits are set accordingly.
Table II. Output Configuration in SD Only Mode
RGB/YUV Output
02h, Bit 5
SD DAC Output 1
42h, Bit 2
SD DAC Output 2
42h, Bit 1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
0
0
0
CVBS
Luma
Chroma
G
B
R
0
0
1
G
B
R
CVBS
Luma
Chroma
0
1
0
G
Luma
Chroma
CVBS
B
R
0
1
1
CVBS
B
R
G
Luma
Chroma
1
0
0
CVBS
Luma
Chroma
Y
U
V
1
0
1
Y
U
V
CVBS
Luma
Chroma
1
1
0
Y
Luma
Chroma
CVBS
U
V
1
1
1
CVBS
U
V
Y
Luma
Chroma
Luma/Chroma Swap 44h, Bit 7
0
Table as above
1
Table above with all Luma/Chroma instances swapped
Table III. Output Configuration in HD/PS Only Mode
HD/PS
Input
Format
HD/PS RGB
Input 15h,
Bit 1
RGB/YPrPb
Output 02h,
Bit 5
HD/PS Color
Swap 15h, Bit 3
DAC A
DAC B
DAC C
DAC D
DAC E
YCrCb 4:2:2
0
0
0
N/A
N/A
N/A
G
B
R
YCrCb 4:2:2
0
0
1
N/A
N/A
N/A
G
R
B
YCrCb 4:2:2
0
1
0
N/A
N/A
N/A
Y
Pb
Pr
YCrCb 4:2:2
0
1
1
N/A
N/A
N/A
Y
Pr
Pb
YCrCb 4:4:4
0
0
0
N/A
N/A
N/A
G
B
R
YCrCb 4:4:4
0
0
1
N/A
N/A
N/A
G
R
B
YCrCb 4:4:4
0
1
0
N/A
N/A
N/A
Y
Pb
Pr
DAC F
YCrCb 4:4:4
0
1
1
N/A
N/A
N/A
Y
Pr
Pb
RGB 4:4:4
1
0
0
N/A
N/A
N/A
G
B
R
RGB 4:4:4
1
0
1
N/A
N/A
N/A
G
R
B
RGB 4:4:4
1
1
0
N/A
N/A
N/A
G
B
R
RGB 4:4:4
1
1
1
N/A
N/A
N/A
G
R
B
Table IV. Output Configuration in Simultaneous SD and HD/PS Only Mode
RGB/YPrPb
Output 02h, Bit 5
HD/PS Color
Swap 15h, Bit 3
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
ITU-R.BT656 and
HD YCrCb in 4:2:2
0
0
CVBS
Luma
Chroma
G
B
R
ITU-R.BT656 and
HD YCrCb in 4:2:2
0
1
CVBS
Luma
Chroma
G
R
B
ITU-R.BT656 and
HD YCrCb in 4:2:2
1
0
CVBS
Luma
Chroma
Y
Pb
Pr
ITU-R.BT656 and
HD YCrCb in 4:2:2
1
1
CVBS
Luma
Chroma
Y
Pr
Pb
Input Formats
REV. 0
–33–
ADV7312
TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bit 3, 2]
In async mode, the PLL must be turned off [Subaddress 00h,
Bit 1 = 1].
For any input data that does not conform to the standards selectable in input mode, Subaddress 10h, asynchronous timing mode
can be used to interface to the ADV7312. Timing control signals for
HSYNC, VSYNC, and BLANK have to be programmed by the
user. Macrovision and programmable oversampling rates are not
available in async timing mode.
Figure 28a and Figure 28b show examples of how to program
the ADV7312 to accept a different high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358.
The following truth table must be followed when programming the
control signals in async timing mode. For standards that do not
require a tri-sync level, P_BLANK must be tied low at all times.
CLK
P_HSYNC
PROGRAMMABLE
INPUT TIMING
P_VSYNC
P_BLANK
SET ADDRESS 10h,
BIT 6 TO 1
HORIZONTAL SYNC
ACTIVE VIDEO
ANALOG
OUTPUT
81
66
a
66
b
243
c
1920
d
e
Figure 28a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
CLK
P_HSYNC
0
P_VSYNC
1
P_BLANK
SET ADDRESS 10h,
BIT 6 TO 1
HORIZONTAL SYNC
ACTIVE VIDEO
ANALOG OUTPUT
a
b
c
d
e
Figure 28b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
–34–
REV. 0
ADV7312
Table V. Async Timing Mode Truth Table
P_HSYNC
P_VSYNC
P_BLANK*
Reference
Reference
in Figure 28
1→0
0
0 or 1
50% point of falling edge of trilevel horizontal sync signal
a
0
0→1
0 or 1
25% point of rising edge of trilevel horizontal sync signal
b
0→1
0 or 1
0
50% point of falling edge of trilevel horizontal sync signal
c
1
0 or 1
0→1
50% start of active video
d
1
0 or 1
1→0
50% end of active video
e
*When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 14h, Bit 0] from 0 to 1. In this state the horizontal
and vertical counters will remain reset. When this bit is set back
to 0, the internal counters will commence counting again.
REV. 0
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.
–35–
ADV7312
SD Real-Time Control, Subcarrier Reset, and Timing Reset
[Subaddress 44h, Bit 2, 1]
This reset signal will have to be held high for a minimum of
one clock cycle.
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 44h, Bit 1, 2], the ADV7312 can be used in (a) timing
reset mode, (b) subcarrier phase reset mode, or (c) RTC mode.
Since the field counter is not reset, it is recommended that
the reset signal be applied in Field 7 [PAL] or Field 3 [NTSC].
The reset of the phase will then occur on the next field, i.e.,
Field 1, being lined up correctly with the internal counters.
The field count register at Address 7Bh can be used to identify the number of the active field.
a. A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set
to low), the internal counters will commence counting again,
the field count will start on Field 1, and the subcarrier phase
will be reset.
c. In RTC mode, the ADV7312 can be used to lock to an
external video source. The real-time control mode allows the
ADV7312 to automatically alter the subcarrier frequency to
compensate for line length variations. When the part is connected to a device that outputs a digital data stream in the
RTC format, such as an ADV7183A video decoder (see
Figure 31), the part will automatically change to the compensated subcarrier frequency on a line by line basis. This
digital data stream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00h
should be written into all four subcarrier frequency registers
when this mode is used.
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized.
This timing reset applies to the SD timing counters only.
b. In subcarrier phase reset, a low-to-high transition on the
RTC_SCR_TR pin (Pin 31) will reset the subcarrier phase to
zero on the field following the subcarrier phase reset when the
SD RTC/TR/SCR control bits at Address 44h are set to 01.
DISPLAY
307
START OF FIELD 4 OR 8
310
FSC PHASE = FIELD 4 OR 8
313
320
NO TIMING RESET APPLIED
DISPLAY
START OF FIELD 1
307
1
2
3
4
FSC PHASE = FIELD 1
5
6
7
21
TIMING RESET PULSE
TIMING RESET APPLIED
Figure 29. Timing Reset Timing Diagram
DISPLAY
307
310
START OF FIELD 4 OR 8
313
FSC PHASE = FIELD 4 OR 8
320
NO FSC RESET APPLIED
DISPLAY
307
310
START OF FIELD 4 OR 8
313
FSC PHASE = FIELD 1
320
FSC RESET PULSE
FSC RESET APPLIED
Figure 30. Subcarrier Reset Timing Diagram
–36–
REV. 0
ADV7312
Reset Sequence
A reset is activated with a high-to-low transition on the RESET
pin [Pin 33] according to the timing specifications. The ADV7312
will revert to the default output configuration.
Figure 32 illustrates the RESET sequence timing.
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct number of lines/fields are reached; in rewind mode, this sync signal
usually occurs after the total number of lines/fields are reached.
Conventionally this means that the output video will have corrupted field signals, one generated by the incoming video and
one generated when the internal lines/field counters reach the
end of a field.
When the VCR FF/RW sync control is enabled [Subaddress 42h
Bit 5] the lines/field counters are updated according to the
incoming VSYNC signal and the analog output matches the
incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
ADV7312
CLKIN_A
DAC A
DAC B
LCC1
COMPOSITE
VIDEO1
GLL
RTC_SCR_TR
P17–P10
VIDEO
DECODER
Y7-Y0/S7–S05
ADV7183A
DAC C
DAC D
DAC E
DAC F
4 BITS
RESERVED
14 BITS
H/L TRANSITION
SUBCARRIER
COUNT START
LOW PHASE
128
13
0
21
SEQUENCE
BIT3
FSC PLL INCREMENT2
RESET
BIT4
RESERVED
0
RTC
TIME SLOT 01
14
6768
19
VALID INVALID
SAMPLE SAMPLE
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
NOTES
1i.e., VCR OR CABLE
2F
SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7312 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7312.
3SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
4RESET ADV7312 DDS
5SELECTED BY REGISTER ADDRESS 0x01 BIT 7
Figure 31. RTC Timing and Connections
RESET
DACs
A, B, C
XXXXXX
DIGITAL TIMING
XXXXXX
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
PIXEL DATA
VALID
Figure 32. RESET Timing Sequence
REV. 0
–37–
VALID VIDEO
TIMING ACTIVE
ADV7312
Vertical Blanking Interval
Subcarrier Frequency Registers
[Subaddress 4Ch–4Fh]
The ADV7312 accept input data that contains VBI data
[CGMS, WSS, VITS, and so on] in SD and HD modes.
For SMPTE 293M [525p] standards, VBI data can be inserted
on Lines 13 to 42 of each frame, or on Lines 6 to 43 for the
ITU-R BT.1358 [625p] standard.
For SD NTSC this data can be present on Lines 10 to 20, and
in PAL on Lines 7 to 22.
Subcarrier Frequency Register =
Number of subcarrier frequency values in one video line
223 *
Number of 27 MHz clk cycles in one video line
*Rounded to the nearest integer
If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.
For example, in NTSC mode,
 227.5 
23
Subcarrier FrequencyValue = 
 × 2 = 569408542
 1716 
In Slave Mode 0, if VBI is enabled, the blanking bit in the
EAV/SAV code is overwritten, and it is possible to use VBI in
this timing mode as well.
Subcarrier Register Value = 21F07C1Eh
In Slave Mode 1 or 2, the BLANK control bit must be set to
enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7312. Otherwise, the ADV7312 automatically blanks
the VBI to standard.
If CGMS is enabled and VBI is disabled, the CGMS data will
nevertheless be available at the output.
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the equation
SD FSC Register 0: 1Eh
SD FSC Register 1: 7Ch
SD FSC Register 2: F0h
SD FSC Register 3: 21h
Refer to the MPU Port Description section for more details on
how to access the subcarrier frequency registers.
Square Pixel Timing
[Register 42h, Bit 4]
In square pixel mode, the following timing diagrams apply.
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
4 CLOCK
SAV CODE
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 33. EAV/SAV Embedded Timing
HSYNC
FIELD
PAL = 44 CLOCK CYCLES
NTSC = 44 CLOCK CYCLES
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 136 CLOCK CYCLES
NTSC = 208 CLOCK CYCLES
Figure 34. Active Pixel Timing
–38–
REV. 0
ADV7312
FILTER SECTION
HD Sinc Filter
Table VI shows an overview of the programmable filters available
on the ADV7312.
0.5
0.4
Table VI. Selectable Filters
0.3
Subaddress
0.2
SD Luma LPF NTSC
SD Luma LPF PAL
SD Luma Notch NTSC
SD Luma Notch PAL
SD Luma SSAF
SD Luma CIF
SD Luma QCIF
SD Chroma 0.65 MHz
SD Chroma 1.0 MHz
SD Chroma 1.3 MHz
SD Chroma 2.0 MHz
SD Chroma 3.0 MHz
SD Chroma CIF
SD Chroma QCIF
SD UV SSAF
HD Chroma Input
HD Sinc Filter
HD Chroma SSAF
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
42h
13h
13h
13h
0.1
GAIN (dB)
Filter
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
5
10
15
20
FREQUENCY (MHz)
25
30
Figure 35. HD Sinc Filter Enabled
0.5
0.4
0.3
GAIN (dB)
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
5
10
15
20
FREQUENCY (MHz)
25
Figure 36. HD Sinc Filter Disabled
REV. 0
–39–
30
ADV7312
SD Internal Filter Response
[Subaddress 40h; Subaddress 42, Bit 0]
Table VII. Internal Filter Specifications
The Y filter supports several different frequency responses including
two low-pass responses, two notch responses, an extended (SSAF)
response with or without gain boost attenuation, a CIF response,
and a QCIF response. The UV filter supports several different
frequency responses including six low-pass responses, a CIF
response, and a QCIF response, as can be seen in the figures on
the following pages.
If SD SSAF gain is enabled, there is the option of 12 responses
in the range from –4 dB to +4 dB [Subaddress 47, Bit 4]. The
desired response can be chosen by the user by programming the
correct value via the I2C [Subaddress 62h]. The variation of frequency responses can be seen in the figures on the following pages.
If this filter is disabled, the selectable chroma filters shown in
Table VII can be used for the CVBS or Luma/Chroma signal.
Pass-Band
Ripple1 (dB)
3 dB
Bandwidth2 (MHz)
Luma LPF NTSC
Luma LPF PAL
Luma Notch NTSC
Luma Notch PAL
Luma SSAF
Luma CIF
Luma QCIF
Chroma 0.65 MHz
Chroma 1.0 MHz
Chroma 1.3 MHz
Chroma 2.0 MHz
Chroma 3.0 MHz
Chroma CIF
Chroma QCIF
0.16
0.1
0.09
0.1
0.04
0.127
Monotonic
Monotonic
Monotonic
0.09
0.048
Monotonic
Monotonic
Monotonic
4.24
4.81
2.3/4.9/6.6
3.1/5.6/6.4
6.45
3.02
1.5
0.65
1
1.395
2.2
3.2
0.65
0.5
NOTES
1
Pass-band ripple is the maximum fluctuation from the 0 dB response in the
pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz)
frequency limits for a low-pass filter, 0 Hz to f1 (Hz) and f2 (Hz) to infinity for
a notch filter, where fc, f1, and f2 are the –3 dB points.
2
3 dB bandwidth refers to the –3 dB cutoff frequency.
EXTENDED UV FILTER MODE
0
–10
GAIN (dB)
In addition to the chroma filters listed in Table VII, the
ADV7312 contains an SSAF filter specifically designed for and
applicable to the color difference component outputs, U and V.
This filter has a cutoff frequency of about 2.7 MHz and –40 dB
at 3.8 MHz, as can be seen in Figure 37. This filter can be
controlled with Address 42h, Bit 0.
Filter
–20
–30
–40
–50
–60
0
1
2
3
4
5
6
FREQUENCY (MHz)
Figure 37. UV SSAF Filter
–40–
REV. 0
Typical Performance Characteristics–ADV7312
PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4
Y PASS BAND IN PS OVERSAMPLING MODE
1.0
0
0.5
–10
0
–0.5
–30
GAIN (dB)
GAIN (dB)
–20
–40
–1.0
–1.5
–50
–60
–2.0
–70
–2.5
–80
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–3.0
200
TPC 1. PS—UV 8× Oversampling Filter (Linear)
0
2
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–70
–70
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–80
200
TPC 2. PS—UV 8× Oversampling Filter (SSAF)
0
20
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–70
–70
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–80
200
TPC 3. PS—Y (8× Oversampling Filter)
REV. 0
120
140
–40
–50
20
60
80
100
FREQUENCY (MHz)
Y RESPONSE IN HDTV OVERSAMPLING MODE
0
GAIN (dB)
GAIN (dB)
Y RESPONSE IN PS OVERSAMPLING MODE
0
40
TPC 5. HDTV—UV (2× Oversampling Filter)
0
–80
12
–40
–50
20
10
Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE
0
GAIN (dB)
GAIN (dB)
PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
0
6
8
FREQUENCY (MHz)
TPC 4. PS—Y 8× Oversampling Filter (Pass Band)
0
–80
4
0
20
40
60
80
100
FREQUENCY (MHz)
120
140
TPC 6. HDTV—Y (2× Oversampling Filter)
–41–
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
ADV7312
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
0
TPC 7. Luma NTSC Low-Pass Filter
2
4
6
8
FREQUENCY (MHz)
10
12
TPC 10. Luma PAL Notch Filter
0
–10
–10
–20
–20
GAIN (dB)
MAGNITUDE (dB)
Y RESPONSE IN SD OVERSAMPLING MODE
0
–30
–40
–30
–40
–50
–50
–60
–60
–70
–80
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
0
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
200
TPC 11. Y—16× Oversampling Filter
TPC 8. Luma PAL Low-Pass Filter
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
20
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
0
TPC 9. Luma NTSC Notch Filter
2
4
6
8
FREQUENCY (MHz)
10
12
TPC 12. Luma SSAF Filter up to 12 MHz
–42–
REV. 0
ADV7312
4
0
2
–10
MAGNITUDE (dB)
MAGNITUDE (dB)
0
–2
–4
–6
–20
–30
–40
–50
–8
–60
–10
–70
–12
0
1
2
3
4
5
6
0
7
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 13. Luma SSAF Filter—Programmable Responses
TPC 16. Luma CIF Low-Pass Filter
5
4
–10
3
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
0
2
1
–30
–40
–50
0
–60
–70
–1
0
1
2
3
4
5
6
0
7
2
4
6
8
10
12
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 14. Luma SSAF Filter—Programmable Gain
TPC 17. Luma QCIF Low-Pass Filter
1
0
–10
–1
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
0
–2
–3
–30
–40
–50
–4
–60
–70
–5
0
1
2
3
4
5
6
0
7
FREQUENCY (MHz)
4
6
8
10
FREQUENCY (MHz)
TPC 15. Luma SSAF Filter—Programmable Attenuation
REV. 0
2
TPC 18. Chroma 3.0 MHz Low-Pass Filter
–43–
12
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
ADV7312
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
2
4
FREQUENCY (MHz)
8
10
12
TPC 22. Chroma 0.65 MHz Low-Pass Filter
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
TPC 19. Chroma 2.0 MHz Low-Pass Filter
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
2
4
FREQUENCY (MHz)
6
8
10
12
FREQUENCY (MHz)
TPC 20. Chroma 1.3 MHz Low-Pass Filter
TPC 23. Chroma CIF Low-Pass Filter
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
MAGNITUDE (dB)
6
FREQUENCY (MHz)
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
12
0
FREQUENCY (MHz)
2
4
6
8
10
12
FREQUENCY (MHz)
TPC 21. Chroma 1.0 MHz Low-Pass Filter
TPC 24. Chroma QCIF Low-Pass Filter
–44–
REV. 0
ADV7312
COLOR CONTROLS AND RGB MATRIX
HD Y Level, HD Cr Level, HD Cb Level
[Subaddress 16h–18h]
Programming the RGB Matrix
Three 8-bit registers at Address 16h, 17h, 18h are used to program
the output color of the internal HD test pattern generator, be it
the lines of the cross hatch pattern or the uniform field test
pattern. They are not functional as color controls on external
pixel data input. For this purpose the RGB matrix is used.
The standard used for the values for Y and the color difference
signals to obtain white, black, and the saturated primary and
complementary colors conforms to the ITU-R BT.601-4 standard.
Table VIII shows sample color values to be programmed into
the color registers when Output Standard Selection is set to EIA 770.2.
Y
Value
Cr
Value
Cb
Value
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
235 (EB)
16 (10)
81 (51)
145 (91)
41 (29)
210 (D2)
170 (AA)
106 (6A)
128 (80)
128 (80)
240 (F0)
34 (22)
110 (6E)
146 (92)
16 (10)
222 (DE)
128 (80)
128 (80)
90 (5A)
54 (36)
240 (F0)
16 (10)
166 (A6)
202 (CA)
GY at address 03h and 05h control the output levels on the green
signal, BU at 04h and 08h the blue signal output levels and RV
at 04h and 09h the red output levels. To control YPrPb output
levels, YUV output should be enabled [Address 02h, Bit 5]. In
this case GY [Address 05h; Address 03, Bit 0-1] is used for the
Y output, RV [Address 09; Address 04, Bit 0-1] is used for the
Pr output, and BU [Address 08h; Address 04h, Bit 2-3] is used
for the Pb output.
If RGB output is selected the RGB matrix scaler uses the
following equations:
Table VIII. Sample Color Values for EIA 770.2 Output
Standard Selection
Sample
Color
The RGB matrix should be enabled [Address 02h, Bit 3], the
output should be set to RGB [Address 02h, Bit 5], sync on PrPb
should be disabled [Address 15h, Bit 2], and sync on RGB is
optional [Address 02h, Bit 4].
G = GY × Y + GU × Pb + GV × Pr
B = GY × Y + BU × Pb
R = GY × Y + RV × Pr
If YPrPb output is selected the following equations are used:
Y = GY × Y
U = BU × Pb
V = RV × Pr
On power-up, the RGB matrix is programmed with the default
values below.
Table IX. RGB Matrix Default Values
HD RGB Matrix
[Subaddress 03h–09h]
When the programmable RGB matrix is disabled [Address 02h,
Bit 3], the internal RGB matrix takes care of all YCrCb to YUV
or RGB scaling according to the input standard programmed
into the device.
When the programmable RGB matrix is enabled, the color components are converted according to the 1080i standard [SMPTE 274M]:
Y' = 0.2126 R' + 0.7152G' + 0.0722 B'
CB' = [0.5 / (1 − 0.0722)](B' − Y' )
CR' = [0.5 / (1 − 0.2126 )](R' − Y' )
If another input standard is used, the scale values for GY, GU,
GV, BU, and RV have to be adjusted according to this input
standard. The user must consider the fact that the color component conversion might use different scale values. For example,
SMPTE 293M uses the following conversion:
The programmable RGB matrix can be used to control the HD
output levels in cases where the video output does not conform
to standard due to altering the DAC output stages such as termination resistors. The programmable RGB matrix is used for
external HD data and is not functional when the HD test pattern
is enabled.
REV. 0
Default
03h
04h
05h
06h
07h
08h
09h
03h
F0h
4Eh
0Eh
24h
92h
7Ch
When the programmable RGB matrix is not enabled, the
ADV7312 automatically scales YCrCb inputs to all standards
supported by this part.
This is reflected in the preprogrammed values for GY = 138Bh,
GU = 93h, GV = 3B, BU = 248h, and RV = 1F0.
Y' = 0.299 R' + 0.587 G' + 0.114 B'
CB' = [0.5 / (1 − 0.114 )](B' − Y' )
CR' = [0.5 / (1 − 0.299)](R' − Y' )
Address
SD Luma and Color Control
[Subaddress 5Ch, 5Dh, 5Eh, 5Fh]
SD Y Scale, SD Cr Scale, and SD Cb Scale are three 10-bit
wide control registers to scale the Y, U, and V output levels.
Each of these registers represents the value required to scale the
U or V level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 of
its initial level. The value of these 10 bits is calculated using the
following equation:
Y, U, or V ScalarValue = Scale Factor × 512
For example:
Scale Factor = 1.18
Y, U, or V Scale Value = 1.18 × 512 = 665.6
Y, U, or V Scale Value = 665 (rounded to the nearest integer)
Y, U, or V Scale Value = 1010 0110 01 b
Address 5Ch, SD LSB Register = 15h
Address 5Dh, SD Y Scale Register = A6h
Address 5Eh, SD V Scale Register = A6h
Address 5Fh, SD U Scale Register = A6h
–45–
ADV7312
Standard: PAL.
To add –7IRE brightness level, write 72h to Address 61h,
SD brightness.
SD Hue Adjust Value
[Subaddress 60h]
The hue adjust value is used to adjust the hue on the composite
and chroma outputs.
[ IREValue × 2.015631] =
These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier during
active video with respect to the phase of the subcarrier during
the color burst. The ADV7312 provides a range of 22.5o
increments of 0.17578125o. For normal operation (zero adjustment), this register is set to 80h. FFh and 00h represent the
upper and lower limits (respectively) of adjustment attainable.
[7 × 2.015631] = [14.109417] = 0001110b
[0001110] into twos complement = [1110010] b = 72h
Table X. Brightness Control Values*
(Hue Adjust) [o] = 0.17578125o × (HCR d – 128), for positive
hue adjust value.
o
For example, to adjust the hue by +4 , write 97h to the Hue
Adjust Value register:
4



 + 128 = 105d* = 97h
 0.17578125 
*rounded to the nearest integer
Setup
Level In
NTSC with
Pedestal
Setup
Level In
NTSC No
Pedestal
Setup
Level In
PAL
SD
Brightness
22.5 IRE
15 IRE
7.5 IRE
0 IRE
15 IRE
7.5 IRE
0 IRE
–7.5 IRE
15 IRE
7.5 IRE
0 IRE
–7.5 IRE
1Eh
0Fh
00h
71h
*Values in the range from 3Fh to 44h might result in an invalid output signal.
To adjust the hue by –4o, write 69h to the Hue Adjust Value
register:
SD Brightness Detect
[Subaddress 7Ah]
−4



 + 128 = 105d* = 69h
 0.17578125 
The ADV7312 allow monitoring of the brightness level of the
incoming video data. Brightness detect is a read-only register.
*rounded to the nearest integer
Double Buffering
[Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]
SD Brightness Control
[Subaddress 61h]
The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0IRE to 22.5IRE. For NTSC without pedestal and
PAL, the setup can vary from –7.5IRE to +15IRE.
The brightness control register is an 8-bit register. Seven bits of
this 8-bit register are used to control the brightness level. This
brightness level can be a positive or negative value.
For example:
Standard: NTSC with Pedestal.
To add +20IRE brightness level, write 28h to Address 61h,
SD brightness.
Double buffered registers are updated once per field on the
falling edge of the VSYNC signal. Double buffering improves
the overall performance since modifications to register settings
will not be made during active video, but take effect on the start
of the active video.
Double buffering can be activated on the following HD registers:
HD Gamma A and Gamma B curves and HD CGMS registers.
Double buffering can be activated on the following SD registers:
SD Gamma A and Gamma B curves, SD Y Scale, SD U Scale,
SD V Scale, SD Brightness, SD Closed Captioning, and
SD Macrovision Bits 5–0.
[SD BrightnessValue ] h =
[ IREValue × 2.015631] h =
[20 × 2.015631] h = [40.31262] h = 28h
NTSC WITHOUT PEDESTAL
+7.5 IRE
100 IRE
0 IRE
–7.5 IRE
NO SETUP
VALUE ADDED
POSITIVE SETUP
VALUE ADDED
NEGATIVE SETUP
VALUE ADDED
Figure 38. Examples of Brightness Control Values
–46–
REV. 0
ADV7312
PROGRAMMABLE DAC GAIN CONTROL
DACs A, B, and C are controlled by REG 0A.
DACs D, E, and F are controlled by REG 0B.
The I2C control registers will adjust the output signal gain up or
down from its absolute level.
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0Ah, 0Bh
In case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the signal
is increased from the reference signal.
In case B, the video output signal is reduced. The absolute level
of the sync tip and blanking level both decrease with respect to
the reference video output signal. The overall gain of the signal
is reduced from the reference signal.
The range of this feature is specified for ± 7.5% of the nominal
output from the DACs. For example, if the output current of
the DAC is 4.33 mA, the DAC tune feature can change this
output current from 4.008 mA (–7.5%) to 4.658 mA (+7.5%).
700mV
The reset value of the vid_out_ctrl registers is 00h → nominal
DAC output current. The following table is an example of how
the output current of the DACs varies for a nominal 4.33 mA
output current.
Table XI.
300mV
CASE B
700mV
300mV
Figure 39. Programmable DAC Gain—Positive and
Negative Gain
REV. 0
Reg 0Ah or 0Bh
DAC
Current
(mA)
% Gain
0100 0000 (40h)
0011 1111 (3Fh)
0011 1110 (3Eh)
...
...
0000 0010 (02h)
0000 0001 (01h)
0000 0000 (00h)
4.658
4.653
4.648
...
...
4.43
4.38
4.33
7.5000%
7.3820%
7.3640%
...
...
0.0360%
0.0180%
0.0000%
1111 1111 (FFh)
1111 1110 (FEh)
...
...
1100 0010 (C2h)
1100 0001 (C1h)
1100 0000 (C0h)
4.25
4.23
...
...
4.018
4.013
4.008
–0.0180%
–0.0360%
...
...
–7.3640%
–7.3820%
–7.5000%
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0Ah, 0Bh
–47–
(I2C Reset Value,
Nominal)
ADV7312
For example:
Gamma Correction
[Subaddress 24h–37h for HD, Subaddress 66h–79h for SD]
y24 = [(8 / 224)0.5 × 224] + 16 = 58*
y32 = [(16 / 224)0.5 × 224] + 16 = 76*
y48 = [(32 / 224)0.5 × 224] + 16 = 101*
y64 = [(48 / 224)0.5 × 224] + 16 =120*
y80 = [(64 / 224)0.5 × 224] + 16 =136*
y96 = [(80 / 224)0.5 × 224] + 16 = 150*
y128 = [(112 / 224)0.5 × 224] + 16 = 174*
y160 = [(144 / 224)0.5 × 224] + 16 = 195*
y192 = [(176 / 224)0.5 × 224] + 16 = 214*
y224 = [(208 / 224)0.5 × 224] + 16 = 232*
Gamma correction is available for SD and HD video. For each
standard, there are twenty 8-bit wide registers. They are used to
program the gamma correction curves A and B. HD gamma
curve A is programmed at Addresses 24h to 2Dh, HD gamma
curve B at 2Eh to 7h. SD gamma curve A is programmed at
Addresses 66h to 6Fh, and SD gamma curve B at Addresses
70h to 79h.
Generally gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied wherever
nonlinear processing is used.
*rounded to the nearest integer
The gamma curves in Figures 40 and 41 are examples only; any
user defined curve is acceptable in the range of 16 to 240.
Gamma correction uses the function
SignalOUT = (Signal IN
)
γ
GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
300
GAMMA CORRECTED AMPLITUDE
where = gamma power factor.
Gamma correction is performed on the luma data only. The user
may choose either of two different curves, curve A or curve B.
At any one time, only one of these curves can be used.
The response of the curve is programmed at 10 predefined locations. In changing the values at these locations, the gamma curve
can be modified. Between these points, linear interpolation is
used to generate intermediate values. Considering the curve to
have a total length of 256 points, the 10 locations are at 24, 32,
48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240,
and 255 are fixed and cannot be changed.
For the length of 16 to 240, the gamma correction curve has to
be calculated as follows:
250
SIGNAL OUTPUT
200
0.5
150
100
SIGNAL INPUT
50
0
y = xγ
0
50
100
150
LOCATION
200
250
Figure 40. Signal Input (Ramp) and Signal Output
for Gamma 0.5
where:
y = gamma corrected output
x = linear input signal
= gamma power factor
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR
VARIOUS GAMMA VALUES
To program the gamma correction registers, the seven values for
y have to be calculated using the following formula:
 x( n −16) 
yn = 
 × (240 − 16) + 16
 (240 − 16) 
where:
x(n – 16) = Value for x along x axis at points
n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224
yn = Value for y along the y axis, which has to be written into
the gamma correction register
GAMMA CORRECTED AMPLITUDE
300
250
0.3
200
0.5
150
100
G
SI
N
AL
IN
PU
T
1.5
1.8
50
0
0
50
100
150
LOCATION
200
250
Figure 41. Signal Input (Ramp) and Selectable
Output Curves
–48–
REV. 0
ADV7312
The derivative of the incoming signal is compared to the three programmable threshold values: HD adaptive filter threshold A, B, C.
The recommended threshold range is from 16 to 235 although
any value in the range of 0 to 255 can be used.
HD SHARPNESS FILTER CONTROL AND
ADAPTIVE FILTER CONTROL
[Subaddress 20h, 38h–3Dh]
There are three filter modes available on the ADV7312/ADV7311:
sharpness filter mode and two adaptive filter modes.
The edges can then be attenuated with the settings in HD adaptive filter gain 1, 2, 3 registers and HD sharpness filter gain
register.
HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges
shown in the figures below, the following register settings must
be used: HD sharpness filter must be enabled and HD adaptive
filter enable must be set to disabled.
According to the settings of the HD adaptive filter mode control,
there are two adaptive filter modes available:
1. Mode A is used when adaptive filter mode is set to 0. In this
case, Filter B (LPF) will be used in the adaptive filter block.
Also, only the programmed values for Gain B in the HD sharpness filter gain, HD adaptive filter gain 1, 2, 3 are applied when
needed. The Gain A values are fixed and cannot be changed.
To select one of the 256 individual responses, the according
gain values for each filter, which range from –8 to +7, must
be programmed into the HD sharpness filter gain register at
Address 20h.
HD Adaptive Filter Mode
The HD adaptive filter threshold A, B, C registers, the HD
adaptive filter gain 1, 2, 3 registers, and the HD sharpness gain
register are used in adaptive filter mode. To activate the adaptive
filter control, the HD sharpness filter must be enabled and HD
adaptive filter enable must be enabled.
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK
1.5
1.4
1.3
1.3
1.2
1.2
1.1
1.0
0.9
1.1
1.0
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
1.6
MAGNITUDE RESPONSE (Linear Scale)
1.4
MAGNITUDE
INPUT
SIGNAL:
STEP
MAGNITUDE
1.5
2. Mode B is used when adaptive filter mode is set to 1. In this
mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the HD sharpness filter gain,
HD adaptive filter gain 1, 2, 3 become active when needed.
0.5
1.5
1.4
1.3
1.2
1.1
1.0
FREQUENCY (MHz)
FREQUENCY (MHz)
FILTER A RESPONSE (Gain Ka)
FILTER B RESPONSE (Gain Kb)
0
2
4
6
8
10
FREQUENCY (MHz)
12
FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 42. Sharpness and Adaptive Filter Control Block
REV. 0
–49–
ADV7312
The effect of the sharpness filter can also be seen when using
the internally generated cross hatch pattern.
HD Sharpness Filter and Adaptive Filter Application
Examples
HD Sharpness Filter Application
Table XIII.
The HD sharpness filter can be used to enhance or attenuate
the Y video output signal. The following register settings were
used to achieve the results shown in the figures below. Input
data was generated by an external signal source.
Table XII.
Address
Register Setting
Reference*
00h
01h
02h
10h
11h
20h
20h
20h
20h
20h
20h
FCh
10h
20h
00h
81h
00h
08h
04h
40h
80h
22h
a
b
c
d
e
f
Address
Register Setting
00h
01h
02h
10h
11h
20h
FCh
10h
20h
00h
85h
99h
*See Figure 43.
d
a
R2
1
e
b
R4
R1
f
c
1
R2
CH1 500mV
REF A
500mV 4.00s
M 4.00s
1
9.99978ms
CH1
ALL FIELDS
CH1 500mV
REF A
500mV 4.00s
1
M 4.00s
9.99978ms
CH1
ALL FIELDS
Figure 43. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Value
–50–
REV. 0
ADV7312
Adaptive Filter Control Application
Figures 44 and 45 show typical signals to be processed by the
adaptive filter control block.
When changing the adaptive filter mode to Mode B [Address 15h,
Bit 6], the following output can be obtained:
: 674mV
@: 446mV
: 332ns
@: 12.8ms
: 692mV
@: 446mV
: 332ns
@: 12.8ms
Figure 46. Output Signal from Adaptive Filter Control
Figure 44. Input Signal to Adaptive Filter Control
: 692mV
@: 446mV
: 332ns
@: 12.8ms
The adaptive filter control can also be demonstrated using the
internally generated cross hatch test pattern and toggling the
adaptive filter control bit [Address 15h, Bit 7].
Table XV.
Figure 45. Output Signal after Adaptive Filter Control
The following register settings were used to obtain the results
shown in Figure 45, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.
Table XIV.
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
38h
20h
00h
81h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
All other registers are set as normal/default.
REV. 0
–51–
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
38h
20h
00h
85h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
ADV7312
SD Digital Noise Reduction
[Subaddress 63h, 64h, 65h]
DNR MODE
DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
[DNR input select]. The absolute value of the filter output is
compared to a programmable threshold value ['DNR threshold
control]. There are two DNR modes available: DNR mode and
DNR sharpness mode.
In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount [coring gain border, coring gain data] of this noise
signal will be subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than
the programmed threshold, it is assumed to be noise, as before.
Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal [coring gain border,
coring gain data] will be added to the original signal in order to
boost high frequency components and sharpen the video image.
GAIN
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
INPUT FILTER
BLOCK
FILTER
OUTPUT
< THRESHOLD?
Y DATA
INPUT
FILTER OUTPUT
> THRESHOLD
SUBTRACT SIGNAL
IN THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
–
+
DNR OUT
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels ×
16 pixels for MPEG1 systems [block size control]. DNR can be
applied to the resulting block transition areas that are known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels [border area].
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the [DNR
block offset].
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
INPUT FILTER
BLOCK
Y DATA
INPUT
FILTER
OUTPUT
> THRESHOLD?
FILTER OUTPUT
< THRESHOLD
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
ADD SIGNAL
ABOVE THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
+
+
DNR OUT
MAIN SIGNAL PATH
Figure 47. DNR Block Diagram
–52–
REV. 0
ADV7312
Coring Gain Border
[Address 63h, Bits 3–0]
Block Size Control
[Address 64h, Bit 7]
These four bits are assigned to the gain factor applied to
border areas.
This bit is used to select the size of the data blocks to be processed. Setting the block size control function to a Logic 1 defines
a 16 pixel × 16 pixel data block, and a Logic 0 defines an 8 pixel ×
8 pixel data block, where one pixel refers to two clock cycles
at 27 MHz.
In DNR mode, the range of gain values is 0 to 1 in increments
of 1/8. This factor is applied to the DNR filter output, which
lies below the set threshold range. The result is then subtracted
from the original signal.
DNR Input Select Control
[Address 65h, Bit 2–0]
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range.
Three bits are assigned to select the filter, which is applied to
the incoming Y data. The signal that lies in the pass band of
the selected filter is the signal that will be DNR processed.
Figure 50 shows the filter responses selectable with this control.
The result is added to the original signal.
Coring Gain Data
[Address 63h, Bits 7–4]
These four bits are assigned to the gain factor applied to the
luma data inside the MPEG pixel block.
1.0
In DNR mode, the range of gain values is 0 to 1 in increments
of 1/8. This factor is applied to the DNR filter output, which
lies below the set threshold range. The result is then subtracted
from the original signal.
0.8
MAGNITUDE
FILTER D
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range.
FILTER C
0.6
0.4
FILTER B
0.2
FILTER A
The result is added to the original signal.
APPLY DATA
CORING GAIN
0
APPLY BORDER
CORING GAIN
DNR27 – DNR24 = 01h
5
6
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
DNR Threshold
[Address 64h, Bits 5–0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area
[Address 64h, Bit 6]
When this bit is set to a Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to a Logic 0,
the border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
2-PIXEL
BORDER DATA
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using Extended SSAF filter).
Block Offset Control
[Address 65h, Bits 7–4]
Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel
such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
88 PIXEL BLOCK
Figure 49. DNR Border Area
REV. 0
3
4
FREQUENCY (Hz)
This bit controls the DNR mode selected. A Logic 0 selects
DNR mode; a Logic 1 selects DNR sharpness mode.
OXXXXXXOOXXXXXXO
88 PIXEL BLOCK
2
DNR Mode Control
[Address 65h, Bit 4]
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
Figure 48. DNR Offset Control
720485 PIXELS
(NTSC)
1
Figure 50. DNR Input Select
OXXXXXXOOXXXXXXO
OXXXXXXOOXXXXXXO
0
–53–
ADV7312
SD ACTIVE VIDEO EDGE
[Subaddress 42h, Bit 7]
SAV/EAV Step Edge Control
The ADV7312 has the capability of controlling fast rising and
falling signals at the start and end of active video to minimize
ringing.
When the active video edge is enabled, the first three pixels and
the last three pixels of the active video on the luma channel are
scaled in such a way that maximum transitions on these pixels
are not possible. The scaling factors are ×1/8, ×1/2, and × 7/8.
All other active video passes through unprocessed.
An algorithm monitors SAV and EAV and governs when the
edges are too fast. The result will be reduced ringing at the start
and end of active video for fast transitions.
Subaddress 0x42, Bit 7 = 1 enables this feature.
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
100 IRE
100 IRE
87.5 IRE
50 IRE
12.5 IRE
0 IRE
0 IRE
Figure 51. Example of Active Video Edge Functionality
VOLTS
IRE:FLT
100
0.5
50
0
0
F2
L135
–50
0
2
4
6
8
10
12
Figure 52. Address 0x42, Bit 7 = 0
VOLTS
IRE:FLT
100
0.5
50
0
0
F2
L135
–50
–2
0
2
4
6
8
Figure 53. Address 0x42, Bit 7 = 1
–54–
10
12
REV. 0
ADV7312
BOARD DESIGN AND LAYOUT CONSIDERATIONS
DAC Termination and Layout Considerations
10H
DAC
OUTPUT
The ADV7312 contain an on-board voltage reference. The
ADV7312 can be used with an external VREF (AD1580).
3
600
22pF
75
600
BNC
OUTPUT
1
4
The RSET resistors are connected between the RSET pins and
AGND and are used to control the full-scale output current and
therefore the DAC voltage output levels. For full-scale output,
RSET must have a value of 3040 Ω. The RSET values should not
be changed. RLOAD has a value of 300 Ω for full-scale output.
560
560
Figure 54. Example of Output Filter for SD,
16 × Oversampling
Video Output Buffer and Optional Output Filter
Output buffering on all six DACs is necessary in order to drive
output devices, such as SD or HD monitors. Analog Devices
produces a range of suitable op amps for this application, for
example the AD8061. More information on line driver buffering
circuits is given in the relevant op amps’ data sheets.
An optional analog reconstruction low-pass filter (LPF) may be
required as an anti-imaging filter if the ADV7312 is connected
to a device that requires this filtering.
0
0
CIRCUIT FREQUENCY RESPONSE
24n
–30
–10
21n
MAGNITUDE (dB)
–60
–20
18n
–90
GAIN (dB)
–30
The filter specifications vary with the application.
15n
–120
–40
12n
–150
PHASE (Deg)
–50
9n
–180
GROUP DELAY (sec)
–60
Table XVI. External Filter Requirements
Cutoff
Frequency Attenuation
Application Oversampling (MHz)
–50 dB @ (MHz)
SD
SD
PS
PS
HDTV
HDTV
REV. 0
2×
16×
1×
8×
1×
2×
>6.5
>6.5
>12.5
>12.5
>30
>30
20.5
209.5
14.5
203.5
44.25
118.5
6n
–210
–70
–80
1M
10M
100M
FREQUENCY (Hz)
3n
–240
0
1G
Figure 55. Filter Plot for Output Filter for SD,
16× Oversampling
–55–
ADV7312
4.7H
DAC
OUTPUT
6.8pF
600
75
600
6.8pF
CIRCUIT FREQUENCY RESPONSE
0
3
18n
BNC
OUTPUT
1
480
400
–10
MAGNITUDE (dB)
4
16n
–20
320
–30
240
14n
560
GAIN (dB)
560
Figure 56. Example of Output Filter for PS,
8× Oversampling
GROUP DELAY (Sec)
–40
PHASE (Deg) 160
12n
10n
–50
80
–60
0
–70
–80
–80
–160
8n
6n
DAC
OUTPUT
4n
3
1
300
4
75
470nH
220nH
BNC
OUTPUT
3
33pF
82pF
75
–90
1M
1
10M
100M
FREQUENCY (Hz)
2n
–240
0
1G
4
Figure 58. Filter Plot for Output Filter for PS,
8× Oversampling
500
500
CIRCUIT FREQUENCY RESPONSE
0
Figure 57. Example of Output Filter for HDTV,
2× Oversampling
18n
MAGNITUDE (dB)
–10
Table XVII. Possible Output Rates From the ADV7312
Output
Rate (MHz)
SD Only
Off
On
27 (2×)
216 (16×)
GAIN (dB)
PLL
Address 00h, Bit 1
360
15n
240
–20
Input Mode
Address 01h, Bit 6–4
480
12n
GROUP DELAY (sec)
120
–30
9n
0
–40
6n
PHASE (Deg)
PS Only
Off
On
27 (1×)
216 (8×)
–50
HDTV Only
Off
On
74.25 (1×)
148.5 (2×)
–60
1M
–120
3n
10M
100M
FREQUENCY (Hz)
–240
0
1G
Figure 59. Filter Plot for Output Filter for HDTV,
2× Oversampling
–56–
REV. 0
ADV7312
PCB Board Layout Considerations
Supply Decoupling
The ADV7312 are optimally designed for lowest noise performance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7312, it is imperative
that great care be given to the PC board layout.
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.
Optimum performance is achieved by the use of 10 nF and
0.1 µF ceramic capacitors. Each group of VAA, VDD, or VDD_IO
pins should be individually decoupled to ground. This should
be done by placing the capacitors as close as possible to the
device with the capacitor leads as short as possible, thus minimizing lead inductance.
The layout should be optimized for lowest noise on the ADV7312
power and ground lines. This can be achieved by shielding
the digital inputs and providing good decoupling. The lead
length between groups of VAA and AGND, VDD and DGND,
and VDD_IO and GND_IO pins should be kept as short as possible to minimized inductive ringing.
A 1 µF tantalum capacitor is recommended across the VAA
supply in addition to 10 nF ceramic.
It is recommended that a 4-layer printed circuit board is used,
with power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Component placement should be carefully considered in order to
separate noisy circuits, such as crystal clocks, high speed logic
circuitry, and analog circuitry.
See the circuit layout in Figure 60.
There should be a separate analog ground plane and a separate
digital ground plane.
Due to the high clock rates used, long clock lines to the
ADV7312 should be avoided to minimize noise pickup.
Power planes should encompass a digital power plane and an
analog power plane. The analog power plane should contain the
DACs and all associated circuitry, VREF circuitry. The digital
power plane should contain all logic circuitry.
Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not the
analog power plane.
The analog and digital power planes should be individually
connected to the common power plane at a single point through
a suitable filtering device, such as a ferrite bead.
The ADV7312 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections due to impedance mismatch.
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the DAC
outputs and should overlay the PCB’s ground plane. As well as
minimizing reflections, short analog output traces will reduce
noise pickup due to neighboring digital circuitry.
For optimum performance, the analog outputs should each
be source and load terminated, as shown in Figure 60. The
termination resistors should be as close as possible to the
ADV7312 to minimize reflections.
To avoid crosstalk between the DAC outputs, it is recommended
that as much space as possible be left between the tracks of the
individual DAC output pins. The addition of ground tracks
between outputs is also recommended.
Any unused inputs should be tied to ground.
REV. 0
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.
Analog Signal Interconnect
For optimum performance, it is recommended that all decoupling
and external components relating to the ADV7312 be located
on the same side of the PCB and as close as possible to the
ADV7312.
–57–
ADV7312
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1F
VAA
+
VAA VAA
10nF
1F
10nF
0.1F
VDD
0.1F
VDD_IO
10, 56
5k
45
36
COMP1, 2
41
VAA
10nF
1
0.1F
1.1k
VDD VDD_IO
19 I2C
VREF 46
ADV7312
S0–S7
RECOMMENDED EXTERNAL
AD1580 FOR OPTIMUM
PERFORMANCE
100nF
DAC A 44
300
50 S_HSYNC
49 S_VSYNC
DAC B 43
48 S_BLANK
300
DAC C 42
C0–C7
UNUSED
INPUTS
SHOULD BE
GROUNDED
VAA
VDD_IO
300
DAC D 39
Y0–Y7
300
63 CLKIN_B
DAC E 38
300
23 P_HSYNC
24 P_VSYNC
VAA
DAC F 37
25 P_BLANK
4.7k
300
33 RESET
4.7F
+
SCLK 22
32 CLKIN_A
VAA
SDA 21
820pF
34 EXT_LF
VDD_IO
100
5k
3040
64
AGND DGND
I2C BUS
VDD_IO
RSET2 35
GND_ IO
5k
100
ALSB 20
680 3.9nF
VDD_IO
5k
SELECTION HERE
DETERMINES
DEVICE ADDRESS
RSET1 47
3040
40
11, 57
Figure 60. Circuit Layout
–58–
REV. 0
ADV7312
APPENDIX 1—COPY GENERATION
MANAGEMENT SYSTEM
PS CGMS Data Registers 2–0
[Subaddress 21h, 22h, 23h]
1080i System
PS CGMS is available in 525p mode conforming to CGMS-A
EIA-J CPR1204-1, transfer method of video ID information using
vertical blanking interval (525p system), March 1998, and
IEC61880, 1998, Video systems (525/60)—video and accompanied data using the vertical blanking interval—analog interface.
If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC
[Subaddress 12h, Bit 7] is set to a Logic 1, the last six bits,
C19–C14, which comprise the 6-bit CRC check sequence, are
calculated automatically on the ADV7312 based on the lower
14 bits (C0–C13) of the data in the data registers and output
with the remaining 14 bits to form the complete 20 bits of the
CGMS data. The calculation of the CRC sequence is based
on the polynomial x6 + x + 1 with a preset value of 111111. If SD
CGMS CRC [Address 59h, Bit 4] and PS/HD CGMS CRC
[Address 12h, Bit 7] is set to a Logic 0, all 20 bits (C0–C19) are
output directly from the CGMS registers (no CRC is calculated,
must be calculated by the user).
CGMS data is applied to Line 19 and on Line 582 of the luminance vertical blanking interval.
When PS CGMS is enabled [Subaddress 12h, Bit 6 = 1], CGMS
data is inserted on line 41. The PS CGMS data registers are at
Addresses 21h, 22h, and 23h.
SD CGMS Data Registers 2–0
[Subaddress 59h, 5Ah, 5Bh]
The ADV7312 supports Copy Generation Management System
(CGMS), conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields.
Bits C/W05 and C/W06 control whether or not CGMS data is
output on odd and even fields. CGMS data can be transmitted
only when the ADV7312 is configured in NTSC mode. The
CGMS data is 20 bits long, and the function of each of these bits
is as shown in the following table. The CGMS data is preceded by
a reference pulse of the same amplitude and duration as a
CGMS bit; see Figure 62.
HD/PS CGMS [Address 12h, Bit 6]
CGMS Functionality
Table XVIII.
Bit
Function
WORD0
B1
B2
B3
Aspect ratio
Display format
Undefined
WORD0
B4, B5, B6
The ADV7312 supports Copy Generation Management System
(CGMS) in HDTV mode (720p and 1080i) in accordance
with EIAJ CPR-1204-2.
WORD1
B7, B8, B9, B10
The HD CGMS data registers are to be found at address 021h,
22h, 23h.
WORD2
B11, B12, B13, B14
Function of CGMS Bits
Word 0–6 bits; Word 1–4 bits; Word 2–6 bits; CRC 6 bits CRC
polynomial = x6 + x + 1 (preset to 111111)
720p System
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
REV. 0
–59–
1
16:9
Letterbox
0
4:3
Normal
Identification information about video
and other signals (e.g., audio)
Identification signal incidental to Word 0
Identification signal and information
incidental to Word 0
ADV7312
CRC SEQUENCE
+700mV
REF
70% 10%
BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
21.2s 0.22s
22T
5.8s 0.15 s
6T
T = 1/(fH 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T 30ns
Figure 61. Progressive Scan CGMS Waveform
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
–40 IRE
49.1s 0.5s
11.2s
2.235s 20ns
Figure 62. Standard Definition CGMS Waveform Diagram
CRC SEQUENCE
+700mV
REF
70% 10%
BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
T 30ns
17.2s 160ns
22 T
4T
3.128s 90ns
T = 1/(fH 1650/58) = 781.93ns
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 63. HDTV 720p CGMS Waveform
CRC SEQUENCE
+700mV
REF
70% 10%
BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
T 30ns
4T
4.15s 60ns
22.84s 210ns
22 T
T = 1/(fH 2200/77) = 1.038s
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 64. HDTV 1080i CGMS Waveform
–60–
REV. 0
ADV7312
APPENDIX 2—SD WIDE SCREEN SIGNALING
[Subaddress 59h, 5Ah, 5Bh]
The ADV7312 support wide screen signaling (WSS) conforming
to the standard. WSS data is transmitted on Line 23. WSS data
can be transmitted only when the device is configured in PAL
mode. The WSS data is 14 bits long, and the function of each of
these bits is shown in Table XIX. The WSS data is preceded by
a run-in sequence and a start code; see Figure 65. If SD WSS
[Address 59h, Bit 7] is set to a Logic 1, it enables the WSS data
to be transmitted on Line 23. The latter portion of Line 23
(42.5 µs from the falling edge of HSYNC) is available for the
insertion of video.
It is possible to blank the WSS portion of Line 23 with
Subaddress 61h, Bit 7.
Table XIX. Function of WSS Bits
Bit
Description
Bit
Description
Bit 0–Bit 2
Aspect Ratio/Format/Position
Bit 3
Odd Parity Check of Bit 0 to Bit 2
B5
0
1
Standard Coding
Motion Adaptive Color Plus
B6
0
1
No Helper
Modulated Helper
B0,
0
1
0
1
0
1
0
1
1
B1,
0
0
1
1
0
0
1
1
1
B2,
0
0
0
0
1
1
1
1
1
B3
1
0
0
1
0
1
1
0
0
B4
0
1
Aspect Ratio
4:3
14:9
14:9
16:9
16:9
>16:9
14:9
16:9
16:9
Format
Full Format
Letterbox
Letterbox
Letterbox
Letterbox
Letterbox
Full Format
N/A
Position
N/A
Center
Top
Center
Top
Center
Center
N/A
B7
B9
0
1
0
1
Camera Mode
Film Mode
Reserved
B10
0
0
1
1
No Open Subtitles
Subtitles in Active Image Area
Subtitles out of Active Image Area
Reserved
B11
0
1
No Surround Sound Information
Surround Sound Mode
B12
Reserved
B13
Reserved
500mV
RUN-IN
SEQUENCE
START
CODE
W0
W1
W2
W3
W4
W5
W6
W7
W8
11.0s
38.4s
42.5s
Figure 65. WSS Waveform Diagram
REV. 0
–61–
W9
W10
W11
W12
W13
ACTIVE
VIDEO
ADV7312
APPENDIX 3—SD CLOSED CAPTIONING
[Subaddress 51h–54h]
All pixels inputs are ignored during Lines 21 and 284 if
closed captioning is enabled.
The ADV7312 support closed captioning conforming to the
standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked
active line time of Line 21 of the odd fields and Line 284 of the
even fields.
FCC Code of Federal Regulations (CFR) 47 section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.
Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic 1 start bit. Sixteen bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits, and
one odd parity bit. The data for these bytes is stored in the SD
closed captioning registers [Address 53h–54h].
The ADV7312 also support the extended closed captioning
operation, which is active during even fields and is encoded on
Scan Line 284. The data for this operation is stored in the SD
closed captioning registers [Address 51h–52h].
All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7312.
10.5 0.25s
The ADV7312 use a single buffering method. This means that
the closed captioning buffer is only 1-byte deep; therefore
there will be no frame delay in outputting the closed captioning
data unlike other 2-byte deep buffering systems. The data must
be loaded one line before (Line 20 or Line 283) it is output on
Line 21 and Line 284. A typical implementation of this method is
to use VSYNC to interrupt a microprocessor, which in turn will
load the new data (two bytes) in every field. If no new data is
required for transmission, 0s must be inserted in both data
registers; this is called nulling. It is also important to load control codes, all of which are double bytes on Line 21, or a TV
will not recognize them. If there is a message like “Hello World”
that has an odd number of characters, it is important to pad it
out to even in order to get “end of caption” 2-byte control code
to land in the same field.
12.91s
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
P
A
R
I
T
Y
D0–D6
D0–D6
BYTE 0
P
A
R
I
T
Y
BYTE 1
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003s
27.382s
33.764s
Figure 66. Closed Captioning Waveform, NTSC
–62–
REV. 0
ADV7312
APPENDIX 4—TEST PATTERNS
The ADV7312 can generate SD and HD test patterns.
T
T
2
2
CH2 200mV
M 10.0s
A CH2
30.6000s
T
1.20V
CH2 100mV
Figure 67. NTSC Color Bars
M 10.0s
CH2
1.82600ms
T
EVEN
Figure 70. PAL Black Bar [–21 mV, 0 mV, 3.5 mV,
7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV]
T
T
2
2
CH2 200mV
M 10.0s
A CH2
30.6000s
T
1.21V
CH2 200mV
Figure 68. PAL Color Bars
EVEN
Figure 71. 525p Hatch Pattern
T
T
2
2
CH2 100mV
M 10.0s
CH2
1.82380ms
T
EVEN
CH2 200mV
Figure 69. NTSC Black Bar [–21 mV, 0 mV,
3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV]
REV. 0
M 4.0s
CH2
1.82944ms
T
M 4.0s
CH2
1.84208ms
T
Figure 72. 625p Hatch Pattern
–63–
EVEN
ADV7312
T
T
2
2
CH2 200mV
M 4.0s
CH2
1.82872ms
T
EVEN
CH2 100mV
Figure 73. 525p Field Pattern
M 4.0s
CH2
1.82936ms
T
EVEN
Figure 75. 525p Black Bar [–35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV]
T
T
2
2
CH2 200mV
M 4.0s
CH2
1.84176ms
T
EVEN
CH2 100mV
Figure 74. 625p Field Pattern
M 4.0s
CH2
1.84176ms
T
EVEN
Figure 76. 625p Black Bar [–35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV]
–64–
REV. 0
ADV7312
The following register settings are used to generate an SD NTSC
CVBS output on DAC A:
Subaddress
Register
Setting
00h
40h
42h
44h
4Ah
80h
10h
40h
40h
08h
For PAL black bar pattern output on DAC A, the same settings
are used except that subaddress = 40h and register setting = 11h.
The following register settings are used to generate a 525p hatch
pattern on DAC D:
All other registers are set as normal/default.
For PAL CVBS output on DAC A, the same settings are used
except that subaddress = 40h and register setting = 11h.
The following register settings are used to generate an SD NTSC
black bar pattern output on DAC A:
Subaddress
Register
Setting
00h
02h
40h
42h
44h
4Ah
80h
04h
10h
40h
40h
08h
Register
Setting
00h
01h
10h
11h
16h
17h
18h
10h
10h
40h
05h
A0h
80h
80h
All other registers are set as normal/default.
For 625p hatch pattern on DAC D, the same register settings
are used except that subaddress = 10h and register setting = 50h.
For a 525p black bar pattern output on DAC D, the same settings
are used as above except that subaddress = 02h and register
setting = 24h.
For 625p black bar pattern output on DAC D, the same settings
are used as above except that subaddress = 02h and register
setting = 24h; and subaddress = 10h and register setting = 50h.
All other registers are set as normal/default.
REV. 0
Subaddress
–65–
ADV7312
APPENDIX 5—SD TIMING MODES
[Subaddress 4Ah]
Mode 0 (CCIR-656)—Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7312 is controlled by the SAV (start active video) and
EAV (end active video) time codes in the pixel data. All timing
information is transmitted using a 4-byte synchronization pattern.
A synchronization pattern is sent immediately before and after
each line during active picture and retrace. S_VSYNC,
S_HSYNC, and S_BLANK (if not used) pins should be tied
high during this mode. Blank output is available.
ANALOG
VIDEO
EAV CODE
INPUT PIXELS
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
4 CLOCK
SAV CODE
0 F F A A A
0 F F B B B
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
1440 CLOCK
4 CLOCK
4 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
4 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
280 CLOCK
1440 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 77. SD Slave Mode 0
–66–
REV. 0
ADV7312
Mode 0 (CCIR-656)—Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7312 generates H, V, and F signals required for the
SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. The H bit is output on the
S_HSYNC, the V bit is output on S_BLANK, and the F bit is
output on S_VSYNC.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
11
20
21
22
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
H
V
ODD FIELD
F
EVEN FIELD
Figure 78. SD Master Mode 0, NTSC
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
H
V
F
ODD FIELD
EVEN FIELD
Figure 79. SD Master Mode 0, PAL
REV. 0
–67–
320
334
335
336
ADV7312
ANALOG
VIDEO
H
F
V
Figure 80. SD Master Mode 0, Data Transitions
Mode 1—Slave Option
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode, the ADV7312 accept horizontal sync and odd/
even field signals. A transition of the field input when HSYNC
is low indicates a new frame, i.e., vertical retrace. The BLANK
signal is optional. When the BLANK input is disabled, the
ADV7312 automatically blank all normally blank lines as per
CCIR-624. HSYNC is input on S_HSYNC, BLANK on
S_BLANK, and FIELD on S_VSYNC.
DISPLAY
DISPLAY
522
523
VERTICAL BLANK
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
260
261
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 81. SD Slave Mode 1 (NTSC)
–68–
REV. 0
ADV7312
Mode 1—Master Option
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7312 can generate horizontal sync and
odd/even field signals. A transition of the field input when
HSYNC is low indicates a new frame, i.e., vertical retrace. The
blank signal is optional. When the BLANK input is disabled, the
ADV7312 automatically blank all normally blank lines as per
CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC is output on the
S_HSYNC, BLANK on S_BLANK, and FIELD on
S_VSYNC.
DISPLAY
DISPLAY
622
623
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
HSYNC
BLANK
ODD FIELD
FIELD
EVEN FIELD
Figure 82. SD Slave Mode 1 (PAL)
HSYNC
FIELD
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 83. SD Timing Mode 1—Odd/Even Field Transitions Master/Slave
REV. 0
–69–
Cr
Y
336
ADV7312
Mode 2— Slave Option
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7312 accepts horizontal and vertical sync
signals. A coincident low transition of both HSYNC and VSYNC
inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field.
The BLANK signal is optional. When the BLANK input is disabled, the ADV7312 automatically blank all normally blank lines
as per CCIR-624. HSYNC is input S_HSYNC, BLANK on
S_BLANK, and VSYNC on S_VSYNC.
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
2
3
4
6
5
7
8
10
9
20
11
21
22
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
Figure 84. SD Slave Mode 2 (NTSC)
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 85. SD Slave Mode 2 (PAL)
–70–
REV. 0
ADV7312
Mode 2—Master Option
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7312 can generate horizontal and vertical
sync signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC
low transition when HSYNC is high indicates the start of an
even field. The BLANK signal is optional. When the BLANK
input is disabled, the ADV7312 automatically blank all normally blank lines as per CCIR-624. HSYNC is output on
S_HSYNC , BLANK on S_BLANK, and VSYNC on
S_VSYNC.
HSYNC
VSYNC
BLANK
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
PIXEL
DATA
Cb
Y
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 86. SD Timing Mode 2 Even to Odd Field Transition Master/Slave
HSYNC
VSYNC
BLANK
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
PAL = 864 CLOCK/2
NTSC = 858 CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 87. SD Timing Mode 2 Odd to Even Field Transition Master/Slave
REV. 0
–71–
Cr
Y
ADV7312
Mode 3—Master/Slave Option
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7312 accept or generate horizontal sync
and odd/even field signals. A transition of the field input when
HSYNC is high indicates a new frame, i.e., vertical retrace. The
BLANK signal is optional. When the BLANK input is disabled,
the ADV7312 automatically blank all normally blank lines as per
CCIR-624. HSYNC is output in master mode and input in slave
mode on S_VSYNC, BLANK on S_BLANK, and VSYNC on
S_VSYNC.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260
DISPLAY
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 88. SD Timing Mode 3 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 89. SD Timing Mode 3 (PAL)
–72–
REV. 0
ADV7312
APPENDIX 6—HD TIMING
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
P_VSYNC
P_HSYNC
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
583
P_VSYNC
P_HSYNC
Figure 90. 1080i HSYNC and VSYNC Input Timing
REV. 0
–73–
584
585
1123
ADV7312
APPENDIX 7—VIDEO OUTPUT LEVELS
HD YPrPb Output Levels
INPUT CODE
EIA-770.2, STANDARD FOR Y
OUTPUT VOLTAGE
INPUT CODE
940
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE
940
700mV
700mV
64
64
300mV
300mV
EIA-770.3, STANDARD FOR Pr/Pb
EIA-770.2, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
OUTPUT VOLTAGE
960
960
600mV
512
700mV
512
700mV
64
64
Figure 91. EIA 770.2 Standard Output Signals
(525p/625p)
INPUT CODE
EIA-770.1, STANDARD FOR Y
Figure 93. EIA 770.3 Standard Output Signals
(1080i, 720p)
OUTPUT VOLTAGE
782mV
INPUT CODE
Y–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
940
700mV
714mV
64
64
300mV
286mV
EIA-770.1, STANDARD FOR Pr/Pb
INPUT CODE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
1023
960
512
Pr/Pb–OUTPUT LEVELS FOR
FULL INPUT SELECTION
700mV
700mV
64
300mV
64
Figure 94. Output Levels for Full Input Selection
Figure 92. EIA 770.1 Standard Output Signals
(525p/625p)
–74–
REV. 0
ADV7312
RGB Output Levels
Pattern: 100%/75% Color Bars
700mV
700mV
525mV
300mV
300mV
700mV
525mV
700mV
525mV
700mV
525mV
300mV
300mV
700mV
525mV
300mV
300mV
Figure 97. SD RGB Output Levels—RGB Sync Disabled
Figure 95. PS RGB Output Levels
700mV
700mV
525mV
300mV
300mV
0mV
0mV
700mV
525mV
300mV
300mV
0mV
0mV
700mV
525mV
300mV
300mV
0mV
0mV
525mV
700mV
525mV
700mV
525mV
Figure 98. SD RGB Output Levels—RGB Sync Enabled
Figure 96. PS RGB Output Levels—RGB Sync Enabled
REV. 0
525mV
–75–
ADV7312
YPrPb Levels—SMPTE/EBU N10
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Pattern: 100% Color Bars
700mV
700mV
BLUE
BLACK
BLUE
BLACK
RED
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
MAGENTA
Figure 102. Pr Levels—PAL
Figure 99. Pb Levels—NTSC
700mV
700mV
300mV
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YELLOW
Figure 103. Y Levels—NTSC
Figure 100. Pb Levels—PAL
700mV
700mV
300mV
Figure 104. Y Levels—PAL
Figure 101. Pr Levels—NTSC
–76–
REV. 0
ADV7312
VOLTS
IRE:FLT
100
0.5
50
0
0
–50
0
F1
L76
10
20
APL = 44.5%
525 LINE NTSC
SLOW CLAMP TO 0.00V AT 6.72s
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SYNC = A
FRAMES SELECTED 1 2
Figure 105. NTSC Color Bars 75%
VOLTS
0.4
IRE:FLT
50
0.2
0
0
–0.2
–50
–0.4
F1
L76
0
10
NOISE REDUCTION: 15.05dB
APL NEEDS SYNC-SOURCE.
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
20
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SYNC = B
FRAMES SELECTED 1 2
Figure 106. NTSC Chroma
REV. 0
–77–
ADV7312
VOLTS
IRE:FLT
0.6
0.4
50
0
0.2
0
0
–0.2
F2
L238
10
20
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SYNC = SOURCE
FRAMES SELECTED 1 2
NOISE REDUCTION: 15.05dB
APL = 44.3%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
Figure 107. NTSC Luma
VOLTS
0.6
0.4
0.2
0
–0.2
L608
0
10
NOISE REDUCTION: 0.00dB
APL = 39.1%
625 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
20
30
40
50
60
MICROSECONDS
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1 2 3 4
Figure 108. PAL Color Bars 75%
–78–
REV. 0
ADV7312
VOLTS
0.5
0
–0.5
L575
10
20
APL NEEDS SYNC-SOURCE.
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
30
40
50
60
MICROSECONDS
NO BUNCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 109. PAL Chroma
VOLTS
0.5
0
L575
0
10
APL NEEDS SYNC-SOURCE.
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72s
20
30
40
50
60
70
MICROSECONDS
NO BUNCH SIGNAL
PRECISION MODE OFF
SYNCHRONOUS
SOUND-IN-SYNC OFF
FRAMES SELECTED 1
Figure 110. PAL Luma
REV. 0
–79–
ADV7312
APPENDIX 8—VIDEO STANDARDS
0HDATUM
SMPTE 274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING
*1
4T
272T
4T
1920T
EAV CODE
ANCILLARY DATA
(OPTIONAL) OR BLANKING CODE
SAV CODE
DIGITAL
ACTIVE LINE
F
F
INPUT PIXELS
0
0
0 F
0 V
H*
F
F
4 CLOCK
SAMPLE NUMBER
2112
C
0 F C
0 V b Y r
H*
0
0
C
Y
r
4 CLOCK
0
2199
2116 2156
44
188
192
2111
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
FOR A FIELD RATE OF 30Hz: 40 SAMPLES
FOR A FIELD RATE OF 25Hz: 480 SAMPLES
Figure 111. EAV/SAV Input Data Timing Diagram—SMPTE 274M
SMPTE 293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
EAV CODE
F
F
INPUT PIXELS
0
0
F
0 V
0 H*
F
F
4 CLOCK
SAMPLE NUMBER
719
DIGITAL
ACTIVE LINE
SAV CODE
0
0
F
0
V
0
H*
C
C
b Y r
C
Y r
Y
4 CLOCK
723 736
0HDATUM
799
853
857
0
719
DIGITAL HORIZONTAL BLANKING
FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8
Figure 112. EAV/SAV Input Data Timing Diagram—SMPTE 293M
–80–
REV. 0
ADV7312
ACTIVE
VIDEO
522
523
ACTIVE
VIDEO
VERTICAL BLANK
524
525
1
2
5
6
7
8
9
12
13
14
15
16
42
43
44
Figure 113. SMPTE 293M (525p)
ACTIVE
VIDEO
622
623
ACTIVE
VIDEO
VERTICAL BLANK
624
625
1
2
4
5
6
7
8
9
10
11
12
13
43
44
45
Figure 114. ITU-R BT.1358 (625p)
DISPLAY
VERTICAL BLANKING INTERVAL
747
748
749
750
1
2
3
4
5
6
7
8
25
26
27
744
745
Figure 115. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
Figure 116. SMPTE 274M (1080i)
REV. 0
–81–
583
584
585
1123
ADV7312
OUTLINE DIMENSIONS
64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
0.75
0.60
0.45
12.00 BSC
SQ
1.60
MAX
64
49
1
48
SEATING
PLANE
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
10ⴗ
6ⴗ
2ⴗ
SEATING
PLANE
0.20
0.09
VIEW A
7ⴗ
3.5ⴗ
0ⴗ
0.08 MAX
COPLANARITY
16
33
32
17
0.50
BSC
VIEW A
ROTATED 90ⴗ CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026BCD
–82–
REV. 0
–83–
–84–
C04483–0–11/03(0)