HANBit HMN4M8D Non-Volatile SRAM MODULE 32Mbit (4,096K x 8-Bit), 40Pin-DIP, 5V Part No. HMN4M8D GENERAL DESCRIPTION The HMN4M8D Nonvolatile SRAM is a 33,554,432-bit static RAM organized as 4,194,304 bytes by 8 bits. The HMN4M8D has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-oftolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain the memory until after VCC returns valid. The HMN4M8D uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide nonvolatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES PIN ASSIGNMENT w Access time : 70, 85, 120, 150 ns w High-density design : 32Mbit Design NC A21 A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC w Battery internally isolated until power is applied w Industry-standard 40-pin 4,096K x 8 pinout w Unlimited write cycles w Data retention in the absence of VCC w 5-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss w Industrial temperature operation OPTIONS MARKING w Timing 70 ns - 70 85 ns - 85 120 ns -100 150 ns -150 URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC VCC A19 NC A15 A17 /WE A13 A8 A9 A11 /OE A10 /CE DQ7 DQ6 DQ5 DQ4 DQ3 NC 40-pin Encapsulated Package 1 HANBit Electronics Co.,Ltd HANBit HMN4M8D FUNCTIONAL DESCRIPTION The HMN4M8D executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A0-A19) defines which of the 4,194,304 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable. When power is valid, the HMN4M8D operates as a standard CMOS SRAM. During power-down and power-up cycles, the HMN4M8D acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN4M8D is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge. The HMN4M8D provides full functional capability for Vcc greater than 4.5 V and write protects by 4.37 V nominal. Powerdown/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold VPFD. When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and all outputs are high impedance. As Vcc falls below approximately 3 V, the power switching circuit connects the lithium energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 4.5 volts. BLOCK DIAGRAM PIN DESCRIPTION ` /OE SRAM /WE Block Power A0-A21 : Address Input A0-A19 4 x 1024K x 8 /CE : Chip Enable DQ0-DQ7 VSS : Ground DQ0-DQ7 : Data In / Data Out /CE CON /WE : Write Enable /CE A20 A21 VCC Power – Fail /OE : Output Enable Control VCC: Power (+5V) Lithium Cell URL : www.hbe.co.kr Rev. 1.0 (May, 2002) NC : No Connection 2 HANBit Electronics Co.,Ltd HANBit HMN4M8D TRUTH TABLE MODE /OE /CE CE2 /WE I/O OPERATION POWER Not selected X H X X High Z Standby Output disable H L H H High Z Active Read L L H H DOUT Active Write X L H L DIN Active ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING DC voltage applied on VCC relative to VSS VCC -0.5V to 7.0V DC Voltage applied on any pin excluding VCC relative to VSS VT -0.3V to 7.0V Operating temperature TOPR CONDITIONS 0 to 70°C Commercial -40 to 85°C Industrial Storage temperature TSTG -55°C to 125°C Temperature under bias TBIAS -40°C to 85°C TSOLDER 260°C Soldering temperature For 10 second NOTE: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. RECOMMENDED DC OPERATING CONDITIONS ( TA= TOPR ) SYMBOL MIN TYPICAL MAX Supply Voltage PARAMETER VCC 4.5V 5.0V 5.5V Ground VSS 0 0 0 Input high voltage VIH 2.2 - Input low voltage VIL NOTE: -0.5 2) - VCC+0.5V 1) 0.8V 1. Overshoot: VCC+3.0V in case of pulse width ≤30ns. 2. Undershoot: -3.0V in case of pulse width ≤30ns. URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 3 HANBit Electronics Co.,Ltd HANBit HMN4M8D CAPACITANCE (TA=25℃ , f=1MHz, VCC=5.0V) DESCRIPTION Input Capacitance Input/Output Capacitance CONDITIONS SYMBOL MAX MIN UNIT Input voltage = 0V CIN 32 - pF Output voltage = 0V CI/O 40 - pF DC AND OPERATION CHARACTERISTICS (TA= TOPR, VCCmin £ VCC≤ VCCmax ) PARAMETER CONDITIONS SYMBOL MIN TYP. MAX UNIT Input Leakage Current VIN=VSS to VCC ILI - - ± 4 mA Output Leakage Current /CE=VIH or /OE=VIH or /WE=VIL ILO - - ± 4 mA Output high voltage IOH=-1.0Ma VOH 2.4 - - V Output low voltage IOL= 2.1mA VOL - - 0.4 V Standby supply current Commerci Standby al supply /CE=VIH ISB - - 12 ㎃ /CE≥ VCC-0.2V, 0V≤ VIN≤ 0.2V, or VIN≥ VCC-0.2V ISB1 - - 200 - - 320 ICC - - 54 ㎃ Power-fail-detect voltage VPFD 4.30 4.37 4.50 V Supply switch-over voltage VSO - 3 - V current Industrial Operating supply current Min.cycle,duty=100%,/CE=VIL, II/O=0㎃ , A20<VIL or A20>VIH A21<VIL or mA A21>VIH CHARACTERISTICS (Test Conditions) PARAMETER Input pulse levels Input rise and fall times Input and output timing reference levels Output load (including scope and jig) URL : www.hbe.co.kr Rev. 1.0 (May, 2002) +5V VALUE 1.9KΩ DOUT 0.4 to 2.2V 5 ns 1.5V ( unless otherwise specified) 4 1.9KΩ DOUT 100㎊ 1KΩ See Figure 1 and 2 +5V 5㎊ 1KΩ Figure 1. Figure 2. Output Load A Output Load B HANBit Electronics Co.,Ltd HANBit HMN4M8D READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax ) PARAMETER SYMBOL Read Cycle Time tRC Address Access Time tACC Chip enable access time CONDITIONS -70 -85 -120 -150 UNIT MIN MAX MIN MAX MIN MAX MIN MAX 70 - 85 - 120 - 150 - ns Output load A - 70 - 85 - 120 - 150 ns tACE Output load A - 70 - 85 - 120 - 150 ns Output enable to Output valid tOE Output load A - 35 - 45 - 60 - 70 ns Chip enable to output in low Z tCLZ Output load B 5 - 5 - 5 - 10 - ns Output enable to output in low Z tOLZ Output load B 5 - 0 - 0 - 5 - ns Chip disable to output in high Z tCHZ Output load B 0 25 0 35 0 45 0 60 ns Output disable to output high Z tOHZ Output load B 0 25 0 25 0 35 0 50 ns Output hold from address change tOH Output load A 10 - 10 - 10 - 10 - ns WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax ) PARAMETER SYMBOL CONDITIONS -70 MIN -85 MAX MIN -120 MAX -150 UNI MIN MAX Min Max T Write Cycle Time tWC 70 - 85 - 120 - 150 - ns Chip enable to end of write tCW Note 1 65 - 75 - 100 - 100 - ns Address setup time tAS Note 2 0 - 0 - 0 - 0 - ns Address valid to end of write tAW Note 1 65 - 75 - 100 - 90 - ns Write pulse width tWP Note 1 55 - 65 - 85 - 90 - ns Write recovery time (write cycle 1) tWR1 Note 3 5 - 5 - 5 - 5 - ns Write recovery time (write cycle 2) tWR2 Note 3 15 - 15 - 15 - 15 - ns Data valid to end of write tDW 30 - 35 - 45 - 50 - ns Data hold time (write cycle 1) tDH1 Note 4 0 - 0 - 0 - 0 - ns Data hold time (write cycle 2) tDH2 Note 4 10 - 10 - 10 - 0 - ns Write enabled to output in high Z tWZ Note 5 0 25 0 30 0 40 0 50 ns Output active from end of write tOW Note 5 5 - 0 - 0 - 5 - ns NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high. 2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE going low and /WE going low. 3. Either tWR1 or tWR2 must be met. 4. Either tDH1 or tDH2 must be met. 5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in highimpedance state. URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 5 HANBit Electronics Co.,Ltd HANBit HMN4M8D DATA RETENTION CHARACTERISTICS (TA= TOPR, VCC=5V) PARAMETER SYMBOL CONDITIONS Vcc for data retention VDR CE≥Vcc-0.2V Data retention current IDR Vcc=3.0V, CE≥Vcc Data retention set-up time tSDR Recovery time See data retention waveform tRDR MIN TYP. MAX UNIT 2.0 - 5.5 V - 20 uA 0 - - 5 - - MIN TYP. MAX UNIT ms POWER-DOWN/POWER-UP CYCLE (TA= TOPR, VCC=5V) PARAMETER SYMBOL VCC slew, 4.75 to 4.25V tPF 300 - - ㎲ VCC slew, 4.75 to VSO tFS 10 - - ㎲ tPU 0 - - ㎲ 40 80 120 ms 5 - - years 40 100 150 ㎲ VCC slew, VSO to VPFD (max) Chip enable recovery time tCER CONDITIONS Time during which SRAM is write-protected after VCC passes VPFD on power-up. Data-retention time in Absence of VCC tDR TA = 25℃ Write-protect time tWPT Delay after Vcc slews down past VPFD before SRAM is Write-protected. TIMING WAVEFORM - Read Cycle No.1 (Address Access)*1,2 tRC Address tACC tOH DOUT URL : www.hbe.co.kr Rev. 1.0 (May, 2002) Previous Data Valid Data Valid 6 HANBit Electronics Co.,Ltd HANBit HMN4M8D - Read Cycle No.2 (/CE Access)*1,3,4 tRC /CE tACE tCHZ tCLZ DOUT High-Z High-Z - Read Cycle No.3 (/OE Access)*1,5 tRC Address tACC /OE tOE DOUT tOHZ tOLZ Data Valid High-Z High-Z NOTES: 1. /WE is held high for a read cycle. 2. Device is continuously selected: /CE = /OE =VIL. 3. Address is valid prior to or coincident with /CE transition low. 4. /OE = VIL. 5. Device is continuously selected: /CE = VIL - WRITE CYCLE NO.1 (/WE-CONTROLLED)*1,2,3 tWC Address tAW tWR1 tCW /CE tAS tWP /WE tDW DIN Data-in Valid tWZ DOUT Rev. 1.0 (May, 2002) tOW High-Z Data Undefined (1) URL : www.hbe.co.kr tDH1 7 HANBit Electronics Co.,Ltd HANBit HMN4M8D - WRITE CYCLE NO.2 (/CE-Controlled)*1,2,3,4,5 Address tAW tAS tWR2 tCW /CE tWP /WE tDH2 tDW Data-in DIN tWZ DOUT Data NOTE: High-Z Undefined 1. /CE or /WE must be high during address transition. 2. Because I/O may be active (/OE low) during this period, data input signals of opposite polarity to the outputs must not be applied. 3. If /OE is high, the I/O pins remain in a state of high impedance. 4. Either tWR1 or tWR2 must be met. 5. Either tDH1 or tDH2 must be met. - POWER-DOWN/POWER-UP TIMING VCC 4.75 tPF VPFD VPFD 4.25 VSO VSO tFS tPU tCER tDR tWPT /CE URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 8 HANBit Electronics Co.,Ltd HANBit HMN4M8D PACKAGE DIMENSION Dimension Min Max A 2.070 2.100 B 0.710 0.740 C 0.365 0.375 D 0.015 - E 0.008 0.013 F 0.590 0.630 G 0.017 0.023 H 0.090 0.110 I 0.080 0.110 J 0.120 0.150 J A H I G C D E B F All dimensions are in inches. ODERING INFORMATION H M N 4 M 8 D– 70 I Operating Temperature : I = Industrial Temp. (-40~85 °C ) Blank = Commercial Temp. (0~70°C) Speed options : 70 = 70 ns 85 = 85ns 120 = 120ns 150 = 150ns Dip type package Device : 4,096K (4M) x 8 bit Nonvolatile SRAM HANBit Memory Module URL : www.hbe.co.kr Rev. 1.0 (May, 2002) 9 HANBit Electronics Co.,Ltd