Freescale MPC18730EP/R2 Power management ic with five power management ic with five power management ic with five power management ic with five Datasheet

Freescale Semiconductor
Technical Data
Document order number: MPC18730
Rev 1.0, 10/2005
Power Management IC with Five
Regulated Outputs
Programmed Through 3-Wire
Serial Interface
18730
POWER MANAGEMENT IC
The MPC18730 Power Management IC (PMIC) regulates five
independent output voltages from either a single cell Li-Ion (2.7 V to
4.2 V input range) or from a single cell Ni-MH or dry cell (0.9 V to
2.2 V input range).
The PMIC includes 2 DC-DC converters and 3 low drop out (LDO)
linear regulators. The output voltage for each of the 5 output voltages
is set independently through a 3-wire serial interface. The serial
interface also configures the PMIC's versatile start-up control system,
which includes multiple wakeup, sleep, standby, and reset modes to
minimize power consumption for portable equipment.
In single cell Li-Ion applications two DC-DC converters are
configured as buck (step-down) regulators. In single cell Ni-MH or dry
cell applications, one DC-DC converter is configured as a boost
(step-up) regulator, and the other as buck-boost regulator. The DCDC converters' output voltages have set ranges 1.613 V to 3.2 V at
up to 120 mA, and 0.805 V to 1.5 V up to 100 mA through the serial
interface.
Features
• Operates from single cell Li-Ion, Ni-MH, or Alkaline
• 2 DC-DC Converters
• 3 Low Drop Regulators
• Serial Interface Sets Output Voltages
• 4 Wake Inputs
• Low Current Standby Mode
• Pb-Free Packaging Designated by Suffix Code EP
MPC18730
2.7 V to 4.2 V Input VB
VB
VO
EXT_G_ON
MCU
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MPC18730EP/R2
-10°C to 65°C
64 QFN
Programmable
1.613 V to 3.2 V
VCC1
VO1
VREF
RSTO1B
VO
EP SUFFIX
98ARL10571D
64-TERMINAL 0.5 mm PITCH
QFN
Programmable
0.805 V to 1.5 V
SW1
VCC2
VO2
SW2
SREGI1
SREGO1
RSTO2B
SREGI2
CONTROL SREGO2
SREGI3
LOGIC
SREGO3
INPUTS
GND
PGND
VG
Programmable
0.865 V to 2.8 V
Programmable
0.011 V to 2.8 V
Programmable
2.08 V to 2.8 V
VB
SWG
Figure 1. MPC18730 Simplified Application Diagram
* This document contains information on a product under development.
Freescale reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VMODE
HVB
VREF RSTO1B(Int)
VREF
CLR
LSWO
VO1
VB
VB
LVB
Driver
VMODE
VO1
RSTO1B(Int)
BANDGAP
REFERENCE
LVB
VO1
V_STBY
VG
VCC1
RSTO2B(Int) POWER
RSTO1B(Int)
VO1 VG SWITCH1
VO1
RSTO1B
RESET
Block 1
VI1
Step-UpDown
DC/DC
Converter
CH1
CRST1
RST1ADJ
INM1
SW1
PGND1
RF1
VG
DTC1
VO1
VCC2
POWER
SWITCH2
RSTO2B(Int)
VG
VO2IN
RSTO2B(Int)
RSTO2B
RESET
Block 2
VO2
DW_2T
REF2
DW_2B
Step-UpDown
DC/DC
Converter
CH2
CRST2
INM2
RF2
VI2
SW2
DTC2
PGND2
VG
REF3
SREGI1
Series Pass
Regulator1
SREGC1
SREGO1
VG
SREGC2
SREGC3
WAKE1B
WAKE2B
WAKE3B
WAKE4B
SEQSEL
DATA
STRB
SCKIN
CLR
SLEEP
CLKIN
GND
VGSEL1
VGSEL2
WDT
SREGI2
Series Pass
Regulator2
REF4
SREGO2
V_STBY
VG
VO1 VB
CLKIN
RSTO1B(Int)
SREGO3
VB
C1L
CPoff
VB VO1 VG
RSTO2B
CONTROL (Int)
SEQSEL
Control
Logic
VG
Step-Up
DC/DC
Convertor
VG_select
VG_duty
REF2
SREGI3
Series Pass
Regulator3
REF5
REF1
SREG2G
REF4
REF3
VG
REF5
EXT gate
On
Buffer
VREF
On
REF DAC
SWG
PGND3
EXT_G_ON
Figure 2. MPC18730 Simplified Internal Block Diagram
18730
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TERMINAL CONNECTIONS
CLR
SREG2G
SREGO2
SREGI2
SREGC1
SREGO1
SREGI1
GND
VREF
DATA
STRB
SCKIN
WDT
SEQSEL
CLKIN
SLEEP
TERMINAL CONNECTIONS
49 SREGC2
1
WAKE4B
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
2
48
SREGI3
WAKE3B
3
47
SREGO3
WAKE2B
4
46
SREGC3
WAKE1B
5
45
EXT_G_ON
LSWO
6
44
DW_2B
LVB
7
43
DW_2T
HVB
8
42
VO2
V_STBY
9
41
VO2IN
40
VCC2
39
VI2
VO1
10
VCC1
11
VI1
12
38
SW2
SW1
13
37
SW2
SW1
14
36
PGND2
PGND1
15
35
PGND2
PGND1
16
34
RSTO2B
TOP VIEW
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DTC2
RF2
INM2
VGSEL1
VGSEL2
VB
PGND3
SWG
VG
C1L
INM1
RF1
DTC1
RST1ADJ
33 CRST2
CRST1
RSTO1B
17
Figure 3. MPC18730 Terminal Connections
Table 1. MPC18730 Terminal Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Terminal
Number
Terminal
Name
Terminal
Function
Formal Name
1
CLR
Input
Clear
2
WAKE4B
Input
Wake Signal 4
Start-up Signal Input 4
3
WAKE3B
Input
Wake Signal 3
Start-up Signal Input 3
4
WAKE2B
Input
Wake Signal 2
Start-up Signal Input 2
5
WAKE1B
Input
Wake Signal 1
Start-up Signal Input 1
6
LSWO
Output
Low-Side Switch
Output
7
LVB
Input
Low Voltage Battery
VB Power Supply Connection for Ni_mh
8
HVB
Input
High Voltage Battery
VB Power Supply Connection for Li_ion
9
V_STBY
Output
Standby Voltage
Definition
Start-up Signal Input Latch/Clear
Low-Side Switch Output Terminal
V_STBY Voltage Output
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
TERMINAL CONNECTIONS
Table 1. MPC18730 Terminal Definitions (continued)
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Terminal
Number
Terminal
Name
Terminal
Function
Formal Name
Definition
10
VO1
Input
Voltage Input 1
Switching Power Supply Circuit 1, VO1 Voltage Input, VO1 Power Supply
11
VCC1
Output
Voltage Output 1
Power Switch 1 Output
12
VI1
Output
Voltage Output 1
Switching Power Supply Circuit 1 Output
13
SW1
Power
Switching 1
Switching Power Supply Circuit 1 Coil Connection
14
SW1
Power
Switching 1
Switching Power Supply Circuit 1 Coil Connection
15
PGND1
Ground
Power Ground 1
Switching Power Supply Circuit 1 Power GND
16
PGND1
Ground
Power Ground 1
Switching Power Supply Circuit 1 Power GND
17
RSTO1B
Output
Inverted Reset
Reset Circuit 1 Reset Signal Output
Output 1
18
CRST1
Input
Reset Delay
Reset Circuit 1 Reset Signal Delaying Capacitor Connection
Capacitor 1
Switching Power Supply Circuit 1 Reset Voltage Reference Output
19
RST1ADJ
Output
Reset1 Adjustment
20
DTC1
Power
Duty Control
21
RF1
Output
22
INM1
Input
Input Minus 1
Switching Power Supply Circuit 1 Error Amp Inverse Input
23
C1L
Power
Charge Pump
Capacitor
VG Power Supply Circuit Charge Pump Capacitor Connection
24
VG
Output
Gate Voltage
VG Power Supply Circuit Voltage Output, Pre-Diver Circuit Power Supply
25
SWG
Power
Switching
26
PGND3
Ground
Power Ground 3
VG Power Supply Circuit Power GND
27
VB
Power
Battery Voltage
VB Power Supply Connection
28
VGSEL2
Output
VG Select 2
VG Power Supply Circuit Output Voltage Setting 2
29
VGSEL1
Output
VG Select 1
VG Power Supply Circuit Output Voltage Setting 1
30
INM2
Input
Input Minus
Switching Power Supply Circuit 2 Error Amp Inverting Input
31
RF2
Output
32
DTC2
Power
Duty Control
Switching Power Supply Circuit 2 Maximum Duty Setting
33
CRST2
Input
Reset Delay
Reset Circuit 2 Reset Signal Delay Capacitor Connection
Switching Power Supply Circuit 1 Maximum Duty Setting
Reference Feedback 1 Switching Power Supply Circuit 1 Error Amp Output
VG Power Supply Circuit Coil Connection
Reference Feedback 2 Switching Power Supply Circuit 2 Error Amp Output
Capacitor 1
34
RSTO2B
Output
Inverted Reset
Reset Circuit 2 Reset Signal Output
Output 2
35
PGND2
Ground
Power Ground 2
Switching Power Supply Circuit 2 Power GND
36
PGND2
Ground
Power Ground 2
Switching Power Supply Circuit 2 Power GND
37
SW2
Power
Switching
Switching Power Supply Circuit 2 Coil Connection
38
SW2
Power
Switching
Switching Power Supply Circuit 2 Coil Connection
39
VI2
Output
Voltage Output
Switching Power Supply Circuit 2 Output
40
VCC2
Output
Voltage Output
Power Switch 2 Output
41
VO2IN
Input
Voltage Input
Power Switch 2 Voltage Input
42
VO2
Input
Voltage Input
Switching Power Supply Circuit 2 VO2 Voltage Input
18730
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Analog Integrated Circuit Device Data
Freescale Semiconductor
TERMINAL CONNECTIONS
Table 1. MPC18730 Terminal Definitions (continued)
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 14.
Terminal
Number
Terminal
Name
Terminal
Function
Formal Name
Definition
43
DW_2T
Output
Step Down Top FET 2
Switching Power Supply Circuit 2 Step down Top side FET Gate Output
for Ni_mh
44
DW_2B
Output
Step Down Bottom
FET 2
45
EXT_G_ON
Output
Gate Switch
46
SREGC3
Power
Regulator Capacitor 3
47
SREGO3
Output
Regulator Output 3
48
SREGI3
Power
Regulator Input 3
49
SREGC2
Power
Regulator Capacitor 2
Series Pass Power Supply Circuit 2 External Feedback Connection
50
SREG2G
Output
Regulator Gate Output
2
Series Pass Power Supply Circuit 2 External Transistor Gate Signal
Output
51
SREGO2
Output
Regulator Output 2
52
SREGI2
Power
Regulator Input 2
53
SREGC1
Power
Regulator Capacitor 1
54
SREGO1
Output
Regulator Output 1
55
SREGI1
Power
Regulator Input 1
56
GND
Ground
Ground
57
VREF
Output
Reference Voltage
58
DATA
Input
Data Signal
59
STRB
Input
Strobe
Serial Interface Strobe Signal Input
60
SCKIN
Input
Serial Clock
Serial Interface Clock Signal Input
61
WDT
Input
Watch Dog Timer
62
SEQSEL
Input
Sequence Input
63
CLKIN
Input
Clock Input
64
SLEEP
Input
Sleep Signal
Switching Power Supply Circuit 2 Step down Bottom side FRT Gate
Output for Ni_mh
External Transistor Gate Signal Output
Series Pass Power Supply Circuit 3 External Feedback Connection
Series Pass Power Supply Circuit 3 Output
Series Pass Power Supply Circuit 3 Power Supply
Series Pass Power Supply Circuit 2 Output
Series Pass Power Supply Circuit 2 Power Supply
Series Pass Power Supply Circuit 1 External Feedback Connection
Series Pass Power Supply Circuit 1 Output
Series Pass Power Supply Circuit 1 Power Supply
GND
Reference Voltage Output
Serial Interface Data Signal Input
Watchdog Timer Capacitor Connection
Start-Up Sequence Setting Input
External Synchronous Clock Signal Input
Sleep Signal Input
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
VB
-0.5 to 5.0
V
VINAN
-0.5 to VO1+0.5
V
VILRSTB
-0.5 to V_STBY+0.5
VILGC
-0.5 to VO1+0.5
VILGSEL
-0.5 to VB+0.5
IOVO1
120
VCC2 Power Supply Circuit
IOVO2
100
SREG1 Power Supply Circuit
IOREG1
80
SREG2 Power Supply Circuit
IOREG2
100
SREG3 Power Supply Circuit
IOREG3
80
ELECTRICAL RATINGS
Power Supply Voltage
Analog Signal Input
(1)
Logic Signal Input
V
WAKE1~4B
CLR, SLEEP, CLKIN, SCKIN, DATA, STRB
VGSEL1,2
Output Power Current
VCC1 Power Supply Circuit (2)
VG Power Supply Circuit
RSTO1B Power Supply Circuit
mA
IOVG
8
IORSTB
-20
Open-Drain Output Apply Voltage
V
RSTO1B
VIODR
-0.5 to 3.3
LSWO
VIODV
-0.5 to 3.3
VESD1
± 1500
VESD2
± 200
VCDM
± 750
Ambient
TA
-10 to 65
Junction
TJ
150
TSTG
-50 to 150
°C
RθJA
69
°C/W
TSOLDER
260
°C
ESD Voltage
V
Human Body Model (HBM) (3)
Machine Model (MM) (4)
Charge Device Model (CDM)
THERMAL RATINGS
Operating Temperature
Storage Temperature
Thermal Resistance
(5)
°C
Junction to Ambient
Lead Soldering Temperature(6)
Notes
1. VREF, DTC1, DTC2, SREGC1, SREGC2, SREGC3 and RST1ADJ.
2. Includes the series pass power supply circuit output current.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
4.
5.
6.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system
module specification with a capacitor 0.01 µF connected from OUT to GND.
Device mounted on a 2s2p test board, in accordance with JEDEC JESD51-6 and JESD51-7.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
18730
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Analog Integrated Circuit Device Data
Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
GENERAL
VB Power Supply Voltage
V
Power Supply Voltage 1
VLVB
0.9
1.2
2.2
Power Supply Voltage 2
VHVB
2.7
3.5
4.2
Series Regulator Input Voltage (7), (8)
Start-Up Voltage
Analog Signal Input
(10)
VSREGI
VSREG+0.2
(9)
VSREG+0.3
VSREG+0.4
V
VBST
0.9
-
-
V
VIANA
0
-
VO1
V
VILRSTB
0
-
V_STBY
VILGC
0
-
VO1
VILGSEL
0
-
VB
Logic Signal Input
RSTO1 ~ 4B
CLR, SLEEP, CLKIN, DATA, STRB and SCKIN
VGSEL1, 2
V
Output Power Current
VCC1 Power Supply Circuit (11)
mA
IOVCC1
0
-
100
IOVCC2
0
-
80
SREG1 Power Supply Circuit
IOSREG1
5
-
60
SREG2 Power Supply Circuit
IOSREG2
6
-
80
SREG3 Power Supply Circuit
IOSREG3
5
-
60
VCC2 Power Supply Circuit (11)
VG Power Supply Circuit
IOVG
0
-
6
IORSTB
-5
-
0
VB Supply Current (VB = 1.2 V for Ni_MH)
IBSNi
-
5
10
(HVB = 3.5 V for Li-Ion)
IBSLi
-
8
12
VB Supply Current (VB = 1.2 V for Ni_MH)
IBNi
-
9
18
(HVB = 3.5 V for Li-Ion)
IBLi
-
7
14
Output Voltage
VREF
1.255
1.275
1.295
V
Output Current
IOREF
-0.3
-
0.3
mA
VCC1
2.3
2.4
2.5
V
RSTO
Supply Current in Stand-by mode
Supply Current in Operating mode
mA
mA
Reference Power Supply Circuit
Switching Power Supply 1
VCC1 Output Voltage (Io = 0~100 mA)
Notes
7.
8.
9.
10.
11.
When applying voltage from an external source.
0.3 V when VG is 4.5 V.
Provide 2 V or higher for the voltage difference (VG - VO1).
VREF, DTC1, DTC2, SREGC1, SREGC2, SREGC3 and RST1ADJ.
Includes the series pass power supply circuit output current.
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
STATIC ELECTRICAL CHARACTERISTICS
This paragraph is boilerplate - you may add to it but, can not change wording. You may change numeric values
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Switching Power Supply 2
Unit
V
VCC2 Output Voltage (Io = 0~80 mA)
VCC2
1.05
1.15
1.25
DW_2T Output Voltage (12) (Isource = 400 µA)
VDW2TH
5.2
-
VG
(Isink = 400 µA)
0
-
0.3
DW_2B Output Voltage (12) (Isource = 400 µA)
VDW2TL
VDW2BH
5.2
-
VG
(Isink = 400 µA)
VDW2BL
0
-
0.3
VSREG1
2.7
2.8
2.9
V
SR1OFST
-13.5
-
24.5
mV
Series Pass Power Supply Circuit
SREG1 Control Voltage (Io = 5~60 mA) (13)
SREG1-Error AMP Input offset voltage (14)
SREG2 Control Voltage (Io = 6~80 mA) (13)
VSREG2
2.7
2.8
2.9
V
SREG2-Error AMP Input offset voltage (15)
SR2OFST
-17
-
17
mV
SREG3 Control Voltage (Io = 5~60 mA) (13)
2.9
V
VSREG3
2.7
2.8
SREG3-Error AMP Input offset voltage (16)
SR3OFST
-11
-
23
mV
SREG2G Output Voltage (17) (Isource = 2.5 µA)
SREG2GH
5
-
VG
V
(Isink = 2.5 µA)
SREG2GL
0
-
0.5
V
VCC1 Circuit
RVCC1
-
0.4
0.6
VCC2 Circuit
RVCC2
-
0.4
0.6
VG_00
5.5
6.0
6.5
5.4
Power Switch On Resistance
Ω
VG Power Supply Circuit
V
(Io = 0~6 mA) (18)
(Io = 0~6 mA) (19)
VG_10
4.6
5.0
C1L Output Voltage (Isource = 2.5 mA)
VO11LH
VB x 0.85
-
VB
(Isink = 2.5 mA)
VO11LL
0
-
0.4
VGH
-
-
10.5
VLVB
1.75
-
2.45
VGH Voltage (Certified value)
V_STBY Output Voltage for Li_ion (Io = 300 µA)
(20)
V
Notes
12. Connect a transistor with gate capacity of 200 pF or smaller to DW_2T and DW_2B
13. If a capacitor with capacitance of 22µF is connected to SREGO, use a phase compensation capacitor between SREGO and SREGC
when the load is 5 mA (6 mA for SREG2) or lower. The output voltage values shown in the table assume that external resistance is
connected as follows:
SREGI1 = 3.0V to 3.3V, 65.14KΩ between SREGO1 and SREGC1, 34.86KΩ between SREGC1 and GND.
SREGI2 = 3.0V to 3.3V, 54.46KΩ between SREGO2 and SREGC2, 45.54KΩ between SREGC2 and GND.
SREGI3 = 3.0V to 3.3V, 73.84KΩ between SREGO3 and SREGC3, 26.16KΩ between SREGC3 and GND.
14. Calculated by the right formula for input offset: SR1OFST=(Vref x 0.77) - (SREGO1 ÷ (100k ÷ 34.86k))
15. Calculated by the right formula for input offset: SR2OFST=(Vref x 1) - (SREGO1 ÷ (100k ÷ 45.54k))
16. Calculated by the right formula for input offset: SR3OFST=(Vref x 0.58) - (SREGO1 ÷ (100k ÷ 26.16k))
17. Connect a transistor with gate capacity of 300 pF or smaller to REG2G.
18. When VGSEL1 is Low and VGSEL2 is Low, I/O=3mA or higher is certified by specification.
19. When VGSEL1 is High and VGSEL2 is Low, I/O=3mA or higher is certified by specification.
20. When HVB is 4.2V and the load from V_STBY is 0.5µA or higher.
18730
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Analog Integrated Circuit Device Data
Freescale Semiconductor
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Reset Voltage 1
VRST1
0.85 x VO1
0.88 x VO1
0.91 x VO1
V
Reset Voltage 2
VRST2
0.80 x VO2
0.85 x VO2
0.90 x VO2
V
Hysteresis Voltage 1 (@RST1)
VHYRS1
40
78
115
mV
Hysteresis Voltage 2 (@RST2)
VHYRS2
50
75
100
mV
Reset Circuit
RSTB (VRSTB = 2.4 V)
IORSTB1,2
0
-
10
µA
VOLRSTB1,2
0
-
0.5
V
CRST (Isink = 100 µA)
VOLCR1,2
0
-
0.7
V
High Level Threshold Voltage
VIHCR1,2
1.25
1.42
1.65
V
VILCR1,2
0.75
1.00
1.15
V
RPUPRC1,2
50
100
150
KΩ
(Isink = 2 mA)
Low Level Threshold Voltage
CRST Pull-Up Resistance
V_STBY Output Resistance
Ω
Output Resistance (VO1)
RVO1
-
30
45
Output Resistance (VB)
RVB
-
200
400
RLSWO
-
42
50
Ext_G_ON Output Voltage (Isource = 100 µA)
VOHEXTG
VG x 0.9
-
VG
(Isink = 100 µA)
VOLEXTG
0
-
VG x 0.1
VIHVS
V_STBY - 0.2
-
-
V
VILVS
-
-
0.2
V
VIH
1.5
-
-
V
VIL
-
-
0.4
V
VIHVB
VB - 0.2
-
-
V
VILVB
-
-
0.2
V
IIH
-1
-
1
µA
LSWO Output Resistance
Ω
Output Resistance
Ext_G_ON
V
Logic Input
"H" Level Input Voltage (21)
"L" Level Input Voltage (21)
"H" Level Input Voltage (22)
"L" Level Input Voltage (22)
"H" Level Input Voltage (23)
"L" Level Input Voltage (23)
"H" Level Input Current (21), (23)
"L" Level Input Current (23), (24)
Pull Up Resistance (25)
Pull Down Resistance (26)
Notes
21.
22.
23.
24.
25.
26.
IIL
-1
-
1
µA
RPUP
410
590
770
KΩ
RPDW
330
480
625
KΩ
Applied to WAKEB1 ~ 4 and SEQSEL.
Applied to CLR, SLEEP, CLKIN, DATA, STRB and SCKIN.
Applied to VGSEL1 and 2.
Applied to WAKEB1 ~ 3, CLR, SLEEP, CLKIN, DATA, STRB, SCKIN and SEQSEL.
Applied to WAKEB4.
Applied to CLR, SLEEP, CLKIN, DATA, STRB and SCKIN.
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions VB = 1.2 V, VO1 = 2.4 V, VG = 6.0 V, fCLK = 176.4 kHz unless otherwise noted. Typical
values noted reflect the approximate parameter means at TA = 27°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
fICK
150
200
250
kHz
fCLK
-
176.4
-
kHz
DATA Set Up Time
ts
20
-
-
nsec
DATA Hold Time
th
20
-
-
nsec
fsck
-
6.0
-
MHz
SCKIN 'H' Pulse Width
twckh
50
-
-
nsec
SCKIN 'L' Pulse Width
twckl
50
-
-
nsec
SCKIN Hold Time
thck
50
-
-
nsec
STRB Set Up Time
tssb
50
-
-
nsec
STRB Pulse Width
twsb
50
-
-
nsec
OSCILLATOR
Internal Oscillation Frequency
MICRO CONTROLLER INTERFACE
Clock Signal Input (27)
Serial Interface (Refer to Timing Chart below)
SCKIN Clock Frequency
Notes
27. Duty 50%.
18730
10
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DIAGRAMS
FUNCTIONAL DIAGRAMS
WAKE1~4(int)
INT
CLKIN
EXT (Serial setting)
VO1
V_STBY
VB
VB
VB
VB
VG
VG
VB
VB
VO1
RSTO1B(Int)
CRST set value
VO1
RSTO1B
VO1
VO1
VB*1
VB*1
VO1
VCC1
VO2
VO2
VO2
VCC2
VO1
RSTO2B(Int)
CRST set value
VO1
RSTO2B
SEQSEL setting
VSREG1~3
DATA
DATA
STRB
SEQSEL setting
CLR
SLEEP
Standby Mode
Start-Up
*1: When using Ni_mh. High-Z when using Li_ion.
Operation Mode
Standby Mode
Figure 4. Power Supply Start-Up Timing Diagram
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FUNCTIONAL DIAGRAMS
tssb
twckh
twckl
thck
SCKIN
th
ts
DATA
A3
A2
D0
twsb
STRB
Figure 5. Serial Interface Timing Diagrams
18730
12
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DIAGRAMS
Table 5. Serial Interface Functions
Register Name Address
DATA1
DATA2
0
CLR, SLEEP
1000
CLR
SLEEP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
Power Mode
0001
PSW1
PSW2
RSTO1B
VCC2
SREG1
SREG2
SREG3
RSTO2B
2
Clock Select
0010
Ext / Int
Half Freq
RSTB sleep
S_Off_VG
VG_Duty[3]
VG_Duty[2]
VG_Duty[1]
VG_Duty[0]
3
VO1
0011
MSB
VO1 Output Voltage
LSB
S_Off_VO1
4
VO2
0100
MSB
VO2 Output Voltage
LSB
S_Off_VO2
5
SREG1
0101
MSB
SREG1 Output Voltage
LSB
Reserved
6
SREG2
0110
MSB
7
SREG3
0111
MSB
SREG2 Output Voltage
SREG3 Output Voltage
Twelve bits immediately before start-up of STRB are
always effective. Upon power on, the internal power on reset
works to initialize the registers. Serial data is fetched in the
LSB
LSB
CP Off
EXTG On
order of Add_[3], Add_[2], ..., Add_[0], DATA1_[3],
DATA1_[2], ...., DATA2_[0].
Table 6. Block Operation
INPUT
OUTPUT
WAKE(Int)
RSTO1B(Int)
RSTO1B
RSTO2B(Int)
SEQSEL
VG
VO1
VO2
VCC1,2
REG1,2,3
L
X
X
X
X
-
-
-
-
-
H
L
L
L
L
O
O
-
-
-
H
H
L
L
L
O
O
-
-
O
H
H
L
L
H
O
O
-
-
-
H
H
H
H
L
O
O
O
O
O
H
H
H
H
H
O
O
O
O
O
O : Operation, - : Stop, X : Don’t care
Table 7. Start-Up Sequence Settings
SEQSEL
CLR/SLEEP
Series Regulators
V_STBY
RSTO2B(Ext)
RSTO2B(Int)
GND
RSTO1B(Ext)
RSTO1B(Int)
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 18730 power management integrated circuit provides
five independent output voltages for the micro controller from
either a single cell Li-Ion or from a single cell Ni-MH or dry
cell. The PMIC includes two DC to DC converters and three
low drop out linear regulators. The output voltage for each of
the five output voltages is set independently through a 3-wire
serial interface. The PMIC has multiple wakeup, sleep, and
reset modes to minimize power consumption for portable
equipment. In single cell Li-Ion applications two DC-DC
converters are configured as buck regulators. In single cell
Ni-MH or dry cell applications, one DC-DC converter is
configured as a boost regulator, and the other as buck-boost
regulator.
FUNCTIONAL TERMINAL DESCRIPTION
CLEAR TERMINAL (CLR)
VOLTAGE OUTPUT TERMINALS (VCC1, VCC2)
This Clear input signal makes clear internal latches for
WAKE signal holding. The WAKE control circuit can not
receive another WAKE input until the latch is cleared by this
Clear input.
Output ‘VO1’ or ‘VO2’ voltage controlled internal power
switch.
WAKE SIGNAL TERMINALS (WAKE1B, WAKE2B,
WAKE3B, WAKE4B) ... ACTIVE LOW
Any one WAKE input signal of these four WAKE inputs
awakes this device from sleep mode. The WAKE signals can
be made with external low side mechanical switch and
resistance that is pulled up to VSTB rail.
LOW-SIDE SWITCH OUTPUT TERMINAL (LSWO)
POWER INPUT TERMINALS (VI1, VI2)
The power input terminals (VI1, VI2) are drain terminals on
the top side FET of the DC/DC converter switcher. They are
the power input for the buck converter and output for the
boost converter.
SWITCHING TERMINALS (SW1, SW2)
Switching Terminals (SW1, SW2) are the output of the half
bridge and connect to the external inductance.
Low-Side switch output that is turned on with ‘CLR’ signal.
It can be used for external key input latches clear.
POWER GROUND TERMINALS (PGND1, PGND2,
PGND3)
LOW VOLTAGE BATTERY TERMINAL (LVB)
Ground level node for DC/DC converter and Charge Pump
portion.
This input terminal is used for temporarily power supply
while wake up for 1cell Ni-MH battery or 1cell dry cell battery
(= Low Voltage Battery) use. It has to be connected to VB rail.
When Li-Ion battery is used, the terminal has to be open.
INVERTED RESET OUTPUT TERMINALS (RSTO1B,
RSTO2B)
HIGH VOLTAGE BATTERY TERMINAL (HVB)
This input terminal is used for temporarily power supply
while wake up for Li-Ion battery (= High Voltage Battery) use.
It has to be connected to the VB rail. When a Ni-MH battery
is used, the terminal has to be connected to ground level.
STANDBY VOLTAGE TERMINAL (V_STBY)
Standby Voltage is made from LVB or HVB that depends
on which battery is used. This voltage is used for internal
logic and analog circuit at standby (sleep) mode temporarily
before ‘VO1’ voltage is established.
VOLTAGE INPUT TERMINALS (VO1, VO2)
This power supply input terminal named ‘VO1 or VO2’ is
for internal logic and analog circuits and for input of ‘VCC1’
output via power switch. Input for ‘VCC2’ is ‘VO2IN’ terminal.
It is supplied from the output of Channel-1 or Channel-2 DC/
DC converter as ‘VO1 or VO2.
Reset signal output for external MPU or the something
controller. RSTO1B keeps ‘Low’ level while the VO1 voltage
is less than internal reference voltage. RSTO2B follows to
VO2 voltage.
RESET DELAY CAPACITOR TERMINALS (CRST1,
CSRT2)
The capacitor which is connected to this terminal decide
delay time to negate Reset signal from exceeding the
reference voltage level.
RESET 1 ADJUSTMENT TERMINAL (RST1ADJ)
Used to adjust the reset level with external resistance
which is connected to VO1 for RSTO1B.
DUTY CONTROL TERMINALS (DTC1, DTC2)
Connected external voltage to this terminal via
capacitance can control the duty of DC/DC converter
switching. Use of the terminal for this is not recommended.
18730
14
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
REFERENCE FEEDBACK TERMINALS (RF1, RF2)
Output node of internal error amp. for DC/DC converter 1
and 2. For phase compensation use.
Input the feed back voltage that divided SREGO voltage by
resistances.
INPUT MINUS TERMINALS (INM1, INM2)
REGULATOR OUTPUT TERMINALS (SREGO1,
SREGO2, SREGO3)
Minus input of internal error amp. for DC/DC converter 1
and 2. For phase compensation use.
Series regulator output terminals. All output voltages can
be variable with internal DAC via serial I/F.
CHARGE PUMP CAPACITOR TERMINAL (C1L)
REGULATOR INPUT TERMINALS (SREGI1,
SREGI2, SREGI3)
In case of use higher voltage than VG externally, connect
capacitance and diodes between VG. The charge pump
structure can output VG + VB - 2 x VF voltage. There is no
meaning for Ni-MH or dry cell battery, because the VB
voltage is almost same as 2 x VF voltage. Recommend to use
for Li-Ion battery use.
Series regulator power input terminals. To be connected to
battery voltage in general.
GROUND TERMINAL (GND)
GATE VOLTAGE TERMINAL (VG)
Ground terminal for logic and analog circuit portion (not
power portion). Recommend to connect to clean ground
which separated with power ground line.
Output terminal of boost converter for gate drive voltage.
The output voltage is decided by VGSEL input.
REFERENCE VOLTAGE TERMINAL (VREF)
SWITCHING FOR GATE VOLTAGE TERMINAL
(SWG)
Switching terminal for VG boost converter. Connect to
external inductance.
BATTERY VOLTAGE TERMINAL (VB)
Power supply input that connects to Ni-MH or Dry cell or
Li-Ion battery.
VG SELECT TERMINALS (VGSEL1, VGSEL2)
VG output voltage is decided with these two bits input.
VOLTAGE INPUT FOR POWER SWITCH 2
TERMINAL (VO2IN)
Input of VCC2 output via power switch. Connect to VO2
terminal externally.
STEP DOWN FET GATE DRIVE TERMINALS
(DW_2T, DW_2B)
Gate drive output terminals for external FETs to use DC/
DC converter 2 as Buck / Boost converter.
Output of internal reference voltage. It can be used
externally. Output current capacity is less than 300uA.
DATA INPUT TERMINAL (DATA)
Serial data input terminal. The latest 12 bits before strobe
signal are valid.
STROBE TERMINAL (STRB)
Strobe signal input terminal for serial I/F. It establishes the
input 12bits data to internal control registers.
SERIAL CLOCK TERMINAL (SCKIN)
Clock input terminal for serial I/F. Input data are taken in to
I/F with this clock.
WATCH DOG TIMER TERMINAL (WDT)
Watch dog timer prevent unstable wake up (flips between
wake-up and failure). If there is no ‘CLR’ input after any
WAKEnB input before this WDT is expired, this device move
to ‘SLEEP’ mode to prevent wake failure hanging-up
situation.
SEQUENCE SELECT TERMINAL (SEQSEL)
Gate drive output terminal for external low side switch. It
can be used for power switch turning On/OFF for remote
controller part.
Select judgement Reset channel for wake-up complete
with this input. If this input level is VSTB voltage, this device
judges the wake-up completion with Reset2 (DC/DC2). If it is
Ground, judge with Reset1 (DC/DC1). See Table 7, on page
13.
REGULATOR CONTROL TERMINALS (SREGC1,
SREGC2, SREGC3)
CLOCK INPUT TERMINAL (CLKIN)
GATE SWITCH TERMINAL (EXT_G_ON)
Feed back terminal for each series regulators. This
terminal voltage is compared with internal reference voltage.
Clock input terminal for internal switching part. This device
has a oscillator internally, but can be used this input clock for
internal switching frequency. It is selected by Clock select bit.
See Table 19, on page 26.
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
FUNCTIONAL DESCRIPTION
FUNCTIONAL TERMINAL DESCRIPTION
SLEEP MODE TERMINAL (SLEEP)
The sleep input signal puts the device in sleep mode. All
output voltages are down, and internal current consumption
will be minimum.
18730
16
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
START-UP CONTROL INPUT (SYSTEM CONTROL)
The latch is set at the rising edge of any WAKE1B-4B input
pin, and WAKE(int) goes High. WAKE1~4B inputs consist of
OR logic. At this time, the input pin which went Low keeps
latched until CLR goes High. After the latch is reset by CLR,
WAKE(int) goes Low when SLEEP goes High. The latch is
also cleared and WAKE(int) goes Low when SLEEP goes
High before the latch is cleared by CLR. In this case, CLR
keeps negated while RSTO1B, 2B(Ext) is Low. SLEEP keeps
negated while RSTO1B, 2B(Ext) is Low or CLR is High. The
period of time for which CLR and SLEEP are negated can be
set by the SEQSEL pin. Refer to Truth Table 5, on page 13
for the correspondence between the SEQSEL pin settings
and negation period.
If SLEEP goes High to place the chip into the standby
mode while any of the WAKEB pins is Low, the chip can be
awakened again. This may happen if, when an WAKEB pin
and LSWO are connected, SLEEP goes High earlier than the
period of time (*1) specified by the external component of the
WAKEB pin.
Also, if the period of time after WAKE(int) goes High until
CLR goes High from Low is longer than the time specified by
WDT, internal sleep will start up to place the chip into the
standby mode.
(*1: It is 30 µsec when a capacitor is not connected as the
external component.)
WAKEB
CLR
Time specified by WDT
WDT
WAKE(Int)
Figure 6. Start-Up Timing Diagram
STANDBY POWER SUPPLY CIRCUIT
LSWO
Short-circuit VB and LVB, and connect a Schottky
diode between VB and V_STBY only when using
Ni_mh.
CLR
VB
HVB
VO1
Standby
Power
RST1B(Int) Supply
Control
VB
LVB
RST1B
V_STBY
V_STBY
When using Li_ion, leave LVB open, and shortcircuit HVB and VB.
Figure 7. Standby Power Supply Circuit Diagram
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
When RSTO1B(int) is Low, output LVB voltage to V_STBY
terminal. When RSTO1B(int) is High, output VO1 voltage to
V_STBY terminal. When CLR is Low, LSWO is open. When
RSTO1B(int) is High and CLR is High, LSWO output voltage
turns GND. When RSTO1B(int) is Low and RSTO1B is High,
discharge the external capacitor which is connected to
V_STBY. When using Ni_mh, short-circuit VB and LVB to
external components and HVB to GND. When using Li_ion,
short-circuit HVB to VB, and leave LVB open. When using
Ni_MH, the VB voltage is output from V_STBY in Standby
mode. When using Li-Ion, 50% of the VB voltage is output to
V_STBY terminal in Standby Mode.
Table 8. HVB and LVB Connection
MODE
HVB
LVB
Li_ion
VB(28)
open
Ni_mh
GND
VB(28)
Notes
28. Externally connect to VB.
Table 9. V_STBY and LSWO Operation
INPUT
OUTPUT
WAKE(Int)
RSTO1B(Int)
CLR
V_STBY
LSWO
L
X
X
VB
Z
H
L
X
VB
Z
H
H
L
VO1
Z
H
H
H
VO1
L
Z : High Impedance, X : Don’t care
RESET CIRCUIT
VO1
CRST1, 2
VO1, 2 VG
RST1ADJ
(RSTO1B side only)
VO1
BANDGAP
REFERENCE
RST1B, 2B
Reset
Control
CRST1, 2
RSTO1B, 2B(Int)
Figure 8. Reset Circuit Block Diagram
When the VO1 or VO2 voltage is higher than the reference
value, RSTO1B or 2B goes High. When RSTO1B(int) is Low
and RSTO1B is High, SLEEP(int) is forced to place the chip
into the standby mode.
Connect a capacitor between RST1ADJ and CRST. The
capacitor is not necessary if a resistor of 330KΩ or less is
inserted between RST1ADJ and VC1 for reset adjustment
Connect the capacitor between RST1ADJ and RSTB as
directed below.
When SEQSEL is Low: Between RST1ADJ and CRST1
When SEQSEL is High: Between RST1ADJ and CRST2
Use a capacitor with approximately half of the
capacitance between CRST and GND
18730
18
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RST1B(Int)
RST1B
SLEEP(Int)
Figure 9. Reset Timing Diagram
POWER SUPPLY VO1, VO2: NI_MH
The VB voltage rises and is output to VI1. When
RSTO2B(int) is High, the power switch turns ON to output the
VO1 voltage to VCC1. Capacitance value which is connected
to VO1 should be higher than the capacitor connected to
VCC1.
The VB voltage rises or falls and is output to VI2. When
RSTO2B(int) is High, the power switch turns ON to output the
VO2IN voltage to VCC2. If you turn DDC2 OFF using the
register, the power switch 2 also turns OFF. Capacitance
value which is connected to VO2IN should be higher than the
capacitor connected to VCC2.
Table 10. Output Voltage of VO1
Address : 0011(30)
B7
B6
B5
B4
B3
B2
B1
S_Off_VO1
VO1 [V](29)
L
L
L
L
L
L
L
X
1.613
L
L
L
L
L
L
H
X
1.625
L
L
L
L
L
H
L
X
1.638
L
L
L
L
H
L
L
X
1.663
L
L
L
H
L
L
L
X
1.713
L
L
H
L
L
L
L
X
1.813
L
H
L
L
L
L
L
X
2.013
H
L
L
L
L
L
L
X
2.413
H
L
L
L
L
L
H
X
2.425
H
L
L
L
L
H
L
X
2.438
H
L
L
L
H
L
L
X
2.463
H
L
L
H
L
L
L
X
2.513
H
L
H
L
L
L
L
X
2.613
H
H
L
L
L
L
L
X
2.813
H
H
H
H
H
H
H
X
3.200
Notes
29. Operation is not guaranteed when VO1 input voltage is 1.8 V or lower. By connecting a diode between
VI1 and VO1, VI1 can output voltage higher (with the voltage difference Vf) than VO1.
30. All combinations of input are not included.
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 11. Output Voltage of VO2
Address : 0100(31)
B7
B6
B5
B4
B3
B2
B1
S_Off_VO2
VO2 [V]
L
L
L
L
L
L
L
X
0.805
L
L
L
L
L
L
H
X
0.811
L
L
L
L
L
H
L
X
0.816
L
L
L
L
H
L
L
X
0.827
L
L
L
H
L
L
L
X
0.849
L
L
H
L
L
L
L
X
0.893
L
H
L
L
L
L
L
X
0.980
H
L
L
L
L
L
L
X
1.155
H
L
L
L
L
L
H
X
1.161
H
L
L
L
L
H
L
X
1.166
H
L
L
L
H
L
L
X
1.177
H
L
L
H
L
L
L
X
1.199
H
L
H
L
L
L
L
X
1.243
H
H
L
L
L
L
L
X
1.330
H
H
H
H
H
H
H
X
1.500
Notes
31. All combinations of input are not included.
POWER SUPPLY VO1, VO2: LI-ION
The VB voltage falls and is output to VO1. When using
Li_ion, duty limit due to DTC1 is not applied to the switch.
When RSTO2B(int) is High, the power switch turns ON to
output the VO1 voltage to VCC1. Capacitance value which is
connected to VO1 should be higher than the capacitor
connected to VCC1.
The VB voltage falls using only the internal transistor and
is output to VO2. When using Li_ion, duty limit due to DTC2
is not applied to the switch, and DW_2T and DW_2B are Low.
When RSTO2B(int) is High, the power switch turns ON to
output the VO2IN voltage to VCC2. If you turn DDC2 OFF
using the register, the power switch 2 also turns OFF.
Capacitance value which is connected to VO2IN should be
higher than the capacitor connected to VCC2.
18730
20
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SERIES PASS POWER SUPPLY
The series pass outputs the SREGI1 voltage to SREGO1,
the SREGI2 voltage to SREGO2, and the SREGI3 voltage to
SREGO3. If you use MOSFET as the external component in
this case, connect the gate to SREG2G.
Table 12. Output Voltage of SREG1
Address : 0101(31)
B7
B6
B5
B4
B3
B2
B1
Reserved
SREG1 [V](32)
L
L
L
L
L
L
L
H
0.865
L
L
L
L
L
L
H
H
0.880
L
L
L
L
L
H
L
H
0.895
L
L
L
L
H
L
L
H
0.926
L
L
L
H
L
L
L
H
0.986
L
L
H
L
L
L
L
H
1.107
L
H
L
L
L
L
L
H
1.349
H
L
L
L
L
L
L
H
1.833
H
L
L
L
L
L
H
H
1.848
H
L
L
L
L
H
L
H
1.863
H
L
L
L
H
L
L
H
1.893
H
L
L
H
L
L
L
H
1.954
H
L
H
L
L
L
L
H
2.075
H
H
L
L
L
L
L
H
2.317
H
H
H
H
H
H
H
H
2.800
Notes
32. The SREG1 and 3 output voltages are determined by the combination of external resistances connected to
REGC1 and 3 (65.14KΩ between SREGO1 and REGC1, 34.86KΩ between REGC1 and GND, 73.84KΩ
between SREGO3 and REGC3, and 26.16KΩ between REGC3 and GND).
33. All combinations of input are not included.
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 13. Output Voltage of SREG2
Address : 0110(31)
B7
B6
B5
B4
B3
B2
B1
B0
SREG2
[V]
L
L
L
L
L
L
L
L
0.011
L
L
L
L
L
L
L
H
0.022
L
L
L
L
L
L
H
L
0.033
L
L
L
L
L
H
L
L
0.055
L
L
L
L
H
L
L
L
0.098
L
L
L
H
L
L
L
L
0.186
L
L
H
L
L
L
L
L
0.361
L
H
L
L
L
L
L
L
0.711
H
L
L
L
L
L
L
L
1.411
H
L
L
L
L
L
L
H
1.422
H
L
L
L
L
L
H
L
1.433
H
L
L
L
L
H
L
L
1.455
H
L
L
L
H
L
L
L
1.498
H
L
L
H
L
L
L
L
1.586
H
L
H
L
L
L
L
L
1.761
H
H
L
L
L
L
L
L
2.111
H
H
H
H
H
H
H
H
2.800
B2
CP Off
EXTG
On
SREG3
[V](35)
Notes
34. All combinations of input are not included.
Table 14. Output Voltage of SREG3
Address : 0111(31)
B7
B6
B5
B4
B3
L
L
L
L
L
L
X
X
2.080
L
L
L
L
L
H
X
X
2.091
L
L
L
L
H
L
X
X
2.102
L
L
L
H
L
L
X
X
2.125
L
L
H
L
L
L
X
X
2.170
L
H
L
L
L
L
X
X
2.260
H
L
L
L
L
L
X
X
2.440
H
L
L
L
L
H
X
X
2.451
H
L
L
L
H
L
X
X
2.462
H
L
L
H
L
L
X
X
2.485
H
L
H
L
L
L
X
X
2.530
H
H
L
L
L
L
X
X
2.620
H
H
H
H
H
H
X
X
2.800
Notes
35. The SREG1 and 3 output voltages are determined by the combination of external resistances
connected to REGC1 and 3 (65.14KΩ between SREGO1 and REGC1, 34.86KΩ between REGC1
and GND, 73.84KΩ between SREGO3 and REGC3, and 26.16KΩ between REGC3 and GND).
36. All combinations of input are not included.
18730
22
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
VG GENERATOR
VB
VG
VG
Step-Up
Pre Driver
LG
Start Up
VG
VB
VG
PGND3
VG_select
VG_duty
Figure 10. Circuit when using a Step-Up Converter
When WAKE (int) goes High from Low, the start-up circuit
raises the VB voltage and outputs it to VG, then outputs the
VG voltage when RSTO1B (int) goes High. The charge pump
circuit can be used for both Ni_mh and Li_ion by setting the
necessary registers. The charge pump circuit is disabled by
default.
The VG voltage can be set to 6 V to 4.5 V according to the
combination of VGSEL1 and 2 pin connections. Refer to
Table 16, VG Voltage Settings and VGSEL1 and 2 Pin
Connection on page 24 for the VG voltage settings.
When using a charge pump, please refer to Figure 11.
VB
VB
VG
CPoff
C1L
VGH
VG
VG
Start Up
VG
VB
Step-Up
Pre Driver
VG
LG
PGND3
VG_select
VG_duty
Figure 11. Circuit When Using a Charge Pump
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
23
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 15. VG Duty Settings
Address : 0010
Ext/Int
Half Freq
RSTB sleep
S_Off_VG
VG_Duty[3]
VG_Duty[2]
VG_Duty[1]
VG_Duty[0]
Duty
X
X
X
X
L
L
L
L
90 %
X
X
X
X
L
L
L
H
86 %
X
X
X
X
L
L
H
L
82 %
X
X
X
X
L
H
L
L
74 %
X
X
X
X
H
L
L
L
58 %
X
X
X
X
H
L
L
H
54 %
X
X
X
X
H
L
H
L
50 %
X
X
X
X
H
H
L
L
42 %
X
X
X
X
H
H
H
H
30 %
Table 16. VG Voltage Settings and VGSEL1 and 2 Pin Connection
VGSEL1
VGSEL2
VG [V]
GND
GND
6.0
GND
VB
5.5
VB
GND
5.0
VB
VB
4.5
18730
24
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
REGISTER MAPPINGS
Table 17. CLR and SLEEP Control Register
1000
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
CLR
SLEEP
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
0
CLR : CLR Control
1 = CLR is high
0 = CLR is low
SLEEP : SLEEP Control
1 = SLEEP is high
0 = SLEEP is low
Reserved : Freescale defined register *1
1 = Forbidden
0 = Required
Reserved : Freescale defined register *1
1 = Forbidden
0 = Required
Reserved : Freescale defined register *1
1 = Forbidden
0 = Required
Reserved : Freescale defined register *1
1 = Forbidden
0 = Required
Reserved : Freescale defined register *1
1 = Forbidden
0 = Required
Reserved : Freescale defined register *1
1 = Forbidden
0 = Required
Note : Do NOT change Reserved Register from default
value.
*1: Data write to this address (1000) is allowed for the
most significant two bits only. The least significant 6 bits are
only used for the factory test. When writing data, always write
0 to these six bits.
Table 18. Power Mode Register
0001
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
PSW1
PSW2
RSTO1B
VCC2
SREG1
SREG2
SREG3
RSTO2B
Default
1
1
0
1
1
1
1
0
PSW1 : VCC1 Power Switch control
1 = Power Switch on
0 = Power Switch off
PSW2 : VCC2 Power Switch control
1 = Power Switch on
0 = Power Switch off
RSTO1B : RSTO1B Mask *1
1 = RSTO1B mask on
0 = RSTO1B mask off
VO2 : DC/DC Converter Channel 2 output Control *2
1 = DDC2 on
0 = DDC2 off
SREG1 : Series Pass Regulator Channel1 output Control
1 = Regulator on
0 = Regulator off
SREG2 : Series Pass Regulator Channel2 output
Control *3
1 = Regulator off
0 = Regulator on
SREG3 : Series Pass Regulator Channel3 output Control
1 = Regulator on
0 = Regulator off
RSTO2B : RSTO2B Mask
*1
1 = RSTO2B mask on
0 = RSTO2B mask off
*1: When switching the output voltage of VO1 (2), write 1
to the RSTO1B (2) Mask bit in advance to fix the rest output
to High for preventing erroneous operation.
*2: When turning DDC2 OFF, set the RSTO2B bit to High
to Mask RSTO2B. If you turn DDC2 OFF, the power switch 2
also turns OFF.
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
25
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 19. Clock Select Register
0010
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
Ext/Int
Half Freq
RSTB sleep
S_Off_VG
VG_Duty [3]
VG_Duty[2]
VG_Duty[1]
VG_Duty[0]
Default
0
0
1
0
0
0
0
0
Ext / Int : Clock Select control 1
1 = External Clock
0 = Internal Clock
2FS : Clock Select control 2
1 = 2FS on
0 = 2FS off
RSTB Sleep : RSTB Sleep Monitor
*1
1 = RSTB SLEEP Monitor off
0 = RSTB SLEEP Monitor on
S_Off_VG : VG Top side transistor off
1 = Synchronous Rectification Off
0 = Synchronous Rectification On
VG_Duty[3] : VG Duty Control MSB
1 = VG Duty[3] is high
0 = VG Duty[3] is low
VG_Duty[2] : VG Duty Control Bit 2
1 = VG Duty[2] is high
0 = VG Duty[2] is low
VG_Duty[1] : VG Duty Control Bit1
1 = VG Duty[1] is high
0 = VG Duty[1] is low
VG_Duty[0] : VG Duty Control LSB
1 = VG Duty[0] is high
0 = VG Duty[0] is low
VG is controlled by PFM method. This register can change
the duty by 16 steps.
Refer to Table 15, VG Duty Settings on page 24 for the
correspondence between the VG Duty maximum values and
register settings.
Table 20. VO1 Output Voltage Register
0011
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
VO1_V[6]
VO1_V[5]
VO1_V[4]
VO1_V[3]
VO1_V[2]
VO1_V[1]
VO1_V[0]
S_Off_VO1
Default
1
0
0
0
0
0
0
0
VO1_V[6] : Reference DAC MSB
1 = VO1_V[6] on
0 = VO1_V[6] off
VO1_V[1] : Reference DAC Bit1
1 = VO1_V[1] on
0 = VO1_V[1] off
VO1_V[5] : Reference DAC Bit5
1 = VO1_V[5] on
0 = VO1_V[5] off
VO1_V[4] : Reference DAC Bit4
1 = VO1_V[4] on
0 = VO1_V[4] off
VO1_V[3] : Reference DAC Bit3
1 = VO1_V[3] on
0 = VO1_V[3] off
VO1_V[2] : Reference DAC Bit2
1 = VO1_V[2] on
0 = VO1_V[2] off
VO1_V[0]: Reference DAC LSB
1 = VO1_V[0] on
0 = VO1_V[0] off
S_Off_VO1 : DDC1 Top side (Ni_mh) / Bottom side
(Li_ion) transistor off
1 = Synchronous Rectification Off
0 = Synchronous Rectification On
Refer to Table 10, Output Voltage of VO1 on page 19 for
the correspondence between the output voltage and register
settings.
18730
26
Analog Integrated Circuit Device Data
Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 21. VO2 Output Voltage Register
0100
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
VO2_V[6]
VO2_V[5]
VO2_V[4]
VO2_V[3]
VO2_V[2]
VO2_V[1]
VO2_V[0]
S_Off_VO2
Default
1
0
0
0
0
0
0
0
VO2_V[6] : Reference DAC MSB
1 = VO2_V[6] on
0 = VO2_V[6] off
VO2_V[5] : Reference DAC Bit5
1 = VO2_V[5] on
0 = VO2_V[5] off
VO2_V[4] : Reference DAC Bit4
1 = VO2_V[4] on
0 = VO2_V[4] off
VO2_V[3] : Reference DAC Bit3
1 = VO2_V[3] on
0 = VO2_V[3] off
VO2_V[2] : Reference DAC Bit2
1 = VO2_V[2] on
0 = VO2_V[2] off
VO2_V[1] : Reference DAC Bit1
1 = VO2_V[1] on
0 = VO2_V[1] off
VO2_V[0]: Reference DAC LSB
1 = VO2_V[0] on
0 = VO2_V[0] off
S_Off_VO2 : DDC2 Top side & DW2B (Ni_mh) / Bottom
side (Li_ion) transistor off
1 = Synchronous Rectification Off
0 = Synchronous Rectification On
Refer to Table 11, Output Voltage of VO2 on page 20 for
the correspondence between the output voltage and register
settings.
Table 22. Regulator1 Output Voltage Register
0101
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
SREG1_V[6]
SREG1_V[5]
SREG1_V[4]
SREG1_V[3]
SREG1_V[2]
SREG1_V[1]
SREG1_V[0]
Reserved
Default
1
1
1
1
1
1
1
1
SREG1_V[6] : Reference DAC MSB
1 = SREG1_V[6] on
0 = SREG1_V[6] off
SREG1_V[5] : Reference DAC Bit5
1 = SREG1_V[5] on
0 = SREG1_V[5] off
SREG1_V[4] : Reference DAC Bit4
1 = SREG1_V[4] on
0 = SREG1_V[4] off
SREG1_V[3] : Reference DAC Bit3
1 = SREG1_V[3] on
0 = SREG1_V[3] off
SREG1_V[2] : Reference DAC Bit2
1 = SREG1_V[2] on
0 = SREG1_V[2] off
SREG1_V[1] : Reference DAC Bit1
1 = SREG1_V[1] on
0 = SREG1_V[1] off
SREG1_V[0]: Reference DAC LSB
1 = SREG1_V[0] on
0 = SREG1_V[0] off
Reserved : Blank register bit (Freescale Pre-Defined
Register)
1 = Preferred
0 = Forbidden
Note : Do NOT change Reserved Register from default
value.
Refer to Table 12, Output Voltage of SREG1 on page 21
for the correspondence between the output voltage and
register settings.
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 23. Regulator2 Output Voltage Register
0110
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
SREG2_V[7]
SREG2_V[6]
SREG2_V[5]
SREG2_V[4]
SREG2_V[3]
SREG2_V[2]
SREG2_V[1]
SREG2_V[0]
Default
1
1
1
1
1
1
1
1
SREG2_V[7]: Reference DAC MSB
1 = SREG2_V[7] on
0 = SREG2_V[7] off
SREG2_V[6] : Reference DAC Bit6
1 = SREG2_V[6] on
0 = SREG2_V[6] off
SREG2_V[5] : Reference DAC Bit5
1 = SREG2_V[5] on
0 = SREG2_V[5] off
SREG2_V[4] : Reference DAC Bit4
1 = SREG2_V[4] on
0 = SREG2_V[4] off
SREG2_V[3] : Reference DAC Bit3
1 = SREG2_V[3] on
0 = SREG2_V[3] off
SREG2_V[2] : Reference DAC Bit2
1 = SREG2_V[2] on
0 = SREG2_V[2] off
SREG2_V[1] : Reference DAC Bit1
1 = SREG2_V[1] on
0 = SREG2_V[1] off
SREG2_V[0]: Reference DAC LSB
1 = SREG2_V[0] on
0 = SREG2_V[0] off
Refer to Table 13, Output Voltage of SREG2 on page 22
for the correspondence between the output voltage and
register settings.
Table 24. Regulator3 Output Voltage Register
0111
Data1
Data2
Bit
3
2
1
0
3
2
1
0
Name
SREG3_V[5]
SREG3_V[4]
SREG3_V[3]
SREG3_V[2]
SREG3_V[1]
SREG3_V[0]
CP Off
EXTG On
Default
1
1
1
1
1
1
1
1
SREG3_V[5] : Reference DAC MSB
1 = SREG3_V[5] on
0 = SREG3_V[5] off
SREG3_V[4] : Reference DAC Bit4
1 = SREG3_V[4] on
0 = SREG3_V[4] off
SREG3_V[3] : Reference DAC Bit3
1 = SREG3_V[3] on
0 = SREG3_V[3] off
SREG3_V[2] : Reference DAC Bit2
1 = SREG3_V[2] on
0 = SREG3_V[2] off
SREG3_V[1] : Reference DAC Bit1
1 = SREG3_V[1] on
0 = SREG3_V[1] off
SREG3_V[0]: Reference DAC LSB
1 = SREG3_V[0] on
0 = SREG3_V[0] off
CP Off : Charge Pump Control
1 = Charge Pump off
0 = Charge Pump on
EXTG On : EXT_G_ON Control *
1 = EXT_G_ON is low (GND level)
0 = EXT_G_ON is high (VG level)
EXTG On Register is assumed to use Pch FET as external
MOSFET.
If Nch FET will be used, Control logic should be inverted.
Refer to Table 14, Output Voltage of SREG3 on page 22
for the correspondence between the output voltage and
register settings.
18730
28
Analog Integrated Circuit Device Data
Freescale Semiconductor
TYPICAL APPLICATIONS
LOGIC COMMANDS AND REGISTERS
TYPICAL APPLICATIONS
HVB
VMODE
LVB
Driver
VREF RSTO1B(Int)
CLR
LSWO
VO1
VO1
RSTO1B
VO1
VO1
BANDGAP
REFERENCE
V_STBY
VG
RSTO2B(Int) POWER
RSTO1B(Int)
VO1 VG SWITCH1
VCC1
VO1
VI1
RESET
Block 1
CRST1
VB
VB
LVB
VMODE
RSTO1B(Int)
VO1
VREF
VB
VB
Step-UpDown
DC/DC
Converter
CH1
RST1ADJ
INM1
SW1
PGND1
RF1
CRST1
or
CRST2
VREF
VG
DTC1
VO1
RSTO2B(Int)
VG
VO1
VCC2
POWER
SWITCH2
VO2IN
VO2
RSTO2B(Int)
RSTO2B
RESET
Block 2
CRST2
VB
DW_2T
REF2
DW_2B
Step-UpDown
DC/DC
Converter
CH2
INM2
RF2
VI2
SW2
VREF
DTC2
PGND2
VG
SREGO1
REF3
SREGC1
SREGI1
Series Pass
Regulator1
SREGO1
SREGO2
VG
SREGC2
SREGO3
SREGI2
Series Pass
Regulator2
REF4
SREGO2
SREGC3
V_STBY
WAKE1B
WAKE2B
WAKE3B
WAKE4B
SEQSEL
DATA
STRB
SCKIN
CLR
SLEEP
CLKIN
CLKIN
RSTO1B(Int)
RSTO2B
(Int)
SEQSEL
Control
Logic
VG_duty
WDT
REF4
REF3
VG
VB
SWG
PGND3
VG
REF5
EXT gate
On
Buffer
VREF
On
REF DAC
C1L
Step-Up
DC/DC
Convertor
VG_select
REF2
SREGO3
VB
CPoff
VB VO1 VG
CONTROL
REF1
SREGI3
Series Pass
Regulator3
REF5
GND
VGSEL1
VGSEL2
SREG2G
VG
VO1 VB
EXT_G_ON
Figure 12. MPC18730 Typical Application Diagram (Ni-MH Battery)
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
29
TYPICAL APPLICATIONS
LOGIC COMMANDS AND REGISTERS
VB
HVB
VMODE
LVB
Driver
VO1
VREF
VREF RSTO1B(Int)
CLR
LSWO
VO1
VO1
RSTO1B
VO1
VG
RSTO2B(Int)
POWER
RSTO1B(Int)
VO1 VG SWITCH1
VCC1
VO1
VB
VI1
Step-UpDown
DC/DC
Converter
CH1
SW1
PGND1
RF1
VG
CRST1
or
CRST2
DTC1
VO1
VCC2
POWER
RSTO2B(Int) SWITCH2
VG
VO1
VO2IN
VO2
RSTO2B(Int)
RSTO2B
RESET
Block 2
CRST2
DW_2T
REF2
DW_2B
VB
VI2
Step-UpDown
DC/DC
Converter
INM2
CH2
RF2
SW2
PGND2
DTC2
VG
SREGO1
REF3
SREGC1
SREGI1
Series Pass
Regulator1
SREGO2
SREGO1
VG
SREGC2
SREGO3
REF4
SREGI2
Series
Pass
Regulator2
SREGO2
VG
SREG2G
SREGC3
V_STBY
WAKE1B
WAKE2B
WAKE3B
WAKE4B
SEQSEL
DATA
STRB
SCKIN
CLR
SLEEP
CLKIN
VO1 VB
CONTROL
Control
Logic
SREGI3
Series Pass
Regulator3
REF5
SREGO3
VB
RSTO1B(Int)
CLKIN
RSTO2B
(Int)
SEQSEL
CPoff
VB VO1 VG
C1L
Step-Up
DC/DC
Convertor
VG_select
VG_duty
GND
VGSEL1
VGSEL2
WDT
VB
V_STBY
BANDGAP
REFERENCE
RST1ADJ
INM1
VB
LVB
VMODE
RSTO1B(Int)
RESET
Block 1
CRST1
VO1
VB
VG
SWG
VB
PGND3
VG
REF4
REF2
REF1
REF3
REF5
On
REF DAC
VGH
VREF
EXT gate
On
Buffer
EXT_G_ON
Figure 13. MPC18730 Typical Application Diagram (Li-Ion Battery)
18730
30
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
32
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
34
Analog Integrated Circuit Device Data
Freescale Semiconductor
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
64-TERMINAL 0.5mm pitch
PLASTIC PACKAGE
98ARL10571D
ISSUE B
18730
Analog Integrated Circuit Device Data
Freescale Semiconductor
35
REVISION HISTORY
REVISION HISTORY
Revision
1.0
Date
10/2005
Description of Changes
•
Initial Release
18730
36
Analog Integrated Circuit Device Data
Freescale Semiconductor
REVISION HISTORY
NOTES
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Analog Integrated Circuit Device Data
Freescale Semiconductor
37
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MPC18730
Rev 1.0
10/2005
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