LANSDALE ML12040 Phase-frequency detector Datasheet

ML12040
Phase–Frequency
Detector
Legacy Device: Motorola MC12040
The ML12040 is a phase–frequency detector intended for
use in systems requiring zero phase and frequency difference
at lock. In combination with a voltage controlled oscillator
(such as the ML12149), it is useful in a broad range of
phase–locked loop applications.
14
1
• Operating Frequency = 80 MHz Typical
• Operating Temperature Range TA = 0° to 75°C
P DIP 14 = CP
PLASTIC PACKAGE
CASE 646
Pin Conversion Table
14 Pin DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20 Pin PLCC
2
3
4
6
8
9
10
12
13
14
16
18
19
20
8
19
Outputs
Inputs
3
R
V
U
D
U
D
0
0
1
0
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
0
0
0
1
1
0
1
1
1
0
0
1
4
PLCC 20 = -4P
PLASTIC PACKAGE
CASE 775
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 14
MC12040P
ML12040CP
PLCC 20
MC12040FN
ML12040-4P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN CONNECTIONS
LOGIC DIAGRAM
4 U (fR>fV)
3 U (fR>fV)
R6
R Q
S
VCC1
N.C.
U
U
N.C.
R
VEE
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC2
N.C.
D
D
N.C.
V
N.C.
(Top View)
S
R Q
12 D (fV>fR)
11 D (fV>fR)
V9
VCC1 = Pin 1
VCC2 = Pin 14
VEE = Pin 7
TRUTH TABLE
This is not strictly a functional truth table; i.e., it does not cover all possible
modes of operation. However, it gives a sufficient number of tests to
ensure that the device will function properly in all modes of operation.
Page 1 of 5
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LANSDALE Semiconductor, Inc.
ML12040
ELECTRICAL CHARACTERISTICS
The ML12040 has been designed to meet the DC specifications shown in the test table after thermal equilibrium has been
established. Outputs are terminated through a 50 Ω resistor to
3.0 V for 5.0 V tests and through a 50 Ω resistor to –2.0 V for
–5.2 V tests.
6
R
9
V
U
U
4
3
D
11
D
12
TEST VOLTAGE VALUES
NOTE: For more information on using an ECL device in a
5.0 V system, refer to Application Note AN1406/D,
“Designing with PECL (ECL at 5.0 V)”
(Volts)
@ Test Temperature
Supply Voltage = –5.2V
VIHmax
VILmin
VIHAmin
VILAmax
VEE
0°C
–0.840
–1.870
–1.145
–1.490
–5.2
25°C
–0.810
–1.850
–1.105
–1.475
–5.2
75°C
–0.720
–1.830
–1.045
–1.450
–5.2
MC12040
Symbol
Characteristics
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS BELOW
0°C
Min
25°C
Max
75°C
Min
Max
Min
Max
–120
–60
mAdc
350
350
µAdc
IE
Power Supply Drain
7
IINH
Input Current
6
9
VOH1
Logic “1”
Output Voltage
3
4
11
12
–1.000
–0.840
–0.960
–0.810
–0.900
–0.720
Logic “0”
Output Voltage
3
4
11
12
–1.870
–1.635
–1.850
–1.620
–1.830
–1.595
Logic “1”
Input Voltage
3
4
11
12
–1.020
Logic “0”
Input Voltage
3
4
11
12
VOL1
VOHA2
VOLA2
Unit
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
7
1,14
7
7
1,14
1,14
7
1,14
7
1,14
7
1,14
7
1,14
6
9
Vdc
Vdc
Vdc
–0.980
–0.920
6.9
Vdc
–1.615
–1.600
9
6
9
6
–1.575
6
9
6
9
TEST VOLTAGE VALUES
(Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
0°C
+4.160
+3.130
+3.855
+3.510
+5.0
25°C
+4.190
+3.150
+3.895
+3.525
+5.0
75°C
+4.280
+3.170
+3.955
+3.550
+5.0
Supply Voltage = +5.0V
MC12040
Symbol
Characteristics
Pin
Under
Test
TEST VOLTAGE APPLIED TO PINS BELOW
0°C
Min
25°C
Max
75°C
Min
Max
Min
Max
–115
–60
mAdc
350
350
µAdc
IE
Power Supply Drain
7
IINH
Input Current
6
9
VOH1
Logic “1”
Output Voltage
3
4
11
12
4.000
4.160
4.040
4.190
4.100
4.280
Logic “0”
Output Voltage
3
4
11
12
3.190
3.430
3.210
3.440
3.230
3.470
Logic “1”
Input Voltage
3
4
11
12
3.980
Logic “0”
Input Voltage
3
4
11
12
VOL1
VOHA2
VOLA2
Page 2 of 5
Unit
VIHmax
VILmin
VIHAmin
VILAmax
6
9
VEE
(VCC)
Gnd
1,14
7
1,14
1,14
7
7
1,14
7
1,14
7
1,14
7
1,14
7
Vdc
Vdc
Vdc
4.020
4.080
6.9
Vdc
3.450
3.460
3.490
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9
6
9
6
6
9
6
9
Issue 0
LANSDALE Semiconductor, Inc.
ML12040
Figure 1. AC Tests
VCC = +2.0 V
To Scope Channel A
5.0 µF
0.1 µF
1
14
4
Pulse
Gen 1
PRF = 5.0 MHz
Duty Cycle = 50%
t+ = t– = 1.5 ns ±0.2 ns
6
U
R
3
U
Pulse
Gen 2
To Scope Channel B
11
D
9
V
12
D
7
t–
Pulse
Gen 1
50%
t+
90%
10%
t++
Output
Waveform A
50%
t+–
t++
Output
Waveform B
0.3 V
t–
50%
t+–
VEE = –3.2 or –3.0 V
1.1 V
20ns
Pulse
Gen 2
0.1 µF
50%
t+
NOTES:
1 All input and output cables to the scope are equal lengths of 50 Ω
coaxial cable.
2 Unused input and outputs are connected to a 50 Ω resistor to
ground.
3 The device under test must be preconditioned before performing
the AC tests. Preconditioning may be accomplished by applying
pulse generator 1 for a minimum of two pulses prior to pulse generator 2. The device must be preconditioned again when inputs to
Pins 6 and 9 are interchanged. The same technique applies.
1.1 V
90%
10%
0.3 V
t–
80%
t+
20%
t+
80%
t–
20%
ML12040
0°C
Symbol
Characteristic
25°C
85°C
TEST VOLTAGES/WAVEFORMS
APPLIED TO PINS LISTED
Pulse
Gen 1
Pulse
Gen 2
Pin
Under
Test
Output
Waveform
Max
Max
Max
Unit
VEE
–3.0 or
–3.2 V
VCC
2.0 V
t6+4+
t6+12+
t6+3–
t6+11–
t9+11+
t9+3+
t9+12–
t9+4–
Propagation Delay
6,4
6,12
6,3
6,11
9,11
9,3
9,12
9,4
B
A
A
B
B
A
A
B
4.6
6.0
4.5
6.4
4.6
6.0
4.5
6.4
4.6
6.0
4.5
6.4
4.6
6.0
4.5
6.4
5.0
6.6
4.9
7.0
5.0
6.6
4.9
7.0
ns
6
9
6
9
9
6
9
6
9
6
9
6
6
9
6
9
7
1,14
t3+
t4+
t11+
t14+
Output Rise Time
3
4
11
14
A
B
B
A
3.4
3.4
3.8
ns
6
6
9
9
9
9
6
6
7
1,14
t3–
t4–
t11–
t14–
Output Fall Time
3
4
11
14
A
B
B
A
3.4
3.4
3.8
ns
6
6
9
9
9
9
6
6
7
1,14
Page 3 of 5
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Issue 0
LANSDALE Semiconductor, Inc.
ML12040
Legacy Applications Information
The ML12040 is a logic network designed for use as a phase
comparator for MECL–compatible input signals. It determines
the “lead” or “lag” phase relationship and the time difference
between the leading edges of the waveforms. Since these edges
occur only once per cycle, the detector has a range of ±2π radians.
Operation of the device may be illustrated by assuming two
waveforms, R and V (Figure 2), of the same frequency but differing in phase. If the logic had established by past history that
R was leading V, the U output of the detector (pin 4) would
produce a positive pulse width equal to the phase difference
and the D output (Pin 11 ) would simply remain low.
On the other hand, it is also possible that V was leading R
(Figure 2), giving rise to a positive pulse on the D output and a
constant low level on the U output pin. Both outputs for the
sample condition are valid since the determination of lead or
lag is dependent on past edge crossing and initial conditions at
start–up. A stable phase–locked loop will result from either
condition.
Phase error information is contained in the output duty cycle
that is, the ratio of the output pulse width to total period. By integrating or low–pass filtering the outputs of the detector and shifting the level to accommodate ECL swings, usable analog information for the voltage controlled oscillator can be developed. A
circuit useful for this function is shown in Figure 3.
Figure 2. Timing Diagram
Proper level shifting is accomplished by differentially driving
the operational amplifier from the normally high outputs of the
phase detector (U and D). Using this technique the quiescent
differential voltage to the operational amplifier is zero (assuming matched “1” levels from the phase detector). The U and D
outputs are then used to pass along phase information to the
operational amplifier. Phase error summing is accomplished
through resistors R1 connected to the inputs of the operational
amplifier. Some R–C filtering imbedded within the input network (Figure 3) may be very beneficial since the very narrow
correctional pulses of the ML12040 would not normally be
integrated by the amplifier. Phase detector gain for this configuration is approximately 0.16 volts/radian.
System phase error stems from input offset voltage in the
operational amplifier, mismatching of nominally equal resistors, and mismatching of phase detector “high” states between
the outputs used for threshold setting and phase measuring. All
these effects are reflected in the gain constant. For example, a
16 mV offset voltage in the amplifier would cause an error of
0.016/0.16 = 0.1 radian or 5.7 degrees of error. Phase error can
be trimmed to zero initially by trimming either input offset or
one of the threshold resistors (R1 in Figure 3). Phase error
over temperature depends on how much the offending parameters drift.
Figure 3. Typical Filter and Summing Network
R2
R
3
R1
2
R1
2
R1
2
CC
R1
2
10 to
30V
U
–
V
510
ML12040
Lead
R Leads V
(D Output = “0”)
V Leads R
(D Output = “0”)
Page 4 of 5
C
12
MC1741
+
D
R2
510
CC
Lag
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To
VCO
C
Issue 0
LANSDALE Semiconductor, Inc.
ML12040
OUTLINE DIMENSIONS
P DIP 14 = CP
PLASTIC PACKAGE
(ML12040CP)
CASE 646–06
ISSUE M
14
8
1
7
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
A
F
L
N
C
–T–
SEATING
PLANE
J
K
H
G
D 14 PL
0.13 (0.005)
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
–––
10
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
–––
10
0.38
1.01
M
PLCC 20 = -4P
CASE 775-02
Plastic Package
(ML12040-4P)
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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Issue 0
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