DRV8816 www.ti.com SLRS063 – SEPTEMBER 2013 DMOS DUAL ½-H-BRIDGE MOTOR DRIVERS Check for Samples: DRV8816 FEATURES DESCRIPTION • • • • • • • • The DRV8816 provides a versatile power driver solution with two independent ½-H bridge drivers. The device can drive one brushed DC motor or one winding of a stepper motor, as well as other devices like solenoids. A simple INx/ENx interface allows easy interfacing to controller circuits. 1 Low ON-Resistance (0.83-Ω) Outputs Individual ½-H bridge control Low-Power Sleep Mode 100% PWM Supported 8.0 - 38 V Operating Supply Voltage Range Thermally Enhanced Surface Mount Package Configurable Overcurrent Limit Protection Features – VBB Undervoltage Lockout (UVLO) – Charge Pump Undervoltage (CPUV) – Overcurrent Protection (OCP) – Short-to-Supply Protection (STS) – Short-to-Ground Protection (STG) – Overtemperature Warning (OTW) – Overtemperature Shutdown (OTS) – Fault Condition Indication Pin (nFAULT) APPLICATIONS • • Printers Industrial Automation The output stages use N-channel power MOSFET’s configured as ½-H-bridges. The DRV8816 is capable of peak output currents up to ±2.8 A and operating voltages up to 38 V. An internal charge pump generates needed gate drive voltages. A low-power sleep mode is provided which shuts down internal circuitry to achieve very low quiescent current draw. This sleep mode can be set using a dedicated nSLEEP pin. Internal protection functions are provided for under voltage lockout, charge pump fault, overcurrent protection, short-to-supply protection, short-to-ground protection, overtemperature warning, and overtemperature shutdown. Fault conditions are indicated via an nFAULT pin The DRV8816 is packaged in a 16 pin HTSSOP package with PowerPAD™ (Eco-friendly: RoHS & no Sb/Br) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated DRV8816 SLRS063 – SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. BLOCK DIAGRAM VCP VBB VBB 0.1 µF 100 µF 0.1 µF VCP Predrive CP2 0.1 µF CP1 OUT1 Charge Pump VCP BDC VBB IN1 IN2 Logic PreDrive OUT2 SENSE EN1 x5 EN2 R SENSE VPROPI VCC nSLEEP Undervoltage RVPROPI VCC nFAULT Temperature Sensor GND 2 Submit Documentation Feedback PPAD GND Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 DRV8816 www.ti.com SLRS063 – SEPTEMBER 2013 1 16 PowerPAD - GND nFAULT EN2 IN1 GND nSLEEP EN1 OUT1 SENSE 2 3 4 5 6 7 15 14 13 12 11 10 8 9 IN2 VPROPI VCP GND CP2 CP1 OUT2 VBB TERMINAL FUNCTIONS Name Pin Type Description Comments Power and Ground VBB 9 PWR Power supply Connect to motor supply voltage; bypass to GND with a 0.1 µF plus a 100 µF capacitor rated for VBB GND 4, 13 PWR Device ground Must be connected to ground VCP 14 O Charge pump output Connect a 16 V, 0.1 µF ceramic capacitor to VBB CP1 11 - Charge pump switching node Connect a 0.1 µF X7R capacitor rated for VBB between CP1 and CP2 CP2 12 - IN1 3 I ½-H bridge control IN2 16 Logic high enables the high side ½-H bridge FET; logic low enables the low side FET; internal pulldown EN1 6 I ½-H bridge enable Logic high enables ½-H bridge output; logic low puts the FETs in HI-Z; internal pulldown Control EN2 2 nSLEEP 5 I Device sleep mode Pull logic low to put device into a low-power sleep mode; internal pulldown nFAULT 1 O Fault indication pin Pulled logic low with fault condition; open-drain output requires an external pullup OUT1 7 O ½-H bridge output OUT2 10 O ½-H bridge output SENSE 8 O H-bridge low-side connect 15 O Current-proportional output Output Connect directly to GND or through a sense resistor to set OCP VPROPI VPROPI Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 3 DRV8816 SLRS063 – SEPTEMBER 2013 www.ti.com EXTERNAL COMPONENTS Component Pin 1 Pin 2 CVBB1 VBB GND 0.1 µF capacitor rated for VBB CVBB1 VBB GND 100 µF capacitor rated for VBB CVCP VCP VBB 16 V, 0.1 µF ceramic capacitor (1) (1) RnFAULT VCC RSENSE SENSE Recommended nFAULT > 1 kΩ GND Optional low-side sense resistor connected to shunt VCC is not a pin on the DRV8816, but a VCC supply voltage pullup is required for open-drain output nFAULT ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Load supply voltage -0.6 40 V Charge Pump Voltage (VCP, CP+) -0.6 VBB + 7 V Charge pump negative switching pin range (CP-) -0.6 VBB V Digital pin voltage range (IN1, IN2, EN1, EN2, nSLEEP, nFAULT) –0.3 7 V VBB to OUTx -0.6 40 V OUTx to SENSE -0.6 40 V Sense voltage (SENSE) -0.5 1.0 v 0 2.8 A VPROPI pin voltage range (VPROPI) -0.3 3.6 V TA Operating ambient temperature -40 85 Tj Operating junction temperature -40 190 Tstg Storage temperature range -40 125 VBB VDD VSense H-bridge output current (OUT1, OUT2, SENSE) (1) °C Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE PROTECTION MIN HBM on any other pin 2000 Charge Device Model (CDM) 4 500 Submit Documentation Feedback MAX UNIT V Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 DRV8816 www.ti.com SLRS063 – SEPTEMBER 2013 THERMAL INFORMATION DRV8816 THERMAL METRIC (1) PWP - HTSSOP UNITS 16 PINS Junction-to-ambient thermal resistance (2) θJA 43.9 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 25.3 ψJT Junction-to-top characterization parameter (5) 1.1 ψJB Junction-to-board characterization parameter (6) 25 θJCbot Junction-to-case (bottom) thermal resistance (7) 5.6 (1) (2) (3) (4) (5) (6) (7) 30.8 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS (1) MIN UNIT 38 V VBB Power supply voltage range VCC Logic voltage 5.5 V fPWM Applied PWM signal (IN1 and IN2) 100 kHz IOUT H-bridge output current TA Ambient temperature (1) 8 MAX –40 2.8 A 85 °C Power dissipation and thermal limits must be observed. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 5 DRV8816 SLRS063 – SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VBB) VBB VBB operating voltage 8 fPWM < 50 kHz IVBB VBB operating supply current IVBBQ VBB sleep-mode supply current nSLEEP = 0, TJ = 25°C Charge pump on, Outputs disabled 38 V 6 mA 3.2 mA 10 µA CONTROL INPUTS (IN1, IN2, EN1, EN2, nSLEEP) VIL Input logic low voltage VIH Input logic high voltage IIL Input logic low current IIH Input logic high current IIL Input logic low current IIH Input logic high current VIL Input logic low voltage VIN = 0.8 V VIH Input logic high voltage VIN = 2.8 V IIL Input logic low current IIH Input logic high current RPD Pulldown resistance IN1, IN2, EN1, EN2 IN1, IN2, EN2 EN1 nSLEEP VIN = 0.8 V 0 0.8 VIN = 2.0 V 2 5.5 VIN = 0.8 V –20 +20 VIN = 2.0 V 20 VIN = 0.8 V 16 40 VIN = 2.0 V 40 100 0.8 2.2 μA μA V V VIN = 0.8 V 10 VIN = 2.8 V V 27 50 100 μA kΩ SERIAL AND CONTROL OUTPUT (nFAULT) VOL Output logic low voltage Isink = 1 mA 0.4 V DMOS DRIVERS (OUT1, OUT2, SENSE) Rds(ON) Output ON resistance VTRP SENSE trip voltage Vf Body diode forward voltage tpd Propagation delay time tCOD Crossover delay DAGain Differential amplifier gain Source driver, IOUT = –2.8 A, TJ = 25°C 0.48 Source driver, IOUT = –2.8 A, TJ = 125°C 0.74 Sink driver, IOUT = –2.8 A, TJ = 25°C 0.35 Sink driver, IOUT = –2.8 A, TJ = 125°C 0.52 RSENSE between SENSE and GND 500 0.85 0.7 mV Source diode, If = –2.8 A 1.4 Sink diode, If = 2.8 A 1.4 INx, Change to source or sink ON 600 INx, Change to source or sink OFF 100 Sense = 0.1 V to 0.4 V Ω V ns 500 ns 5 V/V Protection Circuits VUVLO VBB undervoltage lockout VBB rising 6.5 7.5 V VCPUV VCP undervoltage lockout (1) VBB rising; CPUV recovery 12 13.8 V IOCP Overcurrent protection trip level tDEG Overcurrent deglitch time 3.0 µs tOCP Overcurrent retry time 1.6 ms TOTW Thermal shutdown temperature 3 A Die temperature Tj 160 °C TOTW HYS Thermal shutdown hysteresis Die temperature Tj 15 °C TOTS Thermal shutdown hysteresis Die temperature Tj 175 °C Thermal shutdown hysteresis Die temperature Tj 15 °C TOTS (1) 6 HYS Whenever VCP is less than VM + 10 V, a CPUV event occurs. This fault will be asserted whenever VBB is below 12 V. Note that the Hbridges will remain enabled until VBB = VUVLO even through nFAULT is pulled low. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 DRV8816 www.ti.com SLRS063 – SEPTEMBER 2013 FUNCTIONAL DESCRIPTION Power Supervisor Control input nSLEEP is used to minimize power consumption when the DRV8816 is not in use. This disables much of the internal circuitry, including the internal voltage rails and charge pump. nSLEEP is asserted low. A logic high on this input pin results in normal operation. When switching from low to high, the user should allow a 1-ms delay before applying PWM signals. This time is needed for the charge pump to stabilize. Bridge Control The DRV8816 is controlled using separate enable and input pins for each ½-H-bridge. The following table shows the logic for the DRV8816: ENx INx OUTx 0 X Z 1 0 L 1 1 H If a single DC motor is connected to the DRV8816, it is connected between the OUT1 and OUT2 pins as shown in the first image below. Two DC motors may also be connected to the DRV8816. In this mode, it is not possible to reverse the direction of the motors; they will turn only in one direction. The connections are shown below: VBB BDC OUT1 OUT1 VBB OUT1 BDC BDC BDC OUT2 OUT2 OUT2 BDC Motor operation for a single brushed DC motor is controlled as follows: EN1 EN2 IN1 IN2 OUT1 OUT2 Operation 0 X X X Z See (1) Off (coast) X 0 X X See (1) Z Off (coast) 1 1 0 0 L L Brake 1 1 0 1 L H Reverse 1 1 1 0 H L Forward 1 1 1 1 H H Brake Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 7 DRV8816 SLRS063 – SEPTEMBER 2013 www.ti.com Motor operation for dual brushed DC motors is controlled as follows: Motor connected to GND Motor connected to VBB ENx INx OUTx Operation 0 X Z Off (coast) 1 0 L Brake 1 1 H Forward ENx INx OUTx Operation 0 X Z Off (coast) 1 0 L Forward 1 1 H Brake Charge Pump The charge pump is used to generate a supply above VBB to drive the source-side DMOS gates. A 0.1-μF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1-μF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the highside DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. VBB 0.1 µF VCP CP1 VM 0.1 µF CP2 Charge Pump SENSE A low-value resistor can be placed between the SENSE pin and ground for current-sensing purposes. To minimize ground-trace IR drops in sensing the output current level, the current-sensing resistor should have an independent ground return to the star ground point. This trace should be as short as possible. For low-value sense resistors, the IR drops in the PCB can be significant, and should be taken into account. To set a manual overcurrent trip threshold, place a resistor between the SENSE pin and GND. When the SENSE pin rises above 500 mV, the H-bridge output is disabled (High-Z). The device will automatically retry with a period of tOCP. The overcurrent trip threshold can be calculated using Itrip = 500 mV/R. The overcurrent trip level selected cannot be greater than IOCP. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 DRV8816 www.ti.com SLRS063 – SEPTEMBER 2013 VOUT+ VOUT- High-Z IPEAK IOUTx IOCP Enable, Source or Sink tOCP tBLANK nFAULT Motor Lead Short Condition Normal DC No Fault Condition VPROPI The VPROPI output is equal to approximately five times the voltage present on the SENSE pin. VPROPI is meaningful only if there is a resistor connected to the SENSE pin; If SENSE is connected to ground, VPROPI measures 0 V. Also note that during slow decay (brake), VPROPI will measure 0 V. VPROPI can output a maximum of 2.5 V, since at 500 mV on SENSE, the H-bridge is disabled. Protection Circuits The DRV8816 is fully protected against VBB undervoltage, charge pump undervoltage, overcurrent, and overtemperature events. VBB UNDERVOLTAGE LOCKOUT (UVLO) If at any time the voltage on the VBB pin falls below the undervoltage lockout threshold voltage, all FETs in the H-bridge will be disabled and the charge pump will be disabled. Operation will resume when VBB rises above the UVLO threshold. Note that nFAULT does not indicate a UVLO because the CPUV fault is always asserted below VBB = 12 V. VCP UNDERVOLTAGE LOCKOUT (CPUV) During a CPUV event, the VCP voltage is measured to be below VCP + 10 V. If at any time the voltage on the VCP pin falls below the undervoltage lockout threshold voltage, the nFAULT pin will be driven low. The nFAULT pin will be released after operation has resumed. Note that this fault does not disable the output FETs and allows the device to continue operating. When VBB is below 12 V, this fault condition is always asserted and nFAULT is pulled low. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 9 DRV8816 SLRS063 – SEPTEMBER 2013 www.ti.com OVERCURRENT PROTECTION (OCP) The current flowing through the high-side and low-side drivers is monitored to ensure that the motor lead is not shorted to supply or ground. If a short is detected, all FETs in the H-bridge will be disabled, nFAULT is driven low, and a tOCP fault timer is started. After this period, tOCP, the device is then allowed to follow the input commands and another turn-on is attempted (nFAULT becomes high again during this attempt). If there is still a fault condition, the cycle repeats. If after tOCP expires it is determined the short condition is not present, normal operation resumes and nFAULT is released. OVERTEMPERATURE WARNING (OTW) If the die temperature increases past the thermal warning threshold the nFAULT pin will be driven low. Once the die temperature has fallen below the hysteresis level, the nFAULT pin will be released. If the die temperature continues to increase, the device will enter over temperature shutdown as described below. OVERTEMPERATURE SHUTDOWN (OTS) If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the charge pump will be shut down. Once the die temperature has fallen to a safe level operation will automatically resume. THERMAL INFORMATION Thermal Protection If the die temperature exceeds approximately 150°C, the device will be disabled until the temperature drops to a safe level. Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation, insufficient heatsinking, or too high an ambient temperature. Power Dissipation Power dissipation in the DRV8816 is dominated by the power dissipated in the output FET resistance, or RDS(ON). Average power dissipation can be roughly estimated by: PTOT = RD(SON) ´ (IOUT(RMS) )2 (1) where PTOT is the total power dissipation, RD(SON) is the resistance of the HS plus LS FETS, and IOUT(RMS) is the RMS output current being applied to each winding. IOUT(RMS) is equal to approximately 0.7× the full-scale output current setting. The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking. Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. PCB LAYOUT Ground A ground power plane should be located as close to DRV8816 as possible. The copper ground plane directly under the PowerPAD package makes a good location. This pad can then be connected to ground for this purpose. Layout Considerations The printed circuit board (PCB) should use a heavy ground plane. For optimum electrical and thermal performance, the DRV8816 must be soldered directly onto the board. On the underside of the DRV8816 is a PowerPAD package, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. The load supply pin, VBB, should be decoupled with an electrolytic capacitor (typically 100 μF) in parallel with a ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB, connected to VREG, and between CP1 and CP2 should be as close to the pins of the device as possible, in order to minimize lead inductance. 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: DRV8816 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) DRV8816PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DRV8816 DRV8816PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 DRV8816 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV8816PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV8816PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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