TI1 LMP91002SD Sensor afe system: configurable afe potentiostat Datasheet

LMP91002
Sensor AFE System: Configurable AFE Potentiostat for
Low-Power Chemical Sensing Applications
General Description
Features
The LMP91002 is a programmable Analog Front End (AFE)
for use in micro-power electrochemical sensing applications.
It provides a complete signal path solution between a not biased gas sensor and a microcontroller generating an output
voltage proportional to the cell current. The LMP91002’s programmability enables it support not biased electro-chemical
gas sensor with a single design. The LMP91002 supports gas
sensitivities over a range of 0.5 nA/ppm to 9500 nA/ppm. It
also allows for an easy conversion of current ranges from
5μA to 750μA full scale. The LMP91002’s transimpedance
amplifier (TIA) gain is programmable through the I2C interface. The I2C interface can also be used for sensor diagnostics. The LMP91002 is optimized for micro-power applications
and operates over a voltage range of 2.7V to 3.6V. The total
current consumption can be less than 10μA. Further power
savings are possible by switching off the TIA amplifier and
shorting the reference electrode to the working electrode with
an internal switch.
Typical Values, TA = 25°C
2.7 V to 3.6 V
■ Supply voltage
<10 µA
■ Supply current (average over time)
10 mA
■ Cell conditioning current up to
900pA (max)
■ Reference electrode bias current (85°C)
750µA
■ Output drive current
■ Complete potentiostat circuit to interface to most not biased gas sensors
■ Low bias voltage drift
2.75kΩ to 350kΩ
■ Programmable TIA gain
■ I2C compatible digital interface
-40°C to 85°C
■ Ambient operating temperature
14 pin LLP
■ Package
■ Supported by Webench Sensor AFE Designer
Applications
■ Gas detector
■ Amperometric applications
■ Electrochemical blood glucose meter
Typical Application
30182505
AFE Gas Detector
© 2012 Texas Instruments Incorporated
301825 SNIS163
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LMP91002 Sensor AFE System: Configurable AFE Potentiostat for Low-Power Chemical Sensing
Applications
April 24, 2012
LMP91002
Ordering Information
Package
Package
Marking
Part Number
Transport Media
LMP91002SD
14-Pin LLP
NSC Drawing
1k Units Tape and Reel
LMP91002SDE
250 Units Tape and Reel
L91002
LMP91002SDX
SDA14B
4.5k Units Tape and Reel
Connection Diagram
14–Pin LLP
30182502
Top View
Pin Descriptions
Pin
Name
Description
1
DGND
Connect to ground
2
MENB
Module Enable, Active Low
3
SCL
Clock signal for I2C compatible interface
4
SDA
Data for I2C compatible interface
5
NC
6
VDD
7
AGND
Ground
8
VOUT
Analog Output
Supply Voltage
9
C2
External filter connector (Filter between C1 and C2)
10
C1
External filter connector (Filter between C1 and C2)
11
VREF
12
WE
Working Electrode. Output to drive the Working Electrode of the chemical
sensor
13
RE
Reference Electrode. Input to drive Counter Electrode of the chemical sensor
14
CE
Counter Electrode. Output to drive Counter Electrode of the chemical sensor
DAP
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Not Internally Connected
Voltage Reference input
Connect to AGND
2
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model
Charge-Device Model
Machine Model
Voltage between any two pins
Current through VDD or VSS
Current sunk and sourced by CE pin
Current out of other pins(Note 3)
Storage Temperature Range
Junction Temperature (Note 4)
Electrical Characteristics
LMP91002
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
Absolute Maximum Ratings (Note 1)
Operating Ratings
(Note 1)
Supply Voltage VS=(VDD - AGND)
Temperature Range (Note 4)
Package Thermal Resistance (Note 4)
2kV
1kV
200V
6.0V
50mA
10mA
5mA
-65°C to 150°C
150°C
2.7V to 3.6V
-40°C to 85°C
14-Pin LLP (θJA)
44 °C/W
(Note 5)
Unless otherwise specified, all limits guaranteed for TA = 25°C, VS=(VDD – AGND), VS=3.3V and AGND = DGND =0V,
VREF= 2.5V, Internal Zero= 20% VREF. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
Typ
Max
(Note 7) (Note 6) (Note 7)
Units
Power Supply Specification
IS
Supply Current
3-lead amperometric cell mode
MODECN = 0x03
10
15
13.5
Standby mode
MODECN = 0x02
6.5
10
8
Deep Sleep mode
MODECN = 0x00
0.6
1
0.85
µA
Potentiostat
VDD=2.7V;
Internal Zero 50% VDD
-90
-800
90
800
VDD=3.6V;
Internal Zero 50% VDD
-90
-900
90
900
IRE
Input bias current at RE pin
ICE
Minimum operating current
capability
sink
750
source
750
Minimum charging capability
(Note 9)
sink
10
source
10
Open loop voltage gain of
control loop op amp (A1)
300mV≤VCE≤Vs-300mV;
AOL_A1
en_RW
-750µA≤ICE≤750µA
104
Low Frequency integrated noise 0.1Hz to 10Hz
between RE pin and WE pin
(Note 10)
pA
µA
mA
120
dB
3.4
µVpp
0% VREF
Internal Zero=20% VREF
VOS_RW
WE Voltage Offset referred to
RE
0% VREF
Internal Zero=50% VREF
-550
550
µV
-4
4
µV/°C
0% VREF
Internal Zero=67% VREF
0% VREF
Internal Zero=20% VREF
TcVOS_RW
WE Voltage Offset Drift referred
0% VREF
to RE from -40°C to 85°C
Internal Zero=50% VREF
(Note 8)
0% VREF
Internal Zero=67% VREF
3
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LMP91002
Symbol
TIA_GAIN
Parameter
Conditions
Min
Typ
Max
(Note 7) (Note 6) (Note 7)
Units
5
%
±0.05
%
Transimpedance gain accuracy
Linearity
Programmable TIA Gains
TIA_ZV
7 programmable gain resistors
Internal zero voltage
2.75
3.5
7
14
35
120
350
Maximum external gain resistor
350
3 programmable percentages of VREF
20
50
67
3 programmable percentages of VDD
20
50
67
Internal zero voltage Accuracy
RL
PSRR
kΩ
%
±0.04
%
Load Resistor
10
Load accuracy
5
Ω
%
110
dB
Power Supply Rejection Ratio at
RE pin
2.7 ≤VDD≤5.25V
Internal zero 20% VREF
Internal zero 50% VREF
80
Internal zero 67% VREF
External reference specification
VREF
External Voltage reference
range
1.5
Input impedance
I2C Interface
VDD
10
V
MΩ
(Note 5)
Unless otherwise specified, all limits guaranteed for at TA = 25°C, VS=(VDD – AGND), 2.7V <VS< 3.6V and AGND = DGND =0V,
VREF= 2.5V. Boldface limits apply at the temperature extremes
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VOL
Output Low Voltage
Conditions
Max
(Note 7)
Units
V
IOUT=3mA
0.3*VDD
V
0.4
V
V
0.1*VDD
Input Capacitance on all digital pins
Timing Characteristics
Typ
(Note 6)
0.7*VDD
Hysteresis (Note 13)
CIN
Min
(Note 7)
pF
0.5
(Note 5)
Unless otherwise specified, all limits guaranteed for TA = 25°C, VS=(VDD – AGND), VS=3.3V and AGND = DGND =0V, VREF=
2.5V, Internal Zero= 20% VREF. Boldface limits apply at the temperature extremes. Refer to timing diagram in Figure 1.
Symbol
Parameter
fSCL
Clock Frequency
10
tLOW
Clock Low Time
4.7
µs
tHIGH
Clock High Time
4.0
µs
4.0
µs
4.7
µs
0
ns
250
ns
tHD;STA
Data valid
tSU;STA
Set-up time for a repeated START condition
tHD;DAT
Data hold time(Note 12)
tSU;DAT
Data Setup time
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Conditions
After this period, the first clock
pulse is generated
4
Min
Typ
Max
Units
100
kHz
Parameter
tf
SDA fall time (Note 13)
tSU;STO
Set-up time for STOP condition
4.0
µs
tBUF
Bus free time between a STOP and START
condition
4.7
µs
tVD;DAT
Data valid time
3.45
µs
tVD;ACK
Data valid acknowledge time
3.45
µs
tSP
Pulse width of spikes that must be
suppressed by the input filter(Note 13)
50
ns
t_timeout
SCL and SDA Timeout
25
100
ms
tEN;START
I2C Interface Enabling
600
ns
tEN;STOP
I2C Interface Disabling
600
ns
600
ns
tEN;HIGH
time between consecutive
enabling and disabling
Conditions
Min
IL ≤ 3mA;
CL ≤ 400pF
I 2C
interface
Typ
Max
Units
250
ns
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Operating Ratings is not implied. Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such
conditions.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) FieldInduced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: All non-power pins of this device are protected against ESD by snapback devices. Voltage at such pins will rise beyond absmax if current is forced into
pin.
Note 4: The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient
temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board.
Note 5: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >
TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
Note 6: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 7: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using statistical quality
control (SQC) method.
Note 8: Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
Starting from the measured voltage offset at temperature T1 (VOS_RW(T1)), the voltage offset at temperature T2 (VOS_RW(T2)) is calculated according the following
formula: VOS_RW(T2)=VOS_RW(T1)+ABS(T2–T1)* TcVOS_RW.
Note 9: At such currents no accuracy of the output voltage can be expected.
Note 10: This parameter includes both A1 and TIA's noise contribution.
Note 11: In case of external reference connected, the noise of the reference has to be added.
Note 12: LMP91002 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.
Note 13: This parameter is guaranteed by design or characterization.
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LMP91002
Symbol
LMP91002
Timing Diagram
30182541
FIGURE 1. I2C Interface Timing Diagram
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6
Unless otherwise specified, TA = 25°C, VS=(VDD – AGND),
2.7V <VS< 3.6V and AGND = DGND =0V, VREF= 2.5V.
Input VOS_RW vs. temperature
-100
-100
VDD = 2.7V
VDD = 3.3V
-120
-120
-140
-140
-160
-160
-180
-180
VOS (μV)
-200
-220
-200
-220
-240
-240
-260
-260
-280
-280
-300
85°C
25°C
-40°C
-300
-50
-25
0
25
50
75
TEMPERATURE (°C)
100
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
30182563
30182562
IWE Step current response (fall)
NORMALIZED OUTPUT TIA (200mV/DIV)
NORMALIZED OUTPUT (200mV/DIV)
IWE Step current response (rise)
IWE (50μA/DIV)
IWE
2.75kΩ
3.5kΩ
7kΩ
14kΩ
35kΩ
120kΩ
350kΩ
IWE
IWE (50μA/DIV)
VOS (μV)
Input VOS_RW vs. VDD
2.75kΩ
3.5kΩ
7kΩ
14kΩ
35kΩ
120kΩ
350kΩ
TIME (200μs/DIV)
TIME (200μs/DIV)
30182564
30182566
AC PSRR vs. Frequency
Supply current vs. temperature (Deep Sleep Mode)
1.0
140
0.9
SUPPLY CURRENT (μA)
PSRR (dB)
130
120
110
100
90
VDD = 2.7V
VDD = 3.3V
0.8
0.7
0.6
0.5
0.4
0.3
0.2
80
0.1
10
100
1k
10k
FREQUENCY (Hz)
100k
-50
30182560
-25
0
25
50
75
TEMPERATURE (°C)
100
30182591
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LMP91002
Typical Performance Characteristics
LMP91002
Supply current vs. VDD (Deep Sleep Mode)
SUPPLY CURRENT (μA)
0.9
7.50
85°C
25°C
-40°C
VDD = 2.7V
VDD = 3.3V
7.25
SUPPLY CURRENT (μA)
1.0
Supply current vs. temperature (Standby Mode)
0.8
0.7
0.6
0.5
0.4
0.3
7.00
6.75
6.50
6.25
6.00
0.2
5.75
0.1
5.50
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
-50
-25
0
25
50
75
TEMPERATURE (°C)
30182597
Supply current vs. VDD (Standby Mode)
SUPPLY CURRENT (μA)
7.25
30182587
Supply current vs. temperature (3-lead amperometric Mode)
11.0
85°C
25°C
-40°C
VDD = 2.7V
VDD = 3.3V
VDD = 5V
10.8
SUPPLY CURRENT (μA)
7.50
7.00
6.75
6.50
6.25
6.00
5.75
10.6
10.4
10.2
10.0
9.8
9.6
9.4
9.2
5.50
9.0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
-50
-25
0
25
50
75
TEMPERATURE (°C)
30182592
10.6
0.1Hz to 10Hz noise
1.5
85°C
25°C
-40°C
1.0
10.4
EN_RW (μV)
SUPPLY CURRENT (μA)
10.8
10.2
10.0
9.8
9.6
9.4
0.5
0.0
-0.5
-1.0
9.2
9.0
-1.5
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
0
30182593
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100
30182586
Supply current vs. VDD (3-lead amperometric Mode)
11.0
100
1
2
3
4 5 6
TIME (s)
7
8
9 10
30182598
8
LMP91002
A VOUT step response 100 ppm to 400 ppm CO
(CO gas sensor connected to LMP91002)
2.0
LMP91000
1.9
1.8
VOUT (V)
1.7
1.6
1.5
1.4
1.3
1.2
RTIA=35kΩ,
Rload=10Ω,
1.1
1.0
0
25
50
75
100
TIME (s)
125
150
30182568
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LMP91002
2.75kΩ to 350kΩ making it easy to convert current ranges
from 5µA to 750µA full scale. Optimized for micro-power applications, the LMP91002 AFE works over a voltage range of
2.7V to 3.6 V. The cell voltage is user selectable using the on
board programmability. In addition, it is possible to connect
an external transimpedance gain resistor. Depending on the
configuration, total current consumption for the device can be
less than 10µA. For power savings, the transimpedance amplifier can be turned off and instead a load impedance equivalent to the TIA’s inputs impedance is switched in.
Function Description
GENERAL
The LMP91002 is a programmable AFE for use in micropower
chemical sensing applications. The LMP91002 is designed
for 3-lead not biased gas sensors and for 2 leads galvanic
cell. This device provides all of the functionality for detecting
changes in gas concentration based on a delta current at the
working electrode. The LMP91002 generates an output voltage proportional to the cell current. Transimpedance gain is
user programmable through an I2C compatible interface from
30182583
FIGURE 2. System Block Diagram
POTENTIOSTAT CIRCUITRY
The core of the LMP91002 is a potentiostat circuit. It consists
of a differential input amplifier used to compare the potential
between the working and reference electrodes to a zero bias
potential.. The error signal is amplified and applied to the
counter electrode (through the Control Amplifier - A1). Any
changes in the impedance between the working and reference electrodes will cause a change in the voltage applied to
the counter electrode, in order to maintain the constant voltage between working and reference electrodes. A Transimpedance Amplifier connected to the working electrode,
is used to provide an output voltage that is proportional to the
cell current. The working electrode is held at virtual ground
(Internal ground) by the transimpedance amplifier. The potentiostat will compare the reference voltage to the desired
bias potential and adjust the voltage at the counter electrode
to maintain the proper working-to-reference voltage.
Transimpedance amplifier
The transimpedance amplifier (TIA in Figure 2) has 7 programmable internal gain resistors. This accommodates the
full scale ranges of most existing sensors. Moreover an external gain resistor can be connected to the LMP91002 between C1 and C2 pins. The gain is set through the I2C
interface.
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Control amplifier
The control amplifier (A1 op amp in Figure 2) provides initial
charge to the sensor. A1 has the capability to drive up to 10mA into the sensor in order to to provide a fast initial conditioning. A1 is able to sink and source current according to the
connected gas sensor (reducing or oxidizing gas sensor). It
can be powered down to reduce system power consumption.
However powering down A1 is not recommended, as it may
take a long time for the sensor to recover from this situation.
Internal zero
The internal Zero is the voltage at the non-inverting pin of the
TIA. The internal zero can be programmed to be either 67%,
50% or 20%, of the supply, or the external reference voltage.
This provides both sufficient headroom for the counter electrode of the sensor to swing, in case of sudden changes in the
gas concentration, and best use of the ADC’s full scale input
range.
The Internal zero is provided through an internal voltage divider (Vref divider box in Figure 2). The divider is programmed
through the I2C interface.
10
WRITE AND READ OPERATION
In order to start any read or write operation with the
LMP91002, MENB needs to be set low during the whole communication. Then the master generates a start condition by
driving SDA from high to low while SCL is high. The start condition is always followed by a 7-bit slave address and a Read/
Write bit. After these 8 bits have been transmitted by the master, SDA is released by the master and the LMP91002 either
ACKs or NACKs the address. If the slave address matches,
the LMP91002 ACKs the master. If the address doesn't
30182572
(a) Register write transaction
30182571
(b) Pointer set transaction
11
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LMP91002
match, the LMP91002 NACKs the master. For a write operation, the master follows the ACK by sending the 8-bit register
address pointer. Then the LMP91002 ACKs the transfer by
driving SDA low. Next, the master sends the 8-bit data to the
LMP91002. Then the LMP91002 ACKs the transfer by driving
SDA low. At this point the master should generate a stop condition and optionally set the MENB at logic high level (refer
to Figure 3).
A read operation requires the LMP91002 address pointer to
be set first, also in this case the master needs setting at low
logic level the MENB, then the master needs to write to the
device and set the address pointer before reading from the
desired register. This type of read requires a start, the slave
address, a write bit, the address pointer, a Repeated Start (if
appropriate), the slave address, and a read bit (refer to
Figure 3). Following this sequence, the LMP91002 sends out
the 8-bit data of the register.
When just one LMP91002 is present on the I2C bus the MENB
can be tied to ground (low logic level).
I2C INTERFACE
The I2C compatible interface operates in Standard mode
(100kHz). Pull-up resistors or current sources are required on
the SCL and SDA pins to pull them high when they are not
being driven low. A logic zero is transmitted by driving the
output low. A logic high is transmitted by releasing the output
and allowing it to be pulled-up externally. The appropriate
pull-up resistor values will depend upon the total bus capacitance and operating speed. The LMP91002 comes with a 7
bit bus fixed address: 1001 000.
LMP91002
30182570
(c) Register read transaction
FIGURE 3. READ and WRITE transaction
t_timeout, the LMP91002’s I2C interface will be reset so that
the SDA line will be released. Since the SDA is an open-drain
with an external resistor pull-up, this also avoids high power
consumption when LMP91002 is driving the bus and the SCL
is stopped.
TIMEOUT FEATURE
The timeout is a safety feature to avoid bus lockup situation.
If SCL is stuck low for a time exceeding t_timeout, the
LMP91002 will automatically reset its I2C interface. Also, in
the case the LMP91002 hangs the SDA for a time exceeding
REGISTERS
The registers are used to configure the LMP91002.
If writing to a reserved bit, user must write only 0. Readback value is unspecified and should be discarded.
Register map
Address
Name
Power on default
Access
Lockable?
0x00
STATUS
0x00
Read only
N
0x01
LOCK
0x01
R/W
N
0x02 through 0x09
RESERVED
0x10
TIACN
0x03
R/W
Y
0x11
REFCN
0x20
R/W
Y
0x12
MODECN
0x00
R/W
N
0x13 through 0xFF
RESERVED
STATUS -- Status Register (address 0x00)
The status bit is an indication of the LMP91002's power-on status. If its readback is “0”, the LMP91002 is not ready to accept other
I2C commands.
Bit
Name
[7:1]
RESERVED
0
STATUS
Function
Status of Device
0 Not Ready (default)
1 Ready
LOCK -- Protection Register (address 0x01)
The lock bit enables and disables the writing of the TIACN and the REFCN registers. In order to change the content of the TIACN
and the REFCN registers the lock bit needs to be set to “0”.
Bit
Name
[7:1]
RESERVED
0
LOCK
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Function
Write protection
0 Registers 0x10, 0x11 in write mode
1 Registers 0x10, 0x11 in read only mode (default)
12
LMP91002
TIACN -- TIA Control Register (address 0x10)
The parameters in the TIA control register allow the configuration of the transimpedance gain (RTIA).
Bit
Name
[7:5]
RESERVED
[4:2]
TIA_GAIN
[1:0]
RESERVED
Function
RESERVED
TIA feedback resistance selection
000 External resistance (default)
001 2.75kΩ
010 3.5kΩ
011 7kΩ
100 14kΩ
101 35kΩ
110 120kΩ
111 350kΩ
RESERVED
REFCN -- Reference Control Register (address 0x11)
The parameters in the Reference control register allow the configuration of the Internal zero, and Reference source. When the
Reference source is external, the reference is provided by a reference voltage connected to the VREF pin. In this condition the
Internal Zero is defined as a percentage of VREF voltage instead of the supply voltage.
Bit
Name
7
REF_SOURCE
[6:5]
INT_Z
[4]
RESERVED
[3:0]
DIAGNOSTIC
Function
Reference voltage source selection
0 Internal (default)
1 external
Internal zero selection (Percentage of the source reference)
00 20%
01 50% (default)
10 67%
RESERVED
Diagnostic step (Percentage of the source reference)
0000 0% (default)
0001 1%
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LMP91002
MODECN -- Mode Control Register (address 0x12)
The Parameters in the Mode register allow the configuration of the Operation Mode of the LMP91002.
Bit
Name
7
FET_SHORT
Shorting FET feature
0 Disabled (default)
1 Enabled
[6:3]
RESERVED
RESERVED
OP_MODE
Mode of Operation selection
000 Deep Sleep (default)
010 Standby
011 3-lead amperometric cell
[2:0]
Function
and provides the internal zero voltage and bias in case of biased gas sensor. The transimpedance amplifier (TIA) is ON,
it converts the current generated by the gas sensor in a voltage, according to the transimpedance gain:
Gain=RTIA
If different gains are required, an external resistor can be
connected between the pins C1 and C2. In this case the internal feedback resistor should be programmed to “external”.
The RLoad together with the output capacitance of the gas
sensor acts as a low pass filter.
GAS SENSOR INTERFACE
The LMP91002 supports both 3-lead and 2-lead gas sensors.
Most of the toxic gas sensors are amperometric cells with 3
leads (Counter, Worker and Reference). These leads should
be connected to the LMP91002 in the potentiostat topology.
3-lead Amperometric Cell In Potentiostat Configuration
Most of the amperometric cell have 3 leads (Counter, Reference and Working electrodes). The interface of the 3-lead gas
sensor to the LMP91002 is straightforward, the leads of the
gas sensor need to be connected to the namesake pins of the
LMP91002.
The LMP91002 is then configured in 3-lead amperometric cell
mode; in this configuration the Control Amplifier (A1) is ON
30182583
FIGURE 4. 3-Lead Amperometric Cell
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14
30182584
FIGURE 5.
SCL) are shared, while the MENB of each LMP91002 is connected to a dedicate GPIO port of the μcontroller.
The μcontroller starts communication asserting one out of N
MENB signals where N is the total number of LMP91002s
connected to the I2C bus. Only the enabled device will acknowledge the I2C commands. After finishing communicating
with this particular LMP91002, the microcontroller de-asserts
the corresponding MENB and repeats the procedure for other
LMP91002s. Figure 6 shows the typical connection when
more than one LMP91002 is connected to the I2C bus.
Application Information
CONNECTION OF MORE THAN ONE LMP91002 TO THE
I2C BUS
The LMP91002 comes out with a unique and fixed I2C slave
address. It is still possible to connect more than one
LMP91002 to an I2C bus and select each device using the
MENB pin. The MENB simply enables/disables the I2C communication of the LMP91002. When the MENB is at logic level
low all the I2C communication is enabled, it is disabled when
MENB is at high logic level.
In a system based on a μcontroller and more than one
LMP91002 connected to the I2C bus, the I2C lines (SDA and
15
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LMP91002
Control Amplifier (A1) is ON and provides the internal zero
voltage. The transimpedance amplifier (TIA) is also ON, it
converts the current generated by the gas sensor in a voltage,
according to the transimpedance gain:
Gain= RTIA
If different gains are required, an external resistor can be
connected between the pins C1 and C2. In this case the internal feedback resistor should be programmed to “external”.
2-lead Galvanic Cell in Potentiostat Configuration
When the LMP91002 is interfaced to a galvanic cell (for instance to an Oxygen gas sensor) referred to a reference, the
Counter and the Reference pin of the LMP91002 are shorted
together and connected to negative electrode of the galvanic
cell. The positive electrode of the galvanic cell is then connected to the Working pin of the LMP91002.
The LMP91002 is then configured in 3-lead amperometric cell
mode (as for amperometric cell). In this configuration the
LMP91002
30182581
FIGURE 6. More than one LMP91002 on I2C bus
LMP91002. A typical smart gas sensor AFE is shown in Figure 7. The connection of MENB to the hardware address pin
A0 of the EEPROM allows the microcontroller to select the
LMP91002 and its corresponding EEPROM when more than
one smart gas sensor AFE is present on the I2C bus. Note:
only EEPROM I2C addresses with A0=0 should be used in
this configuration.
SMART GAS SENSOR ANALOG FRONT END
The LMP91002 together with an external EEPROM represents the core of a SMART GAS SENSOR AFE. In the
EEPROM it is possible to store the information related to the
GAS sensor type, calibration and LMP91002's configuration
(content of registers 10h, 11h, 12h). At startup the microcontroller reads the EEPROM's content and configures the
30182580
FIGURE 7. SMART GAS SENSOR AFE
smart gas sensor AFE enabled will acknowledge the I2C commands. When the communication with this particular module
ends, the microcontroller de-asserts the corresponding
MENB and repeats the procedure for other modules.
Figure 8 shows the typical connection when several smart gas
sensor AFEs are connected to the I2C bus.
SMART GAS SENSOR AFES ON I2C BUS
The connection of Smart gas sensor AFEs on the I2C bus is
the natural extension of the previous concepts. Also in this
case the microcontroller starts communication asserting 1 out
of N MENB signals where N is the total number of smart gas
sensor AFE connected to the I2C bus. Only one of the devices
(either LMP91002 or its corresponding EEPROM) in the
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16
LMP91002
30182582
FIGURE 8. SMART GAS SENSOR AFEs on I2C bus
17
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Power Consumption Scenario
Deep Sleep
StandBy
3-Lead
Amperometric Cell
Current consumption
(µA)
typical value
0.6
6.5
10
Time ON
(%)
0
60
39
Average
(µA)
0
3.9
3.9
A1
OFF
ON
ON
TIA
OFF
OFF
ON
I2C interface
ON
ON
ON
Total
7.8
Notes
This operation will apply a potential (VRW) between RE
and WE pin (VRE>VWE), VRW=1% Source reference
2. Put in the [3:0] bit of the register REFCN (0x11) the 0000b
value, leaving the other bit unchanged.
This operation will remove the potential (VRW) between
RE and WE pin (VRE>VWE), VRW=0V.
The width of the pulse is simply the time between the two
writing operation.
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LMP91000 OUTPUT
TEST PULSE
INPUT PULSE (50mV/DIV)
SENSOR TEST PROCEDURE
The LMP91002 has all the hardware and programmability
features to implement some test procedures. The purpose of
the test procedure is to:
a) test proper function of the sensor (status of health)
b) test proper connection of the sensor to the LMP91002
The test procedure is very easy. The diagnostic block is user
programmable through the digital interface. A step voltage
can be applied by the end user to the positive input of A1. As
a consequence a transient current will start flowing into the
sensor (to charge its internal capacitance) and it will be detected by the TIA. If the current transient is not detected, either
a sensor fault or a connection problem is present. The slope
and the aspect of the transient response can also be used to
detect sensor aging (for example, a cell that is drying and no
longer efficiently conducts the current). After it is verified that
the sensor is working properly, the LMP91002 needs to be
reset to its original configuration. It is not required to observe
the full transient in order to contain the testing time. All the
needed information are included in the transient slopes (both
edges). Figure 9 shows an example of the test procedure, a
Carbon Monoxide sensor is connected to the LMP91002, a
25mVpp pulse is applied between Reference and Working
pin.
The following procedure shows how to implement the sensor
test:
Preliminary conditions:
The LMP91002 is unlocked and it is in 3-Lead Amperometric
Cell Mode
1. Put in the [3:0] bit of the register REFCN (0x11) the 0001b
value, leaving the other bit unchanged.
OUTPUT VOLTTAGE (500mV/DIV)
LMP91002
-Deep Sleep mode is not used
-The system is used about 8 hours a day, and 16 hours a day
it is in Standby mode.
This results in an average power consumption of approximately 7.8 µA. This can potentially be further reduced, by
using the Standby mode between gas measurements. It may
even be possible, depending on the sensor used, to go into
deep sleep for some time between measurements, further
reducing the average power consumption.
POWER CONSUMPTION
The LMP91002 is intended for use in portable devices, so the
power consumption is as low as possible in order to guarantee
a long battery life. The total power consumption for the
LMP91002 is below 10µA @ 3.3v average over time, (this
excludes any current drawn from any pin). A typical usage of
the LMP91002 is in a portable gas detector and its power
consumption is summarized in the Power Consumption Scenario table. This has the following assumptions:
-Power On only happens a few times over life, so its power
consumption can be ignored
TIME (25ms/DIV)
30182561
FIGURE 9. TEST PROCEDURE EXAMPLE
18
LMP91002
Physical Dimensions inches (millimeters) unless otherwise noted
NS Package Number SDA14B
19
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LMP91002 Sensor AFE System: Configurable AFE Potentiostat for Low-Power Chemical Sensing
Applications
Notes
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