IRF IR1150IPBF Upfc one cycle control pfc ic Datasheet

Data Sheet No. PD60230 revD
IR1150(S)(PbF)
IR1150I(S)(PbF)
µPFC ONE CYCLE CONTROL PFC IC
Features
•
•
•
•
•
•
•
•
•
PFC with IR proprietary “One Cycle Control”
Continuous conduction mode (CCM) boost type PFC
No line voltage sense required
Programmable switching frequency (50kHz-200kHz)
Programmable output overvoltage protection
Brownout and output undervoltage protection
Cycle-by-cycle peak current limit
Soft start
User initiated micropower “Sleep Mode”
•
•
•
•
•
•
•
•
•
•
Open loop protection
Maximum duty cycle limit of 98%
User programmable fixed frequency operation
Min. off time of 150-350ns over freq range
VCC under voltage lockout
Internally clamped 13V gate drive
Fast 1.5A peak gate drive
Micropower startup (<200 µA)
Latch immunity and ESD protection
Parts also available Lead-Free
Description
The µPFC IR1150 is a power factor correction (PFC) control IC designed to
operate in continuous conduction mode (CCM) over a wide range input line
voltages. The IR1150 is based on IR's proprietary "One Cycle Control" (OCC)
technique providing a cost effective solution for PFC.
The proprietary control method allows major reductions in component count,
PCB area and design time while delivering the same high system performance
as traditional solutions.
The IC is fully protected and eliminates the often noise sensitive line voltage
sensing requirements of existing solutions.
The IR1150 features include programmable switching frequency,
programmable dedicated over voltage protection, soft start, cycle- by-cycle
peak current limit, brownout, open loop, UVLO and micropower startup current.
In addition, for low standby power requirements (Energy Star, 1W
Standby, Blue Angel, etc.), the IC can be driven into sleep mode with total
current consumption below 200µA, by pulling the OVP pin below 0.62V.
www.irf.com
Packages
8-Lead SOIC
8-Lead PDIP
1
IR1150(S)/IR1150I(S)(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltages are
absolute voltages referenced to COM. Thermal resistance and power dissipation are measured under board mounted and
still air conditions.
Parameters
Symbols
Min.
Max.
Units
VCC
-0.3
22
V
VFREQ.
-0.3
10.5
V
VISNS
VOVP/EN
VFB
VCOMP
-10
-0.3
-0.3
-0.3
3
9
10.5
10
V
V
V
V
VGATE
-0.3
18
V
IGATE
-5
5
mA
IGATEPK
-1.5
1.5
A
Junction temperature
TJ
-40
150
˚C
Storage temperature
TS
-55
150
˚C
—
—
—
—
—
128
84
675
1000
2
˚C/W
˚C/W
mW
mW
kV
VCC voltage
Freq. voltage
ISNS voltage
OVP/EN voltage
VFB voltage
COMP voltage
Gate voltage
Continuous gate current
Max peak gate current
Thermal resistance
Package power dissipation
ESD protection
Rθ JA
PD
VESD
Remarks
Not internally clamped
SOIC-8
PDIP-8
SOIC-8 TAMB = 25 ˚C
PDIP-8 TAMB = 25 ˚C
Human body model*
Recommended Operating Conditions
Recommended operating conditions for reliable operation with margin
Parameters
Symbols
Supply voltage
VCC
15
Min. Typ.
18
Max. Units
20
V
Junction temperature
Ambient temperature
Ambient temperature
TJ
TA
TA
-25
0
-25
—
—
—
125
70
85
°C
°C
°C
Switching frequency
FSW
50
—
200
kHz
Remarks
IR1150(S)
IR1150I(S)
Electrical Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction
temperature range TJ from – 25°C to 125°C. Typical values represent the median values, which are related to 25°C. If
not otherwise stated, a supply voltage of VCC =15V is assumed for test condition
Supply Section
Parameters
Symbols
Min.
VCC turn-on threshold
VCC turn-off threshold
(under voltage lock out)
VCC ON
12.2
12.7
13.2
V
VCC UVLO
10.2
10.7
11.2
V
Typ. Max.
Units
Remarks
*Per EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5KΩ series resistor)
www.irf.com
2
IR1150(S)/IR1150I(S)(PbF)
Electrical Characteristics cont.
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction
temperature range TJ from – 25°C to 125°C. Typical values represent the median values, which are related to 25°C. If not
otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
Parameters
VCC turn-off hysteresis
Operating current
Startup current
Sleep current
Sleep threshold
Symbols
Min.
Typ.
Max.
VCC HYST
1.8
—
2.2
V
—
—
18
36
22
40
mA
mA
—
8
10
mA
ICCSTART
ISLEEP
VSLEEP
—
—
0.56
—
125
0.62
175
200
0.68
uA
uA
V
ICC
Units
Remarks
CLOAD=1nF fSW=200kHZ
CLOAD=10nF fSW=200kHZ
Standby mode - inactive gate
Internal oscillator running
VCC=VCC ON - 0.1V
VOVP<0.5V, VCC =15V
Oscillator Section
Parameters
Symbols
Min.
Switching frequency
fSW
50
—
200
kHz
Initial accuracy
Voltage stability
Temperature stability
Total variation
Long term stability
Maximum duty cycle
Minimum duty cycle
fSW ACC
VSTAB
TSTAB
fVT
FSTABLT
DMAX
DMIN
—
—
—
—
—
93
—
—
0.2
2
10
0.1
—
—
5
3
—
—
0.5
98
0
%
%
%
%
%
%
%
TA = 25˚C
13V <VCC <20V
-25˚C ≤ TJ≤ 125˚C
Line & temperature
TAMB = 125˚C, 1000Hrs
fSW=200kHz
Toffmin
200
300
400
Ns
fSW= 50kHz to 200kHz
Minimum off time
Typ.
Max.
Units
Remarks
RSET = 165kΩ-37kΩ approx.
Protection Section
Parameters
Symbols
Min.
Open loop protection(OLP)
Vfb threshold
VOLP
Output under voltage
protection (OUV)
Output over voltage
protection (OVP)
OVP hysteresis
Peak current limit protection
(IPKLMT) ISNS voltage
threshold
www.irf.com
Typ.
Max.
Units
17
19
21
%VREF
VOUV
49
51
53
%VREF
VOVP
104
105.5
107
%VREF
—
350
450
550
mV
VISNS
-1.11
-1.04
-0.96
V
Remarks
Brown out protection
3
IR1150(S)/IR1150I(S)(PbF)
Internal Voltage Reference Section
Parameters
Min.
Typ.
Reference voltage
Line regulation
Symbols
VREF
RREG
6.9
—
7.0
12
7.1
25
V
mV
Temp stability
Total variation
TSTAB
∆VTOT
—
6.8
0.4
—
—
7.1
%
V
Min.
Typ.
gm
30
40
55
µS
-25˚C ≤TAMB≤ 125˚C
IOVEA
30
20
40
45
65
90
µA
TAMB = 25˚C
-25˚C ≤TAMB≤ 125˚C
tss
—
40
—
ms
RGAIN=1kΩ , CZERO=0.33µF
CPOLE=0.01µF, fXO=28Hz
VCOMP voltage (fault)
VCOMP FLT
—
1.2
1.5
0.2
Effective VCOMP voltage
VCOMP EFF
Max.
Units
Remarks
TA = 25˚C
13.5V <VCC < 20V
-25˚C ≤TAMB≤ 125˚C
Over VCC and Tj ranges
Voltage Error Amplifier Section
Parameters
Symbols
Transconductance
Source/sink current
Soft start delay time
(calculated)
Input bias current
Max.
6.05
Units
V
V
Remarks
@ 1mA (max) initial
@ 25µA steady state
VFB=0V
-25˚C ≤ TAMB≤ 125˚C
IIB
—
-0.2
-0.5
µA
BW
—
1
—
MHz
TCIOV
—
—
10
µV/˚C
Output low voltage
Output high voltage
CMRR
VOL
VOH
—
—
5.71
100
—
6.15
—
0.5
6.8
dB
V
V
VCOMP start voltage
VCOMP START
300
500
700
mV
Min.
Typ.
Max.
Units
gDC
—
2.5
—
V/V
fC
200
—
280
kHz
Note 1
Input offset voltage
VIO
—
1
4
mV
Note 1
ISNS bias current
Input offset voltage temp
coefficient
ΙIB
—
200
300
µA
VFB=0V,-25˚C ≤ TAMB≤ 125˚C
TCIOV
—
—
10
µV/˚C
Common mode rejection ratio
CMRR
Blanking time
TBLANK
—
230
150
100
350
—
450
600
dB
ns
ns
Open loop bandwidth
Input offset voltage temp
coefficient
Common mode rejection ratio
Note 1
Current Amplifier Section
Parameters
DC gain
Corner frequency
www.irf.com
Symbols
Remarks
Note 1
TAMB = 25˚C
-25˚C ≤TAMB≤ 125˚C
4
IR1150(S)/IR1150I(S)(PbF)
Gate Driver Section
Parameters
Symbols
Typ.
Max.
—
1.2
1.5
VGTH
—
13
18
V
VCC=20V
VGTH
9.5
—
—
V
VCC =11.5V
Rise time
tr
—
—
20
70
—
—
ns
ns
CLOAD = 1nF, VCC=16V
CLOAD = 10nF, VCC=16V
Fall time
tf
—
—
20
70
—
—
ns
ns
CLOAD = 1nF, VCC=16V
CLOAD = 10nF, VCC=16V
IOPK
1.5
—
—
A
CLOAD = 10nF, VCC=16V
VG fault
—
—
1.8
V
IGATE=20mA
Gate low voltage
VGLO
Gate high voltage
Gate high voltage
Out peak current
Gate voltage @ fault
Min.
Units
V
Remarks
IGATE=200mA
Note 1: Guaranteed by design, but not tested in production.
www.irf.com
5
IR1150(S)/IR1150I(S)(PbF)
Block Diagram
0.62V
Lead Assignments & Definitions
Lead Assignment
www.irf.com
Pin#
Symbol
Description
1
COM
Ground
2
FREQ
Frequency Set
3
ISNS
Current Sense
4
OVP/EN
Overvoltage Fault Detect / Enable
5
COMP
6
VFB
Output Voltage Sense
7
VCC
IC Supply Voltage
8
GATE
Gate Drive Output
Voltage Loop Compensation
6
IR1150(S)/IR1150I(S)(PbF)
General Description
The µPFC IR1150 is intended for boost converters for
power factor correction operating at a fixed frequency in
continuous conduction mode. The IC operates with two
loops; an inner current loop and an outer voltage loop.
The inner current loop is fast, reliable and does not
require sensing of the input voltage in order to create a
current reference.
This inner current loop sustains the sinusoidal profile of
the average input current based on the dependency of
the pulse width modulator duty cycle on the input line
voltage in order to determine the analogous input line
current. Thus, the current loop uses the embedded
input voltage signal to control the average input current
to follow the input voltage.
The IR1150 enables excellent THD performance. In
light load conditions, a small distortion occurs at zerocrossing due to the finite boost inductance but this is
negligible and well within EN61000-3-2 Class D
specifications.
The outer voltage loop controls the DC bus voltage.
This voltage is fed into the voltage error amplifier to
control the slope of the integrator ramp and sets the
amplitude of the average input current.
The two loops combine to control the amplitude, phase
and shape of the input current, with respect to the input
voltage, giving near-unity power factor.
The IC is designed for robust operation and provides
protection from system level over current, over voltage,
under voltage, and brownout conditions.
www.irf.com
IC Supply
The UVLO circuit monitors the VCC pin and maintains the
gate drive signal inactive until the VCC pin voltage
reaches the UVLO turn on threshold, (VCC ON). As soon as
the VCC voltage exceeds this threshold, provided that the
VFB pin voltage is greater than 20%VREF, the gate drive
will begin switching (under Soft Start) and increase the
pulse width to its maximum value as demanded by the
output voltage error amplifier. If the voltage on the VCC
pin falls below the UVLO turn off threshold, (VCC UVLO), the
IC turns off, gate drive is terminated, and the turn on
threshold must again be exceeded in order to re-start the
process and move into Soft Start mode.
Soft Start
Soft Start controls the rate of rise of the output voltage
error amplifier in order to obtain a linear control of the
increasing duty cycle as a function of time. The Soft Start
time is controlled by voltage error amplifier compensation
components selected, and is user programmable based
on desired loop crossover frequency.
Frequency Select
The switching frequency of the IC is programmable by an
external resistor at the FREQ pin. The design
incorporates min/max restrictions such that the minimum
and maximum operating frequency fall within the range of
50-200kHz.
Gate Drive
The gate drive is a totem pole driver with 1.5A capability.
If higher currents are required, additional external drivers
can be used.
7
IR1150(S)/IR1150I(S)(PbF)
Detailed Pin Description
COM: Ground
ISNS: Current Sense input
This is the ground potential pin of the integrated control
circuit. All internal devices are referenced to this point.
This pin is the inverting Current Sense Input & Peak
Current Limit. The voltage at this pin is the negative
voltage drop, sensed across the system current sense
resistor, representing the inductor current.
This voltage is fed into the Peak Current Limit protection
comparator with threshold around -1V. This protection
circuit incorporates a leading edge blanking circuit
following the comparator to improve noise immunity of the
protection process.
The current sense signal is also fed into the current sense
amplifier. The signal is amplified, filtered of high frequency
noise and then injected into a summing node where it is
subtracted from the compensation voltage VCOMP.
The signal on this pin must be previously filtered with an
RC cell to provide additional noise immunity. The input
impedance of this pin is 5kΩ .
VFB: Output Voltage Feedback
The output voltage of the boost converter is sensed via a
resistive divider and fed into this pin, which is the inverting
input of the output voltage error amplifier. The impedance
of the divider string must be low enough so as to not
introduce substantial error due to the input bias currents of
the amplifier, yet high enough so as to minimize power
dissipation. A typical value of external divider impedance
is 1MΩ.
The error amplifier is a transconductance type which yields
high output impedance, thus increasing the noise immunity
of the error amplifier output. This also eliminates input
divider string interaction with compensation feedback
capacitors and reducing the loading of divider string due to
a low impedance output of the amplifier.
COMP: Voltage Loop Compensation
External circuitry from this pin to ground compensates the
system voltage loop and soft start time. This is the output
of the voltage error amplifier. This pin will be discharged
via internal resistance when a fault mode occurs.
GATE: Gate Drive Output
This is the gate drive output of the IC. Drive voltage is
internally limited and provides ±1.5A peak with matched
rise and fall times.
FREQ: Frequency Set
This is the user programmable frequency pin. An
external resistor from this pin to the COM pin programs the frequency. The operational switching
frequency range for the device is 50kHz – 200kHz.
www.irf.com
VCC: Supply Voltage
This is the supply voltage pin of the IC and it is monitored
by the under voltage lockout circuit. It is possible to turn
off the IC by pulling this pin below the minimum turn off
threshold voltage, without damage to the IC.
To prevent noise problems, a bypass ceramic capacitor
connected to VCC and COM should be placed as close as
possible to the IR1150.
This pin is not internally clamped, therefore damage will
occur if the maximum voltage is exceeded.
OVP/EN: Over Voltage Protection / Enable
This pin is the input to the over voltage protection
comparator the threshold of which is internally
programmed to 105.5% of VREF.
A resistive divider feeds this pin from the output volt-age
to COM and inhibits the gate drive whenever the threshold
is exceeded. Normal operation resumes when the voltage
level on this pin decreases to below the pin threshold.
This pin is also used to activate “sleep” mode by pulling
the voltage level below 0.62V (typ).
8
IR1150(S)/IR1150I(S)(PbF)
Operating States
UVLO Mode
Normal Mode
The IC remains in the UVLO condition until the voltage on
the VCC pin exceeds the VCC turn on threshold voltage,
VCC ON.
During the time the IC remains in the UVLO state, the gate
drive circuit is inactive and the IC draws a
quiescent current of ICC START. The UVLO mode is
accessible from any other state of operation whenever the
IC supply voltage condition of VCC < VCC UVLO occurs.
The IC enters normal operating mode once the soft start
transition has been completed. At this point the gate drive
is switching and the IC draws a maximum of ICC from the
supply voltage source. The device will initiate another soft
start sequence in the event of a shutdown due to a fault,
which activates the protection circuitry, or if the supply
voltage drops below the UVLO turn off threshold of VCC
UVLO.
Standby Mode
The IC is in this state if the supply voltage has exceeded
VCC ON and the VFB pin voltage is less than 20% of VREF .
The oscillator is running and all internal circuitry is biased
in this state but the gate is inactive. This state is
accessible from any other state of operation except OVP.
The IC enters this state whenever the VFB pin voltage has
decreased to 50% of VREF when operating in normal
mode or during a peak current limit fault condition, or 20%
VREF when operating in soft start mode.
Soft Start Mode
This state is activated once the VCC voltage has
exceeded VCCON and the VFB pin voltage has exceeded
20% of VREF.
The soft start time, which is defined as the time required
for the duty cycle to linearly increase from zero to
maximum, is dependent upon the values selected for
compensation of the voltage loop pin COMP to pin COM.
Throughout the soft start cycle, the output of the voltage
error amplifier (pin COMP) charges through the
compensation network. This forces a linear rise of the
voltage at this node which in turn forces a linear increase
in the gate drive duty cycle from 0. This controlled duty
cycle reduces system component stress during start up
conditions as the input current amplitude is increasing
linearly.
www.irf.com
Fault Protection Mode
The fault mode will be activated when any of the protection
circuits are activated. The IC protection circuits include
Supply Voltage Under Voltage Lockout (UVLO), Output
Over Voltage Protection (OVP), Open Loop Protection
(OLP), Output Undervoltage Protection (OUV), and Peak
Current Limit Protection (IPK LIMIT).
Sleep Mode
The sleep mode is initiated by pulling the OVP pin below
0.62V (typ). In this mode the IC draws a very low
quiescent supply current.
9
IR1150(S)/IR1150I(S)(PbF)
VOVP <0.62V
VOVP >0.62V
VOVP <0.62V
VOVP <0.62V
VOVP <0.62V
VOVP <0.62V
VOVP <99%VREF
VOVP <0.62V
www.irf.com
10
IR1150(S)/IR1150I(S)(PbF)
www.irf.com
11
IR1150(S)/IR1150I(S)(PbF)
www.irf.com
12
IR1150(S)/IR1150I(S)(PbF)
www.irf.com
13
IR1150(S)/IR1150I(S)(PbF)
www.irf.com
14
IR1150(S)/IR1150I(S)(PbF)
Tape & Reel Information (SOIC 8-Lead only)
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
2. CONTROLLING DIMENSION : MILLIMETER.
330.00
(12.992) MAX.
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
www.irf.com
14.40 ( .566 )
12.40 ( .488 )
15
IR1150(S)/IR1150I(S)(PbF)
PART MARKING INFORMATION
ORDER INFORMATION
Basic Part
8-Lead SOIC IR1150STR order IR1150STR
Lead-free Part
8-Lead SOIC IR1150S order IR1150STRPbF
8-Lead SOIC IR1150ISTR order IR1150ISTR 8-Lead SOIC IR1150ISTR order IR1150ISTRPbF
8-Lead PDIP IR1150 order IR1150PbF
8-Lead PDIP IR1150I order IR1150IPbF
The IR1150(S)(PbF) has been designed and qualified for the Consumer Market
The IR1150I(S)(PbF) has been designed and qualified for the Industrial Market
Qualification Standards can be found on IR’s Web site.
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105
http://www.irf.com/ Data and specifications subject to change without notice. 2/5/2007
www.irf.com
16
Similar pages