ATMEL AT93C56AY6-10YH-1.8 Three-wire serial eeprom Datasheet

Features
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
User-selectable Internal Organization
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
Three-wire Serial Interface
Sequential Read Operation
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms Max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP
(MLP 2x3), 8-lead TSSOP and 8-ball dBGA2 Packages
Description
Three-wire
Serial
EEPROM
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable programmable read-only memory (EEPROM) organized as 128/256 words of 16 bits each
(when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the
ORG pin is tied to ground). The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operations are essential.
The AT93C56A/66A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball dBGA2
packages.
AT93C56A
AT93C66A
The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a read instruction at DI, the address is decoded and the
data is clocked out serially on the data output pin DO. The write cycle is completely
self-timed and no separate erase cycle is required before write. The write cycle is only
enabled when the part is in the Erase/Write Enable State. When CS is brought “high”
following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of
the part.
The AT93C56A/66A is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
NC
No Connect
8-lead SOIC
8-ball dBGA2
VCC
NC
ORG
GND
8
1
7
2
6
3
5
4
CS
SK
DI
DO
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
Bottom view
8-lead Ultra Thin mini-MAP (MLP 2x3)
VCC
NC
ORG
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
8-lead PDIP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
Bottom view
8-lead TSSOP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
3378K–SEEPR–12/06
1
Absolute Maximum Ratings*
Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground ........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Figure 1. Block Diagram
Note:
2
When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
COUT
CIN
Note:
Max
Units
Conditions
Output Capacitance (DO)
5
pF
VOUT = 0V
Input Capacitance (CS, SK, DI)
5
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V,
VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Test Condition
Min
Typ
Max
Unit
1.8
5.5
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC
Supply Current
VCC = 5.0V
ISB1
Standby Current
VCC = 1.8V
ISB2
Standby Current
ISB3
IIL
READ at 1.0 MHz
0.5
2.0
mA
WRITE at 1.0 MHz
0.5
2.0
mA
CS = 0V
0
0.1
µA
VCC = 2.7V
CS = 0V
6.0
10.0
µA
Standby Current
VCC = 5.0V
CS = 0V
17
30
µA
Input Leakage
VIN = 0V to VCC
0.1
3.0
µA
0.1
3.0
µA
Output Leakage
VIN = 0V to VCC
(1)
VIL1
VIH1(1)
Input Low Voltage
Input High Voltage
2.7V ≤ VCC ≤ 5.5V
−0.6
2.0
0.8
VCC + 1
V
VIL2(1)
VIH2(1)
Input Low Voltage
Input High Voltage
1.8V ≤ VCC ≤ 2.7V
−0.6
VCC x 0.7
VCC x 0.3
VCC + 1
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
2.7V ≤ VCC ≤ 5.5V
0.4
V
VOL2
VOH2
Output Low Voltage
Output High Voltage
1.8V ≤ VCC ≤ 2.7V
IOL
Note:
IOL = 2.1 mA
IOH = −0.4 mA
2.4
IOL = 0.15 mA
IOH = −100 µA
V
0.2
VCC − 0.2
V
V
1. VIL min and VIH max are reference only and are not tested.
3
3378K–SEEPR–12/06
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
fSK
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
0
0
0
tSKH
SK High Time
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
ns
tSKL
SK Low Time
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
ns
tCS
Minimum CS
Low Time
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
ns
tCSS
CS Setup Time
Relative to SK
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
50
200
ns
tDIS
DI Setup Time
Relative to SK
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400
ns
tCSH
CS Hold Time
Relative to SK
0
ns
tDIH
DI Hold Time
Relative to SK
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
100
400
ns
tPD1
Output Delay to “1”
AC Test
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
ns
tPD0
Output Delay to “0”
AC Test
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
ns
tSV
CS to Status Valid
AC Test
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
250
1000
ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
2.7V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 5.5V
150
400
ns
10
ms
tWP
Write Cycle Time
Endurance
Note:
4
(1)
Min
1.8V ≤ VCC ≤ 5.5V
5.0V, 25°C
0.1
1M
Typ
3
Max
Units
2
1
0.25
MHz
Write Cycles
1. This parameter is characterized and is not 100% tested.
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
Table 5. Instruction Set for the AT93C56A and AT93C66A
Address
Data
SB
Op
Code
x8
x 16
READ
1
10
A8 – A0
A7 – A0
EWEN
1
00
11XXXXXXX
11XXXXXX
ERASE
1
11
A8 – A0
A7 – A0
WRITE
1
01
A8 – A0
A7 – A0
ERAL
1
00
10XXXXXXX
10XXXXXX
WRAL
1
00
01XXXXXXX
01XXXXXX
EWDS
1
00
00XXXXXXX
00XXXXXX
Instruction
Note:
x8
x 16
Comments
Reads data stored in memory, at
specified address.
Write enable must precede all
programming modes.
Erases memory location An – A0.
D7 – D0
D15 – D0
Writes memory location An – A0.
Erases all memory locations. Valid
only at VCC = 4.5V to 5.5V.
D7 – D0
D15 – D0
Writes all memory locations. Valid
only at VCC = 5.0V ±10% and Disable
Register cleared.
Disables all programming
instructions.
The X’s in the address field represent don’t care values and must be clocked.
Functional Description
The AT93C56A/66A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host
processor. A valid instruction starts with a rising edge of CS and consists of a Start
Bit (logic “1”) followed by the appropriate Op Code and the desired memory address
location.
READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A
supports sequential read operations. The device will automatically increment the internal address pointer and clock out the next memory location as long as Chip Select (CS)
is held high. In this case, the dummy bit (logic “0”) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains enabled
until an EWDS instruction is executed or VCC power is removed from the part.
ERASE (ERASE): The Erase instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction
and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is
brought high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO
indicates that the selected memory location has been erased, and the part is ready for
another instruction.
5
3378K–SEEPR–12/06
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle tWP starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1”
indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the Ready/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
Timing Diagrams
Figure 2. Synchronous Data Timing
Note:
6
1. This is the minimum SK period.
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
Table 6. Organization Key for Timing Diagrams
AT93C56A (2K)
Notes:
AT93C66A (4K)
I/O
x8
x 16
x8
x 16
AN
A8(1)
A7(2)
A8
A7
DN
D7
D15
D7
D15
1. A8 is a DON’T CARE value, but the extra clock is required.
2. A7 is a DON’T CARE value, but the extra clock is required.
Figure 3. READ Timing
tCS
CS
SK
DI
DO
High Impedance
Figure 4. EWEN Timing
tCS
CS
SK
DI
1
0
0
1
1
...
Figure 5. EWDS Timing
tCS
CS
SK
DI
1
0
0
0
0
...
7
3378K–SEEPR–12/06
Figure 6. WRITE Timing
tCS
CS
SK
DI
DO
1
0
1
AN
...
A0
DN
...
D0
HIGH IMPEDANCE
BUSY
READY
tWP
Figure 7. WRAL Timing(1)
tCS
CS
SK
DI
DO
1
0
0
0
1
...
DN
...
D0
BUSY
HIGH IMPEDANCE
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
Figure 8. ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
1
1
AN AN-1 AN-2
...
A0
tDF
tSV
DO
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
READY
tWP
8
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
Figure 9. ERAL Timing(1)
tCS
CS
CHECK
STATUS
STANDBY
tSV
tDF
SK
DI
DO
1
0
0
1
0
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
3378K–SEEPR–12/06
AT93C56A Ordering Information(1)
Ordering Code
Package
Operation Range
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U3-1
8Y1
8Y6
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Die Sales
Industrial Temperature
(−40°C to 85°C)
(2)
AT93C56A-10PU-2.7
AT93C56A-10PU-1.8(2)
AT93C56A-10SU-2.7(2)
AT93C56A-10SU-1.8(2)
AT93C56AW-10SU-2.7(2)
AT93C56AW-10SU-1.8(2)
AT93C56A-10TU-2.7(2)
AT93C56A-10TU-1.8(2)
AT93C56AU3-10UU-1.8(2)
AT93C56AY1-10YU-1.8(2) (Not recommended for new design)
AT93C56AY6-10YH-1.8(3)
AT93C56A-W1.8-11(4)
Notes:
1.
2.
3.
4.
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
“U” designates Green package + RoHS compliant.
“H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8U3-1
8-ball, die Ball Grid Array Package (dBGA2)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm)
Options
−2.7
Low-voltage (2.7V to 5.5V)
−1.8
Low-voltage (1.8V to 5.5V)
10
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
AT93C66A Ordering Information(1)
Ordering Code
Package
Operation Range
8P3
8P3
8S1
8S1
8S2
8S2
8A2
8A2
8U3-1
8Y1
8Y6
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Die Sale
Industrial Temperature
(−40°C to 85°C)
(2)
AT93C66A-10PU-2.7
AT93C66A-10PU-1.8(2)
AT93C66A-10SU-2.7(2)
AT93C66A-10SU-1.8(2)
AT93C66AW-10SU-2.7(2)
AT93C66AW-10SU-1.8(2)
AT93C66A-10TU-2.7(2)
AT93C66A-10TU-1.8(2)
AT93C66AU3-10UU-1.8(2)
AT93C66AY1-10YU-1.8(2) (Not recommended for new design)
AT93C66AY6-10YH-1.8(3)
AT93C66A-W1.8-11(4)
Notes:
1.
2.
3.
4.
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table.
“U” designates Green package + RoHS compliant.
“H” designates Green package + RoHS compliant, with NiPdAu Lead Finish.
Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please
contact Serial EEPROM Marketing.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8S2
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8U3-1
8-ball, die Ball Grid Array Package (dBGA2)
8Y1
8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP)
8Y6
8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm)
Options
−2.7
Low-voltage (2.7V to 5.5V)
−1.8
Low-voltage (1.8V to 5.5V)
11
3378K–SEEPR–12/06
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
MIN
NOM
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
Notes:
0.210
0.100 BSC
eA
0.300 BSC
0.115
NOTE
2
3
3
e
L
MAX
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
8S1 – JEDEC SOIC
C
1
E
E1
L
N
∅
Top View
End View
e
B
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.00
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
∅
0˚
–
8˚
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03
R
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
8S1
REV.
B
13
3378K–SEEPR–12/06
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
NOM
MAX
NOTE
A
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
∅
0˚
8˚
e
Notes: 1.
2.
3.
4.
5.
MIN
1.27 BSC
2, 3
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
C
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
8Y1 - MAP
PIN 1 INDEX AREA
A
1
3
2
4
PIN 1 INDEX AREA
E1
D1
D
L
8
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
A
Side View
5
e
End View
Top View
6
b
A1
E
7
SYMBOL
MIN
NOM
MAX
A
–
–
0.90
A1
0.00
–
0.05
D
4.70
4.90
5.10
E
2.80
3.00
3.20
D1
0.85
1.00
1.15
E1
0.85
1.00
1.15
b
0.25
0.30
0.35
e
L
NOTE
0.65 TYP
0.50
0.60
0.70
2/28/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package
(MAP) Y1
DRAWING NO.
REV.
8Y1
C
15
3378K–SEEPR–12/06
8Y6 - Mini-MAP (MLP 2x3)
D2
A
b
(8X)
E
E2
Pin 1
Index
Area
Pin 1 ID
L (8X)
D
A2
e (6X)
A1
1.50 REF.
A3
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
2.00 BSC
E
3.00 BSC
MAX
D2
1.40
1.50
1.60
E2
-
-
1.40
A
-
-
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
A3
L
b
NOTE
0.20 REF
0.20
e
Notes:
NOM
D
0.30
0.40
0.50 BSC
0.20
0.25
0.30
2
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05
R
16
2325 Orchard Parkway
San Jose, CA 95131
DRAWING NO.
TITLE
8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map,
8Y6
Dual No Lead Package (DFN) ,(MLP 2x3)
REV.
C
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
3, 5
E
e
D
A2
6.40 BSC
E1
4.30
4.40
4.50
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
4
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
17
3378K–SEEPR–12/06
8U3-1 – dBGA2
E
D
1.
b
A1
PIN 1 BALL PAD CORNER
A2
Top View
A
Side View
PIN 1 BALL PAD CORNER
1
2
3
4
8
7
6
5
(d1)
d
e
COMMON DIMENSIONS
(Unit of Measure = mm)
(e1)
MIN
NOM
MAX
A
0.713
0.79
0.85
A1
0.09
0.14
0.19
SYMBOL
Bottom View
8 Solder Balls
1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder ball diameter
A2
0.40
0.45
0.50
b
0.20
0.25
0.30
D
1.50 BSC
E
2.00 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
NOTE
2
5/3/05
R
18
TITLE
1150E Cheyenne Mt. Blvd
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Colorado Springs, CO 80906
Small Die Ball Grid Array Package (dBGA2)
DRAWING NO.
REV.
PO8U3-1
b
AT93C56A/66A
3378K–SEEPR–12/06
AT93C56A/66A
Revision History
Revision No.
Date
Comments
3378K
12/06
Removed DC/Don’t Connect and replaced with NC/No Conenct
Adjusted size of Block diagram on pg. 2
Made all diagrams on pages 6-9 consistently the same size
Corrected 8U3-1
19
3378K–SEEPR–12/06
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