LINER LTC6403CUD-1-TRPBF 200mhz, low noise, low power fully differential input/output amplifi er/driver Datasheet

LTC6403-1
200MHz, Low Noise,
Low Power Fully Differential
Input/Output Amplifier/Driver
FEATURES
DESCRIPTION
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The LTC®6403-1 is a precision, very low noise, low distortion, fully differential input/output amplifier optimized
for 3V to 5V, single supply operation. The LTC6403-1 is
unity gain stable. The LTC6403-1 closed-loop bandwidth
extends from DC to 200MHz. In addition to the normal
unfiltered outputs (+OUT and –OUT), the LTC6403-1 has a
built-in 44.2MHz differential single-pole low pass filter and
an additional pair of filtered outputs (+OUTF, and –OUTF).
An input referred voltage noise of 2.8nV/√⎯H⎯z enables the
LTC6403-1 to drive state-of-the-art 14- to 18-bit ADCs
while operating on the same supply voltage, saving system
cost and power. The LTC6403-1 maintains its performance
for supplies as low as 2.7V. It draws only 10.8mA, and
has a hardware shutdown feature which reduces current
consumption to 170μA.
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■
■
■
■
■
■
■
■
■
■
■
Very Low Distortion: (2VP-P, 3MHz): –95dBc
Fully Differential Input and Output
Low Noise: 2.8nV/√Hz Input-Referred
200MHz Gain-Bandwidth Product
Slew Rate: 200V/μs
Adjustable Output Common Mode Voltage
Rail-to-Rail Output Swing
Input Range Extends to Ground
Large Output Current: 60mA (Typ)
DC Voltage Offset <1.5mV (Max)
10.8mA Supply Current
2.7V to 5.25V Supply Voltage Range
Low Power Shutdown
Tiny 3mm × 3mm × 0.75mm 16-Pin QFN Package
APPLICATIONS
■
■
■
■
Differential Input A/D Converter Driver
Single-Ended to Differential Conversion/Amplification
Common Mode Level Translation
Low Voltage, Low Noise, Signal Processing
The LTC6403-1 is available in a compact 3mm × 3mm
16-pin leadless QFN package and operates over a –40°C
to 85°C temperature range.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Single-Ended Input to Differential Output
with Common Mode Level Shifting
Harmonic Distortion vs Frequency
–30
2VP-P
50Ω
392Ω
402Ω
3V 0.1μF
54.9Ω
SIGNAL
GENERATOR
1VP-P
VOCM
0.01μF
+
1.5V
–
1.5V
64031 TA01
402Ω
–70
SECOND
–80
THIRD
–90
–100
LTC6403-1
1VP-P
422Ω
DISTORTION (dBc)
0V
VS
SINGLE-ENDED INPUT
–40 VS = 3V
VOCM = VICM = 1.5V
–50 RF = RI = 402Ω
RLOAD = 800Ω
–60 VOUTDIFF = 2VP-P
–110
–120
1
10
FREQUENCY (MHz)
100
64031 TA01b
64031f
1
LTC6403-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
–OUTF
–OUT
NC
+IN
TOP VIEW
Total Supply Voltage (V+ to V–) ................................5.5V
Input Voltage
(+IN, –IN, VOCM, ⎯S⎯H⎯D⎯N) (Note 2)................... V+ to V–
Input Current
(+IN, –IN, VOCM, ⎯S⎯H⎯D⎯N) (Note 2).....................±10mA
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range
(Note 4) ............................................... –40°C to 85°C
Specified Temperature Range
(Note 5) ............................................... –40°C to 85°C
Junction Temperature ........................................... 150°C
Storage Temperature Range................... –65°C to 150°C
16 15 14 13
3
VOCM
4
11 V+
17
10 V+
9
5
6
7
8
+OUTF
2
V–
12 V–
+OUT
V+
NC
1
–IN
SHDN
V–
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 150°C, θJA = 160°C/W, θJC = 4.2°C/W
EXPOSED PAD (PIN 17) IS V–, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTC6403CUD-1#PBF
LTC6403IUD-1#PBF
LTC6403CUD-1#TRPBF LDBM
LTC6403IUD-1#TRPBF LDBM
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
16-Lead (3mm × 3mm) Plastic QFN
16-Lead (3mm × 3mm) Plastic QFN
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
LTC6403-1 DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = MidSupply, V⎯S⎯H⎯D⎯N = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as
(V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is
defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
VOSDIFF
Differential Offset Voltage (Input Referred)
VS = 2.7V
VS = 3V
VS = 5V
ΔVOSDIFF/ΔT Differential Offset Voltage Drift (Input Referred)
VS = 2.7V
VS = 3V
VS = 5V
MIN
●
●
●
TYP
MAX
UNITS
±0.4
±0.4
±0.4
±1.5
±1.5
±2
mV
mV
mV
1
1
1
μV/°C
μV/°C
μV/°C
64031f
2
LTC6403-1
LTC6403-1 DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = MidSupply, V⎯S⎯H⎯D⎯N = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as
(V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is
defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
IB
Input Bias Current (Note 6)
VS = 2.7V
VS = 3V
VS = 5V
●
●
●
IOS
Input Offset Current (Note 6)
VS = 2.7V
VS = 3V
VS = 5V
●
●
●
RIN
Input Resistance
Common Mode
Differential Mode
1.7
14
MΩ
kΩ
CIN
Input Capacitance
Differential Mode
1
pF
en
Differential Input Referred Noise Voltage Density
f = 1MHz
2.8
nV/√⎯H⎯z
in
Input Noise Current Density
f = 1MHz
1.8
pA/√⎯H⎯z
enVOCM
Input Referred Common Mode Output Noise
Voltage Density
Input Signal Common Mode Range (Note 7)
f = 1MHz, VOCM Shorted to Ground,
V+ = 1.5V, V– = –1.5V
VS = 3V
VS = 5V
VS = 3V, ΔVICM = 0.75V
VS = 5V, ΔVICM = 1.25V
VS = 5V, ΔVOCM = 2V
17
nV/√⎯H⎯z
VICMR
CMRRI
●
●
MIN
TYP
MAX
–25
–25
–25
–7.5
–7.5
–7.5
0
0
0
μA
μA
μA
±0.2
±0.2
±0.2
±5
±5
±5
μA
μA
μA
●
0
0
50
50
50
72
72
90
V
V
dB
dB
dB
●
●
1.6
3.6
UNITS
VS = 2.7V to 5.25V
●
60
97
dB
VS = 2.7V to 5.25V
●
45
63
dB
GCM
Input Common Mode Rejection Ratio
(Input Referred) ΔVICM/ΔVOSDIFF (Note 8)
Output Common Mode Rejection Ratio (Input
Referred) ΔVOCM/ΔVOSDIFF (Note 8)
Differential Power Supply Rejection
(ΔVS/ΔVOSDIFF) (Note 9)
Output Common Mode Power Supply Rejection
(ΔVS/ΔVOSCM) (Note 9)
Common Mode Gain (ΔVOUTCM/ΔVOCM)
VS = 5V, ΔVOCM = 2V
●
ΔGCM
Common Mode Gain Error (100 • (GCM – 1))
VS = 5V, ΔVOCM = 2V
●
–0.4
–0.1
0.3
%
BAL
Output Balance (ΔVOUTCM/ΔVOUTDIFF)
ΔVOUTDIFF = 2V
Single-Ended Input
Differential Input
VS = 2.7V
VS = 3V
VS = 5V
VS = 2.7V
VS = 3V
VS = 5V
VS = 3V
VS = 5V
–63
–66
±10
±10
±10
20
20
20
–45
–45
±25
±25
±25
dB
dB
mV
mV
mV
μV/°C
μV/°C
μV/°C
V
V
kΩ
CMRRIO
PSRR
PSRRCM
VOSCM
Common Mode Offset Voltage (VOUTCM – VOCM)
ΔVOSCM/ΔT
Common Mode Offset Voltage Drift
VOUTCMR
Output Signal Common Mode Range
(Voltage Range for the VOCM Pin) (Note 7)
Input Resistance, VOCM Pin
RINVOCM
1
●
●
●
●
●
●
●
●
1.1
1.1
15
1.45
VOCM
Voltage at the VOCM Pin (Self-Biased)
VS = 3V, VOCM = Open
●
VOUT
Output Voltage, High, Either Output Pin (Note 10)
VS = 3V, IL = 0
VS = 3V, IL = 5mA
VS = 3V, IL = 20mA
VS = 5V, IL = 0
VS = 5V, IL = 5mA
VS = 5V, IL = 20mA
●
●
●
●
●
●
V/V
23
2
4
32
1.5
1.55
V
190
190
340
170
195
380
300
300
490
300
340
550
mV
mV
mV
mV
mV
mV
64031f
3
LTC6403-1
LTC6403-1 DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = MidSupply, V⎯S⎯H⎯D⎯N = OPEN, RI = 402Ω, RF = 402Ω, RL = OPEN, RBAL = 100k (See Figure 1) unless otherwise noted. VS is defined as
(V+ – V–). VOUTCM is defined as (V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is
defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
VOUT
Output Voltage, Low, Either Output Pin (Note 10)
VS = 3V, IL = 0
VS = 3V, IL = –5mA
VS = 3V, IL = –20mA
VS = 5V, IL = 0
VS = 5V, IL = –5mA
VS = 5V, IL = –20mA
VS = 2.7V
VS = 3V
VS = 5V
MIN
TYP
MAX
UNITS
220
245
300
265
275
350
±30
±30
±35
150
165
210
165
175
225
±58
±60
±74
mV
mV
mV
mV
mV
mV
mA
mA
mA
●
●
●
●
●
●
●
●
●
ISC
Output Short-Circuit Current, Either Output Pin
(Note 11)
AVOL
Large-Signal Voltage Gain
VS
Supply Voltage Range
IS
Supply Current
VS = 2.7V
VS = 3V
VS = 5V
●
●
●
I⎯S⎯H⎯D⎯N
Supply Current in Shutdown
VS = 2.7V
VS = 3V
VS = 5V
●
●
●
VIL
⎯S⎯H⎯D⎯N Input Logic Low
VS = 2.7V to 5V
●
VIH
⎯S⎯H⎯D⎯N Input Logic High
R⎯S⎯H⎯D⎯N
⎯S⎯H⎯D⎯N Pull-Up Resistor
VS = 5V, V⎯S⎯H⎯D⎯N = 2.9V to 0V
tON
Turn-On Time
VS = 3V, V⎯S⎯H⎯D⎯N = 0.5V to 3V
4
μs
tOFF
Turn-Off Time
VS = 3V, V⎯S⎯H⎯D⎯N = 3V to 0.5V
350
ns
VS = 3V
90
●
VS = 2.7V to 5V
●
2.7
dB
5.25
V
10.7
10.8
11
11.8
11.8
12.1
mA
mA
mA
0.16
0.17
0.26
0.5
0.5
1
mA
mA
mA
V+ – 2.1
V+ – 0.6
40
V
V
66
90
kΩ
LTC6403-1 AC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
VS⎯ H⎯ D⎯ N⎯ = OPEN, RI = 402Ω, RF = 402Ω, RT = 25.5Ω, unless otherwise noted (See Figure 2). VS is defined (V+ – V–). VOUTCM is defined as
(V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
SR
Slew Rate
GBW
Gain-Bandwidth Product
f3dB
–3dB Frequency (See Figure 2)
VS = 3V
VS = 5V
VS = 3V
VS = 5V
VS = 3V
VS = 5V
VS = 3V, VOUTDIFF = 2VP-P
Single-Ended Input
2nd Harmonic
3rd Harmonic
VS = 3V, VOUTDIFF = 2VP-P
Differential Input
2nd Harmonic
3rd Harmonic
3MHz Distortion
HD2
HD3
3MHz Distortion
HD2
HD3
●
●
MIN
TYP
100
100
200
200
200
200
200
200
MAX
UNITS
V/μS
V/μS
MHz
MHz
MHz
MHz
–97
–95
dBc
dBc
–106
–94
dBc
dBc
64031f
4
LTC6403-1
LTC6403-1 AC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply
over the full operating temperature range, otherwise specifications are at TA = 25°C, V+ = 3V, V– = 0V, VCM = VOCM = VICM = Mid-Supply,
VS⎯ H⎯ D⎯ N⎯ = OPEN, RI = 402Ω, RF = 402Ω, RT = 25.5Ω, unless otherwise noted (See Figure 2). VS is defined (V+ – V–). VOUTCM is defined as
(V+OUT + V–OUT)/2. VICM is defined as (V+IN + V–IN)/2. VOUTDIFF is defined as (V+OUT – V–OUT). VINDIFF is defined as (VINP – VINM).
SYMBOL
PARAMETER
CONDITIONS
IMD
Third-Order IMD at 10MHz
f1 = 9.5MHz, f2 = 10.5MHz
Equivalent OIP3 at 3MHz (Note 12)
VS = 3V, VOUTDIFF = 2VP-P Envelope
–72
dBc
VS = 3V
48
dBm
Settling Time
2V Step at Output
VS = 3V, Single-Ended Input
1% Settling
0.1% Settling
Noise Figure, f = 3MHz
RSOURCE = 804Ω, RI = 402Ω,
RF = 402Ω, VS = 3V
RSOURCE = 200Ω, RI = 100Ω,
RF = 402Ω, VS = 3V
OIP3
tS
NF
f3dBFILTER
Differential Filter 3dB Bandwidth
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs +IN, –IN are protected by a pair of back-to-back diodes.
If the differential input voltage exceeds 1.4V, the input current should be
limited to less than 10mA. Input pins (+IN, –IN, VOCM, and ⎯S⎯H⎯D⎯N) are also
protected by steering diodes to either supply. If the inputs should exceed
either supply voltage, the input current should be limited to less than
10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefinitely. Long term application of output currents in excess of the
absolute maximum ratings may impair the life of the device.
Note 4: The LTC6403-1 is guaranteed functional over the operating
temperature range –40°C to 85°C.
Note 5: The LTC6403C-1 is guaranteed to meet specified performance
from 0°C to 70°C. The LTC6403C-1 is designed, characterized, and
expected to meet specified performance from –40°C to 85°C but is
not tested or QA sampled at these temperatures. The LTC6403I-1 is
guaranteed to meet specified performance from –40°C to 85°C.
Note 6: Input bias current is defined as the average of the input currents
flowing into Pin 6 and Pin 15 (–IN, and +IN). Input offset current is defined
as the difference of the input currents flowing into Pin 15 and Pin 6 (IOS =
IB+ – IB–)
Note 7: Input common mode range is tested using the test circuit of
Figure 1 by measuring the differential gain with a ±1V differential output
with VICM = mid-supply, and also with VICM at the input common mode
range limits listed in the Electrical Characteristics table, verifying that the
differential gain has not deviated from the mid supply common mode input
case by more than 1%, and the common mode offset (VOSCM) has not
deviated from the mid-supply case by more than ±10mV.
MIN
TYP
MAX
UNITS
20
30
10.8
ns
ns
dB
8.9
dB
44.2
MHz
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the VOCM pin and testing at
both mid supply and at the Electrical Characteristics table limits to verify
that the differential gain has not deviated from the mid supply VOCM case
by more than 1%, and the common mode offset (VOSCM) has not deviated
by more than ±10mV from the mid supply case.
Note 8: Input CMRR is defined as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defined as the ratio of the
change in the voltage at the VOCM pin to the change in differential input
referred voltage offset. These specifications are strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs, and it is difficult to measure actual amplifier performance. (See
“The Effects of Resistor Pair Mismatch” in the General Applications
Section of this datasheet.) For a better indicator of actual amplifier
performance independent of feedback component matching, refer to the
PSRR specification.
Note 9: Differential power supply rejection (PSRR) is defined as the ratio
of the change in supply voltage to the change in differential input referred
voltage offset. Common mode power supply rejection (PSRRCM) is
defined as the ratio of the change in supply voltage to the change in the
common mode offset, VOUTCM – VOCM.
Note 10: Output swings are measured as differences between the output
and the respective power supply rail.
Note 11: Extended operation with the output shorted may cause junction
temperatures to exceed the 150°C limit and is not recommended. See Note
3 for more details.
Note 12: A resistive load is not required when driving an AD converter with
the LTC6403-1. Therefore, typical output power is very small. In order to
compare the LTC6403-1 with amplifiers that require 50Ω output load, the
LTC6403-1 output voltage swing driving a given RL is converted to OIP3
as if it were driving a 50Ω load. Using this modified convention, 2VP-P is
by definition equal to 10dBm, regardless of actual RL.
64031f
5
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Common Mode Offset Voltage
vs Temperature
8
0.6
0.4
0.2
0
–0.2
VS = 3V
VOCM = 1.5V
VICM = 1.5V
RI = RF = 402Ω
FIVE TYPICAL UNITS
–0.4
–0.6
–0.8
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
COMMON MODE OFFSET VOLTAGE (mV)
DIFFERENTIAL OFFSET VOLTAGE (mV)
0.8
VS = 3V
VOCM = 1.5V
VICM = 1.5V
FIVE TYPICAL UNITS
6
4
2
0
–2
–4
–6
–8
20 40 60
–60 –40 –20 0
TEMPERATURE (°C)
100
80
6
4
2
VS = 3V
0
0.5
1.0
1.5
2.0
SHDN VOLTAGE (V)
2.5
6
4
TA = –40°C
TA = 25°C
TA = 85°C
2
0
1
2
3
4
SUPPLY VOLTAGE (V)
Frequency Response
vs Load Capacitance
5
VSHDN = V–
0
300
CL = 0pF
CL = 3.9pF
CL = 10pF
–5
250
–10
200
150
–15
–20
VS = 3V
VOCM = VICM = 1.5V
RLOAD = 800Ω
RI = RF = 402Ω
CAPACITOR VALUES ARE FROM
EACH OUTPUT TO GROUND.
NO SERIES RESISTORS ARE USED.
–25
100
TA = –40°C
TA = 25°C
TA = 85°C
50
0
3.0
5
64031 G03
GAIN (dB)
SHUTDOWN SUPPLY CURRENT (μA)
TOTAL SUPPLY CURRENT (mA)
350
TA = –40°C
TA = 25°C
TA = 85°C
8
0
8
Shutdown Supply Current
vs Supply Voltage
Supply Current vs ⎯S⎯H⎯D⎯N Voltage
10
10
0
100
80
VSHDN = OPEN
64031 G02
64031 G01
12
Supply Current vs Supply Voltage
12
TOTAL SUPPLY CURRENT (mA)
Differential Offset Voltage
vs Temperature
1
0
2
3
5
4
–30
–35
–40
1
SUPPLY VOLTAGE (V)
64031 G04
10
100
FREQUENCY (MHz)
1000
64031 G06
64031 G05
Frequency Response vs Gain
50
40
30
AV = 100
AV = 10
AV = 20
AV = 5
RI(Ω)
RF(Ω)
1
402
402
806
2
402
10
5
402
2k
0
10
402
4.02k
20
402
8.06k
100
402
40.2k
20
GAIN (dB)
AV (V/V)
AV = 2
–10
AV = 1
–20
–30
–40
VS = 3V
VOCM = VICM = 1.5V
RLOAD = 800Ω
–50
0.1
1
10
100
FREQUENCY (MHz)
1000
64031 G08
64031f
6
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Harmonic Distortion
vs Output Amplitude
Harmonic Distortion vs Frequency
–40
–80
HD3
–90
HD2
–30
DIFFERENTIAL INPUTS
VS = 3V
–70 VOCM = VICM = 1.5V
RF = RI = 402Ω
RLOAD = 800Ω
–80 fIN = 3MHz
THIRD
–90
–100
–100
SECOND
SINGLE-ENDED INPUT
–40 VS = 3V
VOCM = VICM = 1.5V
–50 RF = RI = 402Ω
RLOAD = 800Ω
–60 VOUTDIFF = 2VP-P
–70
SECOND
–80
THIRD
–90
–100
–110
–110
–110
–120
–120
10
FREQUENCY (MHz)
100
1
2
3
4
100
–80
–90
–100
–110
INPUT VOLTAGE NOISE DENSITY (nV/√Hz)
SECOND
2
3
VOUTDIFF (VP-P)
4
in
10
10
en
1
100
–120
5
100
VS = 3V
VICM = 1.5V
1k
10k
100k
FREQUENCY (Hz)
1M
1000
INPUT CURRENT NOISE DENSITY (pA/√Hz)
THIRD
–70
1
Differential Output Impedance
vs Frequency
Input Noise Density vs Frequency
–30
VS = 3V
RI = RF = 402Ω
100
10
1
0.1
0.01
0.1
1
10M
1
10
100
FREQUENCY (MHz)
Differential Slew Rate
vs Temperature
CMRR vs Frequency
70
220
60
210
1000
64031 G18
64031 G17
64031 G14
100
64031 G12
64031 G11
Harmonic Distortion
vs Output Amplitude
0
10
FREQUENCY (MHz)
1
VOUTDIFF (VP-P)
64031 G09
SINGLE-ENDED INPUT
–40 VS = 3V
VOCM = VICM = 1.5V
–50 RF = RI = 402Ω
RLOAD = 800Ω
–60 fIN = 10MHz
–120
5
OUTPUT IMPEDANCE (Ω)
1
DISTORTION (dBc)
DISTORTION (dBc)
DISTORTION (dBc)
DISTORTION (dBc)
Harmonic Distortion vs Frequency
–60
DIFFERENTIAL INPUTS
VS = 3V
–50
VOCM = VICM = 1.5V
RF = RI = 402Ω
–60
RLOAD = 800Ω
= 2VP-P
V
–70 OUTDIFF
Small Signal Step Response
50
40
30 VS = 3V
VOCM = 1.5V
RI = RF = 402Ω
0.05% FEEDBACK NETWORK RESISTORS
20
1
0.1
10
100
1000
FREQUENCY (MHz)
64031 G19
200
20mV/DIV
VS = 5V
SLEW RATE (V/μs)
CMRR (dB)
+OUT
VS = 3V
190
VS = 3V
VOCM = VICM
= 1.5V
RLOAD = 800Ω
RI = RF = 402Ω
CL = 0pF
VIN = 180mVP-P,
DIFFERENTIAL
180
–OUT
170
20
–60 –40 –20 0
40 60
TEMPERATURE (°C)
80 100
5ns/DIV
64031 G21
64031 G22
64031f
7
LTC6403-1
TYPICAL PERFORMANCE CHARACTERISTICS
Large Signal Step Response
Overdrive Transient Response
3.0
VS = 3V, RLOAD = 800Ω
VIN = 2VP-P DIFFERENTIAL
–OUT
2.5
0.2V/DIV
VOLTAGE (V)
–OUT
2.0
1.5
VS = 3V
VOCM = 1.5V
1.0
0.5
+OUT
+OUT
0
50ns/DIV
20ns/DIV
64031 G23
64031 G24
PIN FUNCTIONS
⎯ ⎯H⎯D⎯N (Pin 1): When ⎯S⎯H⎯D⎯N is floating or directly tied to V+,
S
the LTC6403-1 is in the normal (active) operating mode.
When Pin 1 is pulled a minimum of 2.1V below V+, the
LTC6403-1 enters into a low power shutdown state. See
Applications Information for more details.
V+, V– (Pins 2, 10, 11 and Pins 3, 9, 12): Power Supply
Pins. Three pairs of power supply pins are provided to keep
the power supply inductance as low as possible to prevent
any degradation of amplifier 2nd harmonic performance. It
is critical that close attention be paid to supply bypassing.
For single supply applications (Pins 3, 9 and 12 grounded)
it is recommended that high quality 0.1μF surface mount
ceramic bypass capacitors be placed between Pins 2 and
3, between Pins 11 and 12, and between Pins 10 and 9
with direct short connections. Pins 3, 9 and 10 should be
tied directly to a low impedance ground plane with minimal
routing. For dual (split) power supplies, it is recommended
that at least two additional high quality, 0.1μF ceramic
capacitors are used to bypass pin V+ to ground and V– to
ground, again with minimal routing. For driving large loads
(<200Ω), additional bypass capacitance may be needed for
optimal performance. Keep in mind that small geometry
(e.g. 0603) surface mount ceramic capacitors have a much
higher self resonant frequency than do leaded capacitors,
and perform best in high speed applications.
64031f
8
LTC6403-1
PIN FUNCTIONS
VOCM (Pin 4): Output Common Mode Reference Voltage.
The voltage on VOCM sets the output common mode voltage
level (which is defined as the average of the voltages on
the +OUT and –OUT pins). The VOCM pin is the midpoint
of an internal resistive voltage divider between V+ and
V– that develops a (default) mid-supply voltage potential
to maximize output signal swing. The VOCM pin can be
overdriven by an external voltage reference capable of
driving the input impedance presented by the VOCM pin.
On the LTC6403-1, the VOCM pin has an input resistance
of approximately 23k to a mid-supply potential. The VOCM
pin should be bypassed with a high quality ceramic bypass
capacitor of at least 0.01μF, (unless you are using split
supplies, then connect directly to a low impedance, low
noise ground plane) to minimize common mode noise
from being converted to differential noise by impedance
mismatches both external and internal to the IC.
+OUT, –OUT (Pins 7, 14): Unfiltered Output Pins. Each
amplifier output is designed to drive a load capacitance of
10pF. This means the amplifier can drive 10pF from each
output to ground or 5pF differentially. Larger capacitive
loads should be decoupled with at least 25Ω resistors
from each output.
+OUTF, –OUTF (Pins 8, 13): Filtered Output Pins. These
pins have a series 100Ω resistor connected between the
filtered and unfiltered outputs and three 12pF capacitors.
Both +OUTF, and –OUTF have 12pF to V–, plus an additional 12pF differentially between +OUTF and –OUTF.
This filter creates a differential low pass pole with a –3dB
bandwidth of 44.2MHz.
+IN, –IN (Pins 15, 6): Non-Inverting and Inverting Input
pins of the amplifier, respectively. For best performance,
it is highly recommended that stray capacitance be kept
to an absolute minimum by keeping printed circuit connections as short as possible and stripping back nearby
surrounding ground plane away from these pins.
NC (Pins 5, 16): No Connection. These pins are not connected internally.
Exposed Pad (Pin 17): Tie the pad to V– (Pins 3, 9, and 12).
If split supplies are used, do not tie the pad to ground.
BLOCK DIAGRAM
16
NC
15
+IN
14
–OUT
13
–OUTF
V+
V–
V–
V+
1
V+
12pF
V+
100Ω
V+
V+
2
V+
66k
SHDN
V–
46k
V–
V+
12pF
VOCM
46k
V+
100Ω
–
12pF
V–
4
V+
10
V– V–
9
V–
V–
V–
V+
V–
5
V–
12
V– V+
11
+
VOCM
V–
3
V–
V+
NC
6
–IN
V+
V+
7
+OUT
8
+OUTF
64031 BD
64031f
9
LTC6403-1
APPLICATIONS INFORMATION
RI
RF
V+IN
IL
V–OUT
+
V–OUTF
VINP
–
16
NC
+IN
15
14
–OUT
13
–OUTF
LTC6403-1
SHDN
V–
12
SHDN
VSHDN
1
V– V+
11
V+
V+
2
0.1μF
VCM
V+
V–
+
V+
VOCM
V–
V–
VOCM
VOCM
VOUTCM
0.1μF
0.1μF
VINM
NC
RI
+
–IN
6
7
RF
V–IN
+OUT
V+OUT
8
RBAL
V–
9
5
0.1μF
V+
V–
4
0.01μF
–
0.1μF
V+
10
–
V–
3
RBAL
V–
0.1μF
+OUTF
64031 F01
IL
V+OUTF
Figure 1. DC Test Circuit
APPLICATIONS INFORMATION
0.1μF
RI
VINP
V+IN
RF
340Ω
V–OUT
0.1μF
V–OUTF
RT
16
NC
15
+IN
14
–OUT
13
140Ω
–OUTF
LTC6403-1
SHDN
V–
12
SHDN
50Ω
•
•
V– V+
11
V+
VIN
–
V+
2
0.1μF
V–
V+
+
V+
VOCM
V–
V–
VOCM
VOCM
4
5
VINM
RI
NC
6
V–IN
–IN
RF
7
+OUT
V+OUT
8
50Ω
0.1μF
V–
0.1μF
V–
0.1μF
+OUTF
V+OUTF
0.1μF
MINI-CIRCUITS
TCM4-19
V+
9
0.01μF
0.1μF
0.1μF
V+
10
–
V–
3
V–
•
M/A-COM
ETC1-1-13
1
•
+
VSHDN
64031 F02
340Ω
RT
0.1μF
140Ω
Figure 2. AC Test Circuit (–3dB BW testing)
64031f
10
LTC6403-1
APPLICATIONS INFORMATION
Functional Description
The LTC6403-1 is a small outline, wide band, low noise,
and low distortion fully-differential amplifier with accurate
output phase balancing. The LTC6403-1 is optimized to
drive low voltage, single-supply, differential input analogto-digital converters (ADCs). The LTC6403-1’s output is
capable of swinging rail-to-rail on supplies as low as 2.7V,
which makes the amplifier ideal for converting ground
referenced, single-ended signals into VOCM referenced
differential signals in preparation for driving low voltage,
single-supply, differential input ADCs. Unlike traditional
op amps which have a single output, the LTC6403-1 has
two outputs to process signals differentially. This allows
for two times the signal swing in low voltage systems
when compared to single-ended output amplifiers. The
balanced differential nature of the amplifier also provides
even-order harmonic distortion cancellation, and less
susceptibility to common mode noise (like power supply
noise). The LTC6403-1 can be used as a single ended input
to differential output amplifier, or as a differential input to
differential output amplifier.
The LTC6403-1’s output common mode voltage, defined
as the average of the two output voltages, is independent
of the input common mode voltage, and is adjusted by
applying a voltage on the VOCM pin. If the pin is left open,
an internal resistive voltage divider develops a potential
halfway between the V+ and V– pin voltages. Whenever
VOCM is not hard tied to a low impedance ground plane, it
is recommended that a high quality ceramic capacitor is
used to bypass the VOCM pin to a low impedance ground
plane (See Layout Considerations in this document). The
LTC6403-1’s internal common mode feedback path forces
accurate output phase balancing to reduce even order
harmonics, and centers each individual output about the
potential set by the VOCM pin.
VOUTCM = VOCM =
V+OUT + V–OUT
2
The outputs (+OUT and –OUT) of the LTC6403-1 are
capable of swinging rail-to-rail. They can source or sink
up to approximately 60mA of current.
Additional outputs (+OUTF and –OUTF) are available that
provide filtered versions of the +OUT and –OUT outputs. An
on-chip single pole RC passive filter bandlimits the filtered
outputs to a –3dB frequency of 44.2MHz. The user has a
choice of using the unfiltered outputs, the filtered outputs,
or modifying the filtered outputs to adjust the frequency
response by adding additional components (see Output
Filter Considerations and Use section).
In applications where the full bandwidth of the LTC6403-1
is desired, the unfiltered outputs (+OUT and –OUT) should
be used. The unfiltered outputs +OUT and –OUT are
designed to drive 10pF to ground (or 5pF differentially).
Capacitances greater than 10pF will produce excess
peaking, which can be mitigated by placing at least 25Ω
in series with the output.
Input Pin Protection
The LTC6403-1’s input stage is protected against differential input voltages that exceed 1.4V by two pairs of back
to back diodes connected in anti-parallel series between
+IN and –IN (Pins 6 and 15). In addition, the input pins
have steering diodes to either power supply. If the input
pair is over-driven, the current should be limited to under
10mA to prevent damage to the IC. The LTC6403-1 also
has steering diodes to either power supply on the VOCM,
and ⎯S⎯H⎯D⎯N pins (Pins 4 and 1), and if exposed to voltages
which exceed either supply, they too, should be current
limited to under 10mA.
⎯S⎯H⎯D⎯N Pin
If the ⎯S⎯H⎯D⎯N pin (Pin 1), is pulled 2.1V below the positive
supply, the LTC6403-1 will power down. The pin has the
Thevenin equivalent impedance of approximately 66k to V+.
If the pin is left unconnected, an internal pull-up resistor
of 150k will keep the part in normal active operation. Care
should be taken to control leakage currents at this pin to
under 1μA to prevent inadvertently putting the LTC6403-1
into shutdown. In shutdown, all biasing current sources
are shut off, and the output pins, +OUT and –OUT, will each
appear as an open collector with a non-linear capacitor in
parallel and steering diodes to either supply. Because of
64031f
11
LTC6403-1
APPLICATIONS INFORMATION
the non-linear capacitance, the outputs still have the ability
to sink and source small amounts of transient current if
exposed to significant voltage transients. The inputs (+IN
and –IN) appear as anti-parallel diodes which can conduct
if voltage transients at the input exceed 1.4V. The inputs
also have steering diodes to either supply. The turn-on
time between the shutdown and active states is typically
4μs, and turn-off time is typically 350ns.
General Amplifier Applications
As levels of integration have increased and correspondingly, system supply voltages decreased, there has been
a need for ADCs to process signals differentially in order
to maintain good signal to noise ratios. These ADCs are
typically operated from a single supply voltage which can
be as low as 3V (2.7V min), and will have an optimal common mode input range near mid-supply. The LTC6403-1
makes interfacing to these ADCs trivial, by providing both
single ended to differential conversion as well as common
mode level shifting. The front page of this datasheet shows
a typical application. Referring to Figure 1, the gain to
VOUTDIFF from VINM and VINP is:
VOUTDIFF = V+OUT – V–OUT ≈
RF
• ( VINP – VINM )
RI
Note from the above equation, the differential output
voltage (V+OUT – V–OUT) is completely independent of
input and output common mode voltages. This makes
the LTC6403-1 ideally suited for pre-amplification, level
shifting and conversion of single-ended input signals to
differential output signals in preparation for driving differential input ADCs.
VOUTDIFF = V+OUT – V–OUT ≈
RF
•V
+
RI INDIFF
Δβ
Δβ
• VINCM –
•V
β AVG
β AVG OCM
where:
RF is the average of RF1, and RF2, and RI is the average
of RI1, and RI2.
βAVG is defined as the average feedback factor (or gain)
from the outputs to their respective inputs:
RI2 ⎞
1 ⎛ RI1
β AVG = • ⎜
+
2 ⎝ RI1 + RF1 RI2 + RF 2 ⎟⎠
Δβ is defined as the difference in feedback factors:
Δβ =
RI2
RI1
–
RI2 + RF 2 RI1 + RF1
VINCM is defined as the average of the two input voltages
VINP, and VINM (also called the source-referred input common mode voltage):
1
VINCM = • ( VINP + VINM )
2
and VINDIFF is defined as the difference of the input
voltages:
VINDIFF = VINP – VINM
RI2
V+IN
RF2
+
V–OUT
V–OUTF
VINP
16
–
NC
15
+IN
14
–OUT
13
–OUTF
LTC6403-1
SHDN
Effects of Resistor Pair Mismatch
V–
12
SHDN
VSHDN
Figure 3 shows a circuit diagram with takes into consideration that real world resistors will not perfectly match.
Assuming infinite open loop gain, the differential output
relationship is given by the equation:
1
V–
V+
V+
2
0.1μF
V–
V+
+
V–
–
3
V+
VOCM
V–
–
VINM
+
4
9
0.01μF
5
RI1
NC
6
V–IN
–IN
RF1
7
+OUT
8
0.1μF
0.1μF
V+
V+
10
V– V–
VOCM
VVOCM
V+
11
V–
0.1μF
0.1μF
+OUTF
V–
0.1μF
64031 F03
V+OUTF
V+OUT
Figure 3. Real-World Application with Feedback Resistor
Pair Mismatch
64031f
12
LTC6403-1
APPLICATIONS INFORMATION
When the feedback ratios mismatch (Δβ), common mode
to differential conversion occurs.
Setting the differential input to zero (VINDIFF = 0), the degree of common mode to differential conversion is given
by the equation:
VOUTDIFF = V+OUT – V–OUT ≈ ( VINCM – VOCM ) •
Δβ
β AVG
In general, the degree of feedback pair mismatch is a
source of common mode to differential conversion of
both signals and noise. Using 1% resistors or better will
mitigate most problems, and will provide about 34dB worst
case of common mode rejection. Using 0.1% resistors
will provide about 54dB of common mode rejection. A
low impedance ground plane should be used as a reference for both the input signal source and the VOCM pin.
Directly shorting VOCM to this ground or bypassing the
VOCM with a high quality 0.1μF ceramic capacitor to this
ground plane will further mitigate against common mode
signals being converted to differential.
There may be concern on how feedback ratio mismatch
affects distortion. Distortion caused by feedback ratio mismatch using 1% resistors or better is negligible. However,
in single supply level shifting applications where there is
a voltage difference between the input common mode
voltage and the output common mode voltage, resistor
mismatch can make the apparent voltage offset of the
amplifier appear worse than specified.
The apparent input referred offset induced by feedback
ratio mismatch is derived from the above equation:
VOSDIFF(APPARENT) ≈ (VINCM – VOCM) • Δβ
Using the LTC6403-1 in a single supply application on a
single 5V supply with 1% resistors, and the input common
mode grounded, with the VOCM pin biased at mid-supply,
the worst case mismatch can induce 25mV of apparent
offset voltage. With 0.1% resistors, the worst case apparent offset reduces to 2.5mV.
Input Impedance and Loading Effects
The input impedance looking into the VINP or VINM input
of Figure 1 depends on whether the sources VINP and
VINM are fully differential. For balanced input sources
(VINP = –VINM), the input impedance seen at either input
is simply:
RINP = RINM = RI
For single ended inputs, because of the signal imbalance
at the input, the input impedance increases over the balanced differential case. The input impedance looking into
either input is:
RINP = RINM =
RI
⎛ 1 ⎛ RF ⎞ ⎞
⎜ 1– 2 • ⎜ R + R ⎟ ⎟
⎝ I F ⎠⎠
⎝
Input signal sources with non-zero output impedances can
also cause feedback imbalance between the pair of feedback
networks. For the best performance, it is recommended
that the source’s output impedance be compensated. If
input impedance matching is required by the source, R1
should be chosen (see Figure 4):
R1 =
RINM • RS
RINM – RS
According to Figure 4, the input impedance looking into
the differential amp (RINM) reflects the single ended source
case, thus:
RINM =
RI
⎛ 1 ⎛ RF ⎞ ⎞
⎜ 1– 2 • ⎜ R + R ⎟ ⎟
⎝ I F ⎠⎠
⎝
R2 is chosen to balance R1 || RS:
R2 =
RI • RS
RI + RS
64031f
13
LTC6403-1
APPLICATIONS INFORMATION
VINP (setting VINM to zero), the input common voltage is
approximately:
RINM
RS
RI
RF
R1
VS
–
+
VOCM
+
R1 CHOSEN SO THAT R1 || RINM = RS
R2 CHOSEN TO BALANCE RS || R1
RI
VICM =
–
⎛ RF ⎞ VINP
VCM • ⎜
+
2
⎝ RF + RI ⎟⎠
RF
64031 F04
R2 = RS || R1
Figure 4. Optimal Compensation for Signal Source Impedance
Input Common Mode Voltage Range
The LTC6403-1’s input common mode voltage (VICM) is
defined as the average of the two input voltages, V+IN, and
V–IN. It extends from V– to 1.4V below V+.
For fully differential input applications, where VINP = –VINM,
the input common mode voltage is approximately (Refer
to Figure 5):
⎛ RI ⎞
V+IN + V–IN
≈ VVOCM • ⎜
+
2
⎝ RI + RF ⎟⎠
VICM =
⎛ RF ⎞
VCM • ⎜
⎝ RF + RI ⎟⎠
With singled ended inputs, there is an input signal component to the input common mode voltage. Applying only
RI
V+IN
RF
+
V–OUT
V–OUTF
VINP
16
–
NC
15
+IN
14
–OUT
13
–OUTF
LTC6403-1
SHDN
V–
12
SHDN
VSHDN
1
–
V
V+
V+
VCM
2
0.1μF
V–
V+
+
V–
–
3
V+
VOCM
V–
VVOCM
–
+
V+
11
0.1μF
RI
NC
6
V–IN
–IN
RF
7
+OUT
8
⎛ RF ⎞
•⎜
⎝ RF + RI ⎟⎠
Output Common Mode Voltage Range
The output common mode voltage is defined as the average of the two outputs:
VOUTCM = VVOCM =
V+OUT + V–OUT
2
The VOCM pin sets this average by an internal common
mode feedback loop. The output common mode range
extends from 1.1V above V– to 1V below V+. The VOCM
pin sits in the middle of an internal voltage divider which
sets the default mid-supply open circuit potential.
In single supply applications, where the LTC6403-1 is
used to interface to an ADC, the optimal common mode
input range to the ADC is often determined by the ADC’s
reference. If the ADC makes a reference available for setting the input common mode voltage, it can be directly
tied to the VOCM pin, but must be capable of driving the
input impedance presented by the VOCM as listed in the
Electrical Characteristics Table. This impedance can be
assumed to be connected to a mid-supply potential. If an
external reference drives the VOCM pin, it should still be
bypassed with a high quality 0.01μF or higher capacitor to
a low impedance ground plane to filter any thermal noise
and to prevent common mode signals on this pin from
being inadvertently converted to differential signals.
0.1μF
0.1μF
9
5
0.1μF
V+
V+
10
4
0.01μF
VINM
V–
V– V–
VOCM
⎛ RI ⎞
V+IN + V–IN
≈ VVOCM • ⎜
+
2
⎝ RI + RF ⎟⎠
+OUTF
V–
0.1μF
64031 F05
V+OUTF
V+OUT
Figure 5. Circuit for Common Mode Range
Output Filter Considerations and Use
Filtering at the output of the LTC6403-1 is often desired
to provide either anti-aliasing or improved signal to noise
ratio. To simplify this filtering, the LTC6403-1 includes an
additional pair of differential outputs (+OUTF and –OUTF)
which incorporate an internal lowpass filter network with
a –3dB bandwidth of 44.2MHz (Figure 6).
64031f
14
LTC6403-1
APPLICATIONS INFORMATION
These pins each have an output impedance of 100Ω. Internal capacitances are 12pF to V– on each filtered output,
plus an additional 12pF capacitor connected differentially
between the two filtered outputs. This resistor/capacitor
combination creates filtered outputs that look like a series 100Ω resistor with a 36pF capacitor shunting each
filtered output to AC ground, providing a –3dB bandwidth
of 44.2MHz, and a noise bandwidth of 69.4MHz. The
filter cutoff frequency is easily modified with just a few
external components. To increase the cutoff frequency,
simply add 2 equal value resistors, one between +OUT
and +OUTF and the other between –OUT and –OUTF
(Figure 7). These resistors, in parallel with the internal
100Ω resistors, lower the overall resistance and therefore
increase filter bandwidth. For example, to double the filter
bandwidth, add two external 100Ω resistors to lower the
series filter resistance to 50Ω. The 36pF of capacitance
remains unchanged, so filter bandwidth doubles. Keep in
mind, the series resistance also serves to decouple the
outputs from load capacitance. The unfiltered outputs of
the LTC6403-1 are designed to drive 10pF to ground or
5pF differentially, so care should be taken to not lower the
effective impedance between +OUT and +OUTF or –OUT
and –OUTF below 25Ω.
To decrease filter bandwidth, add two external capacitors,
one from +OUTF to ground, and the other from –OUTF to
ground. A single differential capacitor connected between
14
–OUT
13
+OUTF and –OUTF can also be used, and since it is being
driven differentially it will appear at each filtered output
as a single-ended capacitance of twice the value. To halve
the filter bandwidth, for example, two 36pF capacitors
could be added (one from each filtered output to ground).
Alternatively, one 18pF capacitor could be added between
the filtered outputs, again halving the filter bandwidth.
Combinations of capacitors could be used as well; a three
capacitor solution of 12pF from each filtered output to
ground plus a 12pF capacitor between the filtered outputs
would also halve the filter bandwidth (Figure 8).
100Ω
14
+
–
FILTERED OUTPUT
(88.4MHz)
100Ω
–
12pF V V–
9
7
+OUT
8
+OUTF
64031 F07
100Ω
Figure 7. LTC6403-1 Filter Topology Modified for 2x
Filter Bandwidth (2 External Resistors)
–OUT
13
–OUTF
LTC6403-1
12pF
100Ω
V–
+
–
100Ω
V–
12pF
+OUT
8
–
12pF V V–
V–
+OUTF
FILTERED OUTPUT
(22.1MHz)
100Ω
12pF
9
9
7
12pF
V–
12
12pF
FILTERED OUTPUT
(44.2MHz)
12pF
V–
12
V–
V–
12
V–
LTC6403-1
12pF
14
12pF
–OUTF
100Ω
LTC6403-1
100Ω
–
13
12pF
–OUTF
12pF
+
–OUT
7
+OUT
8
+OUTF
64031 F08
64031 F06
Figure 6. LTC6403-1 Internal Filter Topology
Figure 8. LTC6403-1 Filter Topology Modified for 1/2x
Filter Bandwidth (3 External Capacitors)
64031f
15
LTC6403-1
APPLICATIONS INFORMATION
Noise Considerations
The LTC6403-1’s input referred voltage noise contributes
the equivalent noise of a 480Ω resistor. When the feedback
network is comprised of resistors whose values are less
than this, the LTC6403-1’s output noise is voltage noise
dominant (See Figure 10.):
The LTC6403-1’s input referred voltage noise is on the
order of 2.8nV/√⎯H⎯z. Its input referred current noise is on
the order of 1.8pA/√⎯H⎯z. In addition to the noise generated
by the amplifier, the surrounding feedback resistors also
contribute noise. A noise model is shown in Figure 9.
The output noise generated by both the amplifier and the
feedback components is governed by the equation:
⎛ R ⎞
eno ≈ eni • ⎜ 1+ F ⎟
⎝ RI ⎠
Feedback networks consisting of resistors with values
greater than about 1k will result in output noise which is
resistor noise and amplifier current noise dominant.
2
eno =
⎛
⎛ RF ⎞ ⎞
2
⎜ eni • ⎜ 1+ R ⎟ ⎟ + 2 • (In • RF ) +
⎝
⎝
I ⎠⎠
2
⎛
⎛ R ⎞⎞
2 • ⎜ enRI • ⎜ F ⎟ ⎟ + 2 • enRF 2
⎝ RI ⎠ ⎠
⎝
eno ≈ 2 •
RI2
RF2
⎞
I
Lower resistor values (<400Ω) always result in lower noise
at the penalty of increased distortion due to increased
loading of the feedback network on the output. Higher
A plot of this equation, and a plot of the noise generated
by the feedback components for the LTC6403-1 is shown
in Figure 10.
enRI22
⎛
(In • RF )2 + ⎜⎝ 1+ RRF ⎟⎠ • 4 • k • T • RF
enRF22
in+2
16
NC
15
+IN
14
–OUT
13
–OUTF
LTC6403-1
SHDN
V–
12
SHDN
1
V– V+
11
V+
V+
V+
2
+
V–
encm
3
V+
VOCM
V–
V+
10
–
V–
V+
enof2
eno2
V– V–
2
VOCM
4
9
5
V–
NC
6
–IN
7
+OUT
8
V–
+OUTF
64031 F09
in–2
eni2
enRI12
RI1
RF1
enRF12
Figure 9. Noise Model of the LTC6403-1
64031f
16
LTC6403-1
APPLICATIONS INFORMATION
supplies, it is recommended that at least two additional
high quality, 0.1μF ceramic capacitors are used to bypass
pin V+ to ground and V– to ground, again with minimal
routing. For driving large loads (<200Ω), additional bypass
capacitance may be needed for optimal performance. Keep
in mind that small geometry (e.g. 0603) surface mount
ceramic capacitors have a much higher self resonant
frequency than do leaded capacitors, and perform best
in high speed applications.
100
nV/√Hz
TOTAL (AMPLIFIER AND
FEEDBACK NETWORK)
OUTPUT NOISE
10
FEEDBACK RESISTOR
NETWORK NOISE ALONE
1
100
1k
RF = RI (Ω)
10k
64031 F10
Figure 10. LTC6403-1 Output Spot Noise vs Spot Noise
Contributed by Feedback Network Alone
resistor values (but still less than 2k) will result in higher
output noise, but improved distortion due to less loading
on the output. The optimal feedback resistance for the
LTC6403-1 runs between 400Ω to 2k.
The differential filtered outputs +OUTF and –OUTF will have
a little higher spot noise than the unfiltered outputs (due
to the two 100Ω resistors which contribute 1.3nV/√⎯H⎯z
each), but actually will provide superior signal-to-noise
ratios in noise bandwidths exceeding 69.4Mhz due to the
noise-filtering function the filter provides.
Layout Considerations
Because the LTC6403-1 is a very high speed amplifier, it is
sensitive to both stray capacitance and stray inductance.
Three pairs of power supply pins are provided to keep the
power supply inductance as low as possible to prevent
any degradation of amplifier 2nd Harmonic distortion
performance. It is critical that close attention be paid to
supply bypassing. For single supply applications (Pins
3, 9 and 12 grounded) it is recommended that 3 high
quality 0.1μF surface mount ceramic bypass capacitor be
placed between pins 2 and 3, between pins 11and 12, and
between pins10 and 9 with direct short connections. Pins
3, 9 and 10 should be tied directly to a low impedance
ground plane with minimal routing. For dual (split) power
Any stray parasitic capacitances to ground at the summing junctions +IN, and –IN should be kept to an absolute
minimum even if it means stripping back the ground plane
away from any trace attached to this node. This becomes
especially true when the feedback resistor network uses
resistor values >2k in circuits with RF = RI. Excessive
peaking in the frequency response can be mitigated by
adding small amounts of feedback capacitance around
RF. Always keep in mind the differential nature of the
LTC6403-1, and that it is critical that the load impedances
seen by both outputs (stray or intended) should be as balanced and symmetric as possible. This will help preserve
the natural balance of the LTC6403-1, which minimizes
the generation of even order harmonics, and preserves
the rejection of common mode signals and noise.
It is highly recommended that the VOCM pin be either hard
tied to a low impedance ground plane (in split supply
applications), or bypassed to ground with a high quality
ceramic capacitor whose value exceeds 0.01μF. This will
help stabilize the common mode feedback loop as well as
prevent thermal noise from the internal voltage divider and
other external sources of noise from being converted to
differential noise due to divider mismatches in the feedback networks. It is also recommended that the resistive
feedback networks comprise 1% resistors (or better) to
enhance the output common mode rejection. This will also
prevent the VOCM-referred common mode noise of the
common mode amplifier path (which cannot be filtered)
from being converted to differential noise, degrading the
differential noise performance.
64031f
17
LTC6403-1
APPLICATIONS INFORMATION
Interfacing the LTC6403-1 to A/D Converters
to help absorb the charge injection that comes out of the
ADC from the sampling process. The capacitance of the
filter network serves as a charge reservoir to provide high
frequency charging during the sampling process, while the
two resistors of the filter network are used to dampen and
attenuate any charge kickback from the ADC. The selection
of the R-C time constant is trial and error for a given ADC,
but the following guidelines are recommended: Choosing
too large of a resistor in the decoupling network will create
a voltage divider between the dynamic input impedance of
the ADC and the decoupling resistors leaving insufficient
settling time. Choosing too small of a resistor will possibly
prevent the resistor from properly dampening the load
transient caused by the sampling process, prolonging
the time required for settling. 16-bit applications require
a minimum of 11 R-C time constants to settle. It is recommended that the capacitor chosen have a high quality
dielectric (for example, C0G multilayer ceramic).
The LTC6403-1’s rail-to-rail output and fast settling time
make the LTC6403-1 ideal for interfacing to low voltage,
single supply, differential input ADCs. The sampling process
of ADCs creates a sampling glitch caused by switching
in the sampling capacitor on the ADC front end which
momentarily “shorts” the output of the amplifier as charge
is transferred between the amplifier and the sampling
capacitor. The amplifier must recover and settle from
this load transient before this acquisition period ends for
a valid representation of the input signal. In general, the
LTC6403-1 will settle much more quickly from these periodic load impulses than from a 2V input step, but it is
a good idea to either use the filtered outputs to drive the
ADC (Figure 11 shows an example of this), or to place a
discrete R-C filter network between the differential unfiltered outputs of the LTC6403-1 and the input of the ADC
402Ω
16
NC
402Ω
15
+IN
14
–OUT
13
–OUTF
LTC6403-1
SHDN
V–
12
SHDN
1
V– V+
11
+
V
3.3V
V+
2
0.1μF
+
3
V+
VOCM
V–
V+
10
–
V–
V– V–
VOCM
4
CONTROL
VCM
2.2μF
0.1μF
LTC2207
3.3V
0.1μF
D15
•
•
D0
AIN+
AIN–
GND
3.3V
VDD
1μF
9
0.1μF
5
VIN, 2VP-P
NC
402Ω
6
–IN
7
+OUT
8
+OUTF
64031 F11
402Ω
Figure 11. Interfacing the LTC6403-1 to ADC (Shared 3.3V Supply Voltage)
64031f
18
LTC6403-1
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
3.50 ± 0.05
1.45 ± 0.05
2.10 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ± 0.05
15
16
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
1.45 ± 0.10
(4-SIDES)
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
64031f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC6403-1
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
High-Speed Differential Amplifiers/Differential Op Amps
LT1994
Low Noise, Low Distortion Differential Op Amp
16-Bit Performance at 1MHz, Rail-to-Rail Outputs
LT5514
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
OIP3 = 47dBm at 100MHz, Gain Control Range 10.5dB to 33dB
LT5524
Low Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
OIP3 = 40dBm at 100MHz, Gain Control Range 4.5dB to 37dB
LTC6401-20
1.3GHz Low Noise Low Distortion Differential ADC Driver
AV = 20dB, 50mA Supply Current, IMD = –74dBc at 140MHz
LTC6401-26
1.6GHz Low Noise Low Distortion Differential ADC Driver
AV = 26dB, 45mA Supply Current, IMD = –72dBc at 140MHz
LT6402-6
300MHz Differential Amplifier/ADC Driver
AV = 6dB, Distortion <–80dBc at 25MHz
LT6402-12
300MHz Differential Amplifier/ADC Driver
AV = 12dB, Distortion <–80dBc at 25MHz
LT6402-20
300MHz Differential Amplifier/ADC Driver
AV = 20dB, Distortion <–80dBc at 25MHz
LTC6404-1
600MHz Rail-to-Rail Output Differential Op Amp
AV = 1 Stable, 1.6nV/√⎯H⎯z, –90dBc Distortion at 10MHz
LTC6404-2
900MHz Rail-to-Rail Output Differential Op Amp
AV = 2 Stable, 1.6nV/√⎯H⎯z, –95dBc Distortion at 10MHz
LTC6404-4
1800MHz Rail-to-Rail Output Differential Op Amp
AV = 4 Stable, 1.6nV/√⎯H⎯z, –98dBc Distortion at 10MHz
LTC6406
3GHz Rail-to-Rail Input Differential Op Amp
1.6nV/√⎯H⎯z Noise, –72dBc Distortion at 50MHz, 18mA
LT6411
Low Power Differential ADC Driver/Dual Selectable Gain
Amplifier
16mA Supply Current, IMD3 = –83dBc at 70MHz, AV = 1, –1 or 2
High-Speed Single-Ended Output Op Amps
LT1812/LT1813/
LT1814
High Slew Rate Low Cost Single/Dual/Quad Op Amps
750V/μsec, 3mA Supply Current, 8nV/√⎯H⎯z Noise
LT1815/LT1816/
LT1817
Very High Slew Rate Low Cost Single/Dual/Quad Op Amps
1500V/μsec, 6.5mA Supply Current, 6nV/√⎯H⎯z Noise
LT1818/LT1819
Ultra High Slew Rate Low Cost Single/Dual Op Amps
2500V/μsec, 9mA Supply Current, 6nV/√⎯H⎯z Noise
LT6200/LT6201
Rail-to-Rail Input and Output Low Noise Single/Dual Op Amps 0.95nV/√⎯H⎯z Noise, 165MHz GBW, Distortion = –80dBc at 1MHz
LT6204/LT6203/
LT6204
Rail-to-Rail Input and Output Low Noise Single/Dual/Quad Op 1.9nV/√⎯H⎯z Noise, 3mA Supply Current, 100MHz GBW
Amps
⎯ z⎯ Noise, 3.5mA Supply Current, 215MHz GBW
Rail-to-Rail Output Low Noise Single/Dual/Quad Op Amps
1.1nV/√H
LT6230/LT6231/
LT6232
Rail-to-Rail Output Low Noise Single/Dual/Quad Op Amps
1.9nV/√⎯H⎯z Noise, 1.2mA Supply Current, 60MHz GBW
LTC1562-2
Very Low Noise, 8th Order Filter Building Block
Lowpass and Bandpass Filters Up to 300kHz
LT1568
Very Low Noise, 4th Order Filter Building Block
Lowpass and Bandpass Filters Up to 10MHz
LTC1569-7
Linear Phase, Tunable 10th Order Lowpass Filter
Single-Resistor Programmable Cut-Off to 300kHz
LT6600-2.5
Very Low Noise Differential 2.5MHz Filter
SNR = 86dB at 3V Supply, 4th Order Filter
LT6600-5
Very Low Noise Differential 5MHz Filter
SNR = 82dB at 3V Supply, 4th Order Filter
LT6600-10
Very Low Noise Differential 10MHz Filter
SNR = 82dB at 3V Supply, 4th Order Filter
LT6600-15
Very Low Noise Differential 15MHz Filter
SNR = 76dB at 3V Supply, 4th Order Filter
LT6600-20
Very Low Noise Differential 20MHz Filter
SNR = 76dB at 3V Supply, 4th Order Filter
LT6233/LT6234/
LT6235
Integrated Filters
64031f
20 Linear Technology Corporation
LT 0108 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
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