LINER LTC6957-1 Low phase noise, dual output buffer/driver/logic converter Datasheet

LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Low Phase Noise, Dual
Output Buffer/Driver/
Logic Converter
Description
Features
Low Phase Noise Buffer/Driver
n Optimized Conversion of Sine Wave Signals to
Logic Levels
n Three Logic Output Types Available
– LVPECL
– LVDS
– CMOS
n Additive Jitter 45fs
RMS (LTC6957-1)
n Frequency Range Up to 300MHz
n 3.15V to 3.45V Supply Operation
n Low Skew 3ps Typical
n Fully Specified from –40°C to 125°C
n 12-Lead MSOP and 3mm × 3mm DFN Packages
The LTC®6957-1/LTC6957-2/LTC6957-3/LTC6957-4 is
a family of very low phase noise, dual output AC signal
buffer/driver/logic level translators. The input signal can
be a sine wave or any logic level (≤2VP-P). There are four
members of the family that differ in their output logic
signal type as follows:
n
LTC6957-1: LVPECL Logic Outputs
LTC6957-2: LVDS Logic Outputs
LTC6957-3: CMOS Logic, In-Phase Outputs
LTC6957-4: CMOS Logic, Complementary Outputs
The LTC6957 will buffer and distribute any logic signal
with minimal additive noise, however, the part really excels at translating sine wave signals to logic levels. The
early amplifier stages have selectable lowpass filtering
to minimize the noise while still amplifying the signal to
increase its slew rate. This input stage filtering/noise limiting is especially helpful in delivering the lowest possible
phase noise signal with slow slewing input signals such
as a typical 10MHz sine wave system reference.
Applications
n
n
n
n
n
n
n
n
System Reference Frequency Distribution
High Speed ADC, DAC, DDS Clock Driver
Military and Secure Radio
Low Noise Timing Trigger
Broadband Wireless Transceiver
High Speed Data Acquisition
Medical Imaging
Test and Measurement
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents 7969189 and 8319551.
Typical Application
3.3V
0.1µF
Additive Phase Noise at 100MHz
–140
OCXO
100MHz
+7dBm
SINE WAVE
SD1
FILTB
10nF
OUT1
IN+
IN–
50Ω
10nF
OUT2
SD2
6957 TA01a
LTC6957-2 (LVDS)
–150
LTC6957-4 (CMOS)
–155
–160
GND
SINGLE-ENDED SINE WAVE INPUT
AT +7dBm (500mVRMS)
FILTA = FILTB = GND
–145
TO PLL CHIPS
OR SYSTEM
SAMPLING CLOCKS
PHASE NOISE (dBc/Hz)
FILTA
V+
LTC6957-3
(CMOS)
–165
100
LTC6957-1 (LVPECL)
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
69571234 TA01b
6957f
For more information www.linear.com/LTC6957-1
1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V+ or VDD) to GND...........................3.6V
Input Current (IN+, IN–, FILTA, FILTB, SD1, SD2)
(Note 2)........................................................... ±10mA
LTC6957-1 Output Current ......................... 1mA, –30mA
LTC6957-2 Output Current .................................. ±10mA
LTC6957-3, LTC6957-4 Output Current (Note 3)... ±30mA
Specified Temperature Range
LTC6957I..............................................–40°C to 85°C
LTC6957H........................................... –40°C to 125°C
Junction Temperature ........................................... 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (for MSOP Soldering, 10sec).... 300°C
Pin Configuration
LTC6957-1, LTC6957-2
LTC6957-3, LTC6957-4
TOP VIEW
TOP VIEW
FILTA
1
12 SD1
FILTA
1
V+
2
11 OUT1+
V+
2
IN+
3
10 OUT1–
IN+
3
IN–
4
9 OUT2–
IN–
4
GND
5
GND
5
FILTB
6
8 OUT2+
7 SD2
FILTB
6
13
GND
12 SD1
11 V DD
13
GND
10 OUT1
9 OUT2
8 GNDOUT
7 SD2
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
DD PACKAGE
12-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 58°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, θJA = 58°C/W, θJC = 10°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
LTC6957-1, LTC6957-2
LTC6957-3, LTC6957-4
TOP VIEW
FILTA
V+
IN+
IN–
GND
FILTB
1
2
3
4
5
6
TOP VIEW
12
11
10
9
8
7
SD1
OUT1+
OUT1–
OUT2–
OUT2+
SD2
FILTA
V+
IN+
IN–
GND
FILTB
1
2
3
4
5
6
12
11
10
9
8
7
MS PACKAGE
12-LEAD PLASTIC MSOP
MS PACKAGE
12-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 145°C/W
TJMAX = 150°C, θJA = 145°C/W
SD1
V DD
OUT1
OUT2
GNDOUT
SD2
6957f
2
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
SPECIFIED TEMPERATURE RANGE
LTC6957IDD-1#PBF
LTC6957IDD-1#TRPBF
LFQJ
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6957IDD-2#PBF
LTC6957IDD-2#TRPBF
LFQK
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6957IDD-3#PBF
LTC6957IDD-3#TRPBF
LFQM
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6957IDD-4#PBF
LTC6957IDD-4#TRPBF
LFQN
12-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC6957IMS-1#PBF
LTC6957IMS-1#TRPBF
69571
12-Lead Plastic MSOP
–40°C to 85°C
LTC6957HMS-1#PBF
LTC6957HMS-1#TRPBF
69571
12-Lead Plastic MSOP
–40°C to 125°C
LTC6957IMS-2#PBF
LTC6957IMS-2#TRPBF
69572
12-Lead Plastic MSOP
–40°C to 85°C
LTC6957HMS-2#PBF
LTC6957HMS-2#TRPBF
69572
12-Lead Plastic MSOP
–40°C to 125°C
LTC6957IMS-3#PBF
LTC6957IMS-3#TRPBF
69573
12-Lead Plastic MSOP
–40°C to 85°C
LTC6957HMS-3#PBF
LTC6957HMS-3#TRPBF
69573
12-Lead Plastic MSOP
–40°C to 125°C
LTC6957IMS-4#PBF
LTC6957IMS-4#TRPBF
69574
12-Lead Plastic MSOP
–40°C to 85°C
LTC6957HMS-4#PBF
LTC6957HMS-4#TRPBF
69574
12-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6957f
For more information www.linear.com/LTC6957-1
3
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Electrical Characteristics
LTC6957-1
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
300
MHz
0.8
2
VP-P
0.8
2
VP-P
Inputs (IN–, IN+)
fIN
Input Frequency Range
l
VINSE
Input Signal Level Range, Single-Ended
l
0.2
VINDIFF
Input Signal Level Range, Differential
l
0.2
tMIN
Minimum Input Pulse Width
VINCM
Self-Bias Voltage, IN+, IN–
l
1.8
2.06
2.3
V
RIN
Input Resistance, Differential
l
1.5
2
2.5
kΩ
CIN
Input Capacitance, Differential
BWIN
Input Section Small Signal Bandwidth (–3dB)
High or Low
0.5
ns
0.5
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
pF
1200
500
160
50
MHz
MHz
MHz
MHz
Outputs (LVPECL)
VOH
Output High Voltage
LTC6957I
LTC6957H
l
l
V+ – 1.22 V+ – 0.98 V+ – 0.93
V+ – 1.22 V+ – 0.98 V+ – 0.87
V
V
VOL
Output Low Voltage
LTC6957I
LTC6957H
l
l
V+ – 2.1
V+ – 2.1
V+ – 1.8
V+ – 1.8
V+ – 1.67
V+ – 1.62
V
V
VOD
Output Differential Voltage
l
±660
±810
±965
tr
Output Rise Time
180
ps
tf
Output Fall Time
160
ps
t PD
Propagation Delay
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
l
l
l
l
∆tPD /∆T Propagation Delay Variation Over Temperature
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
l
l
l
l
0.1
0.1
0.11
0.15
∆tPD/∆V Propagation Delay Variation vs Supply Voltage
FILTB = L, FILTA = L
l
4
50
ps/V
l
3
30
ps
2.5
30
ps
3.3
3.45
V
18
15
0.7
58
22
19
1.2
72
mA
mA
mA
mA
tSKEW
Output Skew, Differential, CH1 to CH2
tMATCH
Output Matching (OUTx + to OUTx–)
See Timing Diagram
l
V+
V+ Operating Supply Voltage Range
RLOAD = 50Ω to (V+– 2V)
l
IS
Supply Current
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
Including Output Loads
No Output Loads
No Output Loads
No Output Loads
RLOAD = 50Ω to (V+– 2V), ×4
l
l
l
l
0.35
0.5
0.6
1.1
3.2
0.7
0.8
1.3
4
mV
ns
ns
ns
ns
ps/°C
ps/°C
ps/°C
ps/°C
Power
tENABLE
3.15
Output Enable Time, Other SDx = L
40
µs
tWAKEUP Output Enable Time, Other SDx = H
120
µs
tDISABLE Output Disable Time, Other SDx = L
20
µs
Output Disable Time, Other SDx = H
20
µs
tSLEEP
6957f
4
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Electrical Characteristics
LTC6957-1
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 50Ω connected to 1.3V, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Logic Inputs
VIH
High Level SD or FILT Input Voltage
l
VIL
Low Level SD or FILT Input Voltage
l
IIN_DIG
Input Current SD or FILT Pins
l
V+ – 0.4
V
0.1
0.4
V
±10
µA
Additive Phase Noise and Jitter
fIN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
at 10Hz Offset
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
–130
–140
–150
–157
–157.5
–157.5
123
45
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
fIN = 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
at 10Hz Offset
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
–137
–146
–154.6
–157
–157.2
–157.2
200
114
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
fIN = 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
at 10Hz Offset
at 100Hz Offset
at 1kHz Offset
at 10kHz Offset
at 100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
–138
–148.1
–156.8
–160.6
–161
–161
142
90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
6957f
For more information www.linear.com/LTC6957-1
5
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Electrical Characteristics
LTC6957-2
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
300
MHz
Inputs (IN–, IN+)
fIN
Input Frequency Range
l
VINSE
Input Signal Level Range, Single-Ended
l
0.2
0.8
2
VP-P
VINDIFF
Input Signal Level Range, Differential
l
0.2
0.8
2
VP-P
tMIN
Minimum Input Pulse Width
VINCM
Self-Bias Voltage, IN+, IN–
l
1.8
2
2.3
V
RIN
Input Resistance, Differential
l
1.5
2
2.5
kΩ
CIN
Input Capacitance, Differential
BWIN
Input Section Small Signal Bandwidth
High or Low
0.5
ns
0.5
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
pF
1200
500
160
50
MHz
MHz
MHz
MHz
Outputs (LVDS)
VOD
Output Differential Voltage
l
∆VOD
Delta VOD
l
VOS
Output Offset Voltage
l
∆VOS
Delta VOS
l
ISC
Short-Circuit Current
l
tr
Output Rise Time
170
ps
tf
Output Fall Time
170
ps
t PD
Propagation Delay
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
l
l
l
l
∆tPD /∆T
Propagation Delay Variation Over Temperature
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
l
l
l
l
0.5
0.6
0.7
1.8
∆tPD /∆V Propagation Delay Variation vs Supply Voltage
FILTB = L, FILTA = L
l
5
60
ps/V
Output Skew, Differential, CH1 to CH2
l
3
50
ps
V+
V+ Operating Supply Voltage Range
l
3.3
3.45
V
IS
Supply Current
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
l
l
l
38
26
0.7
45
30
1.2
mA
mA
mA
tSKEW
250
1.125
0.65
360
450
mV
0.2
50
mV
1.25
1.375
1.5
50
mV
3.9
6
mA
0.84
0.9
1.35
3.5
1.15
1.3
1.8
4.4
V
ns
ns
ns
ns
ps/°C
ps/°C
ps/°C
ps/°C
Power
3.15
tENABLE
Output Enable Time, Other SDx = L
300
ns
tWAKEUP
Output Enable Time, Other SDx = H
400
ns
tDISABLE
Output Disable Time, Other SDx = L
40
ns
tSLEEP
Output Disable Time, Other SDx = H
50
ns
6957f
6
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Electrical Characteristics
LTC6957-2
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. V+ = 3.3V,
SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 110Ω differential, unless otherwise specified. All voltages are with respect to ground.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Logic Inputs
VIH
High Level SD or FILT Input Voltage
l
VIL
Low Level SD or FILT Input Voltage
l
IIN_DIG
Input Current SD or FILT Pins
l
V+ – 0.4
V
0.1
0.4
V
±10
µA
Additive Phase Noise and Jitter
fIN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
–124
–134
–143.5
–151.3
–154
–154
183
67
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
fIN = 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
–132.5
–142.5
–150.7
–156
–157
–157
203
116
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
fIN = 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
–132
–142
–151
–157.5
–159.5
–159.5
169
107
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
6957f
For more information www.linear.com/LTC6957-1
7
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Electrical Characteristics
LTC6957-3/LTC6957-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD /2, unless otherwise specified. All voltages are with
respect to ground.
SYMBOL PARAMETER
CONDITIONS
Inputs (IN–, IN+)
Input Frequency Range
fIN
Input Signal Level Range, Single-Ended
VINSE
VINDIFF Input Signal Level Range, Differential
tMIN
Minimum Input Pulse Width
Self-Bias Voltage, IN+, IN–
VINCM
Input Resistance, Differential
RIN
Input Capacitance, Differential
CIN
Input Section Small Signal Bandwidth
BWIN
TYP
0.2
0.2
0.8
0.8
0.6
2
2
0.5
1200
500
160
50
l
l
l
High or Low
l
1.8
1.5
l
l
VDD – 0.1
VDD – 0.2
l
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
Outputs (CMOS)
Output High Voltage
VOH
No Load
–3mA Load
No Load
3mA Load
VOL
Output Low Voltage
tr
tf
tPD
Output Rise Time
Output Fall Time
Propagation Delay
∆tPD/∆T
Propagation Delay Variation Over Temperature
∆tPD/∆V
Propagation Delay Variation vs Supply Voltage
tSKEW
Output Skew, CH1 to CH2
LTC6957-3
LTC6957-4
Power
V+
VDD
IS
MIN
IDD
V+ Operating Supply Voltage Range
VDD Operating Supply Voltage Range
Supply Current, Pin 2
Both Outputs Enabled (SD1 = SD2 = L)
One Output Enabled (SD1 = L, SD2 = H or SD1 = H, SD2 = L)
Both Outputs Disabled (SD1 = SD2 = H)
Supply Current, Pin 11, No Load
tENABLE
tWAKEUP
tDISABLE
tSLEEP
Output Enable Time, Other SDx = L
Output Enable Time, Other SDx = H
Output Disable Time, Other SDx = L
Output Disable Time, Other SDx = H
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
FILTB = L, FILTA = L
FILTB = L, FILTA = H
FILTB = H, FILTA = L
FILTB = H, FILTA = H
FILTB = FILTA = L, V+ = VDD
300
2
2
MHz
VP-P
VP-P
ns
V
kΩ
pF
MHz
MHz
MHz
MHz
2.3
2.5
l
320
300
0.95
1
1.5
3.6
1.7
1.7
2
3
100
200
l
l
5
120
35
250
ps
ps
3.3
3.3
3.45
3.45
V
V
24
24
0.7
0.001
0.056
200
300
20
20
27.5
27.5
1.2
0.01
0.07
mA
mA
mA
mA
mA/MHz
ns
ns
ns
ns
0.1
0.2
l
l
l
l
l
l
0.8
l
l
l
l
l
l
l
l
Static
Dynamic, per Output
UNITS
V
V
V
V
ps
ps
ns
ns
ns
ns
ps/°C
ps/°C
ps/°C
ps/°C
ps/V
l
VDD Must Be ≤V +
MAX
l
l
3.15
2.4
1.6
1.8
2.4
4.8
6957f
8
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Electrical Characteristics
LTC6957-3/LTC6957-4
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = VDD = 3.3V, SD1 = SD2 = 0.4V, FILTA = FILTB = 0.4V, RLOAD = 480Ω to VDD /2, unless otherwise specified. All voltages are with
respect to ground.
SYMBOL PARAMETER
CONDITIONS
Digital Logic Inputs
VIH
High Level SD or Filt Input Voltage
Low Level SD or Filt Input Voltage
VIL
Input Current SD or Filt Pins
IIN_DIG
MIN
l
TYP
MAX
UNITS
0.1
0.4
±10
V
V
µA
V+ – 0.4
l
l
Additive Phase Noise and Jitter
fIN = 300MHz Sine Wave, 7dBm (FILTA = L, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 150MHz)
Jitter (12kHz to 20MHz)
fIN = 122.88MHz Sine Wave, 0dBm (FILTA = H, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 61.44MHz)
Jitter (12kHz to 20MHz)
fIN = 100MHz Sine Wave, 10dBm (FILTA = L, FILTB = L)
10Hz Offset
100Hz Offset
1kHz Offset
10kHz Offset
100kHz Offset
>1MHz Offset
Jitter (10Hz to 50MHz)
Jitter (12kHz to 20MHz)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Input pins IN+, IN–, FILTA, FILTB, SD1 and SD2 are protected by
steering diodes to either supply. If the inputs go beyond either supply rail,
the input current should be limited to less than 10mA. If pushing current
into FILTB, the Pin 6 voltage must be limited to 4V. On the logic pins
(FILTA, FILTB, SD1 and SD2) the Absolute Maximum input current applies
–123
–133
–143
–152
–156
–156
146
53
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
–132
–142
–150.6
–156.5
–157.4
–157.4
192
109
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
–135
–145
–153
–159.8
–161
–161
142
90
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fsRMS
fsRMS
only at the maximum operating supply voltage of 3.45V; 10mA of input
current with the absolute maximum supply voltage of 3.6V may create
permanent damage from voltage stress.
Note 3: With 3.6V Absolute Maximum supply voltage, the LTC6957-3/
LTC6957-4 CMOS outputs can sink 30mA while low, and source 30mA
while high without damage. However, if overdriven or subject to an
inductive load kick outside the supply rails, 30mA can create damaging
voltage stress and is not guaranteed unless VDD is limited to 3.15V.
6957f
For more information www.linear.com/LTC6957-1
9
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical Performance Characteristics
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
20
V+ = 3.45V
16
2.10
SUPPLY CURRENT (mA)
INPUT VOLTAGE (V)
NO OUTPUT LOADS
18
2.15
V+ = 3.3V
2.05
2.00
V+ = 3.15V
18.4
12
TA = –55°C
TA = 25°C
10
8
6
5 25 45 65 85 105 125
TEMPERATURE (°C)
17.2
16.8
0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
SUPPLY VOLTAGE (V)
2.45
Supply Current vs Temperature
58
V+ = 3.3V
50Ω LOADS TO 1.3V
1.55
VOL
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V)
1.60
V+ = 3.45V
56
VOH
2.30
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G03
Output Voltage vs Temperature
2.50
1.50
17.4
16.6
–55 –35 –15
2.4
VOH
V+ = 3.15V
17.8
2
Output Voltage vs Load Current
1.45
18.0
69571234 G02
2.55
2.35
V+ = 3.3V
0
69571234 G01
2.40
V+ = 3.45V
18.2
17.0
4
1.90
–55 –35 –15
NO OUTPUT LOADS
18.8
TA = 125°C
14
1.95
OUTPUT VOLTAGE (V)
Supply Current vs Temperature
18.6
SUPPLY CURRENT (mA)
2.20
LTC6957-1
2.2
1.6
VOL
54
V+ = 3.3V
52
V+ = 3.15V
50
48
50Ω “Y” LOAD TO GROUND
ON BOTH CHANNELS
1.40
–8
–2
–6
–4
LOAD CURRENT (mA)
1.4
–55 –35 –15
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
Enable and Wakeup
WAKE-UP:
OUTPUTS WITH
OTHER CHANNEL OFF
80
NUMBER OF UNITS
2.5V
2.0V
1.5V
ENABLE: OUTPUTS WITH
OTHER CHANNEL ON
3.0V
0V
69571234 G06
Differential Output vs Frequency
Typical Distribution of Skew
100
2.5V
1.5V
SD
60
1.8
OUT1+ TO OUT2+ RISING EDGE
TYPICAL OF ALL OUTPUT EDGES/PAIRS
1.6
2 LOTS, 400
UNITS EACH,
3 TEMPERATURES
= 125°C
= 25°C
= –55°C
40
20
69571234 G07
20ns/DIV
MULTIPLE EXPOSURES, PERSISTENCE MODE
CLOCK I/O = 120MHz
SD DRIVE ~ 140kHz, ASYNCHRONOUS
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G05
69571234 G04
2.0V
46
–55 –35 –15
DIFFERENTIAL OUTPUT (VP-P)
1.35
–10
1.4
1.2
125°C
1.0
0.8
25°C
0.6
0.4
–55°C
0.2
0
–10 –8 –6 –4 –2 0 2
tSKEW (ps)
4
6
8
10
69571234 G08
PRODUCTION DATA,
1ps RESOLUTION, ~1-2ps UNCERTAINTY
0
0dBm INPUT
0
250 500 750 1000 1250 1500 1750 2000
FREQUENCY (MHz)
69571234 G09
6957f
10
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical Performance Characteristics
Additive Phase Noise
vs Input Frequency
300MHz
153.6MHz
–155
–160
–140
–10dBm, FILTA = L, FILTB = H
–145
0dBm, FILTA = H, FILTB = L
–150
–155
–165
100
1M
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 G10
PHASE NOISE (dBc/Hz)
–150
3.45V
3.3V
–160
–145
0dBm, FILTA = H, FILTB = L
–150
–155
7dBm, FILTA = FILTB = L
–165
1k
10k
100k
100
OFFSET FREQUENCY (Hz)
1M
0.550
3.5
FILTA = FILTB = H
69571234 G16
tPD (ns)
tPD (ns)
125°C
0.56
V+ = 3.0V, 50Ω LOADS TO 1.3V
0.54
V+ = 3.3V, 50Ω LOADS TO 1.3V
0.450
–55 –35 –15
50Ω LOADS TO V+ –2V
0.52
0.50
50Ω LOADS TO FIXED 1.3V
0.475
5 25 45 65 85 105 125
TEMPERATURE (°C)
25°C
–3
tPD vs Supply Voltage and
Termination Voltage
0.500
FILTA = H, FILTB = L
0
–55 –35 –15
–1
–2
tPD vs Temperature
0.525
FILTA = FILTB = L
–55°C
0
69571234 G15
V+ = 3.6V, 50Ω LOADS TO 1.9V
3.0
0.5
2
1
69571234 G14
tPD vs Temperature
1.0
3
–4
EACH CURVE NORMALIZED TO 0° AT 0dBm
–5
–10 –8 –6 –4 –2 0 2 4 6 8 10
INPUT AMPLITUDE (dBm)
1M
69571234 G13
FILTA = L, FILTB = H
fIN = 300MHz
V+ = 3.3V
4
–140
1M
AM to PM Conversion
5
–160
3.15V
1k
10k
100k
OFFSET FREQUENCY (Hz)
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 G12
tPD (ns)
PHASE NOISE (dBc/Hz)
1M
SINGLE-ENDED SINE WAVE INPUT
–145
125°C
–55°C
–165
100
–135
–140
25°C
–155
–130
SINGLE-ENDED SINE WAVE INPUT,
100MHz at 7dBm (500mVRMS)
FILTA = FILTB = L
–165
100
–150
Additive Phase Noise at 122.88MHz
–130
–155
–145
69571234 G11
Additive Phase Noise
vs Supply Voltage
–135
–140
–160
+10dBm, FILTA = FILTB = L
1k
10k
100k
OFFSET FREQUENCY (Hz)
SINGLE-ENDED SINE WAVE INPUT,
100MHz at 7dBm (500mVRMS)
FILTA = FILTB = L
–135
–160
100MHz
–165
100
–130
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
PHASE NOISE (dBc/Hz)
–145
–150
–135
PHASE NOISE (dBc/Hz)
–140
Additive Phase Noise
vs Temperature
–130
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mVRMS)
FILTA = FILTB = L
–135
PHASE NOISE (dBc/Hz)
Additive Phase Noise
vs Amplitude
NORMALIZED PHASE (DEG)
–130
LTC6957-1
0.48
FILTA = FILTB = L
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G17
0.46
FILTA = FILTB = L
3
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
3.5
3.6
69571234 G18
6957f
For more information www.linear.com/LTC6957-1
11
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical Performance Characteristics
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
V+ = 3.45V
40
V+ = 3.3V
2.05
2.00
V+ = 3.15V
40.5
35
SUPPLY CURRENT (mA)
30
TA = 125°C
25
20
TA = 25°C
15
TA = –55°C
10
1.95
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
DC DATA,
IN+ > (IN– + 50mV)
VOH, VOL AND VOS (V)
1.0
0
50
410
1.2
VOD (CALCULATED)
400
250
1.0
–55 –35 –15
1.0V
1.5V
3.0V
0V
SD
OUT–
1.1
380
5 25 45 65 85 105 125
TEMPERATURE (°C)
1
ENABLE: OUTPUTS WITH
OTHER CHANNEL ON
69571234 G25
20ns/DIV
MULTIPLE EXPOSURES, PERSISTENCE MODE
CLOCK I/O = 120MHz
SD DRIVE ~ 140kHz, ASYNCHRONOUS
LOAD STRESS PER TIA/EIA-644-A FIGURE 4
0.6
1.2
1.8
VTEST LOAD VOLTAGE (V)
0
69571234 G23
3.95
2.4
69571234 G24
Differential Output vs Frequency
4.00
2.0V
1.0V
1.2
Output Short-Circuit Current
vs Temperature
WAKE-UP:
OUTPUTS WITH
OTHER
CHANNEL OFF
125°C
25°C
–55°C
OUT+
1.3
390
69571234 G22
SHORT-CIRCUIT CURRENT (mA)
1.5V
1.4
VOS (CALCULATED)
Enable and Wakeup
2.0V
420
VOL (MEASURED)
150
100
200
LOAD RESISTOR (Ω)
USE OF RLOAD > 150Ω
NOT RECOMMENDED
fIN MAY BE COMPROMISED
1.5
1.3
1.1
V+ = 3.6V
V+ = 3.3V
V+ = 3V
Output Voltages vs Loading
430
900
V+ = 3.3V
3.90
V+ = 3.15V
3.85
3.80
3.75
–55 –35 –15
–55°C
800
V+ = 3.45V
DIFFERENTIAL OUTPUT (mVP-P)
OUTPUT VOLTAGE (V)
OUT –
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G21
VOD (mV)
1.2
0.8
VOH (MEASURED)
1.4
1.4
V+ = 3.15V
38.5
Output Voltages vs Temperature
1.5
OUT +
39.0
69571234 G20
Output Voltages vs Load Resistor
1.6
39.5
37.5
–55 –35 –15
0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6
SUPPLY VOLTAGE (V)
69571234 G19
1.8
V+ = 3.3V
38.0
5
1.90
–55 –35 –15
V+ = 3.45V
40.0
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
2.15
2.10
Supply Current vs Temperature
41.0
45
SUPPLY CURRENT (mA)
2.20
LTC6957-2
ANY ONE (1) OUTPUT
SHORTED TO GROUND
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G26
700
25°C
600
500
125°C
400
300
200
10dBm INPUT
FILTA = FILTB = L
RLOAD = 100Ω
100
0
0
200
400
600
800
FREQUENCY (MHz)
1000
1200
69571234 G27
6957f
12
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical Performance Characteristics
–140
–145
153.6MHz
–150
300MHz
–155
–160
–135
PHASE NOISE (dBc/Hz)
–135
PHASE NOISE (dBc/Hz)
–130
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mVRMS)
FILTA = FILTB = L
–165
100
–10dBm, FILTA = L, FILTB = H
–145
0dBm, FILTA = H, FILTB = L
–150
1k
10k
100k
OFFSET FREQUENCY (Hz)
–155
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
3.45V
–150
3.3V
–155
3.15V
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
1k
10k
100k
OFFSET FREQUENCY (Hz)
AM to PM Conversion
5
–145
–150
0dBm, FILTA = H, FILTB = L
–155
3
2
1
–55°C
0
–1 25°C
–2
–3
125°C
–4
7dBm, FILTA = FILTB = L
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 G31
fIN = 300MHz
V+ = 3.3V
4
–140
EACH CURVE NORMALIZED TO 0° AT 0dBm
–5
–10 –8 –6 –4 –2 0 2 4 6
INPUT AMPLITUDE (dBm)
1M
69571234 G32
tPD vs Temperature
0.96
0.950
FILTA = FILTB = H
V+ = 3.0V
10
tPD vs Supply Voltage
125°C
0.94
0.925
3.0
8
69571234 G33
tPD vs Temperature
4.0
1M
69571234 G30
SINGLE-ENDED SINE WAVE INPUT
–165
100
1M
125°C
–55°C
–165
100
–160
–160
1k
10k
100k
OFFSET FREQUENCY (Hz)
25°C
–155
–135
–140
–165
100
–150
Additive Phase Noise at 122.88MHz
–130
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 7dBm (500mVRMS)
FILTA = FILTB = L
–145
–145
69571234 G29
Additive Phase Noise
vs Supply Voltage
–135
–140
10dBm, FILTA = FILTB = L
69571234 G28
–130
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 7dBm (500mVRMS)
FILTA = FILTB = L
–160
–165
100
1M
Additive Phase Noise
vs Temperature
–135
–140
–160
100MHz
–130
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
NORMALIZED PHASE (DEG)
–130
Additive Phase Noise
vs Amplitude
PHASE NOISE (dBc/Hz)
Additive Phase Noise
vs Input Frequency
LTC6957-2
FILTA = FILTB = L
100Ω LOAD
1.0
FILTA = L, FILTB = H
V+ = 3.6V
tPD (ns)
1.5
tPD (ns)
tPD (ns)
0.92
0.900
V+ = 3.3V
0.875
0.88
FILTA = H, FILTB = L
0.850
FILTA = FILTB = L
0.5
–55 –35 –15
100Ω LOAD
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G34
0.825
–55 –35 –15
25°C
0.90
FILTA = FILTB = L
100Ω LOAD
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G35
0.86
0.84
–55°C
3
3.1
3.4
3.2
3.3
SUPPLY VOLTAGE (V)
3.5
3.6
69571234 G36
6957f
For more information www.linear.com/LTC6957-1
13
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical Performance Characteristics
Input Self Bias Voltage
vs Temperature
Supply Current vs Supply Voltage
V+ = 3.45V
V+ SUPPLY CURRENT (mA)
V+ = 3.3V
2.05
2.00
V+ = 3.15V
20
15
25°C
10
125°C
5
1.95
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
0.6
0
2.4
1.2
1.8
V+ VOLTAGE (V)
3
69571234 G37
V+ = 3.15V
20.0
0.25
0
5
10
15
LOAD CURRENT (mA)
125°C
VDD – 0.75
VDD = 3.3V
0.50
OUTPUT LOW,
SINKING CURRENT
0.25
0
20
125°C
–55°C
0
21
V DD SUPPLY CURRENT (mA)
125°C
0
0.6
25°C –55°C
2.4
1.2
1.8
VDD VOLTAGE (V)
3
3.6
69571234 G43
2.7V
–155
3.0V
3.3V
–165
100
20
1k
10k
100k
OFFSET FREQUENCY (Hz)
V+ = VDD = 3.3V
20
69571234 G42
3.0
100
10
DYNAMIC, ONE (1)
OUTPUT ACTIVE AT 312.5MHz,
13pF LOAD, LEFT AXIS
19 OTHER OUTPUT DISABLED
1
18
0.1
17
–55 –35 –15
1M
Output Voltage Swing
vs Frequency
STATIC, NO DC LOAD,
RIGHT (LOGARITHMIC)
AXIS
VDD SUPPLY CURRENT (µA)
1
2.4V
–150
Supply Current vs Temperature
5
2
–145
69571234 G41
Supply Current vs Supply Voltage
3
SINGLE-ENDED SINE WAVE INPUT,
at 7dBm (500mVRMS)
–135 100MHz
V+ = 3.3V, VDD AS SHOWN
FILTA = FILTB = L
–140
–160
25°C
5
10
15
LOAD CURRENT (mA)
69571234 G40
4
25°C
OUTPUT HIGH,
SOURCING CURRENT
VDD – 0.5
OUTPUT LOW,
SINKING CURRENT
0
–55°C
PHASE NOISE (dBc/Hz)
0.50
Additive Phase Noise
vs Supply Voltage
–130
VDD – 0.25
VDD = 3.6V
VDD = 3.3V
VDD = 3V
VDD = 2.7V
VDD = 2.4V
VDD – 0.75
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G39
VDD
OUTPUT HIGH,
SOURCING CURRENT
VDD – 0.5
19.5
–55 –35 –15
3.6
Output Voltages vs Load Current
Output Voltages vs Load Current
VDD – 0.25
OUTPUT VOLTAGE (V)
V+ = 3.3V
69571234 G38
OUTPUT VOLTAGE (V)
VDD
VDD CURRENT (mA)
20.5
–55°C
1.90
–55 –35 –15
0
V+ = 3.45V
21.0
0.01
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G44
OUTPUT SWING (VP-P)
INPUT VOLTAGE (V)
2.15
2.10
Supply Current vs Temperature
21.5
25
V + SUPPLY CURRENT (mA)
2.20
LTC6957-3/LTC6957-4
2.5
–55°C
25°C
125°C
2.0
1.5
1
10dBm INPUT
FILTA = FILTB = L
IN DC1766A
RLOAD = 133Ω AC-COUPLED
CAUTION: AT VERY
HIGH FREQUENCIES,
THE CMOS OUTPUTS
MAY NOT TOGGLE
AT ALL DEPENDING
ON INPUT FREQUENCY, AMPLITUDE,
SUPPLY VOLTAGE,
OR TEMPERATURE
0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
69571234 G45
6957f
14
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical Performance Characteristics
–140
300MHz
–145
153.6MHz
–150
–155
–135
PHASE NOISE (dBc/Hz)
–135
PHASE NOISE (dBc/Hz)
–130
SINGLE-ENDED SINE WAVE INPUT
AT 7dBm (500mVRMS)
FILTA = FILTB = L
100MHz
–10dBm, FILTA = L, FILTB = H
–145
0dBm, FILTA = H, FILTB = L
–150
–155
–165
100
–165
100
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 7dBm (500mVRMS)
V+ = VDD
FILTA = FILTB = L
3.15V
3.45V
–155
–160
10dBm, FILTA = FILTB = L
1k
10k
100k
OFFSET FREQUENCY (Hz)
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
–150
0dBm, FILTA = H, FILTB = L
–155
–165
100
1k
10k
100k
OFFSET FREQUENCY (Hz)
3.0
1M
RISING EDGE
tPD (ns)
tPD (ns)
tPD (ns)
69571234 G52
–55°C
–2
–3
0.75
–55 –35 –15
8
10
tPD vs Supply Voltage
V+ = 3.45V
1.02
1.00
V+ = VDD
0.98
FALLING EDGE
0.96
0.80
FALLING EDGE
0
–1
1.04
0.90
5 25 45 65 85 105 125
TEMPERATURE (°C)
1
1.06
0.95
0.85
0.5
–55 –35 –15
2
69571234 G51
1.00
FILTA = H, FILTB = L
3
EACH CURVE NORMALIZED TO 0° AT 0dBm
fIN = 300MHz
V+= VDD = 3.3V
25°C
–4
125°C
–5
–10 –8 –6 –4 –2 0 2 4 6
INPUT AMPLITUDE (dBm)
tPD vs Temperature
1.05
1M
AM to PM Conversion
1.10
1.0
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 G50
1.15
FILTA = L, FILTB = H
–55°C
69571234 G48
4
–145
tPD vs Temperature
FILTA = FILTB = L
125°C
5
–140
FILTA = FILTB = H
1.5
–155
SINGLE-ENDED SINE WAVE INPUT
69571234 G49
4.0
1M
7dBm, FILTA = FILTB = L
3.3V
25°C
–165
100
–160
–165
100
–150
–135
–145
–150
–145
Additive Phase Noise at 122.88MHz
–130
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–140
–140
69571234 G47
Additive Phase Noise
vs Supply Voltage
–135
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 7dBm (500mVRMS)
FILTA = FILTB = L
–160
69571234 G46
–130
–135
–140
–160
1M
–130
SINGLE-ENDED 100MHz SINE WAVE INPUT
SEE APPLICATIONS INFORMATION
–160
1k
10k
100k
OFFSET FREQUENCY (Hz)
Additive Phase Noise
vs Temperature
NORMALIZED PHASE (DEG)
–130
Additive Phase Noise
vs Amplitude
PHASE NOISE (dBc/Hz)
Additive Phase Noise
vs Input Frequency
LTC6957-3/LTC6957-4
FILTA = FILTB = L
5 25 45 65 85 105 125
TEMPERATURE (°C)
69571234 G53
RISING EDGE
0.94
2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6
VDD SUPPLY VOLTAGE (V)
69571234 G54
6957f
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15
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Pin Functions
FILTA, FILTB (Pin 1, Pin 6): Input Bandwidth Limiting
Control. These CMOS logic inputs control the bandwidth
of the early amplifier stages. For slow slewing signals
substantially lower phase noise is achieved by using this
feature. See the Applications Information section for more
details.
V+ (Pin 2): Supply Voltage (3.15V to 3.45V). This supply must be kept free from noise and ripple. It should be
bypassed directly to GND (Pin 5) with a 0.1µF capacitor.
IN+,
IN–
(Pin 3, Pin 4): Input Signal Pins. These inputs
are differential, but can also interface with single-ended
signals. The input can be a sine wave signal or a CML,
LVPECL, TTL or CMOS logic signal. See the Applications
Information section for more details.
GND (Pin 5): Ground. Connect to a low inductance ground
plane for best performance. The connection to the bypass
capacitor for V+ (Pin 2) should be through a direct, low
inductance path.
SD1, SD2 (Pin 12, Pin 7): Output Enable Control. These
CMOS logic inputs control the enabling and disabling of
their respective OUT1 and OUT2 outputs. When both outputs are disabled, the LTC6957 is placed in a low power
shutdown state.
LTC6957-1 Only
OUT1–, OUT1+ (Pin 10, Pin 11): LVPECL Outputs. Differential
logic outputs typically terminated by 50Ω connected to a
supply 2V below the V+ supply. Refer to the Applications
Information section for more details.
OUT2–, OUT2+ (Pin 9, Pin 8): LVPECL Outputs. Differential
logic outputs typically terminated by 50Ω connected to a
supply 2V below the V+ supply. Refer to the Applications
Information section for more details.
LTC6957-2 Only
OUT1–, OUT1+ (Pin 10, Pin 11): LVDS Outputs, Mostly
TIA/EIA-644-A Compliant. Refer to the Applications Information section for more details.
OUT2–, OUT2+ (Pin 9, Pin 8): LVDS Outputs, Mostly TIA/
EIA-644-A Compliant. Refer to the Applications Information
section for more details.
LTC6957-3/LTC6957-4 Only
OUT1, OUT2 (Pin 10, Pin 9): CMOS Outputs. Refer to the
Applications Information section for more details.
VDD (Pin 11): Output Supply Voltage (2.4V to 3.45V). For
best performance connect this to the same supply as V+
(Pin 2). If the output needs to be a lower logic rail, this
supply can be separately connected, but this voltage must
be less than or equal to that on Pin 2 for proper operation.
This supply must also be kept free from noise and ripple.
It should be bypassed directly to the GNDOUT pin (Pin 8)
with a 0.1µF capacitor.
GNDOUT (Pin 8): Output Logic Ground. Tie to a low
inductance ground plane for best performance. The connection to the bypass capacitor for VDD (Pin 11) should
be through a direct, low inductance path.
LTC6957-xDD Only
Exposed Pad (Pin 13): Always tie the underlying DFN
exposed pad to GND (Pin 5). To achieve the rated θJA of
the DD package, there should be good thermal contact
to the PCB.
6957f
16
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Block Diagrams
1
6
3
4
FILTA
2
12
V+
SD1
OUT1+
FILTB
OUT1–
IN+
11
10
IN–
OUT2–
OUT2+
5
GND
9
8
SD2
7
LTC6957-1 and LTC6957-2
1
6
3
4
FILTA
2
V+
12
SD1
FILTB
V DD
OUT1
11
10
IN+
IN–
OUT2
9
GNDOUT 8
5
GND
7
SD2
6957 BD
LTC6957-3 and LTC6957-4
6957f
For more information www.linear.com/LTC6957-1
17
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Timing Diagram
SD1
SD2
INPUT
OUT1+/OUT1
OUT1–
OUT2+/OUT2
OUT2–
tDISABLE
tSLEEP
tWAKEUP
tENABLE
DETAIL
INPUT
SEE APPLICATIONS INFORMATION FOR
LOGIC BEHAVIOR DURING SHUTDOWN
SPECIFIC TO LVPECL/LVDS/CMOS
tPD
50%
OUT1+/OUT1
OUT1–
50%
tMATCH
90%
OUT2+/OUT2
OUT2–
10%
tRISE
90%
6957 TD1
10%
tFALL
tSKEW
6957f
18
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
General Considerations
2
The LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 are
low noise, dual output clock buffers that are designed for
demanding, low phase noise applications. Properly applied,
they can preserve phase noise performance in situations
where alternative solutions would degrade the phase noise
significantly. They are also useful as logic converters.
However, no buffer device is capable of removing or
reducing phase noise present on an input signal. As with
most low phase noise circuits, improper application of
the LTC6957-1/LTC6957-2/LTC6957-3/LTC6957-4 can
result in an increase in the phase noise through a variety
of mechanisms. The information below will, hopefully,
allow a designer to avoid such an outcome.
The LTC6957 is designed to be used with high performance
clock signals destined for driving the encode inputs of
ADCs or mixer inputs. Such clocks should not be treated
as digital signals. The beauty of digital logic is that there
is noise margin both in the voltage and the timing, before
any deleterious effects are noticed. In contrast, high performance clock signals have no margin for error in the
timing before the system performance is degraded. Users are encouraged to keep this distinction in mind while
designing the entire clocking signal chain before, during,
and after the LTC6957.
Input Interfacing
The input stage is the same for all versions of the LTC6957
and is designed for low noise and ease of interfacing to
sine-wave and small amplitude signals. Other logic types
can interface directly, or with little effort since they present
a smaller challenge for noise preservation.
Figure 1 shows a simplified schematic of the LTC6957
input stage. The diodes are all for protection, both during
ESD events and to protect the low noise NPN devices from
being damaged by input overdrive.
The resistors are to bias the input stage at an optimal
DC level, but they are too large to leave floating without
increasing the noise. Therefore, for low noise use, always
connect both inputs to a low AC impedance. A capacitor
to ground/return is imperative on the unused input in
single-ended applications.
1
6
3
4
V+
FILTA
FILTERS
FILTB
+
1.8k
1.2k
IN
IN–
1.2k
2mA
3.2k
5
GND
6957 F01
Figure 1
Figure 2a shows how to interface single-ended LVPECL
logic to the LTC6957, while Figure 2b shows how to drive
the LTC6957 with differential LVPECL signals. The capacitors shown are 10nF and can be inexpensive ceramics,
preferably in small SMT cases. For use above 100MHz,
lower value capacitors may be desired to avoid series
resonance, which could increase the noise in Figure 2a
even though the capacitor is just on the DC input. This
comment applies to all capacitors hooked to the inputs
throughout this data sheet.
In Figure 2a, the RTERM implementation is up to the user
and is to terminate the transmission line. If it is connected
to a VTT that is passively generated and heavily bypassed
to ground, the 10nF to ground shown on the inverting
LTC6957 input is the appropriate connection to use.
However, if the termination goes to an actively generated
VTT voltage, lower noise may be achieved by connecting
the capacitor on the inverting input to that VTT rather than
ground.
In Figure 2b, both inputs to the LTC6957 are driven, increasing the differential input signal size and minimizing
noise from any common mode source such as VTT, both
of which improve the achievable phase noise.
A variety of termination techniques can be used, and
as long as the two sides use the same termination, the
configuration used won't matter much. In Figure 2b, the
6957f
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19
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
RTERMs are shown in a "Y" configuration that creates a passive VTT at the common point. Most 3.3V LVPECL devices
have differential outputs and can be terminated with three
50Ω resistors as shown.
Figure 3 shows a 50Ω RF signal source interface to the
LTC6957. For a pure tone (sine wave) input, Figure 3 can
handle up to 10dBm maximum. A broadband 50Ω match
as shown should suffice for most applications, though
for small amplitude input signals a narrow band reactive
matching network may offer incremental improvements
in performance.
3.3V
+
LTC6957
RTERM
–
10nF
6957 F02a
Figure 2a. Single-Ended LVPECL Input
Figure 4 shows the interface between current mode logic
(CML) signals and the LTC6957 inputs. The specifics of
terminating will be dependent on the particular CML driver
used; Figure 4 shows terminations only at the load end
of the line, but the same LTC6957 interface is appropriate for applications with the source end of the line also
terminated. In Figure 4a, a differential signal interface to
the LTC6957 is shown, which must be AC-coupled due to
the DC input levels required at the LTC6957.
Figure 4b shows a single-ended CML signal driving the
LTC6957. This is not commonly used because of noise and
immunity weaknesses compared to the differential CML
case. Because the signal is created by a current pulled
through the termination resistor, the signal is inherently
referenced to the supply voltage to which RTERM is tied. For
that reason, the other LTC6957 should be AC-referenced
to that supply voltage as shown.
The polarity change shown here is for graphic clarity
only, and can be reversed by swapping the LTC6957
input terminals.
3.3V
RTERM
RTERM
10nF
+
LTC6957
10nF
–
+
LTC6957
6957 F04a
–
6957 F02b
Figure 4a. Differential CML Input
3×
RTERM
Figure 2b. Differential LVPECL Input
10nF
+
Figure 2
RTERM
–
10nF
50Ω
6957 F04b
+
LTC6957
50Ω
–
SOURCE
LTC6957
10nF
10nF
6957 F03
Figure 4b. Single-Ended CML Input
Figure 4
Figure 3. Single-Ended 50Ω Input Source
6957f
20
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
Figure 5 shows the LTC6957 being driven by an LVDS
(EIA-644-A) signal pair. This is simply a matter of differentially terminating the pair and AC-coupling as shown
into the LTC6957 whose DC common mode voltage is
incompatible with the LVDS standard.
The choice of 110Ω versus 100Ω termination is arbitrary
(the EIA-644-A standard allows 90Ω to 132Ω) and should
be made to match the differential impedance of the trace
pair. The termination and AC-coupling elements should
be located as close as possible to the LTC6957.
If DC-coupling is desired, for example to control the
LTC6957 output phasing during times the LVDS input
clocks will be halted, a pair of 3k resistors can parallel the
two capacitors in Figure 5. An EIA/TIA-644-A compliant
driver can drive this load, which is less load stress than
specification 4.1.1. The differential voltage into the LTC6957
when clocked (>100kHz) will be full LVDS levels. When
the clocks stop, the DC differential voltage created by the
resistors and the 1.2k internal resistors (Figure 1) will
be 100mV, still sufficient to assure the desired LTC6957
output polarity. Choosing the smallest capacitors needed
for phase noise performance will minimize the settling
transients when the clocks restart.
Interfacing with CMOS Logic
The logic families discussed and illustrated to this point are
generally a better choice for routing and distributing low
phase-noise reference/clock signals than is CMOS logic.
All of the logic types shown so far are well suited for use
with low impedance terminations. Most of the time there
is a differential signal when using LVPECL or CML, and
LVDS always has a differential signal. Differential signals
provide lots of margin for error when it comes to picking up
noise and interference that can corrupt a reference clock.
CMOS on the other hand cannot drive 50Ω loads, is usually
routed single-ended, and by its nature is coupled to the
potentially noisy supply voltage half the time.
The LTC6957-3/LTC6957-4 provide CMOS outputs, so it
may seem surprising to read herein that CMOS is a poor
choice for low phase noise applications. However, these
devices should prove useful for designers that recognize
the challenges and limitations of using CMOS signals for
low phase noise applications. See the CMOS Outputs of
the LTC6957-3/LTC6957-4 section for further information.
The best method for driving the LTC6957 with CMOS
signals would be to provide differential drive, but if that
is not available, there are few ways to create a differential
CMOS signal without running the risk of corrupting the
skew or creating other problems. Therefore, single-ended
CMOS signals are the norm and care must be taken when
using this to drive the LTC6957.
The primary concern is that all routing should be terminated to minimize reflections. With CMOS logic there is
usually plenty of signal (more than the LTC6957 can handle
without attenuation) and the amplitude of the LTC6957
input signal will generally be of secondary importance
compared to avoiding the deleterious effects of signal
reflections. The primary concern about terminations is
that the input waveform presented to the LTC6957 should
have full speed slewing at the all important transitions.
If a rising edge is slowed by the destructive addition of
the ringing/settling of a prior edge reflection, or even the
start of the current edge, the phase noise performance will
suffer. This is true for all logic types, but is particularly
problematic when using CMOS because of the fast slew
rates and because it does not naturally lend itself to clean
terminations.
Point-to-point routing is best, and care should be taken to
avoid daisy-chain routing, because the terminated end may
be the only point along the line that sees clean transitions.
Earlier loads may even see a dwell in the transition region
which will greatly degrade phase noise performance.
10nF
+
110Ω
LTC6957
10nF
–
6957 F05
Figure 5. LVDS Input
6957f
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21
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
Figure 6 shows a suggested CMOS to LTC6957 interface.
The transmission line shown is the PCB trace and the
component values are for a characteristic impedance of
50Ω, though they could be scaled up or down for other
values of Z0. The R1/R2 divider at the CMOS output cuts
the Thevenin voltage in half when the ZOUT of the driver is
included. More importantly, it drives the transmission line
with a Thevenin driving resistance of 50Ω, matching the
Z0 of the line. On the other end of the line, a 50Ω load is
presented, minimizing reflections. This results in a second
2:1 attenuation in voltage, so the LTC6957 input will be
approximately 800mVP-P with 3V CMOS; 1.25VP-P with 5V
and 600mVP-P with 2.5V. All of these levels are less than
the maximum input swing of 2VP-P yet with clean edges
and fast slew rates should be able to realize the full phase
noise performance of the LTC6957.
CMOS
R1
75Ω
ROUT ≈ 25Ω
R2
100Ω
50Ω
LTC6957
–
6957 F06
Figure 6. CMOS Input
The various capacitors are for AC-coupling and should
have Z << 50Ω at the operating frequency. The capacitors
allow the LTC6957 to set its own DC input bias level, and
reduce the DC current drain, which at 12.4mA (for the
case of a driver powered from 3.3V) is significant. This
current drain can be reduced (with some potential for a
noise penalty) by increasing the attenuation at the R1/
R2 network, taking care to keep the Thevenin impedance
equal to the Z0 of the trace.
When using CMOS logic, it is important to consider how
all of the output drivers, in the same IC, are being used.
For best performance, the entire IC should be devoted to
driving the LTC6957, or if other gates in the same package must be put to use, they should only carry the same
timing signal (such as for fan-out) or be multiplexed in
time so that only one timing signal is being processed at
a time, such as for multiplexing selective shutdowns of
different segments of a system. Otherwise performance
is likely to suffer with spurs or other interference in the
22
Input Resistors
The LTC6957 input resistors, seen in Figure 1, are present
at all times, including during shutdown. Although they
constitute a large portion of the shutdown current, this
behavior prevents the shutdown and wake-up cycling of
the LTC6957 from “kicking back” into prior stages, which
could create large transients that could take a while to
settle. Particularly in the common case of AC-coupling
where the coupling cap charge is preserved.
Input Filtering
The LTC6957 includes input filtering with three narrowband
settings in addition to the full bandwidth limitation of the
circuit design.
Table 1
+
Z0 = 50Ω
phase noise spectrum related to the other signals processed in the driver.
FILTA
FILTB
BANDWIDTH
Low
Low
1200MHz (Full Bandwidth)
High
Low
500MHz (–3dB)
Low
High
160MHz (–3dB)
High
High
50MHz (–3dB)
For slow slewing signals (i.e., <100MHz sine wave signals)
substantially lower phase noise can be achieved by using
this feature. Bandwidth limiting is useful because it limits
the impact of all of the spectral energy that will alias down
to (on top of) the fundamental frequency.
The best filter setting to use for a given application will
depend on the clock frequency, amplitude, and waveform
shape, with the single biggest determinant being the slew
rate at the input of the LTC6957. Any amplifier noise will
add phase noise inversely proportional to its input slew
rate, just from the dV/dt changing voltage noise to time
base noise. But a fast slew rate may not be possible with
other design constraints, such as the use of sine waves
for EMI/RFI reasons, signal losses, etc. A limiting amplifier such as the LTC6957 should have enough bandwidth
to preserve the slew rate of the input. But any additional
bandwidth will provide no improvement in phase noise
due to slew rate preservation, while incurring a phase
noise penalty from noise aliasing.
For more information www.linear.com/LTC6957-1
6957f
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
Table 2 has the slew rate ranges most suitable for the four
different filter settings.
Table 2
FILTA
FILTB
INPUT SLEW RATE (V/µs)
Low
Low
>400
High
Low
125 to 400
Low
High
40 to 125
High
High
<40
With +10dBm at 100MHz, the input slew rate is 628V/µs
and Table 2 indicates the best filter setting to use is FILTA
= FILTB = L, which is seen to be the case in Figure 7a.
Another way to look at this is to consider the case of sine
waves, for which the frequency ranges will depend on
input amplitudes, as illustrated in Table 3.
Table 3
FREQUENCY RANGE
INPUT
AMPLITUDE
(dBm)
FILTA = L,
FILTB = L
(MHz)
FILTA = H,
FILTB = L
(MHz)
FILTA = L,
FILTB = H
(MHz)
FILTA = H,
FILTB = H
(MHz)
10
>63
20 to 63
6.3 to 20
<6.3
5
>112
35 to 112
11 to 35
<11
0
>200
63 to 200
20 to 63
<20
–5
>112
35 to 112
<35
–10
>200
63 to 200
<63
Figure 7 has LTC6957-1 100MHz additive phase noise
measurements that illustrate the trade-offs between filter
FILTA = FILTB = H
–150
–155
FILTA = L, FILTB = H
FILTA = H, FILTB = L
–160
–145
–150
The noise at the next filter setting is only slightly higher,
but for the maximum filtering case there is a full 10dB of
additional noise.
With 0dBm at 100MHz, the input slew rate is 198V/µs and
Table 2 indicates the best filter setting to use is FILTA = H,
FILTB = L. Again this is seen to be the case in Figure 7b.
As the input was decreased 10dB from Figure 7a to Figure 7b,
the blue trace rose 5dB while the green trace only rose 3dB.
With –10dBm at 100MHz, the input slew rate is 63V/µs and
Table 2 indicates the best filter setting to use is FILTA = L,
FILTB = H. Again this is seen to be the case in Figure 7c. As
the input was decreased 10dB from Figure 7a to Figure 7b,
and again to Figure 7c, the red trace rose just 3dB then
another 4dB, while the green and blue traces rose much
faster.
FILTA = FILTB = H
FILTA = L, FILTB = H
–155
–160
FILTA = FILTB = L
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
–165
100
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 F07a
(a)
1M
FILTA = FILTB = H
FILTA = FILTB = L
–145
–150
FILTA = H, FILTB = L
FILTA = L, FILTB = H
–155
–160
FILTA = H, FILTB = L
FILTA = FILTB = L
–165
100
–140
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 0dBm (632.5mVP-P)
LTC6957-1
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–145
–140
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT 10dBm (2VP-P)
LTC6957-1
PHASE NOISE (dBc/Hz)
–140
settings at various input slew rates. Each of the three
charts has all four filter settings, and one input amplitude;
Figure 7a has a +10dBm input, Figure 7b has a 0dBm input,
and Figure 7c has a –10dBm input. The four filter settings
are shown in the same colors throughout.
SINGLE-ENDED SINE WAVE INPUT,
100MHz AT –10dBm (200mVP-P)
LTC6957-1
–165
100
1k
10k
100k
OFFSET FREQUENCY (Hz)
69571234 F07c
69571234 F07b
(b)
1M
(c)
Figure 7. 100MHz Additive Phase Noise with Varying Input Amplitudes
6957f
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23
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LTC6957-3/LTC6957-4
Applications Information
Evidently, the input filtering will not significantly help with
large and fast slewing input signals to the LTC6957. As
seen in Figure 1, the input has a differential pair before the
filters, so the limiting will already have happened before
the filter. Fortunately, with large input signals, performance
is typically better than with smaller input signals because
phase noise is a signal-to-noise phenomenon.
Input Drive and Output Skew
All versions of the LTC6957 have very good output skew;
the specification limits consist almost entirely of test
margins. Even laboratory verification of the skew between
different outputs is a challenging exercise, given the need
to measure within ±1ps. With electromagnetic propagation
velocity in FR-4 being well known as 6" per nanosecond,
the skew of the LTC6957 will be impacted by PCB trace
routing length differences of just 6mils.
The LTC6957 tPD and tSKEW are specified for a 100mV
step with 50mV of overdrive. This is common for high
speed comparators, though it may not reflect the typical application usage of parts such as the LTC6957. The
propagation delay of the LTC6957 will increase with less
overdrive and decrease with more overdrive, as would
that of a high speed comparator. To a lesser extent, having the same overdrive but a larger signal (for instance a
differential input step of –200mV to 50mV) will increase
propagation delay, though this effect is smaller and can
usually be ignored.
A consequence of this behavior may be a perceived mismatch between the propagation delay for rising versus
falling edges when driven with an AC-coupled input whose
duty cycle is not exactly 50%. The LTC6957 inputs are
internally DC-coupled, and as shown in Figure 1, biasing
is provided at ~64% of the supply voltage. AC-coupled
input signals with a duty cycle of exactly 50% will see
symmetric levels of overdrive for the two signal directions.
If, for example, the input signal is a 100mVP-P square
wave with a duty-cycle of 48%, meaning it is high 48%
of the time and low 52% of the time, the DC average will
be 48mV above the low voltage level. This means the rising edge has 52mV of overdrive, and the falling edge has
48mV of overdrive.
As a result of this, the rising edge tPD will be faster than
the falling edge tPD. Fortunately, this will make the output
duty cycle closer to 50% than the input duty cycle. Figure 8
is from measurements on the LTC6957-2, with a 2V to
2.1V square wave on IN–, and with IN+ set to various
DC voltages between those two levels. The X-axis is the
overdrive level for the tPD+ data, and is 100mV minus
the overdrive level for the tPD– data, to illustrate the level
of tPD changes that can unexpectedly occur with ACcoupling. The lines are dashed where the measurement
uncertainty becomes large, when single digit millivolts
and picoseconds are being measured1. As can be seen,
the tPD+/ tPD– mismatch is very good at 50mV where the
two overdrive levels are the same.
1500
1400
1300
1200
tPD (ps)
One important observation to take away from Figures 7a
to 7c is that while the worst filter settings for a given set
of conditions should certainly be avoided, it doesn't matter
nearly as much if the optimal or next to optimal filter setting is used, because they are always fairly comparable in
terms of phase noise. So if a design will have an octave or
two range of amplitudes or frequencies, it is sufficient to
choose the filter setting whose range most closely matches
the application's range when using Tables 2 or 3 and the
noise penalty will not be severe anywhere in the range.
1100
tPD+
tPD–
1000
900
800
700
IN+ OFFSETTED ±50mVDC
IN– DRIVEN 100mVP-P
FILTA = FILTB = L
600
500
0
10 20 30 40 50 60 70 80 90 100
OVERDRIVE (mV)
6957 F08
Figure 8. LTC6957-2 Propagation Delay vs Overdrive
1 Below 2mV to 3mV, the input offset and the small input hysteresis play a role too. Fortunately,
neither is large enough to be a concern in normal operation.
6957f
24
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
This data is shown for the LTC6957-2, but the effect is
due to the input stage that is common to all versions, so
any other version will have the same general behavior.
The LTC6957-3 and LTC6957-4 CMOS outputs may have
additional tPD+ vs tPD– discrepancies due to differences
between the NMOS and PMOS output devices, particularly
when driving heavy loads. These are independent of input
overdrive, but can change with supply voltage and temperature, and can vary part to part. The complementary
outputs of the LTC6957-4 will therefore be higher skew
than the like edges of the LTC6957-3. Both the LTC6957-3
and LTC6957-4 will have large (120ps typ) tPD+ to tPD–
discrepancies compared to LVPECL or LVDS outputs.
LVPECL Outputs of the LTC6957-1
Figure 9 shows a simplified schematic of the LTC6957-1
LVPECL output stage. As with most ECL outputs, there are
no internal pull-down devices so the user must provide
both termination and biasing external to the device. Note
V+
that only the current source is cut off during shutdown.
The bases of the output NPNs are still tied to the pull-up
resistors, so both outputs will be pulled high in shutdown,
and it is the user’s responsibility to disconnect the external
loading if power reduction is to be realized.
The simplest way to terminate and bias the LTC6957-1
outputs is to route the differential output to the differential receiver and terminate the lines at that point with the
three resistor network shown in Figure 9. The differential
termination will be 100Ω, while the common mode termination will be 75Ω which could result in additional common
mode susceptibility. A bypass capacitor on the midpoint
of the Y can be used to improve this.
If the common mode termination impedance is not an
issue, the three resistor Y configuration can be changed
to a three resistor delta configuration, which is a simpler
layout in most cases.
V+
24Ω
V+
5Ω
V+
24Ω
V+
PCB ROUTING TRACES
Z0 = 50Ω
50Ω
50Ω
+
50Ω
–
5Ω
6957 F09
LTC6957-1
Figure 9. LTC6957-1 LVPECL Outputs
6957f
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25
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
During transitions to and from shutdown, the LTC6957-1
outputs are not guaranteed to comply with the specified
output levels for any length of time after the rising edge
of SD1/SD2, nor for any time before sufficient tWAKEUP /
t ENABLE subsequent to the falling edge of SD1/SD2. The
output common mode and differential voltage could have
a slow settling time compared to the signal frequency, and
a long string of runt pulses could be seen. The LTC6957-1
shutdown capability should be used as a slow on/off
control, not a logic gating/enable control.
Power Supplies for LVPECL Operation
The LTC6957-1 can operate from 3.15V to 3.45V total
supply voltage difference, irrespective of the absolute
level of those voltages. The convention in LVPECL is that
the negative supply is ground, while in ECL the positive
supply may be ground or 2.0V. The LTC6957-1 can work
in all of these situations provided the total supply voltage
difference is within the 3.15V to 3.45V range. No special
supply sequencing will be needed. With a 2V rail the output terminations go to ground, while, with the positive
supply grounded, the outputs can tolerate short circuits
to ground. However, the four CMOS logic input signals
will need to be driven with respect to whatever absolute
levels of supply voltages are used. If FILTA, FILTB, SD1,
and SD2 are fixed, they can be tied to the appropriate rail
and this is not a problem. Interface logic levels could get
tricky if they need to be programmed in-system.
In any voltage configuration, be aware that the LVPECL
output stage depends on the external load to complete its
biasing and, as such, is susceptible to phase modulation
as the supply voltage changes. The LTC6957-1 is generally less sensitive to variations in the supply voltage if the
termination voltage tracks the supply rather than ground.
With all four outputs terminated or otherwise driving heavy
loads, the LTC6957-1 power consumption and temperature
rise may be an issue.
Fortunately, the data sheet specification for supply current with output loads does not need to be multiplied
by the entire supply voltage to calculate on-chip power
dissipation because most of that current flows through
the loads which will dissipate a significant portion of the
total system power.
Typically, the internal power consumption will be (20mA •
3.3V = ) 66mW, while the on-chip power dissipation from
the output loading will be less than half that number. With a
total power dissipation on-chip of 90mW, the temperature
rise in the MS-12 package will be 13°C given the θJA of that
package. For use to 125°C ambient (H-grade) designers
should be sure to check the temperature rise using their
specific output loading and supply levels. The Absolute
Maximum rating for Junction Temperature is 150°C, and
must be avoided to prevent damaging the device, and as
stated in Note 1: "Exposure to any Absolute Maximum
Rating condition for extended periods of time may affect
device reliability and lifetime."
6957f
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
LVDS Outputs of the LTC6957-2
Figure 10 shows a simplified schematic of the LTC6957-2
LVDS output stage. The TIA/EIA-644-A standard specifies
the generator electrical requirements for this type of interface, and the LTC6957-2 has been verified against that
standard using the following test methods:
SPECIFICATION
LEVEL OF TESTING
4.1.1
100% Production Tested
4.1.2
100% Production Tested
4.1.3
100% Production Tested
4.1.4
100% Production Tested*
4.1.5
Lab Verification of Design Only
6a
100% Production Tested
6b
100% Production Tested
6c
100% Production Tested
rising edge of SD1/SD2, nor for any time before sufficient
tWAKEUP /tENABLE subsequent to the falling edge of SD1/
SD2. The output common mode voltage (VOS in 644-A
parlance) could have a slow settling time compared to the
signal frequency, and a long string of runt pulses could
be seen. The LTC6957-2 shutdown capability should be
used as a slow, power-saving on/off control, not a logic
gating/enable control.
Power Supplies for LVDS Operation
The LTC6957-2 has a single supply that should be within
the 3.15V to 3.45V range.
*The tRISE/tFALL of the LTC6957-2 are not compliant with the standard so
as to preserve full phase noise performance. To slow the edge rates, add
differential capacitance across the outputs. 2.7pF is sufficient to meet the
standard.
The TIA/EIA-644-A standard does not cover driver characteristics during shutdown nor the transitions to and from
shutdown. The LTC6957-2 outputs are not guaranteed to
comply with the standard for any length of time after the
The LTC6957-2 power supply voltage can corrupt the
spectral purity of the clock signal, though to a lesser
degree than with any of the other options. See the Typical
Performance Characteristic chart tPD vs Supply Voltage.
When using both LVDS channels, the LTC6957-2 power
consumption can exceed 120mW, which results in a
junction-to-ambient rise of 17.4°C in the MS-12 package,
more when operated at 3.45V. Again, it is up to the user
to always avoid junction temperatures above the Absolute
Maximum rating, and to stay comfortably below it for any
extended periods of time.
LTC6957-2
3.7mA
V+
650Ω
V+
PCB ROUTING TRACES
Z0 = 50Ω TO 60Ω
+
110Ω
–
650Ω
6957 F10
1.25V
Figure 10. LTC6957-2 LVDS Outputs
6957f
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
CMOS Outputs of the LTC6957-3/LTC6957-4
Figure 11 shows a simplified schematic of the LTC6957-3/
LTC6957-4 CMOS output stage. The LTC6957-3 outputs
are driven synchronously in-phase, while the LTC6957-4
outputs are driven differentially out-of-phase.
Although the LTC6957-3/LTC6957-4 are specified for a
resistive load, the outputs can drive capacitive loads as
well. With more than a few picoFarads of load, the rise
and fall times will be degraded in direct proportion to the
load capacitance.
During shutdown, the LTC6957-3 outputs will both be
set to a logic low.
During shutdown, the LTC6957-4 OUT1 will be set to a
logic low, while OUT2 will be set to a logic high.
During transitions to and from shutdown, the LTC6967-3/
LTC6957-4 outputs may not comply with the specified
output levels for any length of time after the rising edge
of SD1/SD2, nor for any time before sufficient tWAKEUP/
tENABLE subsequent to the falling edge of SD1/SD2. The
LTC6957-3/LTC6957-4
VDD
OUT1
OUT2
GNDOUT
6957 F11
Figure 11. LTC6957-3/LTC6957-4 CMOS Outputs
outputs may have one or two errant transitions resulting
in runt pulses being seen. The LTC6957-3/LTC6957-4
shutdown capability should be used as a slow, powersaving on/off control, not a logic gating/enable control, and
because they can not be put in a high impedance (3-state)
condition, the shutdown functionality is not usable as a
way to multiplex multiple outputs or devices.
Power Supplies for CMOS Operation
The LTC6957-3/LTC6957-4 operate with V+ from 3.15V
to 3.45V only. If the LTC6957-3/LTC6957-4 are used to
drive CMOS logic at a lower voltage rail, the output stage
can be powered (Pin 11) by a lower voltage, down to
2.4VMIN. Note that significant degradation of the spectral
purity could occur if the output supply, VDD, is not clean,
either because of additional broadband noise or discrete
spectral tones. The nature of a CMOS logic gate forms an
AM modulator of low frequency disturbances on the power/
ground that modulate the signal propagating through the
CMOS gate. Numerous common phenomena can serve
to convert the AM to PM/FM and, even if the conversion
efficiency is low, corrupt the phase noise to unacceptable
levels in demanding applications.
If two separate supplies are used, the only supply sequencing issue to be aware of is that if the VDD comes up first,
the OUT1/OUT2 CMOS outputs will be high impedance
until V+ > ~1V. Note that the four CMOS control inputs are
all referenced to V+, not the output supply. Also note that
during operation the output supply should be equal to or
less than V+. The LTC6957-3/LTC6957-4 will function with
VDD several hundred millivolts above the V+ supply, but
depending on the load, this margin for error can largely
be consumed by transient load steps.
When driving capacitive loads at high frequencies, the
LTC6957-3/LTC6957-4 VDD power consumption can jump
considerably over the quiescent power taken from V+. The
Dynamic current specification is with no load and adds
directly to the current needed to repetitively charge and
discharge a capacitive load.
With 24mA drawn from V+ at 3.3V, and another 20mA
to 30mA drawn from VDD (easy to do with two outputs
active at 300MHz), the total power consumption can be
145mW to 178mW, resulting in a junction-to-ambient rise
6957f
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
of 21°C to 26°C in the MS-12 package. For use to 125°C
ambient (H-grade) designers should be sure to check the
temperature rise using their specific output frequency,
loading, and supply voltages. The Absolute Maximum
rating for Junction Temperature is 150°C, which must be
avoided to prevent damaging the device, and as stated
in Note 1: "Exposure to any Absolute Maximum Rating
condition for extended periods of time may affect device
reliability and lifetime."
Low Phase Noise Design Considerations
Phase noise is a frequency domain representation of the
random variation in phase of a periodic signal. It is characterized as the power at a given offset frequency relative
to the power of the fundamental frequency. Phase noise
is specified in dBc/Hz, decibels relative to the carrier in
a 1Hz bandwidth. It is essentially a frequency dependent
signal-to-noise ratio.
Designing for low phase noise is challenging, even with a
solid understanding of phase noise. Any designer attempting such a task will find a good working understanding of
what phase noise is, and how it behaves, to be the most
important tool to achieve success. One of the most intuitive explanations is found in Chapter 3, “The Relationship
Between Phase Jitter and Noise Density,” of W.P. Robins’
1982 text, “Phase Noise in Signal Sources.”
With a solid base of understanding, the designer will now
see that the entire clocking chain is full of potential phase
modulators. The noise of an amplifier is usually thought
of as an additive term, but for phase noise the bias noise,
to the extent that the amplifier bandwidth is dependent on
the bias level, is not an additive term but a modulating
term. The LTC6957 is a monolithic clock limiting amplifier carefully designed so that users do not have to worry
about such details.
However, users of the LTC6957 still need to pay attention
to external considerations that can result in corruption of
the good phase noise performance available from all the
components used.
Timing jitter is a term used to describe the integration of
phase noise over a specified bandwidth which is presented
as a time domain specification.
Unfortunately, the term “low jitter” has become so overused that it is rendered virtually meaningless. High speed
communication links doing de-serialization and the like can
require jitter on the order of 30ps to 50ps. This is lower
jitter than required for a clock on a micro-controller, but for
high frequency sampling, even 1ps can severely impact the
dynamic range achievable. Therefore, it is best to ignore
the term “low jitter” and look for measured values of jitter,
and preferably phase noise. To analyze and measure true
low noise components, most instruments measure phase
noise (in dBc/Hz) rather than jitter.
A second consideration when designing for low phase
noise is that any clock signal is an analog signal and
should be thought of and routed as such. They should
not be run through large FPGAs with lots of activities at
multiple frequencies, they should not be routed through
PCB traces alongside digital data lines, and they should
not be routed through clock fan-out devices that have
features such as zero delay or programmable skew. The
specifics of the PCB traces and what surrounds them
should be analyzed as if the clock signals were among
your most sensitive analog signals, because in demanding
applications that is what your clock signals are. Note that
signal integrity software intended for analyzing crosstalk in
digital systems may only give yes or no answers and that
clocking performance can be compromised at levels 40dB
to 60dB below what is required to get that “yes” answer.
Common pitfalls with clock signals are the same as for
sensitive analog signals: routing near or alongside digital
traces of any kind, crossing digital traces on an adjacent
layer within a sandwich of ground planes, using digital
power planes as part of layer sandwiches, and assuming
all of these are sufficiently mitigated by using differential
clock signaling.
The way to address these issues is also the same as for
sensitive analog signals: routing away from digital traces
wherever possible; routing with shielding of ground,
either planes, adjacent traces, or both; making realistic
assumptions of common mode rejections (30dB to 40dB
at most); and keeping a critical eye out for unintended
couplers during the design and debug phases.
Even if the world’s cleanest reference clock were used
to feed the LTC6957, simply routing it through a poorly
6957f
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
designed system would result in compromised spectral
performance. This often catches designers by surprise
because the mechanisms above are typically additive and
linear, which result in filtering and additional spectral components, but don’t by themselves create phase modulation.
Unfortunately, any limiter, including the LTC6957, will,
through its nonlinear action, transform additive terms into
phase modulation. When a small tone is added to a large
pure tone, the larger tone will appear to have its amplitude
and phase modulated at a rate equal to the difference of
the two frequencies. Pass this through a limiter and only
the phase modulation remains.
AM to PM Conversion at the LTC6957 Inputs
The LTC6957 input stage has some AM to PM conversion,
but as seen in the Typical Performance Characteristics
section, even at 300MHz this is less than 0.5°/dB. One
source of AM to PM conversion at the LTC6957 input is
the optional lowpass filtering, because the upper sideband
and the lower sideband will be attenuated by slightly
different amounts. This difference is quite small for low
offset frequencies, but the difference grows both as the
frequency of the modulation increases, and as the carrier
frequency approaches the filter cutoff frequency where the
filter has a steeper roll-off.
In large complex systems, it may be impractical to eliminate
all potential corrupting of the clock signals. In such a case,
a narrow band filter placed at the inputs of the LTC6957
can remove the unwanted spectral components that are
far enough away from the fundamental.
Therefore, if small amounts of AM are known to be present
and an unacceptable level of PM is seen at the LTC6957
output, it may be helpful to change the input filter setting
to a higher cutoff frequency.
Close-in spectral anomalies will likely be impervious to
such filtering. Therefore, it is doubly important to keep an
eye out for modulating mechanisms. If the clock is routed
through CMOS logic gates, the power supply used for that
gate will AM modulate the signal at the very least. The
modulation could manifest itself as sideband tones if the
power supply has repetitive disturbances, common with
switching power supplies, or it could manifest itself as
random noise if the noise of a linear regulator is too high.
Cross Talk from Loading at the LTC6957 Outputs
Another source of corruption in large systems or laboratory measurements is the use of flexible cabling, which
can have a low level piezoelectric effect that modulates the
electrical length in response to mechanical vibration.
Rigid or semi-rigid cabling and PCB routing can be used
to eliminate this source of signal corruption.
Another mechanism to be aware of in the LTC6957 is
cross-modulation of the outputs. Except for the CMOS
LTC6957-3/LTC6957-4, there is minimal direct AM or
PM modulation of the outputs by the power supply. In
the CMOS case, the VDD power supply will directly AM
modulate the outputs, with a small amount of AM to PM
conversion.
The thing to be aware of here is that there can be loadinduced disturbances internal to the LTC6957 that can
modulate the other output. For instance, hooking up one
output to an ADC encode input and the second output to
the FPGA that performs the first DSP on the ADC outputs,
can result in considerable kickback of FPGA generated
signals into the LTC6957. If this cross-modulates over to
the other output, all kinds of deleterious effects may be
seen including tones, images, etc.
The CMOS LTC6957-3/LTC6957-4 are more susceptible to
this than the LVPECL and LVDS (LTC6957-1/LTC6957-2). To
prevent this, a buffer can be placed between the LTC6957
and the FPGA, even one that compromises the full jitter
performance considerably. Because it is the ADC that is
doing the sampling—the FPGA clock input has enough
margin for error to qualify as a digital signal.
6957f
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
50Ω TERMINATION
2V
MINI-CIRCUITS
ZHL-2010+
–1.3V
DUT
N5500A
REF
1
AGILENT 8644
122.88MHz
12.5dBm
MCL
LFCN
–150
MCL
LFCN
–150
MINI-CIRCUITS
ZFBT-6GW-FT
MINI-CIRCUITS
ZX10-2-12-5
2
6dB
ATTENUATOR
3dB
ATTENUATOR
MINI-CIRCUITS
ZHL-2010+
SIG
SPUR
INPUT
CAL TONE
MONITOR
10dB
ATTENUATOR
10dB
ATTENUATOR
COUPL
OUT
3dB
ATTENUATOR
COUPL
IN
MINI-CIRCUITS
ZFDC-20-5-5+
IN
OUT
MINI-CIRCUITS
ZFDC-20-5-5+
LINE STRETCHER
6957 F12
ARRA L9428A
Figure 12. Setup for LTC6957-1 Phase Noise Measurement Using Agilent E5505
Phase Noise Measurement
Additive (also called residual) phase noise can be particularly challenging to measure. Figure 12 shows a typical
laboratory set-up for testing the LTC6957-1 phase noise.
The LTC6957-1 has the lowest broadband phase noise of
the various dash numbers (equal to that of the LTC6957-3/
LTC6957-4) and the lowest close-in noise with a corner
frequency below 2kHz, so it presents the most challenging case.
The various components and their role will be discussed
as this will illustrate both the care that must be taken
to realize the full performance of the LTC6957, and the
demanding nature of making phase noise measurements.
The signal starts with a 122.88MHz CW tone from the
Agilent 8644 synthesizer at a fairly high power level of
12.5dBm. Two series LPFs at 150MHz cut out all the high
frequency noise components that would otherwise contribute noise because of the aliasing caused by the limiting
action of the LTC6957. A signal splitter then separates the
signal in two; one path will propagate through the DUT and
the other won’t, a common method used for measuring
residual phase noise.
In theory, all the phase noise in the signal source will be
rejected with the reading reflecting only the difference in
noise between the two paths. However, the rejection is
not perfect, particularly at very high offset frequencies
where the phase difference between the two paths progressively increases, thus the successive lowpass filters
on the signal source.
The Agilent 5505 measurement system uses the N5500A
front end, which includes a mixer to compare the signal and
reference phases. For amplifier noise, it is appropriate to
feed the DUT path to the signal input, but for clock buffers
that create fast clock edges, it is usually advantageous to
use the reference input, which seems to be sensitive only
to the edges and not noise throughout the period. This is a
reasonable thing to do because the LTC6957 is designed
to drive ADC encode inputs or mixer ports which have the
same qualitative properties.
Both the signal and reference inputs to the test set need to
be fairly large (15dBm to 20dBm) to realize the best noise
floor, so both signal paths include Mini-Circuits ZHL-2010+
low noise amplifiers to boost the signal. The LTC6957-1
was operated from 2V/–1.3V supplies so it could drive a
6957f
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31
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Applications Information
50Ω load to ground directly, but this creates a DC offset
(the signal is always positive) that the amplifier cannot
take, so a bias tee was included in the DUT signal path.
Only the 122.88MHz sine wave will be in the path without
the DUT, going to the N5500A signal port, until the first
coupler. This coupler allows a spur input to be injected,
while a second coupler allows the size of the spur, relative
to the carrier, to be measured. More on that in a minute.
The three attenuators in this signal path work with the
ZHL-2010+ to manage the dynamic range, while the attenuators on the coupling ports keep these terminals from
degrading the measured noise.
Finally, an ARRA L9428A line stretcher is used to adjust
for quadrature. One last attenuator helps with impedance
matching between the N5500A input and the line stretcher
output port. The E5505A can automatically adjust the signal
source phase/frequency for quadrature when measuring
VCOs or synthesizers, but for additive noise this adjustment
is manual because the adjustment must be made after the
signal is split into the two paths. The line stretcher has a
range of just 166ps, but with 122.88MHz, up to 20ns of
adjustment may be needed (1/4 cycle). Not shown is the
various short lengths of SMA cables and barrel couplers
that can also be added or subtracted to adjust the relative
phase of the two signal paths.
To calibrate E5505/N5500 measurements, the gain of the
mixer must be known. The surest way to measure it at
the actual frequencies being used is to inject a calibration
tone. For a 10kHz offset, a 122.89MHz low level (–10dBm)
signal is fed into the first coupler port. The requirements
for this signal are not demanding, so a general purpose
synthesizer that can be frequency locked, such as the
HP8657B, can be used.
The E5505 measures the amplitude of the resulting 10kHz
mixer output, but to put that in context (so that it can later
calculate results in dBc) it needs to know the size of the
injected spur relative to the carrier. Therefore, that relative
difference is measured using a spectrum analyzer connected to the attenuator on the second coupler.
Hopefully the above discussion conveys the meticulous
effort needed to measure additive phase noise of a single
device, at a single operating frequency. While the circuitry
in Figure 12 can be used to measure the entire spectrum
of phase noise (all offset frequencies) as well as the phase
noise at other clock frequencies, every clock frequency will
require manual adjusting for quadrature. The input LPFs
will either need to be changed to match the new clock
frequency, or possibly amplitudes at various places will
have to be adjusted to account for the frequency roll-off
therein.
6957f
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LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical Applications
Crystal Oscillator
5VIN+
LT1761-3.3V
OUT
BP
0.01µF
3.3V
10µF
1µF
TO ALL V+ POINTS
0.1µF
V+
2
50MHz +
V
BANDWIDTH
1
V+
6
SD1
VDD
FILTB
OUT1
0.1µF
11
10
IN+
3
30pF
12
V+
FILTA
IN–
4
OUT2
2k
GNDOUT
LTC6957-3
5
GND
7
450Ω
9
8
OUT TO 50Ω
0.3VP-P
SQUARE WAVE
SD2
100Ω
10MHz
AT CUT
150Ω
75pF
6957 TA02a
PHASE NOISE (dBc/Hz)
Total Phase Noise of 10MHz Crystal Oscillator
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
MEASURED ON AGILENT E5052A
10 CORRELATIONS
1Hz
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
1
10
–47.34dBc/Hz
–82dBc/Hz
–116.36dBc/Hz
–148.03dBc/Hz
–154.84dBc/Hz
–157.58dBc/Hz
–157.99dBc/Hz
100
1k
10k
OFFSET FREQUENCY (Hz)
100k
1M
6957 TA02b
6957f
For more information www.linear.com/LTC6957-1
33
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
DD12 Package
12-Lead (3mm × 3mm) Plastic DFN
(Reference LTC DWG # 05-08-1725 Rev A)
0.70 ±0.05
3.50 ±0.05
2.10 ±0.05
2.38 ±0.05
1.65 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.45 BSC
2.25 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 ±0.10
(4 SIDES)
R = 0.115
TYP
7
0.40 ± 0.10
12
2.38 ±0.10
1.65 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.25 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.75 ±0.05
6
1
0.23 ± 0.05
0.45 BSC
2.25 REF
0.00 – 0.05
(DD12) DFN 0106 REV A
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
6957f
34
For more information www.linear.com/LTC6957-1
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS Package
12-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1668 Rev Ø)
0.889 ±0.127
(.035 ±.005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.65
(.0256)
BSC
0.42 ±0.038
(.0165 ±.0015)
TYP
12 11 10 9 8 7
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
DETAIL “A”
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
0° – 6° TYP
0.406 ±0.076
(.016 ±.003)
REF
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
1 2 3 4 5 6
0.650
(.0256)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.1016 ±0.0508
(.004 ±.002)
MSOP (MS12) 1107 REV Ø
6957f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of itsinformation
circuits as described
herein will not infringe on existing patent rights.
For more
www.linear.com/LTC6957-1
35
LTC6957-1/LTC6957-2/
LTC6957-3/LTC6957-4
Typical Application
10MHz Frequency Reference Input Stage with Dual CMOS Outputs
Additive Phase Noise
vs Input Amplitude
3.3V
0.1µF
0.1µF
LTC6957-3
FILTA
0.1µF
10MHz
REF IN
–10dBm to
24dBm
COILCRAFT
WBC16-1T
•
R1
100Ω
HSMS-281C
0.1µF
•
0.1µF
R2
604k
1
FILTB
R1
100Ω
SD1OUT
V+
3
IN+
OUT1
4
IN–
OUT2
5
0.1µF
FILTA
2
6
GND
FILTB
VDD
GNDOUT
SD2
12
11
CMOS OUT1,
10MHz
10
9
CMOS OUT2,
10MHz
8
7
6957 TA03a
–140
PHASE NOISE AT 100kHz OFFSET (dBc/Hz)
3.3V
FILTA = L, FILTB = L
FILTA = H, FILTB = L
FILTA = L, FILTB = H
FILTA = H, FILTB = H
OPTIMUM FILT SETTINGS
–145
–150
–155
–160
–165
–170
–10 –8 –6 –4 –2 0 2 4 6 8
10MHz REFERENCE INPUT POWER
WITH REFERENCE TO 50Ω (dBm)
0.1µF
10
69571234 TA03b
100Ω
TO PHASE NOISE MEASUREMENT
100Ω
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LT1715
4ns, 150MHz Dual Comparator
General Purpose Comparator with Flexible Supply Voltages
LTC2209
16-Bit, 160Msps ADC
High Speed and High Resolution Requires Low Phase Noise Clocks
LTC5517
40MHz to 900MHz Quadrature Demodulator
24dBm IIP3 at 240MHz, 9dB NF, 4dB Conversion Gain
LTC5598
5MHz to 1600MHz Direct I/Q Modulator
27.7dBm OIP3 at 140MHz, –160dBm/Hz, –50.4dBc Image Rejection, –55dBm
Carrier Suppression
LTC6945
350MHz to 6GHz PLL Synthesizer
Integer-N PLL, –226dBc/Hz Normalized In-Band Phase Noise Floor
LTC6946-1
373MHz to 3.74GHz PLL + VCO
LTC6946-2
513MHz to 4.91GHz PLL + VCO
Integer-N PLL, –157dBc/Hz Wideband Output Phase Noise Floor, –226dBc/Hz
Normalized In-Band Phase Noise Floor, < –100dBc Spurious Output
LTC6946-3
640MHz to 5.79GHz PLL + VCO
6957f
36 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC6957-1
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com/LTC6957-1
LT 0313 • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2013