SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 D D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family TI-OPC Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels GTLP Buffered SYSCLK Signal (SSCLK) for Source-Synchronous Applications LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) LVTTL Outputs (–24 mA/24 mA) GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND Pins Minimize High-Speed Switching Noise Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DGG OR DGV PACKAGE (TOP VIEW) DIR OE A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLKOUT CKOE 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 FSTA BIAS VCC B1 GND B2 B3 VREF B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 CMS B16 B17 GND B18 SSCLK SYSCLK description/ordering information The SN74GTLPH16927 is a medium-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer. Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous and clock-synchronous applications. Source-synchronous applications require the skew between the clock output and data output to be minimized for optimum maximum-frequency system performance. In order to reduce this skew, a flexible setup-time adjustment (FSTA) feature is incorporated into the device that sets a predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the device. ORDERING INFORMATION PACKAGE† TA –40°C to 85°C ORDERABLE PART NUMBER TOP-SIDE MARKING TSSOP – DGG Tape and reel SN74GTLPH16927GR GTLPH16927 TVSOP – DGV Tape and reel SN74GTLPH16927VR GL927 VFBGA – GQL Tape and reel SN74GTLPH16927KR GL927 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC, TI-OPC, and Widebus are trademarks of Texas Instruments. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 description/ordering information (continued) The system clock (SYSCLK) and CLKOUT pins are LVTTL compatible, while the source-synchronous I/O is GTLP compatible. The benefits include compensation for output-to-output skew coming from the driver itself, and compensation for process skew if more than one driver is used. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 Ω. GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH16927 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 GQL PACKAGE (TOP VIEW) 1 2 3 4 5 terminal assignments 6 A B C D E F G 1 2 3 4 5 6 A A1 OE DIR FSTA BIAS VCC B1 B A3 A2 GND GND B2 B3 C A5 A4 B5 A7 A6 VREF GND B4 D VCC GND B6 B7 E A9 A8 B8 B9 F A10 A11 B11 B10 G A12 A13 GND GND B13 B12 H A14 A15 CMS B15 B14 GND B17 B16 SYSCLK SSCLK B18 H J A16 A17 VCC GND J K A18 CLKOUT CKOE K functional description The SN74GTLPH16927 is a medium-drive (50 mA), 18-bit bus transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent or latched modes and can replace any of the functions shown in Table 1. Data polarity is noninverting. Table 1. SN74GTLPH16927 Bus-Transceiver Replacement Functions 8 BIT 9 BIT 10 BIT 16 BIT 18 BIT Transceiver FUNCTION ’245, ’623, ’645 ’863 ’861 ’16245, ’16623 ’16863 Buffer/driver ’241, ’244, ’541 ’827 ’16241, ’16244, ’16541 ’16825 ’16543 ’16472 ’16373 ’16843 Latched transceiver Latch ’543 ’373, ’573 ’843 ’841 SN74GTLPH16927 bus transceiver replaces all above functions Additionally, the device allows for conversion of the system clock (SYSCLK) to GTLP signal levels (SSCLK) and LVTTL signal levels (CLKOUT). It also provides conversion of a GTLP source-synchronous clock to LVTTL signal levels (CLKOUT). The device allows for conversion of the LVTTL system clock (SYSCLK) to GTLP (SSCLK) and LVTTL (CLKOUT) signal levels when used as the transmitter and GTLP source-synchronous clock (SSCLK) to LVTTL (CLKOUT) signal levels when used as the receiver in source-synchronous applications. Source-synchronous operation removes time-of-flight restrictions and allows for increased data throughput. CMS is used to switch between system-synchronous mode and clock-synchronous mode. The clock output-enable (CKOE) input is used to switch between latched and transparent mode. Data flow in each direction is controlled by CKOE, clock (SYSCLK or SSCLK), DIR, and OE. OE controls the 18 bits of data. The CLKOUT/SSCLK buffered clock path for the A-to-B and B-to-A directions is controlled by CKOE. In the data-isolation mode (OE high, CKOE low), A data can be stored in one register and/or B data can be stored in the other register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 logic diagram (positive logic) OE DIR CMS CKOE 2 1 35 28 CLKOUT FSTA 27 56 30 SYSCLK SSCLK 29 MUX A1 3 One of Eighteen Channels 1D C1 54 CLK B1 1D C1 50 CLK To 17 Other Channels Pin numbers shown are for the DGG and DGV packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VREF SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 Function Tables A-TO-B DIRECTION INPUTS OUTPUTS CKOE OE CMS DIR SYSCLK A SSCLK CLKOUT B L L X L H or L X SYSCLK SYSCLK L L X L ↑ L SYSCLK SYSCLK B1 L L L X L ↑ H SYSCLK SYSCLK H L H X L X X SYSCLK SYSCLK Z H L X L X L Z Z L H L X L X H Z Z H H H X X X X Z Z Z L H H X ↑ X SYSCLK SYSCLK Z L H H X H or L X SYSCLK SYSCLK Z MODE Latched storage of A Clocked storage of A S Source synchronous Data isolation Transparent transmission of A Isolation Transmit SYSCLK B-TO-A DIRECTION INPUTS OUTPUTS CKOE OE CMS DIR SYSCLK SSCLK B SSCLK CLKOUT A L L L H X H or L X Input SSCLK L L L H X ↑ L Input SSCLK A1 L L L L H X ↑ H Input SSCLK H L H L H X X X Input SSCLK Z L L H H H or L Output X SYSCLK SYSCLK L L H H ↑ Output L SYSCLK SYSCLK A1 L L L H H ↑ Output H SYSCLK SYSCLK H L H H H X Output X SYSCLK SYSCLK Z H L X H X Output L Z Z L H L X H X Output H Z Z H H H X X X Output X Z Z Z L H L X X ↑ X Input SSCLK Z L H L X X H or L X Input SSCLK Z POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MODE Latched storage of B Clocked storage of B S Source synchronous Data isolation Latched storage of B Clocked storage of B Cl k Clock synchronous Data isolation Transparent transmission of B Isolation Receive SSCLK 5 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 recommended operating conditions (see Notes 4 through 7) VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High level input voltage High-level VIL Low level input voltage Low-level IIK IOH Input clamp current High-level output current IOL Low level output current Low-level ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 VCC VTT 5.5 B port and SSCLK Except B port and SSCLK B port and SSCLK Except B port, FSTA, and SSCLK VREF+0.05 2 B port and SSCLK V V V V VREF–0.05 0.8 V –18 mA A port and CLKOUT –24 mA A port and CLKOUT 24 B port and SSCLK 50 Except B port, FSTA, and SSCLK Outputs enabled 10 –40 ns/V µs/V 20 Operating free-air temperature mA 85 °C NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable but, generally, GND is connected first. 6. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. 7. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 electrical characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A portt and d CLKOUT A portt and d CLKOUT VOL B port and SSCLK TEST CONDITIONS MIN VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = –18 mA IOH = –100 µA VCC = 3 3.15 15 V IOH = –12 mA IOH = –24 mA TYP† MAX UNIT –1.2 V VCC–0.2 2.4 V 2 IOL = 100 µA IOL = 12 mA 0.2 0.5 VCC = 3.15 V to 3.45 V, IOL = 24 mA IOL = 100 µA 0.2 VCC = 3.15 V IOL = 10 mA IOL = 40 mA IOL = 50 mA 0.55 VCC = 3.15 V to 3.45 V, VCC = 3 3.15 15 V 0.4 0.2 V 0.4 SYSCLK and control inputs VCC = 3.45 V, VI = 0 to 5.5 V ±10 B port and SSCLK VCC = 3.45 V, VREF within 0.6 V of VTT, VO = 0 to 2.3 V ±10 CLKOUT VCC = 3.45 V, VO = 0 to 5.5 V ±10 IOZH‡ IOZL‡ A port VCC = 3.45 V, VO = VCC 10 µA A port VCC = 3.45 V, VO = GND –10 µA IBHL§ IBHH¶ A port VCC = 3.15 V, VCC = 3.15 V, VI = 0.8 V VI = 2 V IBHLO# IBHHO|| A port VCC = 3.45 V, VCC = 3.45 V, VI = 0 to VCC VI = 0 to VCC VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND, VI (B port) = VTT or GND Outputs high 50 Outputs low 50 Outputs disabled 50 II IOZ‡ ICC A port A port t B port, t or A port, SSCLK Ci Ciio SYSCLK inputs Control inputs A port B port or SSCLK µA 75 µA –75 µA 500 µA µA –500 VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND ∆ICCk µA 1.5 VI = 3.15 V or 0 VI = 3.15 V or 0 3.5 5 3.5 5.5 VO = 3.15 V or 0 VO = 1.5 V or 0 7.5 10 9 11 mA mA pF pF Co CLKOUT VO = 3.15 V or 0 6 7.5 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For I/O ports, the parameter II includes the off-state output leakage current. § The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. ¶ The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. k This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 hot-insertion specifications for A port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS MIN MAX UNIT 10 µA VO = 0.5 V to 3 V, VI or VO = 0 to 5.5 V OE = 0 ±30 µA VO = 0.5 V to 3 V, OE = 0 ±30 µA Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS µA ±30 µA BIAS VCC = 0, VO = 0.5 V to 1.5 V, OE = 0 ±30 µA 5 mA 10 µA IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V VO IO VCC = 0, UNIT BIAS VCC = 0, BIAS VCC = 0, VCC = 3.15 V to 3.45 V VCC = 0, MAX 10 VCC = 0, VCC = 0 to 1.5 V, ICC (BIAS VCC) MIN VI or VO = 0 to 1.5 V VO = 0.5 V to 1.5 V, OE = 0 Ioff IOZPU BIAS VCC = 3 3.15 15 V to 3 3.45 45 V V, VO (B port) = 0 to 1.5 15V BIAS VCC = 3.3 V, IO = 0 VO (B port) = 0.6 V BIAS VCC = 3.15 V to 3.45 V, 0.95 1.05 V µA –1 timing requirements over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted) MIN fclock tw tsu th Clock frequency Pulse duration Setup time Hold time POST OFFICE BOX 655303 CKOE high 2.8 SYSCLK or SSCLK high or low 3.3 A before SYSCLK↑ 1.2 B before SYSCLK↑ or SSCLK↑ 2.6 A before CKOE↓ 1.2 B before CKOE↓ 2.6 A after SYSCLK↑ 0.3 B after SYSCLK↑ or SSCLK↑ 0.8 A after CKOE↓ 1.1 B after CKOE↓ 0.3 • DALLAS, TEXAS 75265 MAX UNIT 175 MHz ns ns ns 9 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) MIN A B 175 fmax tPLH A B CKOE B SYSCLK B OE B tPHL tPLH tPHL tPLH tPHL ten tdis MAX UNIT MHz 3.1 6.5 3.1 6.5 3.6 7.1 3.6 7.1 3.7 7.3 3.7 7.3 3.3 7 3.3 7 ns ns ns ns tr Rise time, B and SSCLK outputs (20% to 80%) 2.2 ns tf Fall time, B and SSCLK outputs (80% to 20%) 1.5 ns tPLH tPHL B A tPLH tPHL CKOE A tPLH tPHL SYSCLK A tPLH tPHL SSCLK A tPLH tPHL SYSCLK CLKOUT tPLH tPHL SSCLK CLKOUT ten tdis OE A ten tdis CKOE CLKOUT † All typical values are at VCC = 3.3 V, TA = 25°C 10 TYP† POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 5.3 2 5.3 2.5 5.9 2.5 5.9 2.4 5.9 2.4 5.9 2.9 6.7 2.9 6.7 3.6 7.5 3.6 7.5 4 8.5 4 8.5 2.1 5.8 2.6 6.9 2.2 5.9 1.8 6 ns ns ns ns ns ns ns ns SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 skew characteristics over recommended ranges of supply voltage and operating free-air temperature, VREF = 1 V (unless otherwise noted); standard lumped loads, CL = 30 pF for B port (see Figure 1)† PARAMETER tsk(LH)‡ tsk(HL)‡ tsk(LH)‡ tsk(HL)‡ tsk(LH)‡ tsk(HL)‡ FROM (INPUT) TO (OUTPUT) SYSCLK B SYSCLK SSCLK → Bn (see Figure 2) SYSCLK SYSCLK SYSCLK TEST CONDITIONS FSTA tsk(prLH)§ tsk(prHL)§ SYSCLK SYSCLK MAX 0.5 SSCLK → Bn (see Figure 2) SSCLK → Bn (see Figure 2) SSCLK → Bn (see Figure 2) 0.5 GND GND VCC VCC VCC = 3.15 V, T = 85°C 3.4 4.7 VCC = 3.3 V, T = 25°C 3.2 4.5 VCC = 3.45 V, T = –40°C 3.1 4.4 VCC = 3.15 V, T = 85°C 3.2 4.6 VCC = 3.3 V, T = 25°C 2.8 4.1 VCC = 3.45 V, T = –40°C 2.4 3.7 VCC = 3.15 V, T = 85°C 7.1 8.9 VCC = 3.3 V, T = 25°C 6.6 8.4 VCC = 3.45 V, T = –40°C 6.3 8 VCC = 3.15 V, T = 85°C 7.2 9 VCC = 3.3 V, T = 25°C 6.5 8.2 6 7.6 VCC = 3.45 V, T = –40°C tsk(t)‡ MIN 1.3 B 1.8 B 2.8 UNIT ns ns ns ns ns ns ns † Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. ‡ tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature. The specifications apply to any outputs switching in the same direction, either high to low [tsk(HL)], low to high [tsk(LH)], or in opposite directions, both low to high and high to low [tsk(t)]. § tsk(prLH) or tsk(prHL) – Part-to-part skew is designed as the absolute value of the difference between the actual propagation delay for all outputs from device to device. The parameter is specified for a specific worst-case VCC and temperature. Furthermore, these values are provided by TI SPICE simulations. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω 25 Ω S1 Open 6V GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS tw 3V 3V 1.5 V Input 1.5 V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION tsu th VOH Data Input VM VM 0V 3V Input 1.5 V 1.5 V 0V tPLH tPHL VOLTAGE WAVEFORMS SETUP AND HOLD TIMES (VM = 1.5 V for A port and 1 V for B port) (VOH = 3 V for A port and 1.5 V for B port) VOH Output 1V 1V 3V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 1V 0V tPLH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH tPHL VOH Output 1.5 V tPZL 1.5 V Input Output Control 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) 1.5 V VOH VOH – 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. Load circuit for A outputs is also used for CLKOUT; load circuit for B outputs is also used for SSCLK. Figure 1. Load Circuits and Voltage Waveforms 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 1.5 V 25 Ω From Output Under Test Test Point CL = 30 pF (see Note A) LOAD CIRCUIT FOR B OUTPUTS A SYSCLK B1 through B18 tsk(LH) SYSCLK to B tsk(HL) SYSCLK to B SSCLK tsk(LH) min SYSCLK to SSCLK → Bn FSTA (Fast) tsk(HL) min SYSCLK to SSCLK → Bn FSTA (Fast) tsk(LH) max SYSCLK to SSCLK → Bn FSTA (Fast) tsk(HL) max SYSCLK to SSCLK → Bn FSTA (Fast) tsk(LH) min SYSCLK to SSCLK → Bn FSTA (Slow) tsk(HL) min SYSCLK to SSCLK → Bn FSTA (Slow) tsk(LH) max SYSCLK to SSCLK → Bn FSTA (Slow) tsk(HL) max SYSCLK to SSCLK → Bn FSTA (Slow) NOTES: A. B. C. D. CL includes probe and jig capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. The outputs are measured one at a time with one transition per measurement. Load circuit for B outputs also is used for SSCLK. Figure 2. Load Circuit and SYSCLK to SSCLK → Bn Skew Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN74GTLPH16927 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS SCES413 – OCTOBER 2002 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation is shown in Figure 3. This backplane, or distributed load, can be closely approximated to a resistor inductance capacitance (RLC) circuit, as shown in Figure 4. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer to better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 1.5 V ZO = 70 Ω .25” 2” 2” 1.5 V 38 Ω 38 Ω 1.5 V .25” 19 Ω Conn. 1” Conn. 1” Conn. 1” Conn. LL = 19 nH From Output Under Test 1” Test Point CL = 9 pF Rcvr Rcvr Rcvr Slot 2 Slot 19 Slot 20 Drvr Slot 1 Figure 4. Medium-Drive RLC Network Figure 3. Medium-Drive Test Backplane switching characteristics over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 4) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A B tPLH tPHL SYSCLK B 4.3 4.3 5 5 UNIT ns ns tr Rise time, B and SSCLK outputs (20% to 80%) 1.2 ns tf Fall time, B and SSCLK outputs (80% to 20%) 1.8 ns † All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI SPICE models. 14 TYP† POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74GTLPH16927DGG PREVIEW TSSOP DGG 56 35 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74GTLPH16927GR ACTIVE TSSOP DGG 56 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM SN74GTLPH16927KR ACTIVE VFBGA GQL 56 1000 None SNPB Level-1-240C-UNLIM SN74GTLPH16927VR ACTIVE TVSOP DGV 56 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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