Actel A40MX02-PQ208A 40mx and 42mx automotive fpga family Datasheet

v3.1
40MX and 42MX Automotive FPGA Families
Features
High Capacity
Ease of Integration
•
•
•
•
•
•
Single-Chip ASIC Alternative for Automotive
Applications
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
•
•
•
•
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
SRAM Modules
(64x4 or 32x8)
–
–
–
–
–
10
Dedicated Flip-Flops
–
–
348
624
954
1,230
Maximum Flip-Flops
147
273
516
928
1,410
1,822
Clocks
1
1
2
2
2
6
Maximum User I/Os
57
69
104
140
176
202
Boundary Scan Test (BST)
–
–
–
–
Yes
Yes
68
100
80
–
84
100
80
–
84
100, 160
100
176
–
208
100
176
–
160, 208
–
176
–
208, 240
–
–
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
Note: While the automotive-grade MX devices are offered in standard speed grade only, the MX family is also offered in commercial,
industrial and military temperature grades with -F, Std, -1, -2 and -3 speed grades. Refer to the 40MX and 42MX Family FPGAs
datasheet for more details.
May 2006
© 2006 Actel Corporation
i
See the Actel website (www.actel.com) for the latest version of this datasheet.
40MX and 42MX Automotive FPGA Families
Ordering Information
A42MX16 _
PQ
208
A
Application (Temperature Range)
A
= Automotive (–40 to +125˚C)
Package Lead Count
Package Type
PL =
Plastic Leaded Chip Carrier
PQ =
Plastic Quad Flat Pack
TQ =
Thin Quad Flat Pack (1.4 mm)
VQ =
Very Thin Quad Flat Pack (1.0 mm)
Speed Grade
(Blank for Standard)
Part Number
A40MX02
=
3,000 System Gates
A40MX04
=
6,000 System Gates
A42MX09
=
14,000 System Gates
A42MX16
=
24,000 System Gates
A42MX24
=
36,000 System Gates
A42MX36
=
54,000 System Gates
Note: Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded based
on characterization across the recommended operating conditions. A-grade parts are not tested at extended temperatures. If
testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel Sales office to
discuss testing options available.
Plastic Device Resources
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
PLCC
68-Pin
57
–
–
–
–
–
PLCC
84-Pin
–
69
72
–
–
–
PQFP
100-Pin
57
69
83
–
–
–
PQFP
160-Pin
–
–
101
–
125
–
User I/Os
PQFP
208-Pin
–
–
–
140
176
176
PQFP
240-Pin
–
–
–
–
–
202
VQFP
80-Pin
57
69
–
–
–
–
VQFP
100-Pin
–
–
83
83
–
–
TQFP
176-Pin
–
–
104
140
150
–
Note: Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack
Speed Grade and Temperature Grade Matrix
Std
A
✓
Note: Refer to the 40MX and 42MX Family FPGAs datasheet for details on
commercial-, industrial- and military-grade MX offerings.
Contact your local Actel representative for device availability.
ii
v3.1
40MX and 42MX Automotive FPGA Families
Table of Contents
40MX and 42MX Automotive FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Timing Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Dual-Port SRAM Timing Waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-25
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45
Package Pin Assignments
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
100-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
160-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
80-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
240-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
v3.1
iii
40MX and 42MX Automotive FPGA Families
40MX and 42MX Automotive FPGA Families
General Description
flops can be constructed from logic modules whenever
required in the application.
Actels' automotive-grade MX families provide a highperformance, single-chip solution for shortening the
system design and development cycle, offering a costeffective alternative to ASICs for in-cabin telematics and
automobile interconnect applications. The 40MX and
42MX devices are excellent choices for integrating logic
that is currently implemented in multiple PALs, CPLDs,
and FPGAs.
The 42MX devices contain three types of logic modules:
combinatorial (C-modules), sequential (S-modules) and
decode
(D-modules).
Figure 1-2
illustrates
the
combinatorial logic module. The S-module, shown in
Figure 1-3 on page 1-2, implements the same
combinatorial logic function as the C-module while
adding a sequential element. The sequential element can
be configured as either a D-flip-flop or a transparent
latch. The S-module register can be bypassed so that it
implements purely combinatorial logic.
The MX device architecture is based on Actel’s patented
antifuse technology implemented in a 0.45µm triplemetal CMOS process. With capacities ranging from 3,000
to 54,000 system gates, the MX devices are live on
power-up and have one-fifth the standby power
consumption of comparable FPGAs. Actel’s MX FPGAs
provide up to 202 user I/Os and are available in a wide
variety of packages and speed grades.
A42MX24 and A42MX36 devices contain D-modules,
which are arranged around the periphery of the device.
D-modules contain wide-decode circuitry, providing a
fast, wide-input AND function similar to that found in
CPLD architectures (Figure 1-4 on page 1-2). The Dmodule allows A42MX24 and A42MX36 devices to
perform wide-decode functions at speeds comparable to
CPLDs and PALs. The output of the D-module has a
programmable inverter for active HIGH or LOW
assertion. The D-module output is hardwired to an
output pin, and can also be fed back into the array to be
incorporated into other logic.
The automotive-grade 42MX24 and 42MX36 include
system-level features such as IEEE Standard 1149.1 (JTAG)
Boundary Scan Testing and fast wide-decode modules. In
addition, the A42MX36 device offers dual-port SRAM for
implementing fast FIFOs, LIFOs, and temporary data
storage. The storage elements can efficiently address
applications requiring wide datapath manipulation.
MX Architectural Overview
The MX devices are composed of fine-grained building
blocks that enable fast, efficient logic designs. All devices
within these families are composed of logic modules, I/O
modules, routing resources and clock networks, which
are the building blocks for fast logic designs. In addition,
the A42MX36 device contains embedded dual-port
SRAM modules, which are optimized for high-speed
datapath functions such as FIFOs, LIFOs and scratchpad
memory. A42MX24 and A42MX36 also contain widedecode modules.
Figure 1-1 • 40MX Logic Module
A0
B0
Logic Modules
S0
D00
The 40MX logic module is an eight-input, one-output
logic circuit designed to implement a wide range of logic
functions with efficient use of interconnect routing
resources (Figure 1-1).
D01
Y
D10
D11
The logic module can implement the four basic logic
functions (NAND, AND, OR and NOR) in gates of two,
three, or four inputs. The logic module can also
implement a variety of D-latches, exclusivity functions,
AND-ORs and OR-ANDs. No dedicated hardwired latches
or flip-flops are required in the array; latches and flip-
A1
B1
S1
Figure 1-2 • 42MX C-Module Implementation
v3.1
1-1
40MX and 42MX Automotive FPGA Families
D00
D01
D00
D01
Y
D10
D
S0
D11
S1
Q
OUT
Y
D10
D11
S1
CLR
S0
D
Q
OUT
GATE
Up to 7-Input Function Plus Latch
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D00
D0
D01
Y
D1
S
D
Q
OUT
Y
OUT
D10
D11
S1
GATE
CLR
S0
Up to 8-Input Function (Same as C-Module)
Up to 4-Input Function Plus Latch with Clear
Figure 1-3 • 42MX S-Module Implementation
7 Inputs
Hard-Wire to I/O
Programmable
Inverter
Feedback to Array
Figure 1-4 • A42MX24 and A42MX36 D-Module Implementation
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules,
which are arranged in 256-bit blocks and can be
configured as 32x8 or 64x4. SRAM modules can be
cascaded together to form memory spaces of userdefinable width and depth. A block diagram of the
A42MX36 dual-port SRAM block is shown in Figure 1-5
on page 1-3.
The A42MX36 SRAM modules are true dual-port
structures containing independent read and write ports.
Each SRAM module contains six bits of read and write
addressing (RDAD[5:0] and WRAD[5:0], respectively) for
64x4-bit blocks. When configured in byte mode, the
highest order address bits (RDAD5 and WRAD5) are not
used. The read and write ports of the SRAM block
1 -2
v3.1
contain independent clocks (RCLK and WCLK) with
programmable polarities offering active HIGH or LOW
implementation. The SRAM block contains eight data
inputs (WD[7:0]) and eight outputs (RD[7:0]), which are
connected to segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal
solution for high-speed buffered applications requiring
FIFO and LIFO queues. The ACTgen Macro Builder within
Actel's Designer software provides capability to quickly
design memory functions with the SRAM blocks.
40MX and 42MX Automotive FPGA Families
WD[7:0]
Latches
[7:0]
WRAD[5:0]
MODE
BLKEN
WEN
[5:0]
Write
Port
Logic
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
[5:0]
Read
Port
Logic
Read
Logic
Latches
RD[7:0]
Write
Logic
WCLK
Latches
RDAD[5:0]
REN
RCLK
Routing Tracks
Figure 1-5 • A42MX36 Dual-Port SRAM Block
Routing Structure
above and two below), except near the top and bottom
of the array, where edge effects occur. Long vertical
tracks contain either one or two segments. An example
of vertical routing tracks and segments is shown in
Figure 1-6.
The MX architecture uses vertical and horizontal routing
tracks to interconnect the various logic and I/O modules.
These routing tracks are metal interconnects that may be
continuous or split into segments. Varying segment
lengths allow the interconnect of over 90% of design
tracks to occur with only two antifuse connections.
Segments can be joined together at the ends using
antifuses to increase their lengths up to the full length of
the track. All interconnects can be accomplished with a
maximum of four antifuses.
Segmented
Horizontal
Routing
Horizontal Routing
Logic
Modules
Antifuses
Horizontal routing tracks span the whole row length or
are divided into multiple segments and are located in
between the rows of modules. Any segment that spans
more than one-third of the row length is considered a
long horizontal segment. A typical channel is shown in
Figure 1-6. Within horizontal routing, dedicated routing
tracks are used for global clock networks and for power
and ground tie-off tracks. Non-dedicated tracks are used
for signal nets.
Vertical Routing Tracks
Figure 1-6 • MX Routing Structure
Antifuse Structures
An antifuse is a "normally open" structure. The use of
antifuses to implement a programmable logic device
results in highly testable structures as well as efficient
programming algorithms. There are no pre-existing
connections; temporary connections can be made using
pass transistors. These temporary connections can isolate
individual antifuses to be programmed and individual
circuit structures to be tested, which can be done before
and after programming. For instance, all metal tracks can
be tested for continuity and shorts between adjacent
tracks, and the functionality of all logic modules can be
verified.
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks: input,
output, and long. Long tracks span the column length of
the module, and can be divided into multiple segments.
Each segment in an input track is dedicated to the input
of a particular module; each segment in an output track
is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two
v3.1
1-3
40MX and 42MX Automotive FPGA Families
Clock Networks
•
The 40MX devices have one global clock distribution
network (CLK). A signal can be put on the CLK network
by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout
clock distribution networks, referred to as CLKA and
CLKB. Each network has a clock module (CLKMOD) that
can select the source of the clock signal from any of the
following (Figure 1-7):
•
Externally from the CLKA pad, using CLKBUF
buffer
•
Externally from the CLKB pad, using CLKBUF
buffer
•
Internally from the CLKINTA input, using CLKINT
buffer
Internally from the CLKINTB input, using CLKINT
buffer
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can
also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control
resources, called quadrant clock networks (Figure 1-8).
Each quadrant clock provides a local, high-fanout
resource to the contiguous logic modules within its
quadrant of the device. Quadrant clock signals can
originate from specific I/O pins or from the internal array
and can be used as a secondary register clock, register
clear, or output enable.
CLKB
CLKINB
CLKA
From
Pads
CLKINA
CLKMOD
S0
S1
Internal
Signal
CLKO(17)
Clock
Drivers
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
Figure 1-7 • Clock Networks of 42MX Devices
QCLKA
QCLKB
QCLKC
Quad
Clock
Modul
QCLK3
QCLK1
Quad
Clock
Modul
*QCLK1IN
*QCLK3IN
S0 S1
Quad
Clock
Modul
S1 S0
QCLK2
QCLK4
Quad
Clock
Modul
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
1 -4
QCLKD
v3.1
40MX and 42MX Automotive FPGA Families
I/O Modules
there is the Security Fuse which, when programmed,
both disables the probing circuitry and prohibits further
programming of the device.
The I/O modules provide the interface between the
device pins and the logic array. Figure 1-9 is a block
diagram of the 42MX I/O module. A variety of user
functions, determined by a library macro selection, can
be implemented in the module. (Refer to the Antifuse
Macro Library Guide for more information.) All 42MX I/O
modules contain tristate buffers, with input and output
latches that can be configured for input, output, or
bidirectional operation.
Look for this symbol to ensure your valuable IP is secure.
™
u e
42MX devices contain flexible I/O structures, where each
output pin has a dedicated output-enable control
(Figure 1-9). The I/O module can be used to latch input or
output data, or both, providing fast setup time. In
addition, the Actel Designer software tools can build a Dtype flip-flop using a C-module combined with an I/O
module to register input and output signals. Refer to the
Antifuse Macro Library Guide for more details.
Figure 1-10 • Fuselock
For more information, refer to Actel's Implementation of
Security in Actel Antifuse FPGAs application note.
Programming
Device programming is supported through the Silicon
Sculptor series of programmers. Silicon Sculptor II is a
compact, robust, single-site and multi-site device
programmer for the PC. With standalone software,
Silicon Sculptor II is designed to allow concurrent
programming of multiple units from the same PC.
Actel's Designer software development tools provide a
design library of I/O macro functions that can implement
all I/O configurations supported by the MX FPGAs.
EN
Q
Silicon Sculptor II programs devices independently to
achieve the fastest programming times possible. After
being programmed, each fuse is verified to insure that it
has been programmed correctly. Furthermore, at the end
of programming, there are integrity tests that are run to
ensure no extra fuses have been programmed. Not only
does
it
test
fuses
(both
programmed
and
nonprogrammed), Silicon Sculptor II also allows self-test
to verify its own hardware extensively.
D
PAD
From Array
G/CLK*
To Array
Q
D
G/CLK*
The procedure for programming an MX device using
Silicon Sculptor II is as follows:
Note: *Can be configured as a Latch or D Flip-Flop (Using
C-Module)
1. Load the .AFM file
2. Select the device to be programmed
Figure 1-9 • 42MX I/O Module
3. Begin programming
When the design is ready to go to production, Actel
offers device volume-programming services either
through distribution partners or via In-House
Programming from the factory.
Other Architectural Features
User Security
For more details on programming MX devices, please
refer to the Programming Antifuse Devices and the
Silicon Sculptor II user's guides.
The Actel FuseLock provides robust security against
design theft. Special security fuses are hidden in the
fabric of the device and prevent unauthorized users from
accessing the programming and/or probe interfaces. It is
virtually impossible to identify or bypass these fuses
without damaging the device, making Actel antifuse
FPGAs immune to both invasive and noninvasive attacks.
Special security fuses in 40MX devices include the Probe
Fuse and Program Fuse. The former disables the probing
circuitry while the latter prohibits further programming
of all fuses, including the Probe Fuse. In 42MX devices,
v3.1
1-5
40MX and 42MX Automotive FPGA Families
Power Supply
Automotive MX devices are designed to operate in 5.0V environments. Table 1-1 describes the voltage settings of
automotive MX devices.
Table 1-1 • Voltage Support of Automotive-Grade MX Devices
Device
VCC
VCCA
VCCI
Maximum Input Tolerance
Nominal Output Voltage
40MX
5.0V
–
–
5.25V
5.0V
42MX
–
5.0V
5.0V
5.25V
5.0V
Power-Up/Down
When powering up MX devices, VCCA must be greater
than or equal to VCCI throughout the power-up
sequence. If VCCI exceeds VCCA during power-up, either
the input protection junction on the I/Os will be forwardbiased or the I/Os will be at logical High, and ICC rises to
high levels. During power-down, VCCA must be smaller
than or equal to VCCI.
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides builtin access to every node in a design, via the use of Silicon
Explorer II. Silicon Explorer II is an integrated hardware
and software solution that, in conjunction with the
Designer software, allow users to examine any of the
internal nodes of the device while it is operating in a
prototyping or a production system. The user can probe
an MX device without changing the placement and
routing of the design and without using any additional
resources. Silicon Explorer II's noninvasive method does
not alter timing or loading effects, thus shortening the
debug cycle and providing a true representation of the
device under actual functional situations.
Silicon Explorer II samples data at 100 MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard serial port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
1 -6
v3.1
Silicon Explorer II is used to control the MODE, DCLK, SDI
and SDO pins in MX devices to select the desired nets for
debugging. The user simply assigns the selected internal
nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is
activated when the MODE pin is held HIGH.
Figure 1-11 on page 1-7 illustrates the interconnection
between Silicon Explorer II and 40MX devices, while
Figure 1-12 on page 1-7 illustrates the interconnection
between Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must
not be programmed. (Refer to "User Security" section on
page 1-5 for the security fuses of 40MX and 42MX
devices). Table 1-2 on page 1-7 summarizes the possible
device configurations for probing.
PRA and PRB pins are dual-purpose pins. When the
"Reserve
Probe
Pin"
is
checked
in
the
Designer software, PRA and PRB pins are reserved as
dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and
"Reserve Probe Pin" is checked, the layout tool will
override the option and place user I/Os on PRA and PRB
pins.
40MX and 42MX Automotive FPGA Families
16 Logic Analyzer Channels
40MX
Serial Connection
to Windows PC
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRB
PRA
Figure 1-11 • Silicon Explorer II Setup with 40MX
16 Logic Analyzer Channels
42MX
Serial Connection
to Windows PC
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRB
PRA
Figure 1-12 • Silicon Explorer II Setup with 42MX
Table 1-2 • Device Configuration Options for Probe Capability
MODE
PRA, PRB1
SDI, SDO, DCLK1
No
LOW
User I/Os2
User I/Os2
No
HIGH
Probe Circuit Outputs
Probe Circuit Inputs
Yes
–
Probe Circuit Secured
Probe Circuit Secured
Security Fuse(s) Programmed
Notes:
1. Avoid using SDI, SDO, DCLK, PRA, and PRB pins as input or bidirectional ports. Since these pins are active during probing, input
signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the "Pin Descriptions" section on
page 1-45 for information on unused I/O pins.
v3.1
1-7
40MX and 42MX Automotive FPGA Families
Design Consideration
It is recommended to use a series 70Ω termination
resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70Ω series termination is used
to prevent data transmission corruption during probing
and reading back the checksum.
IEEE Standard 1149.1 Boundary Scan Test
(BST) Circuitry
Automotive-grade 42MX24 and 42MX36 devices are
compatible with IEEE Standard 1149.1 (informally known
as Joint Testing Action Group Standard or JTAG), which
defines a set of hardware architecture and mechanisms
for cost-effective, board-level testing. The basic MX
boundary-scan logic circuit is composed of the TAP (test
access port), TAP controller, test data registers and
instruction register (Figure 1-13). This circuit supports all
mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/
PRELOAD and BYPASS) and some optional instructions.
Table 1-3 on page 1-9 describes the ports that control
JTAG testing, while Table 1-4 on page 1-9 describes the
test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has
four associated pins: TCK (test clock input), TDI and TDO
(test data input and output), and TMS (test mode
selector).
The TAP controller is a four-bit state machine. The '1's
and '0's represent the values that must be present at TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles.
Automotive-grade 42MX24 and 42MX36 devices support
three types of test data registers: bypass, device
identification, and boundary scan. The bypass register is
selected when no other register needs to be accessed in a
device. This speeds up test data transfer to other devices
in a test data path. The 32-bit device identification
register is a shift register with four fields (lowest
significant byte (LSB), ID number, part number and
version). The boundary-scan register observes and
controls the state of each I/O pin.
Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Boundary Scan Register
Bypass
Register
Control Logic
JTAG
TMS
TCK
TAP Controller
Instruction
Decode
JTAG
TDI
Instruction
Register
Figure 1-13 • 42MX IEEE 1149.1 Boundary Scan Circuitry
1 -8
v3.1
Output
MUX
TDO
40MX and 42MX Automotive FPGA Families
Table 1-3 • Test Access Port Descriptions
Port
TMS
(Test
Select)
Description
Mode Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK)
TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge
of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency
for TCK is 20 MHz
TDI (Test Data Input)
TDO
(Test
Output)
Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock
Data Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high
impedance) when data scanning is not in progress
Table 1-4 • Supported BST Public Instructions
Instruction
IR Code [2:0]
Instruction Type
Description
EXTEST
000
Mandatory
Allows the external circuitry and board-level interconnections to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins
SAMPLE/PRELOAD
001
Mandatory
Allows a snapshot of the signals at the device pins to be
captured and examined during operation
HIGH Z
101
Optional
Tristates all I/Os to allow external signals to drive pins. Please
refer to the IEEE Standard 1149.1 specification for details
CLAMP
110
Optional
Allows state of signals driven from component pins to be
determined from the Boundary-Scan Register. Please refer to
the IEEE Standard 1149.1 specification for details
BYPASS
111
Mandatory
Enables the bypass register between the TDI and TDO pins. The
test data passes through the selected device to adjacent devices
in the test chain
v3.1
1-9
40MX and 42MX Automotive FPGA Families
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer
software by selecting Tools and then Device Selection.
This brings up the Device Selection dialog box as shown
in Figure 1-14. The JTAG test logic circuit can be enabled
by clicking the "Reserve JTAG Pins" check box. Table 1-5
explains the pins' behavior in either mode.
Figure 1-14 • Device Selection Wizard
Table 1-5 • Boundary Scan Pin Configuration and Functionality
Reserve JTAG
Checked
Unchecked
TCK
BST input; must be terminated to logical HIGH or LOW to avoid floating
User I/O
TDI, TMS
BST input; may float or be tied to HIGH. TDI may be tied to TDO of another device
User I/O
TDO
BST output; may float or be connected to TDI of another device
User I/O
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX
devices contain power-on circuitry that resets the
boundary-scan circuitry upon power-up. Also, the TMS
pin is equipped with an internal pull-up resistor. This
allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
Boundary Scan Description Language
(BSDL) File
Conforming to the IEEE Standard 1149.1 requires that
the operation of the various JTAG components be
documented. The BSDL file provides the standard format
to describe the JTAG components that can be used by
automatic test equipment software. The file includes the
instructions that are supported, instruction-bit pattern,
and the boundary-scan chain order. For an in-depth
discussion on BSDL files, please refer to Actel BSDL Files
Format Description application note.
Actel BSDL files are grouped into two categories—
generic and device-specific. The generic files assign all
user I/Os as inouts. Device-specific files assign user I/Os as
inputs, outputs, or inouts.
Generic files for MX devices are available on Actel's website
at http://www.actel.com/techdocs/models/bsdl.html.
1 -1 0
v3.1
40MX and 42MX Automotive FPGA Families
Development Tool Support
Related Documents
The automotive-grade MX family of FPGAs is fully
supported by both Actel's Libero™ Integrated Design
Environment (IDE) and Designer FPGA Development
software. Actel Libero IDE is a design management
environment, seamlessly integrating design tools while
guiding the user through the design flow, managing all
design and log files, and passing necessary design data
among tools. Libero IDE allows users to integrate both
schematic and HDL synthesis into a single flow and verify
the entire design in a single environment. Libero IDE
includes Synplify® for Actel from Synplicity®, ViewDraw
for Actel from Mentor Graphics, ModelSim™ HDL
Simulator from Mentor Graphics®, WaveFormer Lite™
from SynaptiCAD™, and Designer software from Actel.
Refer to the Libero IDE flow (located on Actel’s website)
diagram for more information.
Application Notes
Actel BSDL Files Format Description
www.actel.com/documents/BSDLformat_AN.pdf
Programming Antifuse Devices
http://www.actel.com/documents/
AntifuseProgram_AN.pdf
Actel's Implementation of Security in Actel Antifuse
FPGAs
www.actel.com/documents/Antifuse_Security_AN.pdf
User’s Guides and Manuals
Antifuse Macro Library Guide
Actel's Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven place-and-route, and a world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results
of place-and-route. Additionally, the back-annotation
flow is compatible with all the major simulators and the
simulation results can be cross-probed with Silicon
Explorer II, Actel’s integrated verification and logic
analysis tool. Another tool included in the Designer
software is the ACTgen macro builder, which easily
creates popular and commonly used logic functions for
implementation into your schematic or HDL design.
Actel's Designer software is compatible with the most
popular FPGA design entry and verification tools from
companies such as Mentor Graphics, Synplicity, Synopsys,
and Cadence Design Systems. The Designer software is
available for both the Windows and UNIX operating
systems.
www.actel.com/documents/libguide_UG.pdf
Silicon Sculptor II
www.actel.com/techdocs/manuals/default.asp#programmers
Miscellaneous
Libero IDE Flow Diagram
www.actel.com/products/tools/libero/flow.html
v3.1
1-11
40MX and 42MX Automotive FPGA Families
5.0V Operating Conditions
Absolute Maximum Ratings*
Recommended Operating Conditions
Free Air Temperature Range
Symbol
Parameter
VCC/VCCA/VCCI DC Supply Voltage
Automotive1
Units
Temperature Range
-40 to +125
°C
Parameter
2
Limits
Units
–0.5 to +6.5
V
VCCI
4.75 to 5.25
V
VI
Input Voltage
–0.5 to VCC +0.5
V
VCCA
4.75 to 5.25
V
VO
Output Voltage
–0.5 to VCC +0.5
V
VCC
4.75 to 5.25
V
TSTG
Storage Temperature
–65 to +150
°C
Notes:
Note: *Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for
extended periods may affect device reliability. Devices
should not be operated outside the Recommended
Operating Conditions.
1. Automotive grade parts (A grade) devices are tested at room
temperature to specifications that have been guard banded
based on characterization across the recommended
operating conditions. A-grade parts are not tested at
extended temperatures. If testing to ensure guaranteed
operation at extended temperatures is required, please
contact your local Actel Sales office to discuss testing
options available.
2. Ambient temperature (TA)
Electrical Specifications
Automotive
Parameter
Conditions
Min.
VOH1
Output High Voltage
(IOH = –4 mA)
3.1
VOL1
Output Low Voltage
(IOL = 4 mA)
VIL
Input Low Voltage
VIH
Input High Voltage
2.1
IIL, IIH
Input Leakage Current
–20
20
µA
IOZ
Tristate Output Leakage Current
–20
20
µA
tR, tF
Input Transition Time
250
ns
CIO
I/O Capacitance
10
pF
ICC2
Standby Current
35
mA
IIO
I/O source sink current
V
0.4
V
0.6
V
V
Can be derived from the IBIS model (http://www.actel.com/techdocs/models/ibis.html)
Notes:
1. Only one output tested at a time. VCC/VCCI = min.
2. All outputs unloaded. All inputs = VCC/VCCI or GND.
1 -1 2
Max.
Units
Symbol
v3.1
40MX and 42MX Automotive FPGA Families
Power Dissipation
Active Power Component
Power dissipation in CMOS devices is usually dominated
by the active (dynamic) power dissipation. This
component is frequency-dependent and a function of
the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the
interconnect, unprogrammed antifuses, module inputs,
and module outputs, plus external capacitance due to PC
board traces and load device inputs. An additional
component of the active power dissipation is the totem
pole current in the CMOS transistor pairs. The net effect
can be associated with an equivalent capacitance that
can be combined with frequency and voltage to
represent active power dissipation.
General Power Equation
P = [ICCstandby + ICCactive] * VCCI + IOL* VOL* N
+ IOH * (VCCI – VOH) * M
where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS
switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
The power dissipated by a CMOS circuit can be expressed
by the equation:
N equals the number of outputs driving TTL loads to
VOL.
Power (µW) = CEQ * VCCA2 * F
M equals the number of outputs driving TTL loads to
VOH.
EQ 1-1
Accurate values for N and M are difficult to determine
because they depend on the family type, on design
details, and on the system I/O. The power can be divided
into two components: static and active.
where:
Static Power Component
Actel FPGAs have small static power components that
result in power dissipation lower than PALs or CPLDs. By
integrating multiple PALs/CPLDs into one FPGA, an even
greater reduction in board-level power dissipation can
be achieved.
CEQ
=
Equivalent
capacitance
picofarads (pF)
expressed
VCCA
=
Power supply in volts (V)
F
=
Switching frequency in megahertz (MHz)
in
Equivalent Capacitance
Equivalent capacitance is calculated by measuring
ICCactive at a specified frequency and voltage for each
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of VCC.
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown on
the following page.
The power due to standby current is typically a small
component of the overall power.
The static power dissipation by TTL loads depends on the
number of outputs driving HIGH or LOW, and on the DC
load current. Again, this number is typically small. For
instance, a 32-bit bus sinking 4 mA at 0.33V will generate
42 mW with all outputs driving LOW, and 140 mW with
all outputs driving HIGH. The actual dissipation will
average somewhere in between, as I/Os switch states
with time.
v3.1
1-13
40MX and 42MX Automotive FPGA Families
CEQ Values for Actel MX FPGAs
Modules (CEQM)
3.5
Input Buffers (CEQI)
6.9
Output Buffers (CEQO)
18.2
Routed Array Clock Buffer Loads (CEQCR)
1.4
Fixed Capacitance Values
for MX FPGAs (pF)
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. The equation below shows a
piece-wise linear summation over all components.
Power = VCCA2 * [(m x CEQM * fm)Modules +
(n * CEQI * fn)Inputs + (p * (CEQO + CL) * fp)outputs +
0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 +
0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2
EQ 1-2
where:
m
= Number of logic modules switching at frequency fm
n
=
Number of input buffers switching at frequency fn
p
=
Number of output buffers switching at frequency fp
q1
=
Number of clock loads on the first routed array
clock
q2
r1
routed_Clk1
r2
routed_Clk2
A40MX02
41.4
N/A
A40MX04
68.6
N/A
A42MX09
118
118
A42MX16
165
165
A42MX24
185
185
A42MX36
220
220
Device Type
Determining Average Switching
Frequency
To determine the switching frequency for a design, the
data input values to the circuit must be clearly
understood. The following guidelines represent worstcase scenarios; these can be used to generally predict the
upper limits of power dissipation.
Logic Modules (m)
=
80% of
Combinatorial
Modules
= Number of clock loads on the second routed array
clock
Inputs Switching (n)
=
# of Inputs/4
r1
=
Fixed capacitance due to first routed array clock
Outputs Switching (p)
=
# of Outputs/4
r2
=
Fixed capacitance due to second routed array clock
First Routed Array Clock Loads (q1)
=
40% of Sequential
Modules
CEQM
= Equivalent capacitance of logic modules in pF
CEQI
= Equivalent capacitance of input buffers in pF
Second Routed Array Clock Loads =
(q2)
40% of Sequential
Modules
CEQO
= Equivalent capacitance of output buffers in pF
Load Capacitance (CL)
35 pF
CEQCR =
Equivalent capacitance of routed array clock in pF
Average Logic Module Switching =
Rate (fm)
F/10
CL
=
fm
= Average logic module switching rate in MHz
Average Input Switching Rate (fn)
=
F/5
fn
=
Average input buffer switching rate in MHz
Average Output Switching Rate (fp)
=
F/10
fp
=
Average output buffer switching rate in MHz
fq1
=
Average first routed array clock rate in MHz
fq2
=
Average second routed array clock rate in MHz
1 -1 4
Output load capacitance in p
=
v3.1
Average First Routed Array Clock =
Rate (fq1)
F
Average Second Routed Array Clock =
Rate (fq2)
F/2
40MX and 42MX Automotive FPGA Families
Junction Temperature
∆T = θja * P
The temperature variable in the Designer software refers
to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is
usually hotter than the ambient temperature. EQ 1-3 can
be used to calculate junction temperature.
θja = Junction to ambient of package. θja numbers are
located in the "Package Thermal Characteristics" section.
Junction Temperature = ∆T + Ta (1)
The device junction-to-case thermal characteristic is θjc,
and the junction-to-ambient air characteristic is θja. The
thermal characteristics for θja are shown with two
different air flow rates.
P = Power
Package Thermal Characteristics
EQ 1-3
Where:
Maximum junction temperature is 150°C.
Ta = Ambient Temperature
A sample calculation of the absolute maximum power
dissipation allowed for a PQFP 160-pin package at
automotive temperature is as follows:
∆T = Temperature gradient between junction (silicon)
and ambient
Max. junction temp. (°C) – Max. automotive temp.
150°C – 125°C
----------------------------------------------------------------------------------------------------------------------------------- = --------------------------------------- = 0.95 W
θ ja (°C/W)
26.2 °C/W
Table 1-6 • Package Thermal Characteristics
θja
Pin Count
θjc
Still Air
1.0 m/s
200 ft./min.
2.5 m/s
500 ft./min.
Units
Plastic Quad Flat Pack
100
12.0
27.8
23.4
21.2
°C/W
Plastic Quad Flat Pack
160
10.0
26.2
22.8
21.1
°C/W
Plastic Quad Flat Pack
208
8.0
26.1
22.5
20.8
°C/W
Plastic Quad Flat Pack
240
8.5
25.6
22.3
20.8
°C/W
Plastic Leaded Chip Carrier
68
13.0
25.0
21.0
19.4
°C/W
Plastic Leaded Chip Carrier
84
12.0
22.5
18.9
17.6
°C/W
Thin Plastic Quad Flat Pack
176
11.0
24.7
19.9
18.0
°C/W
Very Thin Plastic Quad Flat Pack
80
12.0
38.2
31.9
29.4
°C/W
Very Thin Plastic Quad Flat Pack
100
10.0
35.3
29.4
27.1
°C/W
Plastic Packages
v3.1
1-15
40MX and 42MX Automotive FPGA Families
Timing Information
Predicted
Routing
Delays
Internal Delays
Input Delay
I/O Module
t INYL = 1.2 ns
Output Delay
I/O Module
tIRD2 = 4.6 ns
Logic Module
t DLH = 5.9 ns
t IRD1 = 3.7 ns
t IRD4 = 6.5 ns
t IRD8 = 10.2 ns
Array
Clock
tCKH = 8.1 ns
t PD = 2.2 ns
t CO = 2.2 ns
t RD1 = 2.3 ns
t RD2 = 3.2 ns
t RD4 = 5.1 ns
t RD8 = 8.8 ns
tENHZ = 14.1 ns
FO = 128
F MAX = 116 MHz
Note: * Values are shown for 40MX at worst-case 5.0V automotive conditions.
Figure 1-15 • 40MX Timing Model*
Input Delays
Internal Delays
I/O Module
t INYL = 1.3 ns
Predicted
Routing
Delays
tIRD1 =
3.4 ns †
Output Delays
I/O Module
Combinatorial
Logic Module
D
Q
t DLH = 4.0 ns
t RD1 = 1.1 ns
t RD2 = 1.6 ns
tRD4 = 2.2 ns
t RD8 = 3.8 ns
t PD = 2.0 ns
G
Sequential
Logic Module
tINH = 0.0 ns
tINSU = 0.4 ns
tINGL = 2.1 ns
Array
Clocks
t CKH = 4.0 ns
Combinatorial
Logic
included
in t SUD
FO = 32
FMAX = 192 MHz
D
Q
D
t RD1 = 1.1 ns
G
t SUD = 0.4 ns
t HD = 0.0 ns
t CO = 2.1 ns
t LCO = 8.6 ns (light loads, pad-to-pad)
Notes:
*Values are shown for A42MX09 at worst-case 5.0V automotive conditions.
† Input module predicted routing delay
Figure 1-16 • 42MX Timing Model*
1 -1 6
I/O Module
t DLH= 4.0 ns
v3.1
Q
tENHZ = 8.2 ns
tOUTH = 0.00 ns
tOUTSU = 0.4 ns
tGLH = 4.3 ns
40MX and 42MX Automotive FPGA Families
Input Delays
Internal Delays
I/O Module
tINPY = 1.7 ns t
= 3.3 ns
IRD1
Predicted
Routing
Delays
Output Delays
I/O Module
Combinatorial
Module
D
Q
t DLH= 4.3 ns
tRD1 = 1.6 ns
tRD2 = 2.2 ns
tRD4 = 3.3 ns
tPD = 2.3 ns
G
tINH = 0.0 ns
tINSU = 0.8 ns
tINGO = 2.4 ns
Decode
Module
tRDD = 0.6 ns
tPDD = 2.7 ns
I/O Module
tDLH = 4.3 ns
Sequential
Logic Module
tRD1= 1.6 ns
Combinatorial
Logic
included
in t SUD
D
D
Q
G
tSUD = 0.6 ns
tHD = 0.0 ns
Quadrant
Clocks
Q
tCO = 2.2 ns
tENHZ = 8.8 ns
t LH = 0.0 ns
tLSU = 0.8 ns
tGHL = 5.0 ns
tCKH = 4.5 ns†
FMAX = 116 MHz
Notes:
* Values are shown for A42MX36 at worst-case 5.0V automotive conditions.
†Load-dependent
Figure 1-17 • A42MX36 Timing Model (Logic Functions using Quadrant Clocks)*
v3.1
1-17
40MX and 42MX Automotive FPGA Families
Input Delays
I/O Module
t INPY = 1.7 ns
D
t IRD1 = 3.3 ns
Q
G
t INSU = 0.8 ns
t INH = 0.0 ns
t INGO = 2.4 ns
Predicted
Routing
Delays
WD [7:0]
WRAD [5:0]
Array
Clocks
RD [7:0]
RDAD [5:0]
tRD1 = 1.6 ns
BLKEN
REN
D
WEN
WCLK
RCLK
G
tADSU = 2.7 ns
tADH = 0.0 ns
t WENSU = 4.5 ns
t BENS = 4.6 ns
tADSU = 2.7 ns
tADH = 0.0 ns
tRENSU = 1.0 ns
t RCO = 5.7 ns
FMAX = 123 MHz
Note: *Values are shown for A42MX36 at worst-case 5.0V automotive conditions.
Figure 1-18 • A42MX36 Timing Model (SRAM Functions)*
1 -1 8
I/O Module
tDLH = 4.3 ns
v3.1
Q
tGHL = 5.0 ns
tLSU = 0.8 ns
t LH = 0.0 ns
40MX and 42MX Automotive FPGA Families
Parameter Measurement
E
D
In
50% 50%
VOH
1.5V
PAD
1.5V
VOL
tDHL
tDLH
TRIBUFF
PAD To AC test loads (shown below)
E
50% 50%
VCCI
1.5V
PAD
10%
VOL
tENZL
tENLZ
E
50% 50%
VOH
PAD
90%
1.5V
GND
tENHZ
tENZH
Figure 1-19 • Output Buffer Delays
Load 2
(Used to measure rising/falling edges)
Load 1
(Used to measure propagation delay)
VCCI
To the output under test
35 pF
To the output under test
GND
R to VCCI for tPLZ /t PZL
R to GND for t PHZ /t PZH
R = 1 kΩ
35 pF
Figure 1-20 • AC Test Loads
v3.1
1-19
40MX and 42MX Automotive FPGA Families
Sequential Timing Characteristics
PAD
S
A
B
Y
INBUF
Y
S, A or B 50% 50%
PAD
Y
GND
3V
1.5V 1.5V
VCCI
50%
Y
0V
50%
tPLH
Y
PHL
50%
tPHL
tINYL
t INYH
Figure 1-21 • Input Buffer Delays
50%
50%
50%
tPLH
Figure 1-22 • Module Delays
D
E
CLK
PRE
Y
CLR
(Positive Edge-Triggered)
t HD
D1
t SUD
tA
t WCLKA
G, CLK
t WCLKI
t SUENA
t HENA
E
t CO
Q
t RS
PRE, CLR
t WASYN
Note: D represents all data functions involving A. B. and S for multiplexed flip-flops.
Figure 1-23 • Flip-Flops and Latches
1 -2 0
v3.1
40MX and 42MX Automotive FPGA Families
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
Figure 1-25 • Output Buffer Latches
DATA
PAD
IBDL
G
CLK
PAD
DATA
tINH
G
tINSU
tH EXT
CLK
tSU EXT
Figure 1-24 • Input Buffer Latches
v3.1
1-21
40MX and 42MX Automotive FPGA Families
Decode Module Timing
A
B
C
D
E
F
G
Y
H
A–G, H
50%
Y
tPHL
tPLH
Figure 1-26 • Decode Module Timing
Read Port
Write Port
WRAD [5:0]
BLKEN
WEN
RDAD [5:0]
RAM Array
3 2x8 or 64x4
(2 56 Bits)
WCLK
REN
RCLK
WD [7:0]
RD [7:0]
Figure 1-27 • SRAM Timing Characteristics
1 -2 2
LEW
v3.1
40MX and 42MX Automotive FPGA Families
Dual-Port SRAM Timing Waveforms
t RCKHL
t RCKHL
WCLK
tADSU
WD[7:0]
WRAD[5:0]
tADH
Valid
t WENSU
t WENH
t BENSU
tBENH
WEN
BLKEN
Valid
Note: Identical timing for falling edge clock.
Figure 1-28 • 42MX SRAM Write Operation
t CKHL
t RCKHL
RCLK
tRENSU
tRENH
REN
tADSU
Valid
RDAD[5:0]
tDOH
RD[7:0]
tADH
Old Data
tRCO
New Data
Note: Identical timing for falling edge clock.
Figure 1-29 • 42MX SRAM Synchronous Read Operation
v3.1
1-23
40MX and 42MX Automotive FPGA Families
(Read Address Controlled)
t RDADV
RDAD[5:0]
ADDR1
ADDR2
t RPD
t DOH
Data 1
RD[7:0]
Data 2
Figure 1-30 • 42MX SRAM Asynchronous Read Operation—Type 1
(Write Address Controlled)
WEN
WD[7:0]
WRAD[5:0]
BLKEN
t WENSU
t WENH
Valid
tADH
tADSU
WCLK
tRPD
tDOH
RD[7:0]
Old Data
Figure 1-31 • 42MX SRAM Asynchronous Read Operation—Type 2
1 -2 4
v3.1
New Data
40MX and 42MX Automotive FPGA Families
Predictable Performance: Tight
Delay Distributions
Critical Nets and Typical Nets
Propagation delays in this datasheet apply to typical
nets, which are used for initial design performance
evaluation. Critical net delays can then be applied to the
most timing critical paths. Critical nets are determined by
net property assignment in Actel's Designer software
prior to placement and routing. Up to 6% of the nets in
a design may be designated as critical.
Propagation delay between logic modules depends on
the resistive and capacitive loading of the routing tracks,
the interconnect elements, and the module inputs being
driven. Propagation delay increases as the length of
routing tracks, the number of interconnect elements, or
the number of inputs increases.
From a design perspective, the propagation delay can be
statistically correlated or modeled by the fanout
(number of loads) driven by a module. Higher fanout
usually requires some paths to have longer routing
tracks.
Long Tracks
Some nets in the design use long tracks, which are
special routing resources that span multiple rows,
columns, or modules. Long tracks employ three and
sometimes four antifuse connections, which increase
capacitance and resistance, resulting in longer net delays
for macros connected to long tracks. Typically, up to
6 percent of nets in a fully utilized device require long
tracks. Long tracks add approximately a 3 ns to a 6 ns
delay, which is represented statistically in higher fanout
(FO=8) routing delays in the datasheet specifications
section beginning on page 1-16.
The MX FPGAs deliver a tight fanout delay distribution,
which is achieved in two ways: by decreasing the delay of
the interconnect elements and by decreasing the number
of interconnect elements per path.
Actel’s patented antifuse offers a very low resistive/
capacitive interconnect. The antifuses, fabricated in
0.45 µ lithography, offer nominal levels of 100 Ω
resistance and 7.0 femtofarad (fF) capacitance per
antifuse.
Timing Derating
MX fanout distribution is also tight due to the low
number of antifuses required for each interconnect path.
The proprietary architecture limits the number of
antifuses per path to a maximum of four, with
90 percent of interconnects using only two antifuses.
MX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature and best-case
processing. Maximum timing parameters reflect
minimum operating voltage, maximum operating
temperature and worst-case processing.
Timing Characteristics
Device timing characteristics fall into three categories:
family-dependent, device-dependent, and designdependent. The input and output buffer characteristics
are common to all MX devices. Internal routing delays
are device-dependent. Design dependency means actual
delays are not determined until after place-and-route of
the user’s design is complete. Delay values may then be
determined by using the Timer tool in the Designer
software or by performing simulation with postlayout delays.
v3.1
1-25
40MX and 42MX Automotive FPGA Families
Temperature and Voltage Derating Factors
Table 1-7 • 42MX Temperature and Voltage Derating Factors
(Normalized to TJ = 125°C, VCCA/VCCI = 4.75V)
Temperature
42MX
Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.75
0.66
0.67
0.74
0.78
0.89
0.91
1.00
5.00
0.64
0.65
0.72
0.75
0.87
0.89
0.97
5.25
0.62
0.64
0.70
0.73
0.84
0.86
0.94
42MX Derating Factor (Normalized to TJ = 125°C, VCCA /VCCI =4.75V)
1.10
Derating Factor
1.00
-55°C
0.90
-40°C
0°C
0.80
25°C
0.70
70°C
85°C
0.60
125°C
0.50
0.40
4.75
5.00
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-32 • 42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 125°C, VCCA/VCCI = 4.75V)
1 -2 6
v3.1
5.25
40MX and 42MX Automotive FPGA Families
Table 1-8 • 40MX Temperature and Voltage Derating Factors
(Normalized to TJ = 125°C, VCC = 4.75V)
Temperature
40MX
Voltage
–55°C
–40°C
0°C
25°C
70°C
85°C
125°C
4.75
0.62
0.64
0.71
0.75
0.86
0.90
1.00
5.00
0.60
0.62
0.69
0.73
0.84
0.88
0.97
5.25
0.58
0.60
0.67
0.71
0.82
0.85
0.94
40MX Derating Factor (Normalized to TJ = 125°C, VCC = 4.75V)
1.10
Derating Factor
1.00
-55°C
0.90
-40°C
0°C
0.80
25°C
0.70
70°C
85°C
0.60
125°C
0.50
0.40
4.75
5.00
5.25
Voltage (V)
Note: This derating factor applies to all routing and propagation delays.
Figure 1-33 • 40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 125°C, VCC 4.75V)
v3.1
1-27
40MX and 42MX Automotive FPGA Families
Timing Characteristics
The timing numbers in the datasheet represent sample timing characteristics of the devices. Refer to the Timer tool in
the Designer software for design-specific timing information.
Table 1-9 • A40MX02 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
2.2
ns
tPD2
Dual-Module Macros
4.7
ns
tCO
Sequential Clock-to-Q
2.2
ns
tGO
Latch G-to-Q
2.2
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.2
ns
1
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
2.3
ns
tRD2
FO=2 Routing Delay
3.2
ns
tRD3
FO=3 Routing Delay
4.2
ns
tRD4
FO=4 Routing Delay
5.1
ns
tRD8
FO=8 Routing Delay
8.8
ns
2
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Set-Up
5.4
ns
tHD3
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
5.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
5.8
ns
tWASYN
Flip-Flop (Latch)
5.8
ns
tA
Flip-Flop Clock Input Period
8.7
ns
fMAX
Flip-Flop (Latch) Clock Frequency
116
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.3
ns
tINYL
Pad-to-Y LOW
1.2
ns
Input Module Predicted Routing Delays
1
tIRD1
FO=1 Routing Delay
3.7
ns
tIRD2
FO=2 Routing Delay
4.6
ns
tIRD3
FO=3 Routing Delay
5.6
ns
tIRD4
FO=4 Routing Delay
6.5
ns
tIRD8
FO=8 Routing Delay
10.2
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
macro.
4. Delays based on 35 pF loading.
1 -2 8
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-9 • A40MX02 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C (Continued)
Std. Speed
Parameter
Description
Min.
Max.
Units
FO = 16
8.1
ns
FO = 128
8.1
ns
FO = 16
8.6
ns
FO = 128
8.6
ns
Global Clock Networks
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
fMAX
Input Low to HIGH
Input High to LOW
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Minimum Period
Maximum Frequency
FO = 16
3.9
ns
FO = 128
4.2
ns
FO = 16
3.9
ns
FO = 128
4.2
ns
FO = 16
0.7
ns
FO = 128
0.9
ns
FO = 16
8.3
ns
FO = 128
8.7
ns
FO = 16
120
MHz
FO = 128
116
MHz
TTL Output Module Timing4
tDLH
Data-to-Pad HIGH
5.9
ns
tDHL
Data-to-Pad LOW
7.1
ns
tENZH
Enable Pad Z to HIGH
6.7
ns
tENZL
Enable Pad Z to LOW
8.3
ns
tENHZ
Enable Pad HIGH to Z
14.1
ns
tENLZ
Enable Pad LOW to Z
10.4
ns
dTLH
Delta LOW to HIGH
0.03
ns/pF
dTHL
Delta HIGH to LOW
0.05
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
macro.
4. Delays based on 35 pF loading.
v3.1
1-29
40MX and 42MX Automotive FPGA Families
Table 1-10 • A40MX04 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
2.2
ns
tPD2
Dual-Module Macros
4.7
ns
tCO
Sequential Clock-to-Q
2.2
ns
tGO
Latch G-to-Q
2.2
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.2
ns
Logic Module Predicted Routing
Delays1
tRD1
FO=1 Routing Delay
2.4
ns
tRD2
FO=2 Routing Delay
3.4
ns
tRD3
FO=3 Routing Delay
4.3
ns
tRD4
FO=4 Routing Delay
5.2
ns
tRD8
FO=8 Routing Delay
9.0
ns
Logic Module Sequential
Timing2
tSUD
Flip-Flop (Latch) Data Input Set-Up
5.4
ns
tHD3
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
5.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
5.8
ns
tWASYN
Flip-Flop (Latch)
5.8
ns
tA
Flip-Flop Clock Input Period
8.7
ns
fMAX
Flip-Flop (Latch) Clock Frequency
116
MHz
1.3
ns
1.2
ns
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
tINYL
Pad-to-Y LOW
Input Module Predicted Routing
Delays1
tIRD1
FO=1 Routing Delay
3.7
ns
tIRD2
FO=2 Routing Delay
4.6
ns
tIRD3
FO=3 Routing Delay
5.6
ns
tIRD4
FO=4 Routing Delay
6.5
ns
tIRD8
FO=8 Routing Delay
10.2
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
macro.
4. Delays based on 35 pF loading.
1 -3 0
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-10 • A40MX04 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCC = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
FO = 16
8.2
ns
FO = 128
8.2
ns
FO = 16
8.7
ns
FO = 128
8.7
ns
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tP
fMAX
Input Low to HIGH
Input High to LOW
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Minimum Period
Maximum Frequency
TTL Output Module Timing
FO = 16
3.9
ns
FO = 128
4.2
ns
FO = 16
3.9
ns
FO = 128
4.2
ns
FO = 16
0.7
ns
FO = 128
0.9
ns
FO = 16
8.3
ns
FO = 128
8.7
ns
FO = 16
120
MHz
FO = 128
116
MHz
4
tDLH
Data-to-Pad HIGH
5.9
ns
tDHL
Data-to-Pad LOW
7.1
ns
tENZH
Enable Pad Z to HIGH
6.7
ns
tENZL
Enable Pad Z to LOW
8.3
ns
tENHZ
Enable Pad HIGH to Z
14.1
ns
tENLZ
Enable Pad LOW to Z
10.4
ns
dTLH
Delta LOW to HIGH
0.03
ns/pF
dTHL
Delta HIGH to LOW
0.05
ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Setup times assume a fanout of 3. Further testing information can be obtained from the Timer tool.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool in Designer to check the hold time for this
macro.
4. Delays based on 35 pF loading.
v3.1
1-31
40MX and 42MX Automotive FPGA Families
Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Logic Module Propagation
Min.
Max.
Units
Delays1
tPD1
Single Module
2.0
ns
tCO
Sequential Clock-to-Q
2.1
ns
tGO
Latch G-to-Q
2.0
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.4
ns
Logic Module Predicted Routing Delays
2
tRD1
FO=1 Routing Delay
1.1
ns
tRD2
FO=2 Routing Delay
1.6
ns
tRD3
FO=3 Routing Delay
1.9
ns
tRD4
FO=4 Routing Delay
2.2
ns
tRD8
FO=8 Routing Delay
3.8
ns
Logic Module Sequential
Timing3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.4
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.6
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
4.8
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
6.3
ns
tA
Flip-Flop Clock Input Period
4.8
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.4
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
174
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.8
ns
tINYL
Pad-to-Y LOW
1.3
ns
tINGH
G to Y HIGH
2.1
ns
tINGL
G to Y LOW
2.1
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -3 2
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
2
Input Module Predicted Routing Delays
tIRD1
FO=1 Routing Delay
3.4
ns
tIRD2
FO=2 Routing Delay
3.8
ns
tIRD3
FO=3 Routing Delay
4.2
ns
tIRD4
FO=4 Routing Delay
4.6
ns
tIRD8
FO=8 Routing Delay
6.2
ns
FO = 32
4.0
ns
FO = 256
4.5
ns
FO = 32
5.8
ns
FO = 256
6.4
ns
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
fMAX
Input Low to HIGH
Input High to LOW
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Input Latch External Setup
Input Latch External Hold
Minimum Period
Maximum Frequency
TTL Output Module
FO = 32
2.0
ns
FO = 256
2.2
ns
FO = 32
2.0
ns
FO = 256
2.2
ns
FO = 32
0.6
ns
FO = 256
0.6
ns
FO = 32
0.0
ns
FO = 256
0.0
ns
FO = 32
3.9
ns
FO = 256
4.4
ns
FO = 32
5.3
ns
FO = 256
5.8
ns
FO = 32
192
MHz
FO = 256
174
MHz
Timing5
tDLH
Data-to-Pad HIGH
4.0
ns
tDHL
Data-to-Pad LOW
4.8
ns
tENZH
Enable Pad Z to HIGH
4.4
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v3.1
1-33
40MX and 42MX Automotive FPGA Families
Table 1-11 • A42MX09 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
tENZL
Enable Pad Z to LOW
4.8
ns
tENHZ
Enable Pad HIGH to Z
8.2
ns
tENLZ
Enable Pad LOW to Z
8.9
ns
tGLH
G-to-Pad HIGH
4.3
ns
tGHL
G-to-Pad LOW
4.3
ns
tLSU
I/O Latch Set-Up
0.8
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading
8.6
ns
tACO
Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading
12.2
ns
dTLH
Capacity Loading, LOW to HIGH
0.04
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.06
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -3 4
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
Single Module
2.2
ns
tCO
Sequential Clock-to-Q
2.4
ns
tGO
Latch G-to-Q
2.2
ns
tRS
Flip-Flop (Latch) Reset-to-Q
2.6
ns
Logic Module Predicted Routing
Delays2
tRD1
FO=1 Routing Delay
1.3
ns
tRD2
FO=2 Routing Delay
1.7
ns
tRD3
FO=3 Routing Delay
2.1
ns
tRD4
FO=4 Routing Delay
2.6
ns
tRD8
FO=8 Routing Delay
4.3
ns
Logic Module Sequential Timing3,4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.6
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.1
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
5.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.4
ns
tA
Flip-Flop Clock Input Period
11.3
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.8
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.8
ns
fMAX
Flip-Flop (Latch) Clock Frequency
139
MHz
Input Module Propagation Delays
tINYH
Pad-to-Y HIGH
1.8
ns
tINYL
Pad-to-Y LOW
1.3
ns
tINGH
G to Y HIGH
2.4
ns
tINGL
G to Y LOW
2.4
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v3.1
1-35
40MX and 42MX Automotive FPGA Families
Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
3.0
ns
tIRD2
FO=2 Routing Delay
3.5
ns
tIRD3
FO=3 Routing Delay
3.9
ns
tIRD4
FO=4 Routing Delay
4.4
ns
tIRD8
FO=8 Routing Delay
6.1
ns
FO = 32
4.4
ns
FO = 384
4.8
ns
FO = 32
6.3
ns
7.4
ns
Global Clock Network
tCKH
Input Low to HIGH
tCKL
Input High to LOW
tPWH
Minimum Pulse Width HIGH
FO = 384
tPWL
tCKSW
tSUEXT
Minimum Pulse Width LOW
Maximum Skew
Input Latch External Setup
tHEXT
Input Latch External Hold
tP
Minimum Period
fMAX
Maximum Frequency
TTL Output Module
FO = 32
5.3
ns
FO = 384
6.1
ns
FO = 32
5.3
ns
FO = 384
6.1
ns
FO = 32
0.6
ns
FO = 384
0.6
ns
FO = 32
0.0
ns
FO = 384
0.0
ns
FO = 32
4.6
ns
FO = 384
5.3
ns
FO = 32
6.5
ns
FO = 384
7.2
ns
FO = 32
153
MHz
FO = 384
139
MHz
Timing5
tDLH
Data-to-Pad HIGH
4.2
ns
tDHL
Data-to-Pad LOW
4.9
ns
tENZH
Enable Pad Z to HIGH
4.5
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -3 6
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-12 • A42MX16 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Max.
Units
tENZL
Enable Pad Z to LOW
Description
Min.
4.9
ns
tENHZ
Enable Pad HIGH to Z
9.0
ns
tENLZ
Enable Pad LOW to Z
8.3
ns
tGLH
G-to-Pad HIGH
4.8
ns
tGHL
G-to-Pad LOW
4.8
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading
9.4
ns
tACO
Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading
13.3
ns
dTLH
Capacity Loading, LOW to HIGH
0.04
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.06
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v3.1
1-37
40MX and 42MX Automotive FPGA Families
Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
Logic Module Combinatorial Functions1
tPD
Internal Array Module Delay
2.0
ns
tPDD
Internal Decode Module Delay
2.4
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
1.4
ns
tRD2
FO=2 Routing Delay
1.7
ns
tRD3
FO=3 Routing Delay
2.2
ns
tRD4
FO=4 Routing Delay
2.5
ns
tRD8
FO=8 Routing Delay
4.1
ns
Logic Module Sequential Timing3, 4
tCO
Flip-Flop Clock-to-Output
2.2
ns
tGO
Latch Gate-to-Output
2.0
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.6
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
0.7
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
5.5
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.4
ns
2.4
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.7
ns
tINGO
Input Latch Gate-to-Output
2.2
ns
tINH
Input Latch Hold
0.0
ns
tINSU
Input Latch Set-Up
0.8
ns
tILA
Latch Active Pulse Width
7.8
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -3 8
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
3.1
ns
tIRD2
FO=2 Routing Delay
3.5
ns
tIRD3
FO=3 Routing Delay
3.8
ns
tIRD4
FO=4 Routing Delay
4.2
ns
tIRD8
FO=8 Routing Delay
5.8
ns
FO = 32
4.4
ns
FO = 486
4.9
ns
FO = 32
6.1
ns
FO = 486
7.1
ns
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
fMAX
Input Low to HIGH
Input High to LOW
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Input Latch External Setup
Input Latch External Hold
Minimum Period
Maximum Frequency
FO = 32
3.6
ns
FO = 486
4.0
ns
FO = 32
3.6
ns
FO = 486
4.0
ns
FO = 32
0.9
ns
FO = 486
0.9
ns
FO = 32
0.0
ns
FO = 486
0.0
ns
FO = 32
4.6
ns
FO = 486
5.5
ns
FO = 32
7.4
ns
FO = 486
8.0
ns
FO = 32
135
MHz
FO = 486
124
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v3.1
1-39
40MX and 42MX Automotive FPGA Families
Table 1-13 • A42MX24 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, VCCA = 4.75V, TJ = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
TTL Output Module Timing5
tDLH
Data-to-Pad HIGH
4.1
ns
tDHL
Data-to-Pad LOW
4.8
ns
tENZH
Enable Pad Z to HIGH
4.3
ns
tENZL
Enable Pad Z to LOW
4.8
ns
tENHZ
Enable Pad HIGH to Z
8.6
ns
tENLZ
Enable Pad LOW to Z
8.0
ns
tGLH
G-to-Pad HIGH
4.9
ns
tGHL
G-to-Pad LOW
4.9
ns
tLSU
I/O Latch Set-Up
0.8
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad), 64 Clock Loading
9.2
ns
tACO
Array Clock-to-Out (Pad-to-Pad), 64 Clock Loading
17.8
ns
dTLH
Capacity Loading, LOW to HIGH
0.06
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.05
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -4 0
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, V CCA = 4.75V, T J = 125°C
Std. Speed
Parameter
Description
Min.
Max.
Units
2.3
ns
2.7
ns
1
Logic Module Combinatorial Functions
tPD
Internal Array Module Delay
tPDD
Internal Decode Module Delay
Logic Module Predicted Routing Delays
2
tRD1
FO=1 Routing Delay
1.6
ns
tRD2
FO=2 Routing Delay
2.2
ns
tRD3
FO=3 Routing Delay
2.7
ns
tRD4
FO=4 Routing Delay
3.3
ns
tRD8
FO=8 Routing Delay
5.5
ns
tRDD
Decode-to-Output Routing Delay
0.6
ns
Logic Module Sequential Timing
3, 4
tCO
Flip-Flop Clock-to-Output
2.2
ns
tGO
Latch Gate-to-Output
2.2
ns
tSUD
Flip-Flop (Latch) Set-Up Time
0.6
ns
tHD
Flip-Flop (Latch) Hold Time
0.0
ns
tRO
Flip-Flop (Latch) Reset-to-Output
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.1
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
5.5
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.2
ns
2.6
ns
Synchronous SRAM Operations
tRC
Read Cycle Time
11.3
ns
tWC
Write Cycle Time
11.3
ns
tRCKHL
Clock HIGH/LOW Time
5.7
ns
tRCO
Data Valid After Clock HIGH/LOW
tADSU
Address/Data Set-Up Time
2.7
ns
tADH
Address/Data Hold Time
0.0
ns
5.7
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v3.1
1-41
40MX and 42MX Automotive FPGA Families
Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, V CCA = 4.75V, T J = 125°C (Continued)
Std. Speed
Parameter
Description
Min.
Max.
Units
tRENSU
Read Enable Set-Up
1.0
ns
tRENH
Read Enable Hold
5.7
ns
tWENSU
Write Enable Set-Up
4.5
ns
tWENH
Write Enable Hold
0.0
ns
tBENS
Block Enable Set-Up
4.6
ns
tBENH
Block Enable Hold
0.0
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
13.6
ns
tRDADV
Read Address Valid
14.7
ns
tADSU
Address/Data Set-Up Time
2.7
ns
tADH
Address/Data Hold Time
0.0
ns
tRENSUA
Read Enable Set-Up to Address Valid
1.0
ns
tRENHA
Read Enable Hold
5.7
ns
tWENSU
Write Enable Set-Up
4.5
ns
tWENH
Write Enable Hold
0.0
ns
tDOH
Data Out Hold Time
2.0
ns
Input Module Propagation Delays
tINPY
Input Data Pad-to-Y
1.7
ns
tINGO
Input Latch Gate-to-Output
2.4
ns
tINH
Input Latch Hold
0.0
ns
tINSU
Input Latch Set-Up
0.8
ns
tILA
Latch Active Pulse Width
7.8
ns
Input Module Predicted Routing Delays2
tIRD1
FO=1 Routing Delay
3.3
ns
tIRD2
FO=2 Routing Delay
3.8
ns
tIRD3
FO=3 Routing Delay
4.4
ns
tIRD4
FO=4 Routing Delay
5.0
ns
tIRD8
FO=8 Routing Delay
7.2
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -4 2
v3.1
40MX and 42MX Automotive FPGA Families
Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, V CCA = 4.75V, T J = 125°C (Continued)
Std. Speed
Parameter
Description
Min.
Max.
Units
FO = 32
4.5
ns
FO = 635
5.0
ns
FO = 32
6.3
ns
FO = 635
8.1
ns
Global Clock Network
tCKH
tCKL
tPWH
tPWL
tCKSW
tSUEXT
tHEXT
tP
fMAX
Input Low to HIGH
Input High to LOW
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
Input Latch External Setup
Input Latch External Hold
Minimum Period
Maximum Frequency
TTL Output Module Timing
FO = 32
2.9
ns
FO = 635
3.3
ns
FO = 32
2.9
ns
FO = 635
3.3
ns
FO = 32
1.1
ns
FO = 635
1.1
ns
FO = 32
0.0
ns
FO = 635
0.0
ns
FO = 32
4.8
ns
FO = 635
5.5
ns
FO = 32
8.6
ns
FO = 635
9.4
ns
FO = 32
116
MHz
FO = 635
107
MHz
1
tDLH
Data-to-Pad HIGH
4.3
ns
tDHL
Data-to-Pad LOW
5.0
ns
tENZH
Enable Pad Z to HIGH
4.4
ns
tENZL
Enable Pad Z to LOW
4.9
ns
tENHZ
Enable Pad HIGH to Z
8.8
ns
tENLZ
Enable Pad LOW to Z
8.3
ns
tGLH
G-to-Pad HIGH
5.0
ns
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
v3.1
1-43
40MX and 42MX Automotive FPGA Families
Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, V CCA = 4.75V, T J = 125°C (Continued)
Std. Speed
Parameter
Description
Min.
Max.
Units
5.0
ns
tGHL
G-to-Pad LOW
tLSU
I/O Latch Set-Up
0.8
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-Pad), 32 I/O
9.5
ns
tACO
Array Clock-to-Out (Pad-to-Pad), 32 I/O
13.0
ns
dTLH
Capacity Loading, LOW to HIGH
0.11
ns/pF
dTHL
Capacity Loading, HIGH to LOW
0.11
ns/pF
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer tool.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
1 -4 4
v3.1
40MX and 42MX Automotive FPGA Families
Pin Descriptions
CLK/A/B, I/O
Global Clock
PRA/B, I/O
Clock inputs for clock distribution networks. CLK is for
40MX while CLKA and CLKB are for 42MX devices. The
clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
Probe
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
The Probe pin is used to output data from any userdefined design node within the device. Each diagnostic
pin can be used in conjunction with the other probe pin
to allow real-time diagnostic output of any signal path
within the device. The Probe pin can be used as a userdefined I/O when verification has been completed. The
pin's probe capabilities can be permanently disabled to
protect programmed design confidentiality. The Probe
pin is accessible when the MODE pin is High. This pin
functions as an I/O when the MODE pin is Low.
GND
QCLKA,B,C,D, I/O
DCLK, I/O
Diagnostic Clock
Ground
Input LOW supply voltage.
I/O
Quadrant clock inputs for A42MX36 devices. When not
used as a register control signal, these pins can function
as general-purpose I/Os.
Input/Output
Input, output, tristate, or bidirectional buffer. Input and
output levels are compatible with standard TTL
specifications. Unused I/O pins are configured by the
Designer software as shown in Table 1-15.
SDI, I/O
SDO, TDO, I/O
Configuration
A40MX02, A40MX04
Pulled LOW
A42MX09, A42MX16
Pulled LOW
A42MX24, A42MX36
Tristated
When Silicon Explorer II is being used, SDO will act as an
output while the "checksum" is run. It will return to user
I/O when "checksum" is complete.
TCK, I/O
Mode
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data
into the device. This pin functions as an I/O when
"Reserve JTAG" is not checked in the Designer software.
BST pins are only available in the A42MX24 and
A42MX36 devices.
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). To provide verification capability, the MODE
pin should be held HIGH. To facilitate this, the MODE pin
should be tied to GND through a 10kΩ resistor so that
the MODE pin can be pulled HIGH when required.
NC
Serial Data Output
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is High.
This pin functions as an I/O when the MODE pin is Low.
SDO is available for 42MX devices only.
In all cases, it is recommended to tie all unused I/O pins
to LOW on the board. This applies to all dual-purpose
pins when configured as I/Os as well.
MODE
Serial Data Input
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is High.
This pin functions as an I/O when the MODE pin is Low.
Table 1-15 • Configuration of Unused I/Os
Device
Quadrant Clock
TDI, I/O
No Connection
Test Data In
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when "Reserve JTAG" is not checked in the
Designer software. BST pins are only available in the
A42MX24 and A42MX36 devices.
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
v3.1
1-45
40MX and 42MX Automotive FPGA Families
TDO, I/O
Test Data Out
VCC
Supply Voltage
Serial data output for BST instructions and test data. This
pin functions as an I/O when "Reserve JTAG" is not
checked in the Designer software. BST pins are only
available in the A42MX24 and A42MX36 devices.
Supply voltage for 40MX devices.
TMS, I/O
VCCI
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1
Boundary Scan pins (TCK, TDI, TDO). In flexible mode
when the TMS pin is set LOW, the TCK, TDI and TDO pins
are boundary-scan pins. Once the boundary scan pins are
in test mode, they will remain in that mode until the
internal boundary scan state machine reaches the "logic
reset" state. At this point, the boundary scan pins will be
released and will function as regular I/O pins. The "logic
reset" state is reached five TCK cycles after the TMS pin is
set High. In dedicated test mode, TMS functions as
specified in the IEEE 1149.1 specifications. IEEE JTAG
specification recommends a 10kΩ pull-up resistor on the
pin. BST pins are only available in A42MX24 and
A42MX36 devices.
1 -4 6
v3.1
VCCA
Supply Voltage
Supply voltage for array in 42MX devices.
Supply Voltage
Supply voltage for I/Os in 42MX devices.
WD, I/O
Wide Decode Output
When a wide decode module is used in a an A42MX24 or
A42MX36 device, this pin can be used as a dedicated
output from the wide decode module. This direct
connection eliminates additional interconnect delays
associated with regular logic modules. To implement the
direct I/O connection, connect an output buffer of any
type to the output of the wide decode macro and place
this output on one of the reserved WD pins. When a
wide decode module is not used, this pin functions as a
regular I/O pin.
40MX and 42MX Automotive FPGA Families
Package Pin Assignments
68-Pin PLCC
1 68
68-Pin
PLCC
Figure 2-1 • 68-Pin PLCC
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-1
40MX and 42MX Automotive FPGA Families
68-Pin PLCC
68-Pin PLCC
2 -2
Pin Number
A40MX02 Function
Pin Number
A40MX02 Function
1
I/O
46
I/O
2
I/O
47
I/O
3
I/O
48
I/O
4
VCC
49
GND
5
I/O
50
I/O
6
I/O
51
I/O
7
I/O
52
CLK, I/O
8
I/O
53
I/O
9
I/O
54
MODE
10
I/O
55
VCC
11
I/O
56
SDI, I/O
12
I/O
57
DCLK, I/O
13
I/O
58
PRA, I/O
14
GND
59
PRB, I/O
15
GND
60
I/O
16
I/O
61
I/O
17
I/O
62
I/O
18
I/O
63
I/O
19
I/O
64
I/O
20
I/O
65
I/O
21
VCC
66
GND
22
I/O
67
I/O
23
I/O
68
I/O
24
I/O
25
VCCy
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
GND
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
VCC
39
I/O
40
I/O
41
I/O
42
I/O
43
I/O
44
I/O
45
I/O
v3.1
40MX and 42MX Automotive FPGA Families
84-Pin PLCC
1 84
84-Pin
PLCC
Figure 2-2 • 84-Pin PLCC
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-3
40MX and 42MX Automotive FPGA Families
84-Pin PLCC
2 -4
Pin
Number
A40MX04
Function
1
2
84-Pin PLCC
A42MX09
Function
Pin
Number
A40MX04
Function
A42MX09
Function
I/O
I/O
43
I/O
VCCA
I/O
CLKB, I/O
44
I/O
I/O
3
I/O
I/O
45
I/O
I/O
4
VCC
PRB, I/O
46
VCC
I/O
5
I/O
I/O
47
I/O
I/O
6
I/O
GND
48
I/O
I/O
7
I/O
I/O
49
I/O
GND
8
I/O
I/O
50
I/O
I/O
9
I/O
I/O
51
I/O
I/O
10
I/O
DCLK, I/O
52
I/O
SDO, I/O
11
I/O
I/O
53
I/O
I/O
12
NC
MODE
54
I/O
I/O
13
I/O
I/O
55
I/O
I/O
14
I/O
I/O
56
I/O
I/O
15
I/O
I/O
57
I/O
I/O
16
I/O
I/O
58
I/O
I/O
17
I/O
I/O
59
I/O
I/O
18
GND
I/O
60
GND
I/O
19
GND
I/O
61
GND
I/O
20
I/O
I/O
62
I/O
I/O
21
I/O
I/O
63
I/O
GND
22
I/O
VCCA
64
CLK, I/O
VCCA
23
I/O
VCCI
65
I/O
VCCI
24
I/O
I/O
66
MODE
I/O
25
VCC
I/O
67
VCC
I/O
26
VCC
I/O
68
VCC
I/O
27
I/O
I/O
69
I/O
I/O
28
I/O
GND
70
I/O
GND
29
I/O
I/O
71
I/O
I/O
30
I/O
I/O
72
SDI, I/O
I/O
31
I/O
I/O
73
DCLK, I/O
I/O
32
I/O
I/O
74
PRA, I/O
I/O
33
VCC
I/O
75
PRB, I/O
I/O
34
I/O
I/O
76
I/O
SDI, I/O
35
I/O
I/O
77
I/O
I/O
36
I/O
I/O
78
I/O
I/O
37
I/O
I/O
79
I/O
I/O
38
I/O
I/O
80
I/O
I/O
39
I/O
I/O
81
I/O
PRA, I/O
40
GND
I/O
82
GND
I/O
41
I/O
I/O
83
I/O
CLKA, I/O
42
I/O
I/O
84
I/O
VCCA
v3.1
40MX and 42MX Automotive FPGA Families
100-Pin PQFP
100-Pin
PQFP
100
1
Figure 2-3 • 100-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-5
40MX and 42MX Automotive FPGA Families
100-Pin PQFP
100-Pin PQFP
Pin Number
A40MX02
Function
A40MX04
Function
A42MX09
Function
Pin Number
A40MX02
Function
A40MX04
Function
A42MX09
Function
1
NC
NC
I/O
36
GND
GND
I/O
2
NC
NC
DCLK, I/O
37
GND
GND
I/O
3
NC
NC
I/O
38
I/O
I/O
I/O
4
NC
NC
MODE
39
I/O
I/O
I/O
5
NC
NC
I/O
40
I/O
I/O
VCCA
6
PRB, I/O
PRB, I/O
I/O
41
I/O
I/O
I/O
7
I/O
I/O
I/O
42
I/O
I/O
I/O
8
I/O
I/O
I/O
43
VCC
VCC
I/O
9
I/O
I/O
GND
44
VCC
VCC
I/O
10
I/O
I/O
I/O
45
I/O
I/O
I/O
11
I/O
I/O
I/O
46
I/O
I/O
GND
12
I/O
I/O
I/O
47
I/O
I/O
I/O
13
GND
GND
I/O
48
NC
I/O
I/O
14
I/O
I/O
I/O
49
NC
I/O
I/O
15
I/O
I/O
I/O
50
NC
I/O
I/O
16
I/O
I/O
VCCA
51
NC
NC
I/O
17
I/O
I/O
VCCI
52
NC
NC
SDO, I/O
18
I/O
I/O
I/O
53
NC
NC
I/O
19
VCC
VCC
I/O
54
NC
NC
I/O
20
I/O
I/O
I/O
55
NC
NC
I/O
21
I/O
I/O
I/O
56
VCC
VCC
I/O
22
I/O
I/O
GND
57
I/O
I/O
GND
23
I/O
I/O
I/O
58
I/O
I/O
I/O
24
I/O
I/O
I/O
59
I/O
I/O
I/O
25
I/O
I/O
I/O
60
I/O
I/O
I/O
26
I/O
I/O
I/O
61
I/O
I/O
I/O
27
NC
NC
I/O
62
I/O
I/O
I/O
28
NC
NC
I/O
63
GND
GND
I/O
29
NC
NC
I/O
64
I/O
I/O
GND
30
NC
NC
I/O
65
I/O
I/O
VCCA
31
NC
I/O
I/O
66
I/O
I/O
VCCI
32
NC
I/O
I/O
67
I/O
I/O
VCCA
33
NC
I/O
I/O
68
I/O
I/O
I/O
34
I/O
I/O
GND
69
VCC
VCC
I/O
35
I/O
I/O
I/O
70
I/O
I/O
I/O
2 -6
v3.1
40MX and 42MX Automotive FPGA Families
100-Pin PQFP
Pin Number
A40MX02
Function
A40MX04
Function
A42MX09
Function
71
I/O
I/O
I/O
72
I/O
I/O
GND
73
I/O
I/O
I/O
74
I/O
I/O
I/O
75
I/O
I/O
I/O
76
I/O
I/O
I/O
77
NC
NC
I/O
78
NC
NC
I/O
79
NC
NC
SDI, I/O
80
NC
I/O
I/O
81
NC
I/O
I/O
82
NC
I/O
I/O
83
I/O
I/O
I/O
84
I/O
I/O
GND
85
I/O
I/O
I/O
86
GND
GND
I/O
87
GND
GND
PRA, I/O
88
I/O
I/O
I/O
89
I/O
I/O
CLKA, I/O
90
CLK, I/O
CLK, I/O
VCCA
91
I/O
I/O
I/O
92
MODE
MODE
CLKB, I/O
93
VCC
VCC
I/O
94
VCC
VCC
PRB, I/O
95
NC
I/O
I/O
96
NC
I/O
GND
97
NC
I/O
I/O
98
SDI, I/O
SDI, I/O
I/O
99
DCLK, I/O
DCLK, I/O
I/O
100
PRA, I/O
PRA, I/O
I/O
v3.1
2-7
40MX and 42MX Automotive FPGA Families
160-Pin PQFP
160
1
160-Pin
PQFP
Figure 2-4 • Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
2 -8
v3.1
40MX and 42MX Automotive FPGA Families
160-Pin PQFP
160-Pin PQFP
Pin Number
A42MX09
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX24
Function
1
I/O
I/O
41
I/O
I/O
2
DCLK, I/O
DCLK, I/O
42
I/O
I/O
3
NC
I/O
43
I/O
I/O
4
I/O
WD, I/O
44
GND
GND
5
I/O
WD, I/O
45
I/O
I/O
6
NC
VCCI
46
I/O
I/O
7
I/O
I/O
47
I/O
I/O
8
I/O
I/O
48
I/O
I/O
9
I/O
I/O
49
GND
GND
10
NC
I/O
50
I/O
I/O
11
GND
GND
51
I/O
I/O
12
NC
I/O
52
NC
I/O
13
I/O
WD, I/O
53
I/O
I/O
14
I/O
WD, I/O
54
NC
VCCA
15
I/O
I/O
55
I/O
I/O
16
PRB, I/O
PRB, I/O
56
I/O
I/O
17
I/O
I/O
57
VCCA
VCCA
18
CLKB, I/O
CLKB, I/O
58
VCCI
VCCI
19
I/O
I/O
59
GND
GND
20
VCCA
VCCA
60
VCCA
VCCA
21
CLKA, I/O
CLKA, I/O
61
GND
GND
22
I/O
I/O
62
I/O
TCK, I/O
23
PRA, I/O
PRA, I/O
63
I/O
I/O
24
NC
WD, I/O
64
GND
GND
25
I/O
WD, I/O
65
I/O
I/O
26
I/O
I/O
66
I/O
I/O
27
I/O
I/O
67
I/O
I/O
28
NC
I/O
68
I/O
I/O
29
I/O
WD, I/O
69
GND
GND
30
GND
GND
70
NC
I/O
31
NC
WD, I/O
71
I/O
I/O
32
I/O
I/O
72
I/O
I/O
33
I/O
I/O
73
I/O
I/O
34
I/O
I/O
74
I/O
I/O
35
NC
VCCI
75
NC
I/O
36
I/O
WD, I/O
76
I/O
I/O
37
I/O
WD, I/O
77
NC
I/O
38
SDI, I/O
SDI, I/O
78
I/O
I/O
39
I/O
I/O
79
NC
I/O
40
GND
GND
80
GND
GND
v3.1
2-9
40MX and 42MX Automotive FPGA Families
160-Pin PQFP
160-Pin PQFP
Pin Number
A42MX09
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX24
Function
81
I/O
I/O
121
I/O
I/O
82
SDO, I/O
SDO, TDO, I/O
122
I/O
I/O
83
I/O
WD, I/O
123
I/O
I/O
84
I/O
WD, I/O
124
NC
I/O
85
I/O
I/O
125
GND
GND
86
NC
VCCI
126
I/O
I/O
87
I/O
I/O
127
I/O
I/O
88
I/O
WD, I/O
128
I/O
I/O
89
GND
GND
129
NC
I/O
90
NC
I/O
130
GND
GND
91
I/O
I/O
131
I/O
I/O
92
I/O
I/O
132
I/O
I/O
93
I/O
I/O
133
I/O
I/O
94
I/O
I/O
134
I/O
I/O
95
I/O
I/O
135
NC
VCCA
96
I/O
WD, I/O
136
I/O
I/O
97
I/O
I/O
137
I/O
I/O
98
VCCA
VCCA
138
NC
VCCA
2 -1 0
99
GND
GND
139
VCCI
VCCI
100
NC
I/O
140
GND
GND
101
I/O
I/O
141
NC
I/O
102
I/O
I/O
142
I/O
I/O
103
NC
I/O
143
I/O
I/O
104
I/O
I/O
144
I/O
I/O
105
I/O
I/O
145
GND
GND
106
I/O
WD, I/O
146
NC
I/O
107
I/O
WD, I/O
147
I/O
I/O
108
I/O
I/O
148
I/O
I/O
109
GND
GND
149
I/O
I/O
110
NC
I/O
150
NC
VCCA
111
I/O
WD, I/O
151
NC
I/O
112
I/O
WD, I/O
152
NC
I/O
113
I/O
I/O
153
NC
I/O
114
NC
VCCI
154
NC
I/O
115
I/O
WD, I/O
155
GND
GND
116
NC
WD, I/O
156
I/O
I/O
117
I/O
I/O
157
I/O
I/O
118
I/O
TDI, I/O
158
I/O
I/O
119
I/O
TMS, I/O
159
MODE
MODE
120
GND
GND
160
GND
GND
v3.1
40MX and 42MX Automotive FPGA Families
80-Pin VQFP
80
1
80-Pin
VQFP
Figure 2-5 • 80-Pin VQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-11
40MX and 42MX Automotive FPGA Families
80-Pin VQFP
80-Pin VQFP
Pin Number
A40MX02
Function
A40MX04
Function
Pin Number
A40MX02
Function
A40MX04
Function
1
I/O
I/O
44
I/O
I/O
2
NC
I/O
45
I/O
I/O
3
NC
I/O
46
I/O
I/O
4
NC
I/O
47
GND
GND
5
I/O
I/O
48
I/O
I/O
2 -1 2
6
I/O
I/O
49
I/O
I/O
7
GND
GND
50
CLK, I/O
CLK, I/O
8
I/O
I/O
51
I/O
I/O
9
I/O
I/O
52
MODE
MODE
10
I/O
I/O
53
VCC
VCC
11
I/O
I/O
54
NC
I/O
12
I/O
I/O
55
NC
I/O
13
VCC
VCC
56
NC
I/O
14
I/O
I/O
57
SDI, I/O
SDI, I/O
15
I/O
I/O
58
DCLK, I/O
DCLK, I/O
16
I/O
I/O
59
PRA, I/O
PRA, I/O
17
NC
I/O
60
NC
NC
18
NC
I/O
61
PRB, I/O
PRB, I/O
19
NC
I/O
62
I/O
I/O
20
VCC
VCC
63
I/O
I/O
21
I/O
I/O
64
I/O
I/O
22
I/O
I/O
65
I/O
I/O
23
I/O
I/O
66
I/O
I/O
24
I/O
I/O
67
I/O
I/O
25
I/O
I/O
68
GND
GND
26
I/O
I/O
69
I/O
I/O
27
GND
GND
70
I/O
I/O
28
I/O
I/O
71
I/O
I/O
29
I/O
I/O
72
I/O
I/O
30
I/O
I/O
73
I/O
I/O
31
I/O
I/O
74
VCC
VCC
32
I/O
I/O
75
I/O
I/O
33
VCC
VCC
76
I/O
I/O
34
I/O
I/O
77
I/O
I/O
35
I/O
I/O
78
I/O
I/O
36
I/O
I/O
79
I/O
I/O
37
I/O
I/O
80
I/O
I/O
38
I/O
I/O
39
I/O
I/O
40
I/O
I/O
41
NC
I/O
42
NC
I/O
43
NC
I/O
v3.1
40MX and 42MX Automotive FPGA Families
208-Pin PQFP
1
208
208-Pin PQFP
Figure 2-6 • 208-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-13
40MX and 42MX Automotive FPGA Families
208-Pin PQFP
208-Pin PQFP
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
1
GND
GND
GND
36
I/O
I/O
I/O
2
NC
VCCA
VCCA
37
I/O
I/O
I/O
3
MODE
MODE
MODE
38
I/O
I/O
I/O
4
I/O
I/O
I/O
39
I/O
I/O
I/O
5
I/O
I/O
I/O
40
I/O
I/O
I/O
6
I/O
I/O
I/O
41
NC
I/O
I/O
7
I/O
I/O
I/O
42
NC
I/O
I/O
8
I/O
I/O
I/O
43
NC
I/O
I/O
9
NC
I/O
I/O
44
I/O
I/O
I/O
10
NC
I/O
I/O
45
I/O
I/O
I/O
11
NC
I/O
I/O
46
I/O
I/O
I/O
12
I/O
I/O
I/O
47
I/O
I/O
I/O
13
I/O
I/O
I/O
48
I/O
I/O
I/O
14
I/O
I/O
I/O
49
I/O
I/O
I/O
15
I/O
I/O
I/O
50
NC
I/O
I/O
16
NC
I/O
I/O
51
NC
I/O
I/O
17
VCCA
VCCA
VCCA
52
GND
GND
GND
18
I/O
I/O
I/O
53
GND
GND
GND
19
I/O
I/O
I/O
54
I/O
TMS, I/O
TMS, I/O
20
I/O
I/O
I/O
55
I/O
TDI, I/O
TDI, I/O
21
I/O
I/O
I/O
56
I/O
I/O
I/O
22
GND
GND
GND
57
I/O
WD, I/O
WD, I/O
23
I/O
I/O
I/O
58
I/O
WD, I/O
WD, I/O
24
I/O
I/O
I/O
59
I/O
I/O
I/O
25
I/O
I/O
I/O
60
VCCI
VCCI
VCCI
26
I/O
I/O
I/O
61
NC
I/O
I/O
27
GND
GND
GND
62
NC
I/O
I/O
28
VCCI
VCCI
VCCI
63
I/O
I/O
I/O
29
VCCA
VCCA
VCCA
64
I/O
I/O
I/O
30
I/O
I/O
I/O
65
I/O
I/O
QCLKA, I/O
31
I/O
I/O
I/O
66
I/O
WD, I/O
WD, I/O
32
VCCA
VCCA
VCCA
67
NC
WD, I/O
WD, I/O
33
I/O
I/O
I/O
68
NC
I/O
I/O
34
I/O
I/O
I/O
69
I/O
I/O
I/O
35
I/O
I/O
I/O
70
I/O
WD, I/O
WD, I/O
2 -1 4
v3.1
40MX and 42MX Automotive FPGA Families
208-Pin PQFP
208-Pin PQFP
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
71
I/O
WD, I/O
WD, I/O
106
NC
VCCA
VCCA
72
I/O
I/O
I/O
107
I/O
I/O
I/O
73
I/O
I/O
I/O
108
I/O
I/O
I/O
74
I/O
I/O
I/O
109
I/O
I/O
I/O
75
I/O
I/O
I/O
110
I/O
I/O
I/O
76
I/O
I/O
I/O
111
I/O
I/O
I/O
77
I/O
I/O
I/O
112
NC
I/O
I/O
78
GND
GND
GND
113
NC
I/O
I/O
79
VCCA
VCCA
VCCA
114
NC
I/O
I/O
80
NC
VCCI
VCCI
115
NC
I/O
I/O
81
I/O
I/O
I/O
116
I/O
I/O
I/O
82
I/O
I/O
I/O
117
I/O
I/O
I/O
83
I/O
I/O
I/O
118
I/O
I/O
I/O
84
I/O
I/O
I/O
119
I/O
I/O
I/O
85
I/O
WD, I/O
WD, I/O
120
I/O
I/O
I/O
86
I/O
WD, I/O
WD, I/O
121
I/O
I/O
I/O
87
I/O
I/O
I/O
122
I/O
I/O
I/O
88
I/O
I/O
I/O
123
I/O
I/O
I/O
89
NC
I/O
I/O
124
I/O
I/O
I/O
90
NC
I/O
I/O
125
I/O
I/O
I/O
91
I/O
I/O
QCLKB, I/O
126
GND
GND
GND
92
I/O
I/O
I/O
127
I/O
I/O
I/O
93
I/O
WD, I/O
WD, I/O
128
I/O
TCK, I/O
TCK, I/O
94
I/O
WD, I/O
WD, I/O
129
GND
GND
GND
95
NC
I/O
I/O
130
VCCA
VCCA
VCCA
96
NC
I/O
I/O
131
GND
GND
GND
97
NC
I/O
I/O
132
VCCI
VCCI
VCCI
98
VCCI
VCCI
VCCI
133
VCCA
VCCA
VCCA
99
I/O
I/O
I/O
134
I/O
I/O
I/O
100
I/O
WD, I/O
WD, I/O
135
I/O
I/O
I/O
101
I/O
WD, I/O
WD, I/O
136
VCCA
VCCA
VCCA
102
I/O
I/O
I/O
137
I/O
I/O
I/O
103
SDO, I/O
138
I/O
I/O
I/O
104
I/O
I/O
I/O
139
I/O
I/O
I/O
105
GND
GND
GND
140
I/O
I/O
I/O
SDO, TDO, I/O SDO, TDO, I/O
v3.1
2-15
40MX and 42MX Automotive FPGA Families
208-Pin PQFP
208-Pin PQFP
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
Pin Number
A42MX16
Function
A42MX24
Function
A42MX36
Function
141
NC
I/O
I/O
176
I/O
WD, I/O
WD, I/O
142
I/O
I/O
I/O
177
I/O
WD, I/O
WD, I/O
143
I/O
I/O
I/O
178
PRA, I/O
PRA, I/O
PRA, I/O
144
I/O
I/O
I/O
179
I/O
I/O
I/O
145
I/O
I/O
I/O
180
CLKA, I/O
CLKA, I/O
CLKA, I/O
146
NC
I/O
I/O
181
NC
I/O
I/O
147
NC
I/O
I/O
182
NC
VCCI
VCCI
148
NC
I/O
I/O
183
VCCA
VCCA
VCCA
149
NC
I/O
I/O
184
GND
GND
GND
150
GND
GND
GND
185
I/O
I/O
I/O
151
I/O
I/O
I/O
186
CLKB, I/O
CLKB, I/O
CLKB, I/O
152
I/O
I/O
I/O
187
I/O
I/O
I/O
153
I/O
I/O
I/O
188
PRB, I/O
PRB, I/O
PRB, I/O
154
I/O
I/O
I/O
189
I/O
I/O
I/O
155
I/O
I/O
I/O
190
I/O
WD, I/O
WD, I/O
156
I/O
I/O
I/O
191
I/O
WD, I/O
WD, I/O
157
GND
GND
GND
192
I/O
I/O
I/O
158
I/O
I/O
I/O
193
NC
I/O
I/O
159
SDI, I/O
SDI, I/O
SDI, I/O
194
NC
WD, I/O
WD, I/O
160
I/O
I/O
I/O
195
NC
WD, I/O
WD, I/O
161
I/O
WD, I/O
WD, I/O
196
I/O
I/O
QCLKC, I/O
162
I/O
WD, I/O
WD, I/O
197
NC
I/O
I/O
163
I/O
I/O
I/O
198
I/O
I/O
I/O
164
VCCI
VCCI
VCCI
199
I/O
I/O
I/O
165
NC
I/O
I/O
200
I/O
I/O
I/O
166
NC
I/O
I/O
201
NC
I/O
I/O
167
I/O
I/O
I/O
202
VCCI
VCCI
VCCI
168
I/O
WD, I/O
WD, I/O
203
I/O
WD, I/O
WD, I/O
169
I/O
WD, I/O
WD, I/O
204
I/O
WD, I/O
WD, I/O
170
I/O
I/O
I/O
205
I/O
I/O
I/O
171
NC
I/O
QCLKD, I/O
206
I/O
I/O
I/O
172
I/O
I/O
I/O
207
DCLK, I/O
DCLK, I/O
DCLK, I/O
173
I/O
I/O
I/O
208
I/O
I/O
I/O
174
I/O
I/O
I/O
175
I/O
I/O
I/O
2 -1 6
v3.1
40MX and 42MX Automotive FPGA Families
•
•
•
240-Pin PQFP
240
1
240-Pin
PQFP
•
•
•
•
•
•
•
•
•
Figure 2-7 • 240-Pin PQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-17
40MX and 42MX Automotive FPGA Families
240-Pin PQFP
2 -1 8
240-Pin PQFP
240-Pin PQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
1
I/O
41
I/O
81
I/O
2
DCLK, I/O
42
I/O
82
I/O
3
I/O
43
I/O
83
I/O
4
I/O
44
I/O
84
I/O
5
I/O
45
QCLKD, I/O
85
VCCA
6
WD, I/O
46
I/O
86
I/O
7
WD, I/O
47
WD, I/O
87
I/O
8
VCCI
48
WD, I/O
88
VCCA
9
I/O
49
I/O
89
VCCI
10
I/O
50
I/O
90
VCCA
11
I/O
51
I/O
91
GND
12
I/O
52
VCCI
92
TCK, I/O
13
I/O
53
I/O
93
I/O
14
I/O
54
WD, I/O
94
GND
15
QCLKC, I/O
55
WD, I/O
95
I/O
16
I/O
56
I/O
96
I/O
17
WD, I/O
57
SDI, I/O
97
I/O
18
WD, I/O
58
I/O
98
I/O
19
I/O
59
VCCA
99
I/O
20
I/O
60
GND
100
I/O
21
WD, I/O
61
GND
101
I/O
22
WD, I/O
62
I/O
102
I/O
23
I/O
63
I/O
103
I/O
24
PRB, I/O
64
I/O
104
I/O
25
I/O
65
I/O
105
I/O
26
CLKB, I/O
66
I/O
106
I/O
27
I/O
67
I/O
107
I/O
28
GND
68
I/O
108
VCCI
29
VCCA
69
I/O
109
I/O
30
VCCI
70
I/O
110
I/O
31
I/O
71
VCCI
111
I/O
32
CLKA, I/O
72
I/O
112
I/O
33
I/O
73
I/O
113
I/O
34
PRA, I/O
74
I/O
114
I/O
35
I/O
75
I/O
115
I/O
36
I/O
76
I/O
116
I/O
37
WD, I/O
77
I/O
117
I/O
38
WD, I/O
78
I/O
118
VCCA
39
I/O
79
I/O
119
GND
40
I/O
80
I/O
120
GND
v3.1
40MX and 42MX Automotive FPGA Families
240-Pin PQFP
240-Pin PQFP
240-Pin PQFP
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
Pin
Number
A42MX36
Function
121
GND
161
I/O
201
I/O
122
I/O
162
I/O
202
I/O
123
SDO, TDO, I/O
163
WD, I/O
203
I/O
124
I/O
164
WD, I/O
204
I/O
125
WD, I/O
165
I/O
205
I/O
126
WD, I/O
166
QCLKA, I/O
206
VCCA
127
I/O
167
I/O
207
I/O
128
VCCI
168
I/O
208
I/O
129
I/O
169
I/O
209
VCCA
130
I/O
170
I/O
210
VCCI
131
I/O
171
I/O
211
I/O
132
WD, I/O
172
VCCI
212
I/O
133
WD, I/O
173
I/O
213
I/O
134
I/O
174
WD, I/O
214
I/O
135
QCLKB, I/O
175
WD, I/O
215
I/O
136
I/O
176
I/O
216
I/O
137
I/O
177
I/O
217
I/O
138
I/O
178
TDI, I/O
218
I/O
139
I/O
179
TMS, I/O
219
VCCA
140
I/O
180
GND
220
I/O
141
I/O
181
VCCA
221
I/O
142
WD, I/O
182
GND
222
I/O
143
WD, I/O
183
I/O
223
I/O
144
I/O
184
I/O
224
I/O
145
I/O
185
I/O
225
I/O
146
I/O
186
I/O
226
I/O
147
I/O
187
I/O
227
VCCI
148
I/O
188
I/O
228
I/O
149
I/O
189
I/O
229
I/O
150
VCCI
190
I/O
230
I/O
151
VCCA
191
I/O
231
I/O
152
GND
192
VCCI
232
I/O
153
I/O
193
I/O
233
I/O
154
I/O
194
I/O
234
I/O
155
I/O
195
I/O
235
I/O
156
I/O
196
I/O
236
I/O
157
I/O
197
I/O
237
GND
158
I/O
198
I/O
238
MODE
159
WD, I/O
199
I/O
239
VCCA
160
WD, I/O
200
I/O
240
GND
v3.1
2-19
40MX and 42MX Automotive FPGA Families
100-Pin VQFP
100
1
100-Pin
VQFP
Figure 2-8 • 100-Pin VQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
2 -2 0
v3.1
40MX and 42MX Automotive FPGA Families
100-Pin VQFP
100-Pin VQFP
Pin Number
A42MX09
Function
A42MX16
Function
Pin Number
A42MX09
Function
A42MX16
Function
1
I/O
I/O
36
I/O
I/O
2
MODE
MODE
37
I/O
I/O
3
I/O
I/O
38
VCCA
VCCA
4
I/O
I/O
39
I/O
I/O
5
I/O
I/O
40
I/O
I/O
6
I/O
I/O
41
I/O
I/O
7
GND
GND
42
I/O
I/O
8
I/O
I/O
43
I/O
I/O
9
I/O
I/O
44
GND
GND
10
I/O
I/O
45
I/O
I/O
11
I/O
I/O
46
I/O
I/O
12
I/O
I/O
47
I/O
I/O
13
I/O
I/O
48
I/O
I/O
14
VCCA
NC
49
I/O
I/O
15
VCCI
VCCI
50
SDO, I/O
SDO, I/O
16
I/O
I/O
51
I/O
I/O
17
I/O
I/O
52
I/O
I/O
18
I/O
I/O
53
I/O
I/O
19
I/O
I/O
54
I/O
I/O
20
GND
GND
55
GND
GND
21
I/O
I/O
56
I/O
I/O
22
I/O
I/O
57
I/O
I/O
23
I/O
I/O
58
I/O
I/O
24
I/O
I/O
59
I/O
I/O
25
I/O
I/O
60
I/O
I/O
26
I/O
I/O
61
I/O
I/O
27
I/O
I/O
62
GND
GND
28
I/O
I/O
63
VCCA
VCCA
29
I/O
I/O
64
VCCI
VCCI
30
I/O
I/O
65
VCCA
VCCA
31
I/O
I/O
66
I/O
I/O
32
GND
GND
67
I/O
I/O
33
I/O
I/O
68
I/O
I/O
34
I/O
I/O
69
I/O
I/O
35
I/O
I/O
70
GND
GND
v3.1
2-21
40MX and 42MX Automotive FPGA Families
100-Pin VQFP
Pin Number
A42MX09
Function
A42MX16
Function
71
I/O
I/O
72
I/O
I/O
73
I/O
I/O
74
I/O
I/O
75
I/O
I/O
76
I/O
I/O
77
SDI, I/O
SDI, I/O
78
I/O
I/O
79
I/O
I/O
80
I/O
I/O
81
I/O
I/O
82
GND
GND
83
I/O
I/O
84
I/O
I/O
85
PRA, I/O
PRA, I/O
86
I/O
I/O
87
CLKA, I/O
CLKA, I/O
88
VCCA
VCCA
89
I/O
I/O
90
CLKB, I/O
CLKB, I/O
91
I/O
I/O
92
PRB, I/O
PRB, I/O
93
I/O
I/O
94
GND
GND
95
I/O
I/O
96
I/O
I/O
97
I/O
I/O
98
I/O
I/O
99
I/O
I/O
100
DCLK, I/O
DCLK, I/O
2 -2 2
v3.1
40MX and 42MX Automotive FPGA Families
176-Pin TQFP
176
1
176-Pin
TQFP
Figure 2-9 • 176-Pin TQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-23
40MX and 42MX Automotive FPGA Families
176-Pin TQFP
176-Pin TQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
1
GND
GND
GND
36
I/O
I/O
I/O
2
MODE
MODE
MODE
37
NC
I/O
I/O
3
I/O
I/O
I/O
38
NC
NC
I/O
4
I/O
I/O
I/O
39
I/O
I/O
I/O
5
I/O
I/O
I/O
40
I/O
I/O
I/O
6
I/O
I/O
I/O
41
I/O
I/O
I/O
7
I/O
I/O
I/O
42
I/O
I/O
I/O
8
NC
NC
I/O
43
I/O
I/O
I/O
9
I/O
I/O
I/O
44
I/O
I/O
I/O
10
NC
I/O
I/O
45
GND
GND
GND
11
NC
I/O
I/O
46
I/O
I/O
TMS, I/O
12
I/O
I/O
I/O
47
I/O
I/O
TDI, I/O
13
NC
VCCA
VCCA
48
I/O
I/O
I/O
14
I/O
I/O
I/O
49
I/O
I/O
WD, I/O
15
I/O
I/O
I/O
50
I/O
I/O
WD, I/O
16
I/O
I/O
I/O
51
I/O
I/O
I/O
17
I/O
I/O
I/O
52
NC
VCCI
VCCI
18
GND
GND
GND
53
I/O
I/O
I/O
19
NC
I/O
I/O
54
NC
I/O
I/O
20
NC
I/O
I/O
55
NC
I/O
WD, I/O
21
I/O
I/O
I/O
56
I/O
I/O
WD, I/O
22
NC
I/O
I/O
57
NC
NC
I/O
23
GND
GND
GND
58
I/O
I/O
I/O
24
NC
VCCI
VCCI
59
I/O
I/O
WD, I/O
25
VCCA
VCCA
VCCA
60
I/O
I/O
WD, I/O
26
NC
I/O
I/O
61
NC
I/O
I/O
27
NC
I/O
I/O
62
I/O
I/O
I/O
28
VCCI
VCCA
VCCA
63
I/O
I/O
I/O
29
NC
I/O
I/O
64
NC
I/O
I/O
30
I/O
I/O
I/O
65
I/O
I/O
I/O
31
I/O
I/O
I/O
66
NC
I/O
I/O
32
I/O
I/O
I/O
67
GND
GND
GND
33
NC
NC
I/O
68
VCCA
VCCA
VCCA
34
I/O
I/O
I/O
69
I/O
I/O
WD, I/O
35
I/O
I/O
I/O
70
I/O
I/O
WD, I/O
2 -2 4
v3.1
40MX and 42MX Automotive FPGA Families
176-Pin TQFP
176-Pin TQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
71
I/O
I/O
I/O
106
GND
GND
GND
72
I/O
I/O
I/O
107
NC
I/O
I/O
73
I/O
I/O
I/O
108
NC
I/O
TCK, I/O
74
NC
I/O
I/O
109
LP
LP
LP
75
I/O
I/O
I/O
110
VCCA
VCCA
VCCA
76
I/O
I/O
I/O
111
GND
GND
GND
77
NC
NC
WD, I/O
112
VCCI
VCCI
VCCI
78
NC
I/O
WD, I/O
113
VCCA
VCCA
VCCA
79
I/O
I/O
I/O
114
NC
I/O
I/O
80
NC
I/O
I/O
115
NC
I/O
I/O
81
I/O
I/O
I/O
116
NC
VCCA
VCCA
82
NC
VCCI
VCCI
117
I/O
I/O
I/O
83
I/O
I/O
I/O
118
I/O
I/O
I/O
84
I/O
I/O
WD, I/O
119
I/O
I/O
I/O
85
I/O
I/O
WD, I/O
120
I/O
I/O
I/O
86
NC
I/O
I/O
121
NC
NC
I/O
87
SDO, I/O
SDO, I/O
SDO, TDO, I/O
122
I/O
I/O
I/O
88
I/O
I/O
I/O
123
I/O
I/O
I/O
89
GND
GND
GND
124
NC
I/O
I/O
90
I/O
I/O
I/O
125
NC
I/O
I/O
91
I/O
I/O
I/O
126
NC
NC
I/O
92
I/O
I/O
I/O
127
I/O
I/O
I/O
93
I/O
I/O
I/O
128
I/O
I/O
I/O
94
I/O
I/O
I/O
129
I/O
I/O
I/O
95
I/O
I/O
I/O
130
I/O
I/O
I/O
96
NC
I/O
I/O
131
I/O
I/O
I/O
97
NC
I/O
I/O
132
I/O
I/O
I/O
98
I/O
I/O
I/O
133
GND
GND
GND
99
I/O
I/O
I/O
134
I/O
I/O
I/O
100
I/O
I/O
I/O
135
SDI, I/O
SDI, I/O
SDI, I/O
101
NC
NC
I/O
136
NC
I/O
I/O
102
I/O
I/O
I/O
137
I/O
I/O
WD, I/O
103
NC
I/O
I/O
138
I/O
I/O
WD, I/O
104
I/O
I/O
I/O
139
I/O
I/O
I/O
105
I/O
I/O
I/O
140
NC
VCCI
VCCI
v3.1
2-25
40MX and 42MX Automotive FPGA Families
176-Pin TQFP
176-Pin TQFP
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
Pin Number
A42MX09
Function
A42MX16
Function
A42MX24
Function
141
I/O
I/O
I/O
159
I/O
I/O
I/O
142
I/O
I/O
I/O
160
PRB, I/O
PRB, I/O
PRB, I/O
143
NC
I/O
I/O
161
NC
I/O
WD, I/O
144
NC
I/O
WD, I/O
162
I/O
I/O
WD, I/O
145
NC
NC
WD, I/O
163
I/O
I/O
I/O
146
I/O
I/O
I/O
164
I/O
I/O
I/O
147
NC
I/O
I/O
165
NC
NC
WD, I/O
148
I/O
I/O
I/O
166
NC
I/O
WD, I/O
149
I/O
I/O
I/O
167
I/O
I/O
I/O
150
I/O
I/O
WD, I/O
168
NC
I/O
I/O
151
NC
I/O
WD, I/O
169
I/O
I/O
I/O
152
PRA, I/O
PRA, I/O
PRA, I/O
170
NC
VCCI
VCCI
153
I/O
I/O
I/O
171
I/O
I/O
WD, I/O
154
CLKA, I/O
CLKA, I/O
CLKA, I/O
172
I/O
I/O
WD, I/O
155
VCCA
VCCA
VCCA
173
NC
I/O
I/O
156
GND
GND
GND
174
I/O
I/O
I/O
157
I/O
I/O
I/O
175
DCLK, I/O
DCLK, I/O
DCLK, I/O
158
CLKB, I/O
CLKB, I/O
CLKB, I/O
176
I/O
I/O
I/O
2 -2 6
v3.1
40MX and 42MX Automotive FPGA Families
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version
v3.0
Changes in Current Version v3.1
A note was added to the "Ordering Information".
Page
ii
April 2004
Note 1 was added to "Recommended Operating Conditions".
v2.0
The "Speed Grade and Temperature Grade Matrix" table is new.
page 1-ii
1-12
The "Clock Networks" section was updated.
page 1-4
The "I/O Modules" section was updated.
page 1-5
The "Other Architectural Features" section is new
page 1-5
The "Development Tool Support" section was updated.
page 1-11
The "Electrical Specifications" table was updated.
page 1-12
The "Junction Temperature" section was updated.
page 1-15
Table 1-6 was updated.
page 1-15
Figure 1-15 and Figure 1-16 were updated.
page 1-16
Figure 1-17 was updated.
page 1-17
Figure 1-18 was updated.
page 1-18
The "Critical Nets and Typical Nets" section was updated.
page 1-25
The "Timing Derating" section is new.
page 1-25
Table 1-7 and Figure 1-32 were updated.
page 1-26
Table 1-8 and Figure 1-33 were updated.
page 1-27
All timing numbers contained in Table 1-9 through Table 1-14 were updated.
The "Pin Descriptions" section was updated.
page 1-28 to
page 1-41
page 1-45
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as “Product Brief,” “Advanced,” “Production,” and “Web-only.” The
definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a advanced datasheet (advanced or production) containing general
product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
Unmarked (production)
This datasheet version contains information that is considered to be final.
v3.1
3-1
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
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