LAPIS ML9289 Vacuum fluorescent display tube controller driver Datasheet

FEDL9289-01
Issue Date: May. 15, 2009
ML9289-xx
Vacuum fluorescent display tube controller driver
GENERAL DESCRIPTION
The ML9289-xx is an alphanumeric type vacuum fluorescent display (VFD) tube controller driver IC which can
display alphanumeric characters, symbols, and bar charts.
Vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller. A
display system is easily realized by internal ROM and RAM for character display.
-01 is available as a general-purpose code.
Custom codes are provided on customer’s request.
FEATURES
: 3.3 V10% or 5.0 V10%
 Logic power supply (VDD)
 Vacuum fluorescent display tube driving power supply (VDISP)
: 20V to 42V
 VFD driver output current
(VFD driver output can be connected directly to the VFD tube. No pull-down resistor is required.)
• Segment driver (SEG1–16)
: –6 mA (VDISP = 42 V)
• Segment driver (AD1, 2)
: –15 mA (VDISP = 42 V)
• Grid driver (COM1–16)
: –30 mA (VDISP = 42 V)
 Content of display
• CGROM
: 16 segments
240 types (character data)
• CGRAM
: 16 segments
16 types (character data)
• ADRAM
: 16 (display digit)  2 bits (symbol data)
• DCRAM
: 16 (display digit)  8 bits (register for character data display)
 Display control function
• Display digits
: 1 to 16 digits
• Display duty (brightness adjustment)
: 16 stages
• All display lights ON/OFF
 Four interfaces with microcontroller:
DA, CS, CP, RESET
 Instruction executable with 1 byte (excluding data write for each RAM)
 Built-in oscillation circuit (resistor & capacitor connected externally)
 Package options:
AL-Pad Chip (ML9289-xxWA)
44-pin plastic QFP (QFP44-P-910-0.80-2K) (ML9289-xxGA)
48-pin plastic TQFP (TQFP48-P-0707-0.50-K) (ML9289-xxTB)
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BLOCK DIAGRAM
VDI SP
VDD
GND
DCRAM
16w  8b
CGRAM
16w  16b
RESET
DA
CP
CS
8 bit
Shift
Register
SEG1
CGROM
240w16b
ADRAM
16w  2b
Segment
Driver
SEG16
AD1
AD
Driver
AD2
Address
Selector
Command
Decoder
Write
Address
Counter
Read
Address
Counter
Control
Circuit
Digit
Control
Duty
Control
OSC0
Timing
Timing
Generator 1
Generator 2
COM1
Grid
Driver
COM16
Oscillator
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34 SEG7
37 SEG10
36 SEG9
35 SEG8
40 SEG12
39 GND
38 SEG11
44 SEG16
43 SEG15
42 SEG14
41 SEG13
PIN CONFIGURATION (TOP VIEW)
COM1
COM2
1
33 SEG6
2
32 SEG5
COM3
COM4
3
4
31 SEG4
30 SEG3
COM5
5
29 SEG2
COM6
COM7
6
7
28 SEG1
27 AD2
COM8
8
26 AD1
25 VDI SP
COM9 9
COM10 10
COM11 11
24 DA
CS 22
OSC0 19
VDD 20
RESET 21
GND 17
VDI SP 18
COM14 14
COM15 15
COM16 16
COM12 12
COM13 13
23 CP
44-Pin Plastic QFP
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FEDL9289-01
37 SEG7
40 SEG10
39 SEG9
38 SEG8
43 SEG12
42 GND
41 SEG11
47 SEG16
46 SEG15
45 SEG14
44 SEG13
48 N.C
ML9289-xx
36 SEG6
35 SEG5
COM1
COM2
1
COM3
COM4
3
4
COM5
5
34 SEG4
33 SEG3
32 SEG2
COM6
COM7
6
7
31 SEG1
30 AD2
COM8
8
29 AD1
28 VDI SP
2
COM9 9
COM10 10
COM11 11
25 CS
N.C:
N.C 24
VDD 22
RESET 23
COM16 18
GND 19
VDI SP 20
OSC0 21
COM14 16
COM15 17
12
N.C 13
COM12 14
COM13 15
N.C
27 DA
26 CP
No-Connection pin
48-Pin Plastic TQFP
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PIN CONFIGURATION
Pad Layout
Chip Size:
Chip Thickness:
Pad Size:
2.30  3.20 mm
280 ±30 m
Metal 90  90 m, PV Pad hole 70  70 m
Y
23
32
33
22
X
44
12
11
1
Pad Coordinates
Pad No
Symbol
X (m)
Y (m)
Pad No
Symbol
X (m)
Y (m)
1
SEG7
-638
-1465
23
COM12
811
1465
2
SEG8
-522
-1465
24
COM13
567
1465
3
SEG9
-406
-1465
25
COM14
323
1465
4
SEG10
-290
-1465
26
COM15
79
1465
5
SEG11
-174
-1465
27
COM16
-165
1465
6
GND
-39
-1465
28
GND
-435
1465
7
SEG12
91
-1465
29
VDISP
-575
1465
8
SEG13
207
-1465
30
OSC0
-715
1465
9
SEG14
323
-1465
31
VDD
-855
1465
10
SEG15
439
-1465
32
RESET
-1015
1465
11
SEG16
555
-1465
33
CS
-1015
1225
12
COM1
1015
-1308
34
CP
-1015
985
13
COM2
1015
-1064
35
DA
-1015
745
14
COM3
1015
-820
36
VDISP
-1015
415
15
COM4
1015
-576
37
AD1
-1015
196
16
COM5
1015
-332
38
AD2
-1015
65
17
COM6
1015
-88
39
SEG1
-1015
-123
18
COM7
1015
156
40
SEG2
-1015
-253
19
COM8
1015
400
41
SEG3
-1015
-383
20
COM9
1015
644
42
SEG4
-1015
-513
21
COM10
1015
888
43
SEG5
-1015
-643
22
COM11
1015
1132
44
SEG6
-1015
-773
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PIN DESCRIPTION
Pin
QFP
TQFP
28–38,
40–44
31-41,
1–16
43-47
1-11,
14-18
Symbol
Type
Connects to
SEG1–16
O
VFD tube anode
electrode
VFD tube anode electrode drive output.
Directly connected to the VFD tube and no pull-down
resistor is required. IOH > –6 mA
COM1–16
O
VFD tube grid
electrode
VFD tube grid electrode drive output.
Directly connected to the VFD tube and no pull-down
resistor is required. IOH > –30 mA
O
VFD tube anode
electrode
VFD tube anode electrode drive output.
Directly connected to the VFD tube and no pull-down
resistor is required. IOH > –15 mA
26, 27
29,30
AD1–2
18, 25
20,28
VDISP
20
22
VDD
17,39
19,42
GND
—
Power supply
Description
The voltage supply between VDD and GND is for the
power supply for the internal logic.
The voltage supply between VDISP and GND is for the
power supply for driving the VFD tube.
Apply power to VDD first, then to VDISP.
Serial data input pin.
24
27
DA
I
Microcontroller
23
26
CP
I
Microcontroller
Shift clock input pin.
Serial data is shifted in on a rising edge of CP when CS
pin is “L” level.
22
25
CS
I
Microcontroller
Chip select input pin.
Serial data transfer is enabled when CS pin is “L” level.
21
23
RESET
l
Microcontroller
Data is input from the LSB.
Reset input.
Setting this pin to “Low” initializes all the functions.
Initial status is as follows.
• Address of each RAM ...............Address “00”H
• Data of each RAM.....................Content is undefined
• Display digit...............................16 digits
• Brightness adjustment ..............0/16
• All display lights ON or OFF......OFF mode
• All outputs .................................Low level
Pin for RC oscillation.
Resistors and capacitors are connected externally and
constants vary depending on the VDD voltage used.
The target oscillation frequency is 2MHz.
19
21
OSC0
I/O
C1, R1
OSC0
(RC oscillator circuit)
C1
-
12,13,
24,48
N.C
-
Open
R1
*Refer
Circuit.
to
the
Application
No-Connection pin.
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ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Supply Voltage (1)
Supply Voltage (2)
Input Voltage
VDD
VDISP
VlN
–0.3 to +6.5
–0.3 to +45
–0.3 to VDD+0.3
V
V
V
Power Dissipation
PD
—
—
—
Ta 25C
44-pin plastic QFP
541
mW
TSTG
—
–55 to +150
C
lO1
lO2
IO3
COM1–16
AD1–2
SEG1–16
–40 to 0.0
–20 to 0.0
–10 to 0.0
mA
mA
mA
Storage
Temperature
Output Current
RECOMMENDED OPERATING CONDITIONS-1
 When the unit power supply voltage is 5.0 V (typ.)
Parameter
Symbol
Supply Voltage (1)
Supply Voltage (2)
High Level Input Voltage
Low Level Input Voltage
CP frequency
Self-oscillation frequency
VDD
VDISP
VIH
VIL
fC
fOSC
Frame Frequency
fFR
Operating Temperature
Top
Tj
Condition
—
—
All input pins except OSC0
All input pins except OSC0
—
R1 = 8.2 k5%, C1 = 82 pF5%
DIGIT = 1 to16, R1 = 8.2 k5%,
C1 = 82 pF5%
44-pin plastic QFP
AL-Pad Chip
Min.
Typ.
Max.
Unit
4.5
20
0.7 VDD
—
—
1.4
5.0
—
—
—
—
2.0
5.5
42
—
0.3 VDD
2.0
2.6
V
V
V
V
MHz
MHz
170
244
318
Hz
–40
–40
—
—
85
105
C
Min.
Typ.
Max.
Unit
3.0
20
0.8 VDD
—
—
1.4
3.3
—
—
—
—
2.0
3.6
42
—
0.2 VDD
2.0
2.6
V
V
V
V
MHz
MHz
170
244
318
Hz
–40
–40
—
—
85
105
C
RECOMMENDED OPERATING CONDITIONS-2
 When the unit power supply voltage is 3.3 V (typ.)
Parameter
Symbol
Supply Voltage (1)
Supply Voltage (2)
High Level Input Voltage
Low Level Input Voltage
CP frequency
Self-oscillation frequency
VDD
VDISP
VIH
VIL
fC
fOSC
Frame Frequency
fFR
Operating Temperature
Top
Tj
Condition
—
—
All input pins except OSC0
All input pins except OSC0
—
R1 = 6.8 k5%, C1 = 82 pF5%
DIGIT = 1 to 16,
R1 = 6.8 k5%, C1 = 82 pF5%
44-pin plastic QFP
AL-Pad Chip
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ELECTRICAL CHARACTERISTICS
DC Characteristics-1
(VDD=5.0V10%, VDISP=42V, Ta=–40to+85C, unless otherwise specified)
Parameter
Symbol
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current
IIH
Low Level Input Current
IIL
High Level Output
Voltage
VOH1
VOH2
VOH3
Low Level Output
Voltage
VOL1
Applied pin
CS, CP, DA,
RESET
CS, CP, DA,
RESET
CS, CP, DA,
RESET
CS, CP, DA,
RESET
COM1–16
AD1–2
SEG1–16
COM1–16
AD1–2
SEG1–16
IDD1
VDD
IDD2
fOSC =
2 MHz,
no load
Supply Current
IDISP1
VDISP
IDISP2
fOSC =
2 MHz,
no load
Condition
Min.
Max.
Unit
—
0.7 VDD
—
V
—
—
0.3
VDD
V
VIH = VDD
–1.0
1.0
A
VIL = 0V
–1.0
1.0
A
IOH1 = –30mA
IOH2 = –15mA
IOH3 = –6mA
VDISP – 1.5
VDISP – 1.5
VDISP– 1.5
—
—
—
V
V
V
—
—
1.0
V
—
3
mA
—
3
mA
—
1
mA
—
0.1
mA
Duty = 15/16
Digit =1–16
All output lights ON
Duty = 0/16
Digit = 1–8
All output lights OFF
Duty = 15/16
Digit =1–16
All output lights ON
Duty = 0/16
Digit = 1–8
All output lights OFF
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FEDL9289-01
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DC Characteristics-2
(VDD=3.3V10%, VDISP=42V, Ta=–40to+85C, unless otherwise specified)
Parameter
Symbol
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current
IIH
Low Level Input Current
IIL
High Level Output
Voltage
Low Level Output
Voltage
Applied pin
CS, CP,
DA, RESET
CS, CP,
DA, RESET
CS, CP,
DA, RESET
CS, CP,
DA, RESET
COM1–16
AD1–2
VOH3
VOL1
VOH1
VOH2
Condition
Min.
Max.
Unit
—
0.8 VDD
—
V
—
—
0.2
VDD
V
VIH = VDD
–1.0
1.0
A
VIL = 0V
–1.0
1.0
A
IOH1 = –30mA
IOH2 = –15mA
VDISP – 1.5
VDISP– 1.5
—
—
V
V
SEG1–16
IOH3 = –6mA
VDISP – 1.5
—
V
COM1–16
AD1–2
SEG1–16
—
—
1.0
V
—
2
mA
—
2
mA
—
1
mA
—
0.1
mA
IDD1
VDD
IDD2
fOSC =
2 MHz,
no load
Supply Current
IDISP1
VDISP
IDISP2
fOSC =
2 MHz,
no load
Duty = 15/16
Digit =1–16
All output lights ON
Duty = 0/16
Digit = 1–8
All output lights OFF
Duty = 15/16
Digit =1–16
All output lights ON
Duty = 0/16
Digit = 1–8
All output lights OFF
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AC Characteristics-1
(VDD=5.0V10%, VDISP=42V, Ta=–40to+85C, unless otherwise specified)
Parameter
CP Frequency
Symbol
Condition
Min.
Max.
Unit
fC
—
—
2.0
MHz
CP Pulse Width
tCW
—
250
—
ns
DA Setup Time
tDS
—
250
—
ns
DA Hold Time
tDH
—
250
—
ns
CS Setup Time
tCSS
—
250
—
ns
CS Hold Time
tCSH
R1 = 8.2 k5%, C1 = 82 pF5%
16
—
s
CS Wait Time
tCSW
—
250
—
ns
Data Processing Time
tDOFF
R1 = 8.2 k5%, C1 = 82 pF5%
8
—
s
RESET Pulse Width
tWRES
—
250
—
ns
RESET Time
tRSON
—
250
—
ns
DA Wait Time
tRSOFF
—
All Driver Output Slew
Rate
tR
tF
tR = 20 to 80%
tF = 80 to 20%
Cl = 100 pF
250
—
ns
—
—
2.0
2.0
s
s
AC Characteristics-2
(VDD=3.3V10%, VDISP=42V, Ta=–40 to+85C, unless otherwise specified)
Parameter
CP Frequency
Symbol
Condition
Min.
Max.
Unit
fC
—
—
2.0
MHz
CP Pulse Width
tCW
—
250
—
ns
DA Setup Time
tDS
—
250
—
ns
DA Hold Time
tDH
—
250
—
ns
CS Setup Time
tCSS
—
250
—
ns
CS Hold Time
tCSH
R1 = 6.8 k5%, C1 = 82 pF5%
16
—
s
CS Wait Time
tCSW
—
250
—
ns
Data Processing Time
tDOFF
R1 = 6.8 k5%, C1 = 82 pF5%
8
—
s
RESET Pulse Width
tWRES
—
250
—
ns
RESET Execution Time
tRSON
—
250
—
ns
DA Wait Time
tRSOFF
—
All Driver Output Slew
Rate
tR
tF
Cl = 100 pF
tR = 20 to 80%
tF = 80 to 20%
250
—
ns
—
—
2.0
2.0
s
s
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TIMING DIAGRAMS
1) Data Input Timing
Symbol
VDD = 3.3 V 10%
VDD = 5.0 V 10%
VIH
VIL
0.8 VDD
0.2 VDD
0.7 VDD
0.3 VDD
tCSS
tCSW
CS
VIH
VIL
tCSH
fC
tDOFF
CP
tDS
DA
tCW
tCW
VIH
VIL
tDH
VALID VALID
VIH
VIL
VALID VALID
2) Data Input Timing
VD D
0.8 VDD
GND
tRSON
RESET
t WRES
tRSOF F
VIH
0.5 VDD
VIL
VIH
VIL
DA
3) Output Timing
All driver outputs
tR
tF
0.8 VDI SP
0.2 VDI SP
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4) Digit Output Timing (16-Digit, 15/16-Duty)
T=8 1
fO SC
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
AD1-2
SEG1-16
Frame cycle t1 = 1024T (fos c = 2.0 MHz, t 1 = 4.096 ms)
Display timing t2 = 60T (f os c = 2.0 MHz, t 2 = 240 s)
(f os c = 2.0 MHz, t 3 = 16 s)
Blank timing
t3 = 4T
VDISP
GND
VDISP
GND
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FUNCTIONAL DESCRIPTION
Command List
Command
First byte
LSB
Second byte
MSB LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7 B0 B1
B2
B3
B4
B5
B6
B7
C0 C1
C2
C3
C4
C5
C6
C7
C0 C1
C2
C3
C4
C5
C6
C7
1
DCRAM data write
X0 X1 X2 X3
1
0
0
0
2
CGRAM data write
X0 X1 X2 X3
0
1
0
0
3
ADRAM data write
X0 X1 X2 X3
1
1
0
0
4
Display duty set
D0 D1 D2 D3
1
0
1
0
5
Number of digits set
K0 K1 K2 K3
0
1
1
0
6
All display lights
ON/OFF
1
1
1
0
L
H
*
*
2nd byte
C8 C9 C10 C11 C12 C13 C14 C15 3rd byte
C0 C1
*
Xn
Cn
Dn
Kn
H
L
Others (test mode)
*
*
*
*
*
*
: Don’t care
: Address setting for each RAM
: Character code setting for each RAM
: Display duty setting
: Setting of the number of display digits
: All display lights ON setting
: All display lights OFF setting
When data is written to RAM (DCRAM, CGRAM, and ADRAM) continuously, addresses are internally
incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd
and subsequent bytes.
Note: The test mode is used for inspection before shipment.
It is not a user function.
Positional Relationship Between SEGn and ADn (one digit)
C13
SEG14
C5
SEG6
C2
SEG3
C10
SEG11
C12
SEG13
C6
SEG7
C14
SEG15
C9
SEG10
C11
SEG12
C3
SEG4
C15
SEG16
C1
SEG2
C8
SEG9
C7
SEG8
C0
SEG1
C4
SEG5
C0–7: Corresponds to the 2nd byte of the CGRAM data write
command.
C8–15: Corresponds to the 3rd byte of the CGRAM data write command.
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Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to “Low” level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input
into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each
register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to “High” disables data transfer. Data input from the point when the CS pin changes from
“High” to “Low” is recognized in 8-bit units.
CS
tDOFF
tCSH
CP
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5 B6 B7
LSB
LSB
LSB
DA
When data is written
to DCRAM(*1)
1st byte
MSB
Command and address
data
2nd byte
MSB
Character code data
3rd byte
MSB
Character code data of
the next address
*1 When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally
incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the
2nd and subsequent bytes.
Reset Function
Reset is executed when the RESET pin is set to “L”, (when turning power on, for example) and initializes all
functions.
Initial status is as follows.
•
•
•
•
•
•
•
Address of each RAM .......................Address 00H
Data of each RAM ............................All contents are undefined.
Number of display digits ...................16 digits
Brightness adjustment .......................0/16
All display lights ON or OFF ............OFF mode
Segment output..................................All segment outputs go “Low.”
AD output..........................................All AD outputs go “Low.”
Be sure to execute the reset operation when turning power on and set again according to “Setting Flowchart”
after reset.
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Description of Commands and Functions
1. “DCRAM data write” command
(Specifies the address of DCRAM and writes the character code of CGROM and CGRAM.)
DCRAM (Data Control RAM) has a 4-bit address to store character codes of CGROM and CGRAM.
A character code specified by DCRAM is converted to an alphanumeric character pattern via CGROM or
CGRAM.
The DCRAM can store 16 characters worth of character codes.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
(1st)
X0 X1 X2 X3 1
0
0
0
: Setup and DCRAM address in the write mode
of DCRAM data are specified.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(2nd)
C0 C1 C2 C3 C4 C5 C6 C7
(Example: Specify DCRAM address 0H.)
: Specify character code of CGROM and CGRAM.
(It is written into DCRAM address 00H.)
To specify the character code of CGROM and CGRAM to the next address continuously, specify only character
code as follows.
Since the address of DCRAM is automatically incremented, address specification is unnecessary.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
C0 C1 C2 C3 C4 C5 C6 C7 :
(3rd)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
C0 C1 C2 C3 C4 C5 C6 C7 :
(4th)
Specify character code of CGROM and CGRAM.
(It is written into DCRAM address 1H.)
Specify character code of CGROM and CGRAM.
(It is written into DCRAM address 2H.)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
C0 C1 C2 C3 C4 C5 C6 C7 :
(17th)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
C0 C1 C2 C3 C4 C5 C6 C7 :
(18th)
Specify character code of CGROM and CGRAM.
(It is written into DCRAM address FH.)
Specify character code of CGROM and CGRAM.
(It is rewritten into DCRAM address 0H.)
X0 (LSB) to X3 (MSB): DCRAM address (4 bits: 16 characters worth)
C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters worth)
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[Relationship between DCRAM addresses setup and COM positions]
HEX
X0
X1
X2
X3
COM
position
HEX
X0
X1
X2
X3
COM
position
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
8
9
A
B
C
D
E
F
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
16/31
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2. “CGRAM data write” command
(Specifies the address of CGRAM and writes character pattern data.)
CGRAM (Character Generator RAM) has a 4-bit address to store alphanumeric character patterns.
A character pattern stored in CGRAM can be displayed by specifying the character code (address) by DCRAM.
The addresses of CGRAM are assigned to 00H to 0FH (All the other addresses are the CGROM addresses).
The CGRAM can store 16 types of character patterns.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
X0 X1 X2 X3
(1st)
: Setup and CGRAM address in the write-in
mode of CGRAM data are specified.
LSB
MSB (Example: Specify CGRAM address 00H.)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
C0 C1 C2 C3 C4 C5 C6 C7 : Specify 1st-column data.
(2nd)
(It is written into CGRAM address 00H.)
0
1
0
0
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
3rd byte
C8 C9 C10C11 C12 C13 C14C15 : Specify 2nd-column data.
(3rd)
(It is written into CGRAM address 00H.)
To specify character pattern data continuously to the next address, specify only character pattern data as follows.
Since the address of CGRAM is automatically incremented, address specification is unnecessary.
Data from the 2nd to 6th byte (character pattern) is regarded as one data item taken together, so 250ns s is
sufficient for tDOFF time between bytes.
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
C0 C1 C2 C3 C4 C5 C6 C7 : Specify 1st-column data.
(4th)
(It is written into CGRAM address 01H.)
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
3rd byte C8 C9 C10 C11 C12 C13 C14C15 :
Specify 2nd-column data.
(5th)
(It is written into CGRAM address 01H.)
X0 (LSB) to X3 (MSB): CGRAM address (4 bits: 16 characters worth)
C0 (LSB) to C15 (MSB): Character data of CGRAM (16 bits: 16 outputs per digit)
17/31
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[Positional relationship between CGRAM addresses setup and CGROM addresses]
HEX
X0
X1
X2
X3
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
CGROM
address
RAM00
RAM01
RAM02
RAM03
RAM04
RAM05
RAM06
RAM07
HEX
X0
X1
X2
X3
8
9
A
B
C
D
E
F
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
CGROM
address
RAM08
RAM09
RAM0A
RAM0B
RAM0C
RAM0D
RAM0E
RAM0F
Refer to the ROM Code Tables attached later in this document.
Positional Relationship Between CGROM and CGRAM outputs
C13
SEG14
C5
SEG6
C2
SEG3
C10
SEG11
C12
SEG13
C6
SEG7
C14
SEG15
C9
SEG10
C11
SEG12
C3
SEG4
C15
SEG16
C1
SEG2
C8
SEG9
C7
SEG8
C0
SEG1
C4
SEG5
C0–7: Corresponds to the 2nd byte of the CGRAM data write
command.
C8–15: Corresponds to the 3rd byte of the CGRAM data write commnad.
*On CGROM
A CGROM (Character Generator ROM) has an 8-bit address to generate alphanumeric type matrix
character patterns.
It has a capacity of 240 x 16 bits and can store 240 types of character patterns.
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3. “ADRAM data write” command
(Specifies the address of ADRAM and writes symbol data)
ADRAM (Additional Data RAM) has a 2-bit address to store symbol data.
Symbol data specified by ADRAM is directly output without CGROM and CGRAM.
(The ADRAM can store two types of symbol patterns for each digit.)
The terminal to which the contents of ADRAM are output can be used as a cursor.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
: Setup and DCRAM address in the write-in mode of
X0 X1 X2 X3 1 1 0 0
(1st)
DCRAM data are specified.
LSB
MSB (Example: Specify ADRAM address 0H.)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
: Specify symbol data.
C0 C1 *
*
*
* *
*
(2nd)
(Example: Specify ADRAM address 0H.)
To specify symbol data continuously to the next address, specify only symbol data as follows.
Since the address of ADRAM is automatically incremented, address specification is unnecessary.
LSB
B0 B1 B2 B3 B4 B5 B6
2nd byte
C0 C1 *
*
*
* *
(3rd)
LSB
B0 B1 B2 B3 B4 B5 B6
2nd byte
C0 C1 *
*
*
* *
(4th)
MSB
B7
LSB
B0 B1 B2 B3 B4 B5 B6
2nd byte
C0 C1 *
*
*
* *
(17th)
LSB
B0 B1 B2 B3 B4 B5 B6
2nd byte C0 C1
*
*
*
* *
(18th)
MSB
B7
*
: Specify symbol data.
(It is written into ADRAM address 1H.)
MSB
B7
*
*
: Specify symbol data.
(It is written into ADRAM address 2H.)
: Specify symbol data.
(It is written into ADRAM address FH.)
MSB
B7
*
: Specify symbol data.
(It is rewritten into ADRAM address 0H.)
X0 (LSB) to X3 (MSB) : ADRAM address (4 bits: 16 characters worth)
C0 (LSB) to C1 (MSB) : Symbol data (2 bits: 2 symbols per digit)
* : Don’t care
[Relationship between ADRAM addresses setup and COM positions]
HEX
X0
X1
X2
X3
COM
positions
HEX
X0
X1
X2
X3
COM
positions
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
8
9
A
B
C
D
E
F
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
19/31
FEDL9289-01
ML9289-xx
4. “Display duty set” command
(Writes display duty value into the duty cycle register.)
For display duty, brightness can be adjusted in 16 stages using 4-bit data.
When power is turned on or when the RESET signal is input, the duty cycle register value is “0”.
execute this command before turning the display on, then set a desired duty value.
Always
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
D0 D1 D2 D3 1
0
1
0
: setup and duty value in display duty specification mode are
specified.
D0 (LSB) to D3 (MSB) : Display duty data (4 bits: 16 stages worth)
[Relation between setup data and controlled COM duty]
HEX
D0
D1
D2
D3
COM duty
HEX
D0
D1
D2
D3
COM duty
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0/16
1/16
2/16
3/16
4/16
5/16
6/16
7/16
8
9
A
B
C
D
E
F
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
8/16
9/16
10/16
11/16
12/16
13/16
14/16
15/16
* The state when power is turned on or when the RESET signal is input.
20/31
FEDL9289-01
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5. “Number of display digits set” command
(Writes the number of display digits into the number-of-display-digits register.)
For the number of display digits, 1 to 16 digits can be specified using 4-bit data.
When power is turned on or when a RESET signal is input, the number-of-display-digits register value is “0”.
Always execute this command before turning the display on, then set a desired value.
[Command format]
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
K0 K1 K2 K3
0
1
1
0
: Setup in display digits specification mode and digits value
is specified.
K0 (LSB) to K3 (MSB) : Data of the number of display digits (4 bits: 16 digits worth)
[Relation between data to be set and the number of digits of COM to be controlled]
HEX
K0
K1
K2
K3
8
0
0
0
1
No. of digits
of COM
COM1–8
COM1
9
1
0
0
1
COM1–9
COM1–2
COM1–3
COM1–4
COM1–5
COM1–6
COM1–7
A
B
C
D
E
F
0
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
COM1–10
COM1–11
COM1–12
COM1–13
COM1–14
COM1–15
HEX
K0
K1
K2
K3
0
0
0
0
0
No. of digits
of COM
COM1–16
1
1
0
0
0
2
3
4
5
6
7
0
1
0
1
0
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
* The state when power is turned on or when the RESET signal is input.
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6. “All display lights ON” and “All display lights OFF” commands
(Turns the entire display ON and OFF, respectively.)
All display lights ON is used primarily for display testing.
All display lights OFF is primarily used for display blink and to prevent false display upon power-on.
[Command format]
1st byte
LSB
MSB
B0 B1 B2 B3 B4 B5 B6 B7
L H * * 1 1 1 0
: Select all display lights ON or OFF and specify
their operation.
L: All display lights OFF
H: All display lights ON
* : Don’t Care
[Data to be setup and display state of SEG and AD]
L
H
Display state of SEG and AD
0
0
Normal display
1
0
Sets all outputs to Low
0
1
1
1
Sets all outputs to High
Sets all outputs to High
* The state when power is turned on or when RESET
signal is input
* Priority is given to the All display lights ON command.
22/31
FEDL9289-01
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Setting Flowchart
(Power applying included)
Apply VDD
Apply VDISP
All display lights OFF
* Status of all outputs by RESET
signal input
Setup of the number
display digits
Setup of display duty
* Select a RAM to be used.
DCRAM
data write mode
(including address
setting)
Address is incremented
automatically
Address is incremented
automatically
Address is incremented
automatically
DCRAM
character code
NO
DCRAM
character code
write ended?
ADRAM
data write mode
(including address
setting)
CGRAM
data write mode
(including address
setting)
CGRAM
character code
NO
YES
ADRAM
character code
CGRAM
character code
write ended?
NO
YES
YES
ADRAM
character code
write ended?
YES
Another RAM to
be set?
NO
Release all display lights
OFF mode
* Display operation active
End of Setting
Power-off Flowchart
Display operation active
Turn off VDISP
Turn off VDD
23/31
FEDL9289-01
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POWER-ON/OFF TIMING

To prevent the IC from malfunctioning, turn on the logic power supply first, and then turn on the driver power
supply when applying power. Also, for power-off, turn off the driver power supply first, then turn off the logic
power supply.
[Voltage]
VDISP Terminal Voltage
VDD Terminal Voltage
[Time]
>2.0μSec
>2.0μSec
24/31
FEDL9289-01
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APPLICATION CIRCUIT
Heater transformer
Alphanumeric fluorescent display tubes
ANODE
ANODE
GRID
(SEGMENT) (SEGMENT) (DIGIT)
VDD
2
VDD
VDD
C2
VDD AD1-2
Microcontroller
Output port
C4
RESET
CS
CP
DA
GND
16
16
SEG1-16 COM1-16
ML9289-01
GND VDISP
OSC0
VDD
R1
VDISP
C3
C1
ZD
GND
GND
R2
Notes:
1. The VDD voltage depends on the power supply voltage of the microcontroller used.
constants R1 and C1 to the power supply voltage used.
2. The VDISPvoltage depends on the vacuum fluorescent display tube used.
and ZD to the voltage used.
Adjust the value of the
Adjust the value of the constants R2
Reference data
Shown below is a chart showing the VDISP voltage vs. output current of each driver.
Care must be taken that the entire power consumption will not exceed the power dissipation.
–30
COM1–COM16
(Condition: VO H = VDISP –1.5 V)
Output Current (mA)
–25
–20
–15
AD1–AD2
–10
(Condition: VOH = V DISP–1.5 V)
–5
SEG1–SEG16
(Condition: VOH = V DISP–1.5 V)
0
17
22
27
32
37
42 (V)
VDISP Voltage
VDISP Voltage vs. Output Current of Each Driver
25/31
FEDL9289-01
ML9289-xx
ML9289-01 ROM CODE
*ROM CODE is the character set for SEG1 to SEG16.
*00000000b(00h) to 00001111b(0Fh) are the CGRAM addresses
MSB
LSB
0000
0000
RAM0
0001
RAM1
0010
RAM2
0011
RAM3
0100
RAM4
0101
RAM5
0110
RAM6
0111
RAM7
1000
RAM8
1001
RAM9
1010
RAMA
1011
RAMB
1100
RAMC
1101
RAMD
1110
RAME
1111
RAMF
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
26/31
FEDL9289-01
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16 Segment design
MSB
0000
0001
14 Segment design
0010
0011
0100
0101
0110
0111
0001
0010
7 Segment design
0011
0100
0111
LSB
0000 RAM0
0001 RAM1
0010 RAM2
0011 RAM3
0100 RAM4
0101 RAM5
0110 RAM6
0111 RAM7
1000 RAM8
1001 RAM9
SEG14
SEG6
SEG11
SEG12
SEG5
16 Segment
SEG15
SEG14
SEG10
SEG11
SEG12
SEG6
14 Segment
SEG2
SEG16
SEG7
SEG3
SEG15
SEG10
SEG1
SEG6
SEG16
SEG1
SEG2
SEG5
SEG1
SEG3
RAMF
SEG4
1111
SEG9
RAME
SEG13
1110
SEG8
RAMD
SEG7
1101
SEG3
RAMC
SEG4
1100
SEG9
RAMB
SEG13
1011
SEG8
RAMA
SEG7
1010
SEG4
7 Segment
27/31
FEDL9289-01
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PACKAGE DIMENSIONS
(Unit: mm)
QFP44-P-910-0.80-2K
5
Package material
Lead frame material
Pin treatment
Package weight (g)
Rev. No./Last Revised
Epoxy resin
42 alloy
Sn/Pb
0.41 TYP.
5/Nov. 20, 2002
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM's SEMICONDUCTOR’s responsible
sales person for the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
28/31
FEDL9289-01
ML9289-xx
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
29/31
FEDL9289-01
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REVISION HISTORY
Document
No.
FEDL9289-01
Date
May 15, 2009
Page
Previous Current
Edition
Edition


Description
Final edition 1
30/31
FEDL9289-01
ML9289-xx
NOTICE
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The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
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Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor
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Copyright
2009 - 2011 LAPIS Semiconductor Co., Ltd.
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