SILABS EFM32GG880F512-QFP100 Read-while-write support Datasheet

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EFM32GG880 DATASHEET
F1024/F512
• ARM Cortex-M3 CPU platform
• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4 µA @ 3 V Shutoff Mode with RTC
• 0.8 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 1.1 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 80 µA/MHz @ 3 V Sleep Mode
• 219 µA/MHz @ 3 V Run Mode, with code executed from flash
• 1024/512 KB Flash
• Read-while-write support
• 128 KB RAM
• 85 General Purpose I/O pins
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 12 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 8×36 segments
• Voltage boost, adjustable contrast and autonomous animation
• Backup Power Domain
• RTC and retention registers in a separate power domain, available in all energy modes
• Operation from backup battery when main power drains out
• External Bus Interface for up to 4x256 MB of external
memory mapped space
• TFT Controller with Direct Drive
• Communication interfaces
• 3× Universal Synchronous/Asynchronous Receiver/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Autonomous operation with DMA in Deep Sleep
Mode
2
• 2× I C Interface with SMBus support
• Address recognition in Stop Mode
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sensors and capacitive buttons
• Ultra efficient Power-on Reset and Brown-Out Detector
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Pre-Programmed UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• LQFP100 package
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32GG880 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB)
RAM (kB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32GG880F512-QFP100
512
128
48
1.98 - 3.8
-40 - 85
LQFP100
EFM32GG880F1024-QFP100
1024
128
48
1.98 - 3.8
-40 - 85
LQFP100
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy
saving modes, and a wide selection of peripherals, the EFM32GG microcontroller is well suited for
any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
shows a summary of the configuration for the EFM32GG880 devices. For a complete feature set and
in-depth information on the modules, the reader is referred to the EFM32GG Reference Manual.
A block diagram of the EFM32GG880 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
GG880F512/ 1024
Core and Mem ory
Clock Managem ent
Mem ory
Protection
Unit
ARM Cortex ™- M3 processor
Flash
Program
Mem ory
RAM
Mem ory
Debug
Interface
w/ ETM
DMA
Controller
Energy Managem ent
High Freq.
Crystal
Oscillator
High Freq
RC
Oscillator
Voltage
Regulator
Voltage
Com parator
Aux High Freq.
RC
Oscillator
Low Freq.
RC
Oscillator
Brown- out
Detector
Power- on
Reset
Low Freq.
Crystal
Oscillator
Ultra Low Freq.
RC
Oscillator
Back- up
Power
Dom ain
32- bit bus
Peripheral Reflex System
Serial Interfaces
USART
Low
Energy
UART
UART
2
I C
I/ O Ports
Tim ers and Triggers
Ex t. Bus
Interface
TFT
Driver
Ex ternal
Interrupts
General
Purpose
I/ O
Pin
Reset
Pin
Wakeup
Tim er/
Counter
LESENSE
Low Energy
Tim er
Real Tim e
Counter
Pulse
Counter
Watchdog
Tim er
Back- up
RTC
Analog Interfaces
ADC
LCD
Controller
DAC
Operational
Am plifier
Security
Hardware
AES
Analog
Com parator
2.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone
MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well
as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32
implementation of the Cortex-M3 is described in detail in EFM32 Cortex-M3 Reference Manual.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embedded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer
pin which can be used to output profiling information, data trace and software-generated messages.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32GG microcontroller.
The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is
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divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32GG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32GG microcontrollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the
EFM32GG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH,
ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M3. This enables
seamless access from software without manually manipulating the IO settings each time a read or write
is performed. The data and address lines are multiplexed in order to reduce the number of pins required
to interface the external devices. The timing is adjustable to meet specifications of the external devices.
The interface is limited to asynchronous devices.
2.1.11 TFT Direct Drive
The EBI contains a TFT controller which can drive a TFT via a 565 RGB interface. The TFT controller
supports programmable display and port sizes and offers accurate control of frequency and setup and
hold timing. Direct Drive is supported for TFT displays which do not have their own frame buffer. In
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that case TFT Direct Drive can transfer data from either on-chip memory or from an external memory
device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers
through the EBI interface.
2.1.12 Inter-Integrated Circuit Interface (I2C)
2
2
The I C module provides an interface between the MCU and a serial I C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
2
The interface provided to software by the I C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.13 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, IrDA and I2S devices.
2.1.14 Pre-Programmed UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.15 Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module.
It supports full- and half-duplex asynchronous UART communication.
2.1.16 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
TM
The unique LEUART , the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.17 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/PulseWidth Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
2.1.18 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.19 Backup Real Time Counter (BURTC)
The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz
crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy
Modes and it can also run in backup mode, making it operational even if the main power should drain out.
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2.1.20 Low Energy Timer (LETIMER)
TM
The unique LETIMER , the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
2.1.21 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 – EM3.
2.1.22 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
2.1.23 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.24 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 8 external
pins and 6 internal signals.
2.1.25 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC
is fully differential rail-to-rail, with 12-bit resolution. It has two single ended output buffers which can be
combined into one differential output. The DAC may be used for a number of different applications such
as sensor interfaces or sound output.
2.1.26 Operational Amplifier (OPAMP)
The EFM32GG880 features 3 Operational Amplifiers. The Operational Amplifier is a versatile general
purpose amplifier with rail-to-rail differential input and rail-to-rail single ended output. The input can be set
to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable
and the OPAMP has various internal configurations such as unity gain, programmable gain using internal
resistors etc.
2.1.27 Low Energy Sensor Interface (LESENSE)
TM
The Low Energy Sensor Interface (LESENSE ), is a highly configurable sensor interface with support
for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE
is capable of supporting a wide range of sensors and measurement schemes, and can for instance measure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable
FSM which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in
applications with a strict energy budget.
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2.1.28 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC,
and a set of retention registers, available in all energy modes. This power domain can be configured to
automatically change power source to a backup battery when the main power drains out. The backup
power domain enables the EFM32GG880 to keep track of time and retain data, even if the main power
source should drain out.
2.1.29 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.30 General Purpose Input/Output (GPIO)
In the EFM32GG880, there are 85 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.1.31 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to 8x36 segments. A voltage
boost function enables it to provide the LCD display with higher voltage than the supply voltage for the
device. In addition, an animation feature can run custom animations on the LCD display without any
CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame
Counter interrupt that can wake-up the device on a regular basis for updating data.
2.2 Configuration Summary
The features of the EFM32GG880 is a subset of the feature set described in the EFM32GG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC
Full configuration
NA
DMA
Full configuration
NA
RMU
Full configuration
NA
EMU
Full configuration
NA
CMU
Full configuration
CMU_OUT0, CMU_OUT1
WDOG
Full configuration
NA
PRS
Full configuration
NA
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Module
Configuration
Pin Connections
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY,
EBI_ALE, EBI_BL[1:0], EBI_CS[3:0],
EBI_CSTFT, EBI_DCLK, EBI_DTEN,
EBI_HSNC, EBI_NANDREn,
EBI_NANDWEn, EBI_REn, EBI_VSNC,
EBI_WEn
I2C0
Full configuration
I2C0_SDA, I2C0_SCL
I2C1
Full configuration
I2C1_SDA, I2C1_SCL
USART0
Full configuration with IrDA
US0_TX, US0_RX. US0_CLK, US0_CS
USART1
Full configuration with I2S
US1_TX, US1_RX, US1_CLK, US1_CS
USART2
Full configuration with I2S
US2_TX, US2_RX, US2_CLK, US2_CS
UART0
Full configuration
U0_TX, U0_RX
UART1
Full configuration
U1_TX, U1_RX
LEUART0
Full configuration
LEU0_TX, LEU0_RX
LEUART1
Full configuration
LEU1_TX, LEU1_RX
TIMER0
Full configuration with DTI
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1
Full configuration
TIM1_CC[2:0]
TIMER2
Full configuration
TIM2_CC[2:0]
TIMER3
Full configuration
TIM3_CC[2:0]
RTC
Full configuration
NA
BURTC
Full configuration
NA
LETIMER0
Full configuration
LET0_O[1:0]
PCNT0
Full configuration, 16-bit count register
PCNT0_S[1:0]
PCNT1
Full configuration, 8-bit count register
PCNT1_S[1:0]
PCNT2
Full configuration, 8-bit count register
PCNT2_S[1:0]
ACMP0
Full configuration
ACMP0_CH[7:0], ACMP0_O
ACMP1
Full configuration
ACMP1_CH[7:0], ACMP1_O
VCMP
Full configuration
NA
ADC0
Full configuration
ADC0_CH[7:0]
DAC0
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Full configuration
Outputs: OPAMP_OUTx,
OPAMP_OUTxALT, Inputs:
OPAMP_Px, OPAMP_Nx
AES
Full configuration
NA
GPIO
85 pins
Available pins are shown in
Table 4.3 (p. 65)
LCD
Full configuration
LCD_SEG[35:0], LCD_COM[7:0],
LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
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2.3 Memory Map
The EFM32GG880 memory map is shown in Figure 2.2 (p. 9) , with RAM and Flash sizes for the
largest memory configuration.
Figure 2.2. EFM32GG880 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 10) , by simulation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined in Table 3.2 (p. 10) , by simulation and/or technology characterisation unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 10) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
10) .
Table 3.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Min
Typ
Max
-40
Unit
150
1
TSTG
Storage temperature range
TS
Maximum soldering
temperature
VDDMAX
External main supply voltage
0
3.8 V
VIOPIN
Voltage on any I/O
pin
-0.3
VDD+0.3 V
Latest IPC/JEDEC J-STD-020
Standard
°C
260 °C
1
Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed calibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data retention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
Parameter
TAMB
Ambient temperature range
VDDOP
Operating supply voltage
fAPB
Internal APB clock frequency
48 MHz
fAHB
Internal AHB clock frequency
48 MHz
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Min
Typ
-40
1.98
10
Max
Unit
85 °C
3.8 V
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3.3.2 Environmental
Table 3.3. Environmental
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VESDHBM
ESD (Human Body
Model HBM)
TAMB=25°C
2000 V
VESDCDM
ESD (Charged Device Model, CDM)
TAMB=25°C
750 V
Latch-up sensitivity passed: ±100 mA/1.5 × VSUPPLY(max) according to JEDEC JESD 78 method Class
II, 85°C.
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3.4 Current Consumption
Table 3.4. Current Consumption
Symbol
IEM0
IEM1
IEM2
IEM3
IEM4
Parameter
EM0 current. No
prescaling. Running prime number calculation code
from flash. (Production test condition =
14MHz)
EM1 current (Production test condition = 14MHz)
Condition
Min
Typ
Max
Unit
48 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
219
240 µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
214
261 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
220
263 µA/
MHz
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
223
270 µA/
MHz
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
225
273 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
230
282 µA/
MHz
1.2 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
283
338 µA/
MHz
48 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
80
90 µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
80
90 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
81
91 µA/
MHz
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
83
99 µA/
MHz
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
85
100 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
90
102 µA/
MHz
1.2 MHz HFRCO. all peripheral
clocks disabled, VDD= 3.0 V
122
152 µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
1.1
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
6.0
VDD= 3.0 V, TAMB=25°C
0.8
VDD= 3.0 V, TAMB=85°C
5.8
VDD= 3.0 V, TAMB=25°C
0.02
0.055 µA
VDD= 3.0 V, TAMB=85°C
0.5
0.9 µA
EM2 current
EM3 current
1
1.8
1
µA
1
10.0
1
µA
1
1.3
1
µA
1
9.8
1
µA
EM4 current
1
Only one RAM block enabled.
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
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Table 3.5. Energy Modes Transitions
Symbol
Parameter
Min
Typ
Max
Unit
tEM10
Transition time from EM1 to EM0
0
HFCORECLK
cycles
tEM20
Transition time from EM2 to EM0
2
µs
tEM30
Transition time from EM3 to EM0
2
µs
tEM40
Transition time from EM4 to EM0
163
µs
3.6 Power Management
The EFM32GG requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
Table 3.6. Power Management
Symbol
Parameter
Condition
Min
Typ
Max
VBODextthr-
BOD threshold on
falling external supply voltage
1.74
1.96 V
VBODintthr-
BOD threshold on
falling internally regulated supply voltage
1.57
1.70 V
VBODextthr+
BOD threshold on
rising external supply voltage
VPORthr+
Power-on Reset
(POR) threshold on
rising external supply voltage
tRESET
Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset.
163
µs
CDECOUPLE
Voltage regulator
decoupling capacitor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
1
µF
1.85
Unit
1.98 V
1.98 V
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3.7 Flash
Table 3.7. Flash
Symbol
Parameter
ECFLASH
Flash erase cycles
before failure
Condition
Min
TAMB<150°C
RETFLASH
Flash data retention
tW_PROG
Word (32-bit) programming time
tPERASE
Page erase time
tDERASE
IERASE
IWRITE
VFLASH
Typ
Max
Unit
20000
cycles
10000
h
TAMB<85°C
10
years
TAMB<70°C
20
years
20
µs
LPERASE == 0
20
20.4
20.8 ms
LPERASE == 1
40
40.4
40.8 ms
Device erase time
161.6 ms
LPERASE == 0
14
1
mA
LPERASE == 1
7
1
mA
LPWRITE == 0
14
1
mA
LPWRITE == 1
7
1
mA
Erase current
Write current
Supply voltage during flash erase and
write
1.98
3.8 V
1
Measured at 25°C
3.8 General Purpose Input Output
Table 3.8. GPIO
Symbol
Parameter
VIOIL
Input low voltage
VIOIH
Input high voltage
VIOOH
Output high voltage (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Condition
Min
Typ
Max
Unit
0.30VDD V
0.70VDD
V
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD
V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.90VDD
V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.85VDD
V
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.90VDD
V
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD
V
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.85VDD
V
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
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Symbol
VIOOL
Parameter
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
Condition
Min
Typ
Max
Unit
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.60VDD
V
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.80VDD
V
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD
V
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.10VDD
V
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.10VDD
V
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
0.05VDD
V
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD V
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.20VDD V
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.35VDD V
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
0.20VDD V
IIOLEAK
Input leakage current
RPU
I/O pin pull-up resistor
40
kOhm
RPD
I/O pin pull-down resistor
40
kOhm
RIOESD
Internal ESD series
resistor
200
Ohm
tIOGLITCH
Pulse width of pulses to be removed
by the glitch suppression filter
tIOOF
VIOHYST
High Impedance IO connected
to GROUND or VDD
±0.1
±100 nA
10
50 ns
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capacitance CL=12.5-25pF.
20+0.1CL
250 ns
GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
20+0.1CL
250 ns
Output fall time
I/O pin hysteresis
(VIOTHR+ - VIOTHR-)
VDD = 1.98 - 3.8 V
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
0.10VDD
15
V
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Figure 3.1. Typical Low-Level Output Current, 2V Supply Voltage
5
0.20
4
Low- Level Output Current [m A]
Low- Level Output Current [m A]
0.15
0.10
3
2
0.05
1
- 40°C
25°C
85°C
0.00
0.0
0.5
1.5
1.0
Low- Level Output Voltage [V]
- 40°C
25°C
85°C
0
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
1.5
1.0
Low- Level Output Voltage [V]
2.0
GPIO_Px_CTRL DRIVEMODE = LOW
45
20
40
35
Low- Level Output Current [m A]
Low- Level Output Current [m A]
15
10
30
25
20
15
5
10
5
- 40°C
25°C
85°C
0
0.0
0.5
1.5
1.0
Low- Level Output Voltage [V]
0
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
- 40°C
25°C
85°C
0.5
1.5
1.0
Low- Level Output Voltage [V]
2.0
GPIO_Px_CTRL DRIVEMODE = HIGH
16
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Figure 3.2. Typical High-Level Output Current, 2V Supply Voltage
0.00
0.0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–0.5
High- Level Output Current [m A]
High- Level Output Current [m A]
–0.05
–0.10
–1.0
–1.5
–0.15
–2.0
–0.20
0.0
1.5
0.5
1.0
High- Level Output Voltage [V]
–2.5
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
1.5
0.5
1.0
High- Level Output Voltage [V]
2.0
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–10
High- Level Output Current [m A]
High- Level Output Current [m A]
–5
–10
–20
–30
–15
–40
–20
0.0
1.5
0.5
1.0
High- Level Output Voltage [V]
–50
0.0
2.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
1.5
0.5
1.0
High- Level Output Voltage [V]
2.0
GPIO_Px_CTRL DRIVEMODE = HIGH
17
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0.5
10
0.4
8
Low- Level Output Current [m A]
Low- Level Output Current [m A]
Figure 3.3. Typical Low-Level Output Current, 3V Supply Voltage
0.3
0.2
0.1
6
4
2
- 40°C
25°C
85°C
0.0
0.0
0.5
1.5
1.0
2.0
Low- Level Output Voltage [V]
2.5
- 40°C
25°C
85°C
0
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
1.5
1.0
2.0
Low- Level Output Voltage [V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = LOW
40
50
35
40
Low- Level Output Current [m A]
Low- Level Output Current [m A]
30
25
20
15
30
20
10
10
5
0
0.0
- 40°C
25°C
85°C
0.5
1.5
1.0
2.0
Low- Level Output Voltage [V]
2.5
- 40°C
25°C
85°C
0
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
0.5
1.5
1.0
2.0
Low- Level Output Voltage [V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = HIGH
18
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Figure 3.4. Typical High-Level Output Current, 3V Supply Voltage
0.0
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
High- Level Output Current [m A]
High- Level Output Current [m A]
–0.1
–0.2
–0.3
–2
–3
–4
–0.4
–5
–0.5
0.0
0.5
1.5
1.0
2.0
High- Level Output Voltage [V]
2.5
–6
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = LOWEST
2.5
3.0
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–10
High- Level Output Current [m A]
–10
High- Level Output Current [m A]
1.5
1.0
2.0
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOW
0
–20
–30
–40
–50
0.0
0.5
–20
–30
–40
0.5
1.5
1.0
2.0
High- Level Output Voltage [V]
2.5
–50
0.0
3.0
GPIO_Px_CTRL DRIVEMODE = STANDARD
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
0.5
1.5
1.0
2.0
High- Level Output Voltage [V]
2.5
3.0
GPIO_Px_CTRL DRIVEMODE = HIGH
19
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Figure 3.5. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
14
0.7
12
Low- Level Output Current [m A]
Low- Level Output Current [m A]
0.6
0.5
0.4
0.3
10
8
6
4
0.2
2
0.1
0.0
0.0
- 40°C
25°C
85°C
0.5
1.5
1.0
2.0
2.5
Low- Level Output Voltage [V]
3.0
- 40°C
25°C
85°C
0
0.0
3.5
1.5
1.0
2.0
2.5
Low- Level Output Voltage [V]
3.0
50
50
40
40
30
20
10
30
20
10
- 40°C
25°C
85°C
0
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = LOW
Low- Level Output Current [m A]
Low- Level Output Current [m A]
GPIO_Px_CTRL DRIVEMODE = LOWEST
0.5
0.5
1.5
1.0
2.0
2.5
Low- Level Output Voltage [V]
3.0
- 40°C
25°C
85°C
0
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = STANDARD
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
0.5
1.5
1.0
2.0
2.5
Low- Level Output Voltage [V]
3.0
3.5
GPIO_Px_CTRL DRIVEMODE = HIGH
20
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Figure 3.6. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
0
- 40°C
25°C
85°C
–1
- 40°C
25°C
85°C
–2
High- Level Output Current [m A]
High- Level Output Current [m A]
–0.2
–0.3
–0.4
–0.5
–3
–4
–5
–6
–0.6
–7
–0.7
–0.8
0.0
–8
0.5
1.5
1.0
2.0
2.5
High- Level Output Voltage [V]
3.0
–9
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = LOWEST
3.0
3.5
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–10
High- Level Output Current [m A]
–10
High- Level Output Current [m A]
1.5
1.0
2.0
2.5
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOW
0
–20
–30
–40
–50
0.0
0.5
–20
–30
–40
0.5
1.5
1.0
2.0
2.5
High- Level Output Voltage [V]
3.0
–50
0.0
3.5
GPIO_Px_CTRL DRIVEMODE = STANDARD
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
0.5
1.5
1.0
2.0
2.5
High- Level Output Voltage [V]
3.0
3.5
GPIO_Px_CTRL DRIVEMODE = HIGH
21
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3.9 Oscillators
3.9.1 LFXO
Table 3.9. LFXO
Symbol
Parameter
Condition
Min
Typ
Max
fLFXO
Supported nominal
crystal frequency
ESRLFXO
Supported crystal
equivalent series resistance (ESR)
CLFXOL
Supported crystal
external load range
X
DCLFXO
Duty cycle
48
ILFXO
Current consumption for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190
nA
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
400
ms
32.768
30
1
Unit
kHz
120 kOhm
25 pF
50
53.5 %
1
See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in energyAware Designer in Simplicity Studio
For safe startup of a given crystal, the energyAware Designer in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
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3.9.2 HFXO
Table 3.10. HFXO
Symbol
Parameter
fHFXO
Supported nominal
crystal Frequency
ESRHFXO
The transconductance of the HFXO
input transistor at
crystal startup
CHFXOL
Supported crystal
external load range
DCHFXO
Duty cycle
tHFXO
Min
Typ
Current consumption for HFXO after
startup
Startup time
Max
4
Unit
48 MHz
Crystal frequency 48 MHz
Supported crystal
equivalent series re- Crystal frequency 32 MHz
sistance (ESR)
Crystal frequency 4 MHz
gmHFXO
IHFXO
Condition
50 Ohm
HFXOBOOST in CMU_CTRL
equals 0b11
30
60 Ohm
400
1500 Ohm
20
mS
5
25 pF
46
50
54 %
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85
µA
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
165
µA
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
400
µs
3.9.3 LFRCO
Table 3.11. LFRCO
Symbol
Parameter
fLFRCO
Oscillation frequency , VDD= 3.0 V,
TAMB=25°C
tLFRCO
Startup time not including software
calibration
150
µs
ILFRCO
Current consumption
300
nA
TUNESTEPL-
Frequency step
for LSB change in
TUNING value
1.5
%
FRCO
Condition
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
Min
Typ
31.29
23
Max
32.768
Unit
34.28 kHz
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Figure 3.7. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
42
42
- 40°C
25°C
85°C
40
40
38
Frequency [kHz]
Frequency [kHz]
38
36
34
34
32
32
30
1.8
2.2
2.6
3.0
3.4
1.8 V
3V
3.8 V
36
30
–40
3.8
–15
Vdd [V]
5
25
Tem perature [°C]
45
Typ
Max
65
85
3.9.4 HFRCO
Table 3.12. HFRCO
Symbol
fHFRCO
tHFRCO_settling
IHFRCO
Parameter
Oscillation frequency, VDD= 3.0 V,
TAMB=25°C
Settling time after
start-up
Current consumption (Production test
condition = 14MHz)
DCHFRCO
Duty cycle
TUNESTEPH-
Frequency step
for LSB change in
TUNING value
FRCO
Condition
Min
Unit
28 MHz frequency band
27.5
28.0
28.5 MHz
21 MHz frequency band
20.6
21.0
21.4 MHz
14 MHz frequency band
13.7
14.0
14.3 MHz
11 MHz frequency band
10.8
11.0
11.2 MHz
7 MHz frequency band
6.48
1
6.60
1 MHz frequency band
1.15
2
1.20
1
6.72
1
MHz
2
1.25
2
MHz
fHFRCO = 14 MHz
0.6
fHFRCO = 28 MHz
165
190 µA
fHFRCO = 21 MHz
134
155 µA
fHFRCO = 14 MHz
106
120 µA
fHFRCO = 11 MHz
94
110 µA
fHFRCO = 6.6 MHz
77
90 µA
fHFRCO = 1.2 MHz
25
32 µA
50
51 %
3
%
fHFRCO = 14 MHz
48.5
0.3
Cycles
1
For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3
The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
2
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1.45
1.45
1.40
1.40
1.35
1.35
Frequency [MHz]
Frequency [MHz]
Figure 3.8. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
1.30
- 40°C
25°C
85°C
1.25
1.20
1.30
1.25
1.20
1.15
1.15
1.10
1.10
1.05
2.0
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
1.05
–40
3.8
2.0 V
3.0 V
3.8 V
–15
5
25
Tem perature [°C]
45
65
85
6.70
6.70
6.65
6.65
6.60
6.60
Frequency [MHz]
Frequency [MHz]
Figure 3.9. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
6.55
6.50
6.45
6.40
6.50
6.45
6.40
- 40°C
25°C
85°C
6.35
6.30
2.0
6.55
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0 V
3.0 V
3.8 V
6.35
6.30
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
11.2
11.2
11.1
11.1
11.0
11.0
Frequency [MHz]
Frequency [MHz]
Figure 3.10. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
10.9
10.8
10.8
10.7
10.6
2.0
10.9
10.7
- 40°C
25°C
85°C
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
3.4
3.6
10.6
–40
3.8
25
2.0 V
3.0 V
3.8 V
–15
5
25
Tem perature [°C]
45
65
85
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14.2
14.2
14.1
14.1
14.0
14.0
Frequency [MHz]
Frequency [MHz]
Figure 3.11. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
13.9
13.8
13.7
13.8
13.7
- 40°C
25°C
85°C
13.6
13.5
2.0
13.9
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0 V
3.0 V
3.8 V
13.6
13.5
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
21.2
21.2
21.1
21.1
21.0
21.0
20.9
20.9
Frequency [MHz]
Frequency [MHz]
Figure 3.12. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
20.8
20.7
20.6
20.7
20.6
20.5
20.5
- 40°C
25°C
85°C
20.4
20.3
2.0
20.8
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
3.4
3.6
2.0 V
3.0 V
3.8 V
20.4
20.3
–40
3.8
–15
5
25
Tem perature [°C]
45
65
85
Figure 3.13. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
28.2
28.4
28.2
28.0
28.0
Frequency [MHz]
Frequency [MHz]
27.8
27.6
27.8
27.6
27.4
27.4
27.2
27.0
2.0
- 40°C
25°C
85°C
2.2
2.4
2.6
2.8
3.0
Vdd [V]
3.2
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3.4
3.6
2.0 V
3.0 V
3.8 V
27.2
27.0
–40
3.8
26
–15
5
25
Tem perature [°C]
45
65
85
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3.9.5 AUXHFRCO
Table 3.13. AUXHFRCO
Symbol
fAUXHFRCO
Parameter
Oscillation frequency, VDD= 3.0 V,
TAMB=25°C
Condition
Min
Max
Unit
28 MHz frequency band
27.5
28.0
28.5 MHz
21 MHz frequency band
20.6
21.0
21.4 MHz
14 MHz frequency band
13.7
14.0
14.3 MHz
11 MHz frequency band
10.8
11.0
11.2 MHz
6.48
1
1
1.15
2
7 MHz frequency band
1 MHz frequency band
tAUXHFRCO_settlingSettling time after
start-up
fAUXHFRCO = 14 MHz
DCAUXHFRCO
fAUXHFRCO = 14 MHz
Duty cycle
Typ
6.60
2
1.20
0.6
48.5
TUNESTEPAUX- Frequency step
for LSB change in
HFRCO
TUNING value
6.72
1
MHz
1.25
2
MHz
Cycles
50
51 %
3
%
0.3
1
For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3
The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. There is enough
adjustment range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and
temperature. By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the
TUNING bits and the frequency band to maintain the AUXHFRCO frequency at any arbitrary value between 7 MHz and 28 MHz
across operating conditions.
2
3.9.6 ULFRCO
Table 3.14. ULFRCO
Symbol
Parameter
Condition
Min
Typ
Max
fULFRCO
Oscillation frequency
25°C, 3V
TCULFRCO
Temperature coefficient
0.05
%/°C
VCULFRCO
Supply voltage coefficient
-18.2
%/V
0.70
Unit
1.75 kHz
3.10 Analog Digital Converter (ADC)
Table 3.15. ADC
Symbol
Parameter
VADCIN
Input voltage range
Condition
Min
Single ended
Differential
VADCREFIN
Input range of external reference voltage, single ended
and differential
VADCREFIN_CH7 Input range of external negative reference voltage on
channel 7
See VADCREFIN
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Typ
Max
Unit
0
VREF V
-VREF/2
VREF/2 V
1.25
VDD V
0
VDD - 1.1 V
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Symbol
Parameter
VADCREFIN_CH6 Input range of external positive reference voltage on
channel 6
VADCCMIN
Common mode input range
IADCIN
Input current
CMRRADC
Analog input common mode rejection
ratio
IADC
Average active current
IADCREF
Current consumption of internal voltage reference
CADCIN
Input capacitance
RADCIN
Input ON resistance
RADCFILT
Input RC filter resistance
CADCFILT
Input RC filter/decoupling capacitance
fADCCLK
ADC Clock Frequency
tADCCONV
Condition
Min
See VADCREFIN
Typ
Acquisition time
tADCACQVDD3
Required acquisition time for VDD/3
reference
Unit
0.625
VDD V
0
VDD V
2pF sampling capacitors
<100
nA
65
dB
1 MSamples/s, 12 bit, external
reference
351
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUPMODE in ADCn_CTRL set to
0b00
67
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUPMODE in ADCn_CTRL set to
0b01
63
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUPMODE in ADCn_CTRL set to
0b10
64
µA
Internal voltage reference
65
µA
2
pF
1
MOhm
10
250
kOhm
fF
13 MHz
6 bit
7
ADCCLK
Cycles
8 bit
11
ADCCLK
Cycles
12 bit
13
ADCCLK
Cycles
1
256 ADCCLK
Cycles
Conversion time
tADCACQ
Max
Programmable
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28
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Symbol
tADCSTART
SNRADC
Parameter
Condition
Min
Max
Unit
Startup time of reference generator
and ADC core in
NORMAL mode
5
µs
Startup time of reference generator
and ADC core in
KEEPADCWARM
mode
1
µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
59
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
63
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
65
dB
1 MSamples/s, 12 bit, differential, internal 1.25V reference
60
dB
1 MSamples/s, 12 bit, differential, internal 2.5V reference
65
dB
1 MSamples/s, 12 bit, differential, 5V reference
54
dB
1 MSamples/s, 12 bit, differential, VDD reference
67
dB
1 MSamples/s, 12 bit, differential, 2xVDD reference
69
dB
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
62
dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
63
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
67
dB
200 kSamples/s, 12 bit, differential, internal 1.25V reference
63
dB
200 kSamples/s, 12 bit, differential, internal 2.5V reference
66
dB
200 kSamples/s, 12 bit, differential, 5V reference
66
dB
66
dB
200 kSamples/s, 12 bit, differential, 2xVDD reference
70
dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
58
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
62
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
64
dB
Signal to Noise Ratio (SNR)
200 kSamples/s, 12 bit, differential, VDD reference
SINADADC
Typ
SIgnal-to-Noise
And Distortion-ratio
(SINAD)
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Symbol
Parameter
Condition
Min
SFDRADC
Max
Unit
1 MSamples/s, 12 bit, differential, internal 1.25V reference
60
dB
1 MSamples/s, 12 bit, differential, internal 2.5V reference
64
dB
1 MSamples/s, 12 bit, differential, 5V reference
54
dB
1 MSamples/s, 12 bit, differential, VDD reference
66
dB
1 MSamples/s, 12 bit, differential, 2xVDD reference
68
dB
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
61
dB
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
65
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
66
dB
200 kSamples/s, 12 bit, differential, internal 1.25V reference
63
dB
200 kSamples/s, 12 bit, differential, internal 2.5V reference
66
dB
200 kSamples/s, 12 bit, differential, 5V reference
66
dB
65
dB
200 kSamples/s, 12 bit, differential, 2xVDD reference
69
dB
1 MSamples/s, 12 bit, single
ended, internal 1.25V reference
64
dBc
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
76
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
73
dBc
1 MSamples/s, 12 bit, differential, internal 1.25V reference
66
dBc
1 MSamples/s, 12 bit, differential, internal 2.5V reference
77
dBc
1 MSamples/s, 12 bit, differential, VDD reference
76
dBc
1 MSamples/s, 12 bit, differential, 2xVDD reference
75
dBc
1 MSamples/s, 12 bit, differential, 5V reference
69
dBc
200 kSamples/s, 12 bit, single ended, internal 1.25V reference
75
dBc
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
75
dBc
200 kSamples/s, 12 bit, differential, VDD reference
Spurious-Free Dynamic Range (SFDR)
Typ
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Symbol
Parameter
Condition
Min
dBc
200 kSamples/s, 12 bit, differential, internal 1.25V reference
79
dBc
200 kSamples/s, 12 bit, differential, internal 2.5V reference
79
dBc
200 kSamples/s, 12 bit, differential, 5V reference
78
dBc
79
dBc
200 kSamples/s, 12 bit, differential, 2xVDD reference
79
dBc
After calibration, single ended
0.3
mV
0.3
3 mV
-3
Thermometer output gradient
Differential non-linearity (DNL)
INLADC
Integral non-linearity (INL), End point
method
MCADC
No missing codes
-1
11.999
1
-1.92
mV/°C
-6.3
ADC
Codes/
°C
±0.7
4 LSB
±1.2
±3.0 LSB
12
2
1.25V reference
OFFSETED
68
Offset voltage
DNLADC
GAINED
Unit
76
After calibration, differential
TGRADADCTH
Max
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differential, VDD reference
VADCOFFSET
Typ
0.033
2
0.03
3
%/°C
2
0.7
3
LSB/°C
2
0.62
3
LSB/°C
0.01
Gain error drift
2.5V reference
0.01
1.25V reference
0.2
2.5V reference
0.2
Offset error drift
bits
3
%/°C
1
On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
2
Typical numbers given by abs(Mean) / (85 - 25).
3
Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.14 (p.
32) and Figure 3.15 (p. 32) , respectively.
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Figure 3.14. Integral Non-Linearity (INL)
Digital ouput code
INL= | [(VD- VSS)/ VLSBIDEAL] - D| where 0 < D < 2 N - 1
4095
4094
Actual ADC
tranfer function
before offset and
gain correction
4093
4092
Actual ADC
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Ideal transfer
curve
3
2
1
VOFFSET
0
Analog Input
Figure 3.15. Differential Non-Linearity (DNL)
Digital
ouput
code
DNL= | [(VD+ 1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2 N - 2
Full Scale Range
4095
4094
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
4093
4092
Actual transfer
function with one
m issing code.
Example: Input value
VD corrresponds to
digital output code D
Code width = 2 LSB
DNL= 1 LSB
Ideal transfer
curve
5
0.5
LSB
Ideal spacing
between two
adjacent codes
VLSBIDEAL= 1 LSB
4
3
2
1
Ideal 50%
Transition Point
Ideal Code Center
0
Analog Input
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3.10.1 Typical performance
Figure 3.16. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.17. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.18. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.19. ADC Absolute Offset, Common Mode = Vdd /2
5
2.0
Vref= 1V25
Vref= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
4
1.5
2
Actual Offset [LSB]
Actual Offset [LSB]
3
VRef= 1V25
VRef= 2V5
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
1
0
–1
1.0
0.5
0.0
–2
–0.5
–3
–4
2.0
2.2
2.4
2.6
2.8
3.0
Vdd (V)
3.2
3.4
3.6
–1.0
–40
3.8
Offset vs Supply Voltage, Temp = 25°C
–15
5
25
Tem p (C)
45
65
85
Offset vs Temperature, Vdd = 3V
Figure 3.20. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
79.4
71
2XVDDVSS
70
1V25
79.2
Vdd
69
79.0
67
5VDIFF
2V5
66
SFDR [dB]
SNR [dB]
68
Vdd
2V5
78.8
78.6
2XVDDVSS
78.4
65
78.2
64
63
–40
–15
5
25
Tem perature [°C]
45
65
5VDIFF
1V25
85
78.0
–40
Signal to Noise Ratio (SNR)
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–15
5
25
Tem perature [°C]
45
65
85
Spurious-Free Dynamic Range (SFDR)
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Figure 3.21. ADC Temperature sensor readout
2600
Vdd= 1.8
Vdd= 3
Vdd= 3.8
Sensor readout
2500
2400
2300
2200
2100
–40
–25 –15
–5
5
15 25 35
Tem perature [°C]
45
55
65
75
85
3.11 Digital Analog Converter (DAC)
Table 3.16. DAC
Symbol
VDACOUT
VDACCM
Parameter
Output voltage
range
Condition
Min
Typ
0
VDD V
VDD voltage reference, differential
-VDD
VDD V
0
VDD V
500 kSamples/s, 12 bit
IDAC
100 kSamples/s, 12 bit
1 kSamples/s 12 bit NORMAL
SRDAC
Sample rate
fDAC
DAC clock frequency
400
1
µA
200
1
µA
1
µA
17
500 ksamples/s
Continuous Mode
CYCDACCONV
Clock cyckles per
conversion
tDACCONV
Conversion time
tDACSETTLE
Settling time
SNRDAC
Signal to Noise Ratio (SNR)
Unit
VDD voltage reference, single
ended
Output common
mode voltage range
Active current including references
for 2 channels
Max
1000 kHz
Sample/Hold Mode
250 kHz
Sample/Off Mode
250 kHz
2
2
µs
5
µs
500 kSamples/s, 12 bit, single ended, internal 1.25V reference
58
dB
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
59
dB
500 kSamples/s, 12 bit, differential, internal 1.25V reference
58
dB
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Symbol
SNDRDAC
SFDRDAC
VDACOFFSET
Parameter
Signal to Noisepulse Distortion Ratio (SNDR)
Spurious-Free
Dynamic
Range(SFDR)
Condition
Min
Typ
Max
Unit
500 kSamples/s, 12 bit, differential, internal 2.5V reference
58
dB
500 kSamples/s, 12 bit, differential, VDD reference
59
dB
500 kSamples/s, 12 bit, single ended, internal 1.25V reference
57
dB
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
54
dB
500 kSamples/s, 12 bit, differential, internal 1.25V reference
56
dB
500 kSamples/s, 12 bit, differential, internal 2.5V reference
53
dB
500 kSamples/s, 12 bit, differential, VDD reference
55
dB
500 kSamples/s, 12 bit, single ended, internal 1.25V reference
62
dBc
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
56
dBc
500 kSamples/s, 12 bit, differential, internal 1.25V reference
61
dBc
500 kSamples/s, 12 bit, differential, internal 2.5V reference
55
dBc
500 kSamples/s, 12 bit, differential, VDD reference
60
dBc
After calibration, single ended
2
9 mV
After calibration, differential
2
mV
Offset voltage
DNLDAC
Differential non-linearity
±1
LSB
INLDAC
Integral non-linearity
±5
LSB
MCDAC
No missing codes
12
bits
1
Measured with a static input code and no loading on the output.
3.12 Operational Amplifier (OPAMP)
The electrical characteristics for the Operational Amplifiers are based on simulations.
Table 3.17. OPAMP
Symbol
IOPAMP
Parameter
Active Current
Condition
Min
Typ
Max
Unit
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, Unity
Gain
350
405 µA
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, Unity
Gain
95
115 µA
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Symbol
Parameter
Condition
Min
Typ
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, Unity
Gain
GOL
GBWOPAMP
PMOPAMP
Open Loop Gain
Gain Bandwidth
Product
Phase Margin
RINPUT
Input Resistance
RLOAD
Load Resistance
ILOAD_DC
DC Load Current
VINPUT
Input Voltage
VOUTPUT
17 µA
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
101
dB
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
98
dB
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
91
dB
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
6.1
MHz
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
1.8
MHz
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
0.25
MHz
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, CL=75
pF
64
°
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, CL=75
pF
58
°
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, CL=75
pF
58
°
100
200
Ohm
OPAxHCMDIS=0
VSS
VDD V
OPAxHCMDIS=1
VSS
VDD-1.2 V
VSS
VDD V
Output Voltage
-13
0
11 mV
1
mV
Input Offset Voltage
VOFFSET_DRIFT Input Offset Voltage
Drift
NOPAMP
Mohm
11 mA
Unity Gain, VSS<Vin<VDD-1.2,
OPAxHCMDIS=1
SROPAMP
Unit
13
Unity Gain, VSS<Vin<VDD,
OPAxHCMDIS=0
VOFFSET
Max
Slew Rate
Voltage Noise
0.02 mV/°C
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
3.2
V/µs
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
0.8
V/µs
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
0.1
V/µs
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAxHCMDIS=0
101
µVRMS
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAxHCMDIS=1
141
µVRMS
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
Vout=1V, RESSEL=0, 0.1
Hz<f<1 MHz, OPAxHCMDIS=0
196
µVRMS
Vout=1V, RESSEL=0, 0.1
Hz<f<1 MHz, OPAxHCMDIS=1
229
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=0
1230
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=1
2130
µVRMS
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=0
1630
µVRMS
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=1
2590
µVRMS
Figure 3.22. OPAMP Common Mode Rejection Ratio
Figure 3.23. OPAMP Positive Power Supply Rejection Ratio
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Figure 3.24. OPAMP Negative Power Supply Rejection Ratio
Figure 3.25. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V
Figure 3.26. OPAMP Voltage Noise Spectral Density (Non-Unity Gain)
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3.13 Analog Comparator (ACMP)
Table 3.18. ACMP
Symbol
Parameter
VACMPIN
Input voltage range
0
VDD V
VACMPCM
ACMP Common
Mode voltage range
0
VDD V
IACMP
IACMPREF
Active current
Current consumption of internal voltage reference
Condition
Min
Typ
Max
Unit
BIASPROG=0b0000, FULLBIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1
0.6 µA
BIASPROG=0b1111, FULLBIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
2.87
12 µA
BIASPROG=0b1111, FULLBIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
195
520 µA
Internal voltage reference off.
Using external voltage reference
0
µA
Internal voltage reference
5
µA
0
12 mV
VACMPOFFSET
Offset voltage
BIASPROG= 0b1010, FULLBIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
VACMPHYST
ACMP hysteresis
Programmable
17
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
39
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
71
kOhm
CSRESSEL=0b10 in
ACMPn_INPUTSEL
104
kOhm
CSRESSEL=0b11 in
ACMPn_INPUTSEL
136
kOhm
RCSRES
tACMPSTART
Capacitive Sense
Internal Resistance
Startup time
-12
10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 42) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
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Figure 3.27. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
4.5
2.5
HYSTSEL= 0.0
HYSTSEL= 2.0
HYSTSEL= 4.0
HYSTSEL= 6.0
4.0
3.5
Response Tim e [us]
Current [uA]
2.0
1.5
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0.5
0.0
4
8
ACMP_CTRL_BIASPROG
0
0.0
12
Current consumption, HYSTSEL = 4
0
2
4
6
8
10
ACMP_CTRL_BIASPROG
12
14
Response time
100
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
Hysteresis [m V]
80
60
40
20
0
0
1
2
4
3
ACMP_CTRL_HYSTSEL
5
6
7
Hysteresis
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3.14 Voltage Comparator (VCMP)
Table 3.19. VCMP
Symbol
Parameter
VVCMPIN
Input voltage range
VDD
V
VVCMPCM
VCMP Common
Mode voltage range
VDD
V
IVCMP
Condition
Min
Typ
Max
Unit
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.3
0.6 µA
BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
22
30 µA
NORMAL
10
µs
Single ended
10
mV
Differential
10
mV
61
210 mV
Active current
tVCMPREF
Startup time reference generator
VVCMPOFFSET
Offset voltage
VVCMPHYST
VCMP hysteresis
tVCMPSTART
Startup time
10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
(3.2)
3.15 EBI
Figure 3.28. EBI Write Enable Timing
WRSETUP
(0, 1, 2, ...)
EBI_BL[N- 1:0]
WRSTRB
(1, 2, 3, ...)
Z
EBI_BL
t OSU_WEn
EBI_A[N- 1:0]
t OH_WEn
Z
EBI_A
t OSU_WEn
EBI_AD[15:0]
WRHOLD
(0, 1, 2, ...)
t OH_WEn
Z
DATA[15:0]
t OSU_WEn
t OH_WEn
t OSU_WEn
t OH_WEn
EBI_CSn
t WIDTH_WEn
EBI_WEn
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Table 3.20. EBI Write Enable Timing
Symbol
Parameter
Min
tOH_WEn 1 2 3 4
Output hold time, from trailing EBI_WEn/
EBI_NANDWEn edge to EBI_AD, EBI_A,
EBI_CSn, EBI_BLn invalid
tOSU_WEn 1 2 3 4 5
Output setup time, from EBI_AD, EBI_A,
EBI_CSn, EBI_BLn valid to leading EBI_WEn/
EBI_NANDWEn edge
tWIDTH_WEn 1 2 3 4 5
EBI_WEn/EBI_NANDWEn pulse width
Typ
Max
Unit
-6.00 + (WRHOLD *
tHFCORECLK)
ns
-14.00 + (WRSETUP
* tHFCORECLK)
ns
-7.00 + ((WRSTRB
+1) * tHFCORECLK)
ns
1
Applies for all addressing modes (figure only shows D16 addressing mode)
Applies for both EBI_WEn and EBI_NANWEn (figure only shows EBI_WEn)
3
Applies for all polarities (figure only shows active low signals)
4
Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5
The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFWE=0. The leading edge
of EBI_WEn can be moved to the right by setting HALFWE=1. This decreases the length of tWIDTH_WEn and increases the length
of tOSU_WEn by 1/2 * tHFCLKNODIV.
2
Figure 3.29. EBI Address Latch Enable Related Output Timing
ADDRSETUP
(1, 2, 3, ...)
EBI_AD[15:0]
ADDRHOLD
(0, 1, 2, ...)
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
ADDR[16:1]
WRHOLD
(0, 1, 2, ...)
DATA[15:0]
Z
t WIDTH_ALEn
EBI_ALE
t OSU_ALEn
t WIDTH_ALEn
EBI_CSn
EBI_WEn
Table 3.21. EBI Address Latch Enable Related Output Timing
Symbol
Parameter
Min
Typ
Max
Unit
tOH_ALEn 1 2 3 4
Output hold time, from trailing EBI_ALE edge to
EBI_AD invalid
-6.00 + (AD5
DRHOLD * tHFCORECLK)
ns
tOSU_ALEn 1 2 4
Output setup time, from EBI_AD valid to leading
EBI_ALE edge
-13.00 + (0 * tHFCORECLK)
ns
tWIDTH_ALEn 1 2 3 4
EBI_ALEn pulse width
-7.00 + (ADDRSETUP+1) * tHFCORECLK)
ns
1
Applies to addressing modes D8A24ALE and D16A16ALE (figure only shows D16A16ALE)
Applies for all polarities (figure only shows active low signals)
3
The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFALE=0. The trailing edge
of EBI_ALE can be moved to the left by setting HALFALE=1. This decreases the length of tWIDTH_ALEn and increases the length
of tOH_ALEn by tHFCORECLK - 1/2 * tHFCLKNODIV.
4
Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5
Figure only shows a write operation. For a multiplexed read operation the address hold time is controlled via the RDSETUP state
instead of via the ADDRHOLD state.
2
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Figure 3.30. EBI Read Enable Related Output Timing
RDSETUP
(0, 1, 2, ...)
EBI_BL[1:0]
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
EBI_BL
Z
t SU_REn
EBI_A[27:0]
t H_REn
EBI_A
Z
t H_REn
t SU_REn
EBI_AD[15:8]
ADDR[7:0]
Z
t SU_REn
t H_REn
t SU_REn
t H_REn
EBI_CSn
EBI_AD[7:0]
Z
DATA[7:0]
Z
t WIDTH_REn
EBI_REn
Table 3.22. EBI Read Enable Related Output Timing
Symbol
Parameter
Min
Typ
Max
Unit
tOH_REn 1 2 3 4
Output hold time, from trailing EBI_REn/
EBI_NANDREn edge to EBI_AD, EBI_A, EBI_CSn,
EBI_BLn invalid
-10.00 + (RDHOLD *
tHFCORECLK)
ns
tOSU_REn 1 2 3 4 5
Output setup time, from EBI_AD, EBI_A, EBI_CSn,
EBI_BLn valid to leading EBI_REn/EBI_NANDREn
edge
-10.00 + (RDSETUP
* tHFCORECLK)
ns
tWIDTH_REn 1 2 3 4 5 6
EBI_REn pulse width
-9.00 + ((RDSTRB+1) * tHFCORECLK)
ns
1
Applies for all addressing modes (figure only shows D8A8. Output timing for EBI_AD only applies to multiplexed addressing
modes D8A24ALE and D16A16ALE)
2
Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn)
3
Applies for all polarities (figure only shows active low signals)
4
Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
5
The figure shows the timing for the case that the half strobe length functionality is not used, i.e. HALFRE=0. The leading edge
of EBI_REn can be moved to the right by setting HALFRE=1. This decreases the length of tWIDTH_REn and increases the length
of tOSU_REn by 1/2 * tHFCLKNODIV.
6
When page mode is used, RDSTRB is replaced by RDPA for page hits.
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Figure 3.31. EBI Read Enable Related Timing Requirements
EBI_A[N- 1:0]
ADDR[N:1]
EBI_AD[15:0]
Z
RDHOLD
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDSETUP
(0, 1, 2, ...)
Z
DATA[15:0]
Z
EBI_CSn
t SU_REn
EBI_REn
t H_REn
Table 3.23. EBI Read Enable Related Timing Requirements
Symbol
Parameter
Min
Typ
Max
Unit
tSU_REn 1 2 3 4
Setup time, from EBI_AD valid to trailing EBI_REn
edge
37
ns
tH_Ren 1 2 3 4
Hold time, from trailing EBI_REn edge to EBI_AD
invalid
-1
ns
1
Applies for all addressing modes (figure only shows D16A8).
Applies for both EBI_REn and EBI_NANDREn (figure only shows EBI_REn)
3
Applies for all polarities (figure only shows active low signals)
4
Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
2
Figure 3.32. EBI Ready/Wait Related Timing Requirements
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
SYNC
(3)
RDHOLD
(0, 1, 2, ...)
EBI_RDY
EBI_AD[15:0]
DATA[15:0]
Z
EBI_CSn
t SU_ARDY
EBI_REn
t H_ARDY
Table 3.24. EBI Ready/Wait Related Timing Requirements
Symbol
Parameter
Min
tSU_ARDY 1 2 3 4
Setup time, from EBI_ARDY valid to trailing
EBI_REn, EBI_WEn edge
37 + (3 * tHFCORECLK)
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
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Typ
Max
Unit
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Symbol
Parameter
Min
tH_ARDY 1 2 3 4
Hold time, from trailing EBI_REn, EBI_WEn edge
to EBI_ARDY invalid
Typ
Max
-1 + (3 * tHFCORECLK)
Unit
ns
1
Applies for all addressing modes (figure only shows D16A8.)
Applies for EBI_REn, EBI_WEn (figure only shows EBI_REn)
3
Applies for all polarities (figure only shows active low signals)
4
Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
2
3.16 LCD
Table 3.25. LCD
Symbol
Parameter
fLCDFR
Frame rate
NUMSEG
Number of segments supported
VLCD
LCD supply voltage
range
Condition
Min
Max
30
Unit
200 Hz
36×8
Internal boost circuit enabled
2.0
seg
3.8 V
Display disconnected, static mode, framerate 32 Hz, all
segments on.
250
nA
550
nA
0
µA
Internal voltage boost on,
boosting from 2.2 V to 3.0 V.
8.4
µA
VBLEV of LCD_DISPCTRL
register to LEVEL0
3.02
V
VBLEV of LCD_DISPCTRL
register to LEVEL1
3.15
V
VBLEV of LCD_DISPCTRL
register to LEVEL2
3.28
V
VBLEV of LCD_DISPCTRL
register to LEVEL3
3.41
V
VBLEV of LCD_DISPCTRL
register to LEVEL4
3.54
V
VBLEV of LCD_DISPCTRL
register to LEVEL5
3.67
V
VBLEV of LCD_DISPCTRL
register to LEVEL6
3.73
V
VBLEV of LCD_DISPCTRL
register to LEVEL7
3.74
V
ILCD
Steady state current
consumption.
Display disconnected, quadruplex mode, framerate 32
Hz, all segments on, bias
mode to ONETHIRD in
LCD_DISPCTRL register.
Steady state Current contribution of
internal boost.
Internal voltage boost off
ILCDBOOST
VBOOST
Typ
Boost Voltage
The total LCD current is given by Equation 3.3 (p. 48) . ILCDBOOST is zero if internal boost is off.
Total LCD Current Based on Operational Mode and Internal Boost
ILCDTOTAL = ILCD + ILCDBOOST
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3.17 I2C
Table 3.26. I2C Standard-mode (Sm)
Symbol
Parameter
Min
Typ
Max
fSCL
SCL clock frequency
tLOW
SCL clock low time
4.7
µs
tHIGH
SCL clock high time
4.0
µs
tSU,DAT
SDA set-up time
250
0
Unit
100
1
kHz
ns
2,3
tHD,DAT
SDA hold time
8
3450
ns
tSU,STA
Repeated START condition set-up time
4.7
µs
tHD,STA
(Repeated) START condition hold time
4.0
µs
tSU,STO
STOP condition set-up time
4.0
µs
tBUF
Bus free time between a STOP and START condition
4.7
µs
1
For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32GG Reference Manual.
The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3
-9
When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10 [s] * fHFPERCLK [Hz]) - 4).
2
Table 3.27. I2C Fast-mode (Fm)
Symbol
Parameter
Min
Typ
fSCL
SCL clock frequency
tLOW
SCL clock low time
1.3
µs
tHIGH
SCL clock high time
0.6
µs
tSU,DAT
SDA set-up time
100
ns
tHD,DAT
SDA hold time
tSU,STA
Repeated START condition set-up time
0.6
µs
tHD,STA
(Repeated) START condition hold time
0.6
µs
tSU,STO
STOP condition set-up time
0.6
µs
tBUF
Bus free time between a STOP and START condition
1.3
µs
0
8
Max
Unit
400
1
2,3
900
kHz
ns
1
For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32GG Reference Manual.
The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3
-9
When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10 [s] * fHFPERCLK [Hz]) - 4).
2
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Table 3.28. I2C Fast-mode Plus (Fm+)
Symbol
Parameter
Min
Typ
Max
Unit
fSCL
SCL clock frequency
tLOW
SCL clock low time
0.5
µs
tHIGH
SCL clock high time
0.26
µs
tSU,DAT
SDA set-up time
50
ns
tHD,DAT
SDA hold time
8
ns
tSU,STA
Repeated START condition set-up time
0.26
µs
tHD,STA
(Repeated) START condition hold time
0.26
µs
tSU,STO
STOP condition set-up time
0.26
µs
tBUF
Bus free time between a STOP and START condition
0.5
µs
1
0
1000
kHz
1
For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32GG Reference Manual.
3.18 USART SPI
Figure 3.33. SPI Master Timing
CS
t CS_MO
t SCKL_MO
SCLK
CLKPOL = 0
t SCLK
SCLK
CLKPOL = 1
MOSI
t SU_MI
t H_MI
MISO
Table 3.29. SPI Master Timing
Symbol
Parameter
tSCLK 1 2
SCLK period
Condition
Min
Typ
2 * tHFPER-
Max
Unit
ns
CLK
tCS_MO 1 2
CS to MOSI
-2.00
1.00 ns
tSCLK_MO 1 2
SCLK to MOSI
-4.00
3.00 ns
IOVDD = 1.98 V
36.00
ns
tSU_MI 1 2
MISO setup time
IOVDD = 3.0 V
29.00
ns
-4.00
ns
tH_MI 1 2
MISO hold time
1
Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
2
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Figure 3.34. SPI Slave Timing
CS
t CS_ACT_MI
t CS_DIS_MI
SCLK
CLKPOL = 0
SCLK
CLKPOL = 1
t SCLK_HI
t SU_MO
t SCLK_LO
t SCLK
t H_MO
MOSI
t SCLK_MI
MISO
Table 3.30. SPI Slave Timing
Symbol
Parameter
tSCLK_sl 1 2
SCKL period
Min
Typ
Max
Unit
2 * tHFPER-
ns
CLK
tSCLK_hi 1 2
SCLK high period
3 * tHFPER-
ns
CLK
tSCLK_lo
12
SCLK low period
3 * tHFPER-
ns
CLK
tCS_ACT_MI 1 2
CS active to MISO
4.00
30.00 ns
tCS_DIS_MI 1 2
CS disable to MISO
4.00
30.00 ns
tSU_MO 1 2
MOSI setup time
4.00
ns
tH_MO 1 2
MOSI hold time
2 + 2* tHF-
ns
PERCLK
tSCLK_MI 1 2
SCLK to MISO
9 + tHFPER-
36 + 2*tHF- ns
CLK
PERCLK
1
Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2
Measurement done at 10% and 90% of VDD (figure shows 50% of VDD)
3.19 Digital Peripherals
Table 3.31. Digital Peripherals
Symbol
Parameter
Condition
IUSART
USART current
USART idle current, clock enabled
4.9
µA/
MHz
IUART
UART current
UART idle current, clock enabled
3.4
µA/
MHz
ILEUART
LEUART current
LEUART idle current, clock enabled
140
nA
II2C
I2C current
I2C idle current, clock enabled
6.1
µA/
MHz
ITIMER
TIMER current
TIMER_0 idle current, clock
enabled
6.9
µA/
MHz
ILETIMER
LETIMER current
LETIMER idle current, clock
enabled
119
nA
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Min
51
Typ
Max
Unit
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Symbol
Parameter
Condition
IPCNT
PCNT current
PCNT idle current, clock enabled
54
nA
IRTC
RTC current
RTC idle current, clock enabled
54
nA
ILCD
LCD current
LCD idle current, clock enabled
68
nA
IAES
AES current
AES idle current, clock enabled
3.2
µA/
MHz
IGPIO
GPIO current
GPIO idle current, clock enabled
3.7
µA/
MHz
IEBI
EBI current
EBI idle current, clock enabled
11.8
µA/
MHz
IPRS
PRS current
PRS idle current
3.5
µA/
MHz
IDMA
DMA current
Clock enable
11.0
µA/
MHz
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
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52
Typ
Max
Unit
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32GG880.
4.1 Pinout
The EFM32GG880 pinout is shown in Figure 4.1 (p. 53) and Table 4.1 (p. 53). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32GG880 Pinout (top view, not to scale)
Table 4.1. Device Pinout
Pin Alternate Functionality / Description
Pin #
LQFP100 Pin#
and Name
Pin Name
Analog
EBI
Timers
Communication
Other
1
PA0
LCD_SEG13
EBI_AD09 #0/1/2
TIM0_CC0 #0/1/4
I2C0_SDA #0
LEU0_RX #4
PRS_CH0 #0
GPIO_EM4WU0
2
PA1
LCD_SEG14
EBI_AD10 #0/1/2
TIM0_CC1 #0/1
I2C0_SCL #0
CMU_CLK1 #0
PRS_CH1 #0
3
PA2
LCD_SEG15
EBI_AD11 #0/1/2
TIM0_CC2 #0/1
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Pin #
LQFP100 Pin#
and Name
Pin Name
Pin Alternate Functionality / Description
Analog
EBI
Timers
Communication
Other
ETM_TD0 #3
4
PA3
LCD_SEG16
EBI_AD12 #0/1/2
TIM0_CDTI0 #0
U0_TX #2
LES_ALTEX2 #0
ETM_TD1 #3
5
PA4
LCD_SEG17
EBI_AD13 #0/1/2
TIM0_CDTI1 #0
U0_RX #2
LES_ALTEX3 #0
ETM_TD2 #3
6
PA5
LCD_SEG18
EBI_AD14 #0/1/2
TIM0_CDTI2 #0
LEU1_TX #1
LES_ALTEX4 #0
ETM_TD3 #3
7
PA6
LCD_SEG19
EBI_AD15 #0/1/2
LEU1_RX #1
ETM_TCLK #3
GPIO_EM4WU1
8
IOVDD_0
9
PB0
LCD_SEG32
EBI_A16 #0/1/2
TIM1_CC0 #2
10
PB1
LCD_SEG33
EBI_A17 #0/1/2
TIM1_CC1 #2
11
PB2
LCD_SEG34
EBI_A18 #0/1/2
TIM1_CC2 #2
12
PB3
LCD_SEG20/
LCD_COM4
EBI_A19 #0/1/2
PCNT1_S0IN #1
US2_TX #1
13
PB4
LCD_SEG21/
LCD_COM5
EBI_A20 #0/1/2
PCNT1_S1IN #1
US2_RX #1
14
PB5
LCD_SEG22/
LCD_COM6
EBI_A21 #0/1/2
US2_CLK #1
15
PB6
LCD_SEG23/
LCD_COM7
EBI_A22 #0/1/2
US2_CS #1
16
VSS
17
IOVDD_1
18
PC0
ACMP0_CH0
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
EBI_A23 #0/1/2
TIM0_CC1 #4
PCNT0_S0IN #2
US0_TX #5
US1_TX #0
I2C0_SDA #4
LES_CH0 #0
PRS_CH2 #0
19
PC1
ACMP0_CH1
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
EBI_A24 #0/1/2
TIM0_CC2 #4
PCNT0_S1IN #2
US0_RX #5
US1_RX #0
I2C0_SCL #4
LES_CH1 #0
PRS_CH3 #0
20
PC2
ACMP0_CH2
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
EBI_A25 #0/1/2
TIM0_CDTI0 #4
US2_TX #0
LES_CH2 #0
21
PC3
ACMP0_CH3
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
22
PC4
ACMP0_CH4
DAC0_P0 /
OPAMP_P0
EBI_A26 #0/1/2
TIM0_CDTI2 #4
LETIM0_OUT0 #3
PCNT1_S0IN #0
US2_CLK #0
I2C1_SDA #0
LES_CH4 #0
23
PC5
ACMP0_CH5
DAC0_N0 /
OPAMP_N0
EBI_NANDWEn #0/1/2
LETIM0_OUT1 #3
PCNT1_S1IN #0
US2_CS #0
I2C1_SCL #0
LES_CH5 #0
24
PB7
LFXTAL_P
TIM1_CC0 #3
US0_TX #4
US1_CLK #0
25
PB8
LFXTAL_N
TIM1_CC1 #3
US0_RX #4
US1_CS #0
26
PA7
LCD_SEG35
EBI_CSTFT #0/1/2
27
PA8
LCD_SEG36
EBI_DCLK #0/1/2
TIM2_CC0 #0
28
PA9
LCD_SEG37
EBI_DTEN #0/1/2
TIM2_CC1 #0
29
PA10
LCD_SEG38
EBI_VSNC #0/1/2
TIM2_CC2 #0
30
PA11
LCD_SEG39
EBI_HSNC #0/1/2
Digital IO power supply 0.
Ground
Digital IO power supply 1.
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Pin Alternate Functionality / Description
Pin #
LQFP100 Pin#
and Name
Pin Name
Analog
EBI
Timers
Communication
Other
31
IOVDD_2
32
VSS
33
PA12
LCD_BCAP_P
EBI_A00 #0/1/2
TIM2_CC0 #1
34
PA13
LCD_BCAP_N
EBI_A01 #0/1/2
TIM2_CC1 #1
35
PA14
LCD_BEXT
EBI_A02 #0/1/2
TIM2_CC2 #1
36
RESETn
37
PB9
EBI_A03 #0/1/2
U1_TX #2
38
PB10
EBI_A04 #0/1/2
U1_RX #2
39
PB11
DAC0_OUT0 /
OPAMP_OUT0
LETIM0_OUT0 #1
TIM1_CC2 #3
I2C1_SDA #1
40
PB12
DAC0_OUT1 /
OPAMP_OUT1
LETIM0_OUT1 #1
I2C1_SCL #1
41
AVDD_1
Analog power supply 1.
42
PB13
HFXTAL_P
US0_CLK #4/5
LEU0_TX #1
43
PB14
HFXTAL_N
US0_CS #4/5
LEU0_RX #1
44
IOVDD_3
Digital IO power supply 3.
45
AVDD_0
Analog power supply 0.
46
PD0
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
OPAMP_OUT2 #1
PCNT2_S0IN #0
US1_TX #1
47
PD1
ADC0_CH1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
TIM0_CC0 #3
PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
48
PD2
ADC0_CH2
TIM0_CC1 #3
US1_CLK #1
DBG_SWO #3
49
PD3
ADC0_CH3
OPAMP_N2
TIM0_CC2 #3
US1_CS #1
ETM_TD1 #0/2
50
PD4
ADC0_CH4
OPAMP_P2
LEU0_TX #0
ETM_TD2 #0/2
51
PD5
ADC0_CH5
OPAMP_OUT2 #0
LEU0_RX #0
ETM_TD3 #0/2
52
PD6
ADC0_CH6
DAC0_P1 /
OPAMP_P1
LETIM0_OUT0 #0
TIM1_CC0 #4
PCNT0_S0IN #3
US1_RX #2
I2C0_SDA #1
LES_ALTEX0 #0
ACMP0_O #2
ETM_TD0 #0
53
PD7
ADC0_CH7
DAC0_N1 /
OPAMP_N1
LETIM0_OUT1 #0
TIM1_CC1 #4
PCNT0_S1IN #3
US1_TX #2
I2C0_SCL #1
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
ETM_TCLK #0
54
PD8
BU_VIN
55
PC6
ACMP0_CH6
EBI_A05 #0/1/2
I2C0_SDA #2
LEU1_TX #0
LES_CH6 #0
ETM_TCLK #2
56
PC7
ACMP0_CH7
EBI_A06 #0/1/2
I2C0_SCL #2
LEU1_RX #0
LES_CH7 #0
ETM_TD0 #2
57
VDD_DREG
58
VSS
59
DECOUPLE
Digital IO power supply 2.
Ground
Reset input, active low.
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up ensure
that reset is released.
EBI_A27 #0/1/2
CMU_CLK1 #1
Power supply for on-chip voltage regulator.
Ground
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
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Pin Alternate Functionality / Description
Pin #
LQFP100 Pin#
and Name
Pin Name
Analog
EBI
Timers
Communication
Other
60
PE0
EBI_A07 #0/1/2
TIM3_CC0 #1
PCNT0_S0IN #1
U0_TX #1
I2C1_SDA #2
61
PE1
EBI_A08 #0/1/2
TIM3_CC1 #1
PCNT0_S1IN #1
U0_RX #1
I2C1_SCL #2
62
PE2
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
63
PE3
BU_STAT
EBI_A10 #0
U1_RX #3
ACMP1_O #1
64
PE4
LCD_COM0
EBI_A11 #0/1/2
US0_CS #1
65
PE5
LCD_COM1
EBI_A12 #0/1/2
US0_CLK #1
66
PE6
LCD_COM2
EBI_A13 #0/1/2
US0_RX #1
67
PE7
LCD_COM3
EBI_A14 #0/1/2
US0_TX #1
68
PC8
ACMP1_CH0
EBI_A15 #0/1/2
TIM2_CC0 #2
US0_CS #2
LES_CH8 #0
69
PC9
ACMP1_CH1
EBI_A09 #1/2
TIM2_CC1 #2
US0_CLK #2
LES_CH9 #0
GPIO_EM4WU2
70
PC10
ACMP1_CH2
EBI_A10 #1/2
TIM2_CC2 #2
US0_RX #2
LES_CH10 #0
71
PC11
ACMP1_CH3
EBI_ALE #1/2
US0_TX #2
LES_CH11 #0
72
PC12
ACMP1_CH4
DAC0_OUT1ALT #0/
OPAMP_OUT1ALT
U1_TX #0
CMU_CLK0 #1
LES_CH12 #0
73
PC13
ACMP1_CH5
DAC0_OUT1ALT #1/
OPAMP_OUT1ALT
TIM0_CDTI0 #1/3
TIM1_CC0 #0
TIM1_CC2 #4
PCNT0_S0IN #0
U1_RX #0
LES_CH13 #0
74
PC14
ACMP1_CH6
DAC0_OUT1ALT #2/
OPAMP_OUT1ALT
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
US0_CS #3
U0_TX #3
LES_CH14 #0
75
PC15
ACMP1_CH7
DAC0_OUT1ALT #3/
OPAMP_OUT1ALT
TIM0_CDTI2 #1/3
TIM1_CC2 #0
US0_CLK #3
U0_RX #3
LES_CH15 #0
DBG_SWO #1
76
PF0
TIM0_CC0 #5
LETIM0_OUT0 #2
US1_CLK #2
I2C0_SDA #5
LEU0_TX #3
DBG_SWCLK #0/1/2/3
77
PF1
TIM0_CC1 #5
LETIM0_OUT1 #2
US1_CS #2
I2C0_SCL #5
LEU0_RX #3
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
78
PF2
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
LEU0_TX #4
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
79
PF3
LCD_SEG1
EBI_ALE #0
TIM0_CDTI0 #2/5
PRS_CH0 #1
ETM_TD3 #1
80
PF4
LCD_SEG2
EBI_WEn #0/2
TIM0_CDTI1 #2/5
PRS_CH1 #1
81
PF5
LCD_SEG3
EBI_REn #0/2
TIM0_CDTI2 #2/5
PRS_CH2 #1
82
IOVDD_5
83
VSS
84
PF6
LCD_SEG24
EBI_BL0 #0/1/2
TIM0_CC0 #2
U0_TX #0
85
PF7
LCD_SEG25
EBI_BL1 #0/1/2
TIM0_CC1 #2
U0_RX #0
86
PF8
LCD_SEG26
EBI_WEn #1
TIM0_CC2 #2
87
PF9
LCD_SEG27
EBI_REn #1
88
PD9
LCD_SEG28
EBI_CS0 #0/1/2
89
PD10
LCD_SEG29
EBI_CS1 #0/1/2
Digital IO power supply 5.
Ground
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
ETM_TCLK #1
ETM_TD0 #1
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Pin Alternate Functionality / Description
Pin #
LQFP100 Pin#
and Name
Pin Name
Analog
EBI
Timers
Communication
Other
90
PD11
LCD_SEG30
EBI_CS2 #0/1/2
91
PD12
LCD_SEG31
EBI_CS3 #0/1/2
92
PE8
LCD_SEG4
EBI_AD00 #0/1/2
PCNT2_S0IN #1
93
PE9
LCD_SEG5
EBI_AD01 #0/1/2
PCNT2_S1IN #1
94
PE10
LCD_SEG6
EBI_AD02 #0/1/2
TIM1_CC0 #1
US0_TX #0
BOOT_TX
95
PE11
LCD_SEG7
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
LES_ALTEX5 #0
BOOT_RX
96
PE12
LCD_SEG8
EBI_AD04 #0/1/2
TIM1_CC2 #1
US0_RX #3
US0_CLK #0
I2C0_SDA #6
CMU_CLK1 #2
LES_ALTEX6 #0
97
PE13
LCD_SEG9
EBI_AD05 #0/1/2
US0_TX #3
US0_CS #0
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
98
PE14
LCD_SEG10
EBI_AD06 #0/1/2
TIM3_CC0 #0
LEU0_TX #2
99
PE15
LCD_SEG11
EBI_AD07 #0/1/2
TIM3_CC1 #0
LEU0_RX #2
100
PA15
LCD_SEG12
EBI_AD08 #0/1/2
TIM3_CC2 #0
PRS_CH3 #1
4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 57) . The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout is shown in the column corresponding to LOCATION 0.
Table 4.2. Alternate functionality overview
Alternate
Functionality
LOCATION
0
1
2
3
4
5
6
Description
ACMP0_CH0
PC0
Analog comparator ACMP0, channel 0.
ACMP0_CH1
PC1
Analog comparator ACMP0, channel 1.
ACMP0_CH2
PC2
Analog comparator ACMP0, channel 2.
ACMP0_CH3
PC3
Analog comparator ACMP0, channel 3.
ACMP0_CH4
PC4
Analog comparator ACMP0, channel 4.
ACMP0_CH5
PC5
Analog comparator ACMP0, channel 5.
ACMP0_CH6
PC6
Analog comparator ACMP0, channel 6.
ACMP0_CH7
PC7
Analog comparator ACMP0, channel 7.
ACMP0_O
PE13
ACMP1_CH0
PC8
Analog comparator ACMP1, channel 0.
ACMP1_CH1
PC9
Analog comparator ACMP1, channel 1.
ACMP1_CH2
PC10
Analog comparator ACMP1, channel 2.
ACMP1_CH3
PC11
Analog comparator ACMP1, channel 3.
PE2
PD6
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
Analog comparator ACMP0, digital output.
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Alternate
Functionality
LOCATION
0
1
2
3
4
5
6
Description
ACMP1_CH4
PC12
Analog comparator ACMP1, channel 4.
ACMP1_CH5
PC13
Analog comparator ACMP1, channel 5.
ACMP1_CH6
PC14
Analog comparator ACMP1, channel 6.
ACMP1_CH7
PC15
Analog comparator ACMP1, channel 7.
ACMP1_O
PF2
ADC0_CH0
PD0
Analog to digital converter ADC0, input channel number 0.
ADC0_CH1
PD1
Analog to digital converter ADC0, input channel number 1.
ADC0_CH2
PD2
Analog to digital converter ADC0, input channel number 2.
ADC0_CH3
PD3
Analog to digital converter ADC0, input channel number 3.
ADC0_CH4
PD4
Analog to digital converter ADC0, input channel number 4.
ADC0_CH5
PD5
Analog to digital converter ADC0, input channel number 5.
ADC0_CH6
PD6
Analog to digital converter ADC0, input channel number 6.
ADC0_CH7
PD7
Analog to digital converter ADC0, input channel number 7.
BOOT_RX
PE11
Bootloader RX
BOOT_TX
PE10
Bootloader TX
BU_STAT
PE3
Backup Power Domain status, whether or not the system is in
backup mode
BU_VIN
PD8
Battery input for Backup Power Domain
BU_VOUT
PE2
Power output for Backup Power Domain
CMU_CLK0
PA2
PC12
PD7
Clock Management Unit, clock output number 0.
CMU_CLK1
PA1
PD8
PE12
Clock Management Unit, clock output number 1.
DAC0_N0 /
OPAMP_N0
PC5
Operational Amplifier 0 external negative input.
DAC0_N1 /
OPAMP_N1
PD7
Operational Amplifier 1 external negative input.
OPAMP_N2
PD3
Operational Amplifier 2 external negative input.
DAC0_OUT0 /
OPAMP_OUT0
PB11
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
PC0
OPAMP_OUT0ALT
DAC0_OUT1 /
OPAMP_OUT1
PE3
PC1
PD7
PC2
Analog comparator ACMP1, digital output.
PC3
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PD0
Digital to Analog Converter DAC0_OUT1 /
OPAMP output channel number 1.
PB12
DAC0_OUT1ALT /
PC12
OPAMP_OUT1ALT
PC13
OPAMP_OUT2
PD5
PD0
DAC0_P0 /
OPAMP_P0
PC4
Operational Amplifier 0 external positive input.
DAC0_P1 /
OPAMP_P1
PD6
Operational Amplifier 1 external positive input.
OPAMP_P2
PD4
Operational Amplifier 2 external positive input.
DBG_SWCLK
PF0
PF0
PF0
PF0
DBG_SWDIO
PF1
PF1
PF1
PF1
Note that this function is enabled to pin out of reset, and has
a built-in pull up.
DBG_SWO
PF2
PC15
PD1
PD2
Debug-interface Serial Wire viewer Output.
PC14
PC15
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
PD1
Operational Amplifier 2 output.
Debug-interface Serial Wire clock input.
Note that this function is enabled to pin out of reset, and has
a built-in pull down.
Debug-interface Serial Wire data input / output.
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Alternate
Functionality
LOCATION
0
1
2
3
4
5
6
Description
Note that this function is not enabled after reset, and must be
enabled by software to be used.
EBI_A00
PA12
PA12
PA12
External Bus Interface (EBI) address output pin 00.
EBI_A01
PA13
PA13
PA13
External Bus Interface (EBI) address output pin 01.
EBI_A02
PA14
PA14
PA14
External Bus Interface (EBI) address output pin 02.
EBI_A03
PB9
PB9
PB9
External Bus Interface (EBI) address output pin 03.
EBI_A04
PB10
PB10
PB10
External Bus Interface (EBI) address output pin 04.
EBI_A05
PC6
PC6
PC6
External Bus Interface (EBI) address output pin 05.
EBI_A06
PC7
PC7
PC7
External Bus Interface (EBI) address output pin 06.
EBI_A07
PE0
PE0
PE0
External Bus Interface (EBI) address output pin 07.
EBI_A08
PE1
PE1
PE1
External Bus Interface (EBI) address output pin 08.
EBI_A09
PE2
PC9
PC9
External Bus Interface (EBI) address output pin 09.
EBI_A10
PE3
PC10
PC10
External Bus Interface (EBI) address output pin 10.
EBI_A11
PE4
PE4
PE4
External Bus Interface (EBI) address output pin 11.
EBI_A12
PE5
PE5
PE5
External Bus Interface (EBI) address output pin 12.
EBI_A13
PE6
PE6
PE6
External Bus Interface (EBI) address output pin 13.
EBI_A14
PE7
PE7
PE7
External Bus Interface (EBI) address output pin 14.
EBI_A15
PC8
PC8
PC8
External Bus Interface (EBI) address output pin 15.
EBI_A16
PB0
PB0
PB0
External Bus Interface (EBI) address output pin 16.
EBI_A17
PB1
PB1
PB1
External Bus Interface (EBI) address output pin 17.
EBI_A18
PB2
PB2
PB2
External Bus Interface (EBI) address output pin 18.
EBI_A19
PB3
PB3
PB3
External Bus Interface (EBI) address output pin 19.
EBI_A20
PB4
PB4
PB4
External Bus Interface (EBI) address output pin 20.
EBI_A21
PB5
PB5
PB5
External Bus Interface (EBI) address output pin 21.
EBI_A22
PB6
PB6
PB6
External Bus Interface (EBI) address output pin 22.
EBI_A23
PC0
PC0
PC0
External Bus Interface (EBI) address output pin 23.
EBI_A24
PC1
PC1
PC1
External Bus Interface (EBI) address output pin 24.
EBI_A25
PC2
PC2
PC2
External Bus Interface (EBI) address output pin 25.
EBI_A26
PC4
PC4
PC4
External Bus Interface (EBI) address output pin 26.
EBI_A27
PD2
PD2
PD2
External Bus Interface (EBI) address output pin 27.
EBI_AD00
PE8
PE8
PE8
External Bus Interface (EBI) address and data input / output
pin 00.
EBI_AD01
PE9
PE9
PE9
External Bus Interface (EBI) address and data input / output
pin 01.
EBI_AD02
PE10
PE10
PE10
External Bus Interface (EBI) address and data input / output
pin 02.
EBI_AD03
PE11
PE11
PE11
External Bus Interface (EBI) address and data input / output
pin 03.
EBI_AD04
PE12
PE12
PE12
External Bus Interface (EBI) address and data input / output
pin 04.
EBI_AD05
PE13
PE13
PE13
External Bus Interface (EBI) address and data input / output
pin 05.
EBI_AD06
PE14
PE14
PE14
External Bus Interface (EBI) address and data input / output
pin 06.
EBI_AD07
PE15
PE15
PE15
External Bus Interface (EBI) address and data input / output
pin 07.
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Alternate
Functionality
LOCATION
0
1
EBI_AD08
PA15
PA15
PA15
External Bus Interface (EBI) address and data input / output
pin 08.
EBI_AD09
PA0
PA0
PA0
External Bus Interface (EBI) address and data input / output
pin 09.
EBI_AD10
PA1
PA1
PA1
External Bus Interface (EBI) address and data input / output
pin 10.
EBI_AD11
PA2
PA2
PA2
External Bus Interface (EBI) address and data input / output
pin 11.
EBI_AD12
PA3
PA3
PA3
External Bus Interface (EBI) address and data input / output
pin 12.
EBI_AD13
PA4
PA4
PA4
External Bus Interface (EBI) address and data input / output
pin 13.
EBI_AD14
PA5
PA5
PA5
External Bus Interface (EBI) address and data input / output
pin 14.
EBI_AD15
PA6
PA6
PA6
External Bus Interface (EBI) address and data input / output
pin 15.
EBI_ALE
PF3
PC11
PC11
External Bus Interface (EBI) Address Latch Enable output.
EBI_ARDY
PF2
PF2
PF2
External Bus Interface (EBI) Hardware Ready Control input.
EBI_BL0
PF6
PF6
PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
EBI_BL1
PF7
PF7
PF7
External Bus Interface (EBI) Byte Lane/Enable pin 1.
EBI_CS0
PD9
PD9
PD9
External Bus Interface (EBI) Chip Select output 0.
EBI_CS1
PD10
PD10
PD10
External Bus Interface (EBI) Chip Select output 1.
EBI_CS2
PD11
PD11
PD11
External Bus Interface (EBI) Chip Select output 2.
EBI_CS3
PD12
PD12
PD12
External Bus Interface (EBI) Chip Select output 3.
EBI_CSTFT
PA7
PA7
PA7
External Bus Interface (EBI) Chip Select output TFT.
EBI_DCLK
PA8
PA8
PA8
External Bus Interface (EBI) TFT Dot Clock pin.
EBI_DTEN
PA9
PA9
PA9
External Bus Interface (EBI) TFT Data Enable pin.
EBI_HSNC
PA11
PA11
PA11
External Bus Interface (EBI) TFT Horizontal Synchronization
pin.
EBI_NANDREn
PC3
PC3
PC3
External Bus Interface (EBI) NAND Read Enable output.
EBI_NANDWEn
PC5
PC5
PC5
External Bus Interface (EBI) NAND Write Enable output.
EBI_REn
PF5
PF9
PF5
External Bus Interface (EBI) Read Enable output.
EBI_VSNC
PA10
PA10
PA10
External Bus Interface (EBI) TFT Vertical Synchronization
pin.
EBI_WEn
PF4
PF8
PF4
External Bus Interface (EBI) Write Enable output.
ETM_TCLK
PD7
PF8
PC6
PA6
Embedded Trace Module ETM clock .
ETM_TD0
PD6
PF9
PC7
PA2
Embedded Trace Module ETM data 0.
ETM_TD1
PD3
PD3
PA3
Embedded Trace Module ETM data 1.
ETM_TD2
PD4
PD4
PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PD5
PD5
PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0
PA0
Pin can be used to wake the system up from EM4
GPIO_EM4WU1
PA6
Pin can be used to wake the system up from EM4
GPIO_EM4WU2
PC9
Pin can be used to wake the system up from EM4
GPIO_EM4WU3
PF1
Pin can be used to wake the system up from EM4
GPIO_EM4WU4
PF2
Pin can be used to wake the system up from EM4
GPIO_EM4WU5
PE13
Pin can be used to wake the system up from EM4
PF3
2
3
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5
60
6
Description
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Alternate
Functionality
LOCATION
0
1
2
3
4
5
6
Description
HFXTAL_N
PB14
High Frequency Crystal negative pin. Also used as external
optional clock input pin.
HFXTAL_P
PB13
High Frequency Crystal positive pin.
I2C0_SCL
PA1
PD7
PC7
PC1
PF1
PE13
I2C0 Serial Clock Line input / output.
I2C0_SDA
PA0
PD6
PC6
PC0
PF0
PE12
I2C0 Serial Data input / output.
I2C1_SCL
PC5
PB12
PE1
I2C1 Serial Clock Line input / output.
I2C1_SDA
PC4
PB11
PE0
I2C1 Serial Data input / output.
LCD_BCAP_N
PA13
LCD voltage booster (optional), boost capacitor, negative pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_P
PA12
LCD voltage booster (optional), boost capacitor, positive pin.
If using the LCD voltage booster, connect a 22 nF capacitor
between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the
LCD voltage booster, connect a 1 uF capacitor between this
pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if the
booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this pin
may be left unconnected or used as a GPIO.
LCD_COM0
PE4
LCD driver common line number 0.
LCD_COM1
PE5
LCD driver common line number 1.
LCD_COM2
PE6
LCD driver common line number 2.
LCD_COM3
PE7
LCD driver common line number 3.
LCD_SEG0
PF2
LCD segment line 0. Segments 0, 1, 2 and 3 are controlled
by SEGEN0.
LCD_SEG1
PF3
LCD segment line 1. Segments 0, 1, 2 and 3 are controlled
by SEGEN0.
LCD_SEG2
PF4
LCD segment line 2. Segments 0, 1, 2 and 3 are controlled
by SEGEN0.
LCD_SEG3
PF5
LCD segment line 3. Segments 0, 1, 2 and 3 are controlled
by SEGEN0.
LCD_SEG4
PE8
LCD segment line 4. Segments 4, 5, 6 and 7 are controlled
by SEGEN1.
LCD_SEG5
PE9
LCD segment line 5. Segments 4, 5, 6 and 7 are controlled
by SEGEN1.
LCD_SEG6
PE10
LCD segment line 6. Segments 4, 5, 6 and 7 are controlled
by SEGEN1.
LCD_SEG7
PE11
LCD segment line 7. Segments 4, 5, 6 and 7 are controlled
by SEGEN1.
LCD_SEG8
PE12
LCD segment line 8. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
LCD_SEG9
PE13
LCD segment line 9. Segments 8, 9, 10 and 11 are controlled
by SEGEN2.
LCD_SEG10
PE14
LCD segment line 10. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG11
PE15
LCD segment line 11. Segments 8, 9, 10 and 11 are controlled by SEGEN2.
LCD_SEG12
PA15
LCD segment line 12. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG13
PA0
LCD segment line 13. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG14
PA1
LCD segment line 14. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
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Alternate
Functionality
LOCATION
0
1
2
3
4
5
6
Description
LCD_SEG15
PA2
LCD segment line 15. Segments 12, 13, 14 and 15 are controlled by SEGEN3.
LCD_SEG16
PA3
LCD segment line 16. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG17
PA4
LCD segment line 17. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG18
PA5
LCD segment line 18. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG19
PA6
LCD segment line 19. Segments 16, 17, 18 and 19 are controlled by SEGEN4.
LCD_SEG20/
LCD_COM4
PB3
LCD segment line 20. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM
line 4
LCD_SEG21/
LCD_COM5
PB4
LCD segment line 21. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM
line 5
LCD_SEG22/
LCD_COM6
PB5
LCD segment line 22. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM
line 6
LCD_SEG23/
LCD_COM7
PB6
LCD segment line 23. Segments 20, 21, 22 and 23 are controlled by SEGEN5. This pin may also be used as LCD COM
line 7
LCD_SEG24
PF6
LCD segment line 24. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG25
PF7
LCD segment line 25. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG26
PF8
LCD segment line 26. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG27
PF9
LCD segment line 27. Segments 24, 25, 26 and 27 are controlled by SEGEN6.
LCD_SEG28
PD9
LCD segment line 28. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG29
PD10
LCD segment line 29. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG30
PD11
LCD segment line 30. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG31
PD12
LCD segment line 31. Segments 28, 29, 30 and 31 are controlled by SEGEN7.
LCD_SEG32
PB0
LCD segment line 32. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG33
PB1
LCD segment line 33. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG34
PB2
LCD segment line 34. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG35
PA7
LCD segment line 35. Segments 32, 33, 34 and 35 are controlled by SEGEN8.
LCD_SEG36
PA8
LCD segment line 36. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG37
PA9
LCD segment line 37. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG38
PA10
LCD segment line 38. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LCD_SEG39
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are controlled by SEGEN9.
LES_ALTEX0
PD6
LESENSE alternate exite output 0.
LES_ALTEX1
PD7
LESENSE alternate exite output 1.
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Alternate
Functionality
LOCATION
0
1
2
3
4
5
6
Description
LES_ALTEX2
PA3
LESENSE alternate exite output 2.
LES_ALTEX3
PA4
LESENSE alternate exite output 3.
LES_ALTEX4
PA5
LESENSE alternate exite output 4.
LES_ALTEX5
PE11
LESENSE alternate exite output 5.
LES_ALTEX6
PE12
LESENSE alternate exite output 6.
LES_ALTEX7
PE13
LESENSE alternate exite output 7.
LES_CH0
PC0
LESENSE channel 0.
LES_CH1
PC1
LESENSE channel 1.
LES_CH2
PC2
LESENSE channel 2.
LES_CH3
PC3
LESENSE channel 3.
LES_CH4
PC4
LESENSE channel 4.
LES_CH5
PC5
LESENSE channel 5.
LES_CH6
PC6
LESENSE channel 6.
LES_CH7
PC7
LESENSE channel 7.
LES_CH8
PC8
LESENSE channel 8.
LES_CH9
PC9
LESENSE channel 9.
LES_CH10
PC10
LESENSE channel 10.
LES_CH11
PC11
LESENSE channel 11.
LES_CH12
PC12
LESENSE channel 12.
LES_CH13
PC13
LESENSE channel 13.
LES_CH14
PC14
LESENSE channel 14.
LES_CH15
PC15
LESENSE channel 15.
LETIM0_OUT0
PD6
PB11
PF0
PC4
Low Energy Timer LETIM0, output channel 0.
LETIM0_OUT1
PD7
PB12
PF1
PC5
Low Energy Timer LETIM0, output channel 1.
LEU0_RX
PD5
PB14
PE15
PF1
PA0
LEUART0 Receive input.
LEU0_TX
PD4
PB13
PE14
PF0
PF2
LEUART0 Transmit output. Also used as receive input in half
duplex communication.
LEU1_RX
PC7
PA6
LEUART1 Receive input.
LEU1_TX
PC6
PA5
LEUART1 Transmit output. Also used as receive input in half
duplex communication.
LFXTAL_N
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin.
Also used as an optional external clock input pin.
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
PCNT0_S0IN
PC13
PE0
PC0
PD6
Pulse Counter PCNT0 input number 0.
PCNT0_S1IN
PC14
PE1
PC1
PD7
Pulse Counter PCNT0 input number 1.
PCNT1_S0IN
PC4
PB3
Pulse Counter PCNT1 input number 0.
PCNT1_S1IN
PC5
PB4
Pulse Counter PCNT1 input number 1.
PCNT2_S0IN
PD0
PE8
Pulse Counter PCNT2 input number 0.
PCNT2_S1IN
PD1
PE9
Pulse Counter PCNT2 input number 1.
PRS_CH0
PA0
PF3
Peripheral Reflex System PRS, channel 0.
PRS_CH1
PA1
PF4
Peripheral Reflex System PRS, channel 1.
PRS_CH2
PC0
PF5
Peripheral Reflex System PRS, channel 2.
PRS_CH3
PC1
PE8
Peripheral Reflex System PRS, channel 3.
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Alternate
Functionality
LOCATION
0
1
2
3
4
5
6
Description
TIM0_CC0
PA0
PA0
PF6
PD1
PA0
PF0
Timer 0 Capture Compare input / output channel 0.
TIM0_CC1
PA1
PA1
PF7
PD2
PC0
PF1
Timer 0 Capture Compare input / output channel 1.
TIM0_CC2
PA2
PA2
PF8
PD3
PC1
PF2
Timer 0 Capture Compare input / output channel 2.
TIM0_CDTI0
PA3
PC13
PF3
PC13
PC2
PF3
Timer 0 Complimentary Deat Time Insertion channel 0.
TIM0_CDTI1
PA4
PC14
PF4
PC14
PC3
PF4
Timer 0 Complimentary Deat Time Insertion channel 1.
TIM0_CDTI2
PA5
PC15
PF5
PC15
PC4
PF5
Timer 0 Complimentary Deat Time Insertion channel 2.
TIM1_CC0
PC13
PE10
PB0
PB7
PD6
Timer 1 Capture Compare input / output channel 0.
TIM1_CC1
PC14
PE11
PB1
PB8
PD7
Timer 1 Capture Compare input / output channel 1.
TIM1_CC2
PC15
PE12
PB2
PB11
PC13
Timer 1 Capture Compare input / output channel 2.
TIM2_CC0
PA8
PA12
PC8
Timer 2 Capture Compare input / output channel 0.
TIM2_CC1
PA9
PA13
PC9
Timer 2 Capture Compare input / output channel 1.
TIM2_CC2
PA10
PA14
PC10
Timer 2 Capture Compare input / output channel 2.
TIM3_CC0
PE14
PE0
Timer 3 Capture Compare input / output channel 0.
TIM3_CC1
PE15
PE1
Timer 3 Capture Compare input / output channel 1.
TIM3_CC2
PA15
PE2
Timer 3 Capture Compare input / output channel 2.
U0_RX
PF7
PE1
PA4
PC15
UART0 Receive input.
U0_TX
PF6
PE0
PA3
PC14
UART0 Transmit output. Also used as receive input in half
duplex communication.
U1_RX
PC13
PB10
PE3
UART1 Receive input.
U1_TX
PC12
PB9
PE2
UART1 Transmit output. Also used as receive input in half
duplex communication.
US0_CLK
PE12
PE5
PC9
PC15
PB13
PB13
USART0 clock input / output.
US0_CS
PE13
PE4
PC8
PC14
PB14
PB14
USART0 chip select input / output.
US0_RX
PE11
PE6
PC10
PE12
PB8
PC1
USART0 Asynchronous Receive.
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive input
in half duplex communication.
US0_TX
PE10
PE7
PC11
PE13
PB7
PC0
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
PB7
PD2
PF0
USART1 clock input / output.
US1_CS
PB8
PD3
PF1
USART1 chip select input / output.
US1_RX
PC1
PD1
PD6
USART1 Asynchronous Receive.
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive input
in half duplex communication.
US1_TX
PC0
PD0
PD7
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK
PC4
PB5
USART2 clock input / output.
US2_CS
PC5
PB6
USART2 chip select input / output.
US2_RX
PC3
PB4
US2_TX
PC2
PB3
USART2 Asynchronous Receive.
2014-05-23 - EFM32GG880FXX - d0042_Rev1.30
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive input
in half duplex communication.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32GG880 is shown in Table 4.3 (p. 65) . Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin
9
Pin
8
Pin
7
Pin
6
Pin
5
Pin
4
Pin
3
Pin
2
Pin
1
Pin
0
Port A
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port B
-
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port C
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Port D
-
-
-
PD12
PD11
PD10
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Port E
PE15
PE14
PE13
PE12
PE11
PE10
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
Port F
-
-
-
-
-
-
PF9
PF8
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
4.4 Opamp Pinout Overview
The specific opamp terminals available in EFM32GG880 is shown in Figure 4.2 (p. 65) .
Figure 4.2. Opamp Pinout
PC4
PC5
PD4
PD3
PD6
PD7
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OUT0ALT
+
OPA0
OUT0
+
OPA2
OUT2
OUT1ALT
+
OPA1
OUT1
-
65
PB11
PB12
PC0
PC1
PC2
PC3
PD0
PD1
PD5
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4.5 LQFP100 Package
Figure 4.3. LQFP100
Note:
1. Datum 'T', 'U' and 'Z' to be determined at datum plane 'H'.
2. Datum 'D' and 'E' to be determined at seating plane datum 'Y'.
3. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25 per side. Dimensions 'D1' and 'E1' do include mold mismatch and are determined at datum plane datum 'H'.
4. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause the
lead width to exceed the maximum 'b' dimension by more than 0.08 mm. Dambar can not be located
on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm
5. Exact shape of each corner is optional.
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Table 4.4. LQFP100 (Dimensions in mm)
SYMBOL
MIN
NOM
MAX
total thickness
A
--
--
1.6
stand off
A1
0.05
--
0.15
mold thickness
A2
1.35
1.4
1.45
lead width (plating)
b
0.17
0.2
0.27
lead width
b1
0.17
--
0.23
L/F thickness (plating)
c
0.09
--
0.2
lead thickness
c1
0.09
--
0.16
x
D
16 BSC
y
E
16 BSC
x
D1
14 BSC
y
E1
14 BSC
e
0.5 BSC
body size
lead pitch
L
footprint
0.45
L1
0.6
0.75
1 REF
θ
0°
3.5°
7°
θ1
0°
--
--
θ2
11°
12°
13°
θ3
11°
12°
13°
R1
0.08
--
--
R1
0.08
--
0.2
S
0.2
--
--
package edge tolerance
aaa
0.2
lead edge tolerance
bbb
0.2
coplanarity
ccc
0.08
lead offset
ddd
0.08
mold flatness
eee
0.05
The LQFP100 Package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. LQFP100 PCB Land Pattern
a
p8
p7
p6
p1
b
e
c
p2
p5
p3
p4
d
Table 5.1. QFP100 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
Symbol
Pin number
Symbol
Pin number
a
1.45
P1
1
P6
75
b
0.30
P2
25
P7
76
c
0.50
P3
26
P8
100
d
15.40
P4
50
-
-
e
15.40
P5
51
-
-
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Figure 5.2. LQFP100 PCB Solder Mask
a
b
e
c
d
Table 5.2. QFP100 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
1.57
b
0.42
c
0.50
d
15.40
e
15.40
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Figure 5.3. LQFP100 PCB Stencil Design
a
b
e
c
d
Table 5.3. QFP100 PCB Stencil Design Dimensions (Dimensions in mm)
1.
2.
3.
4.
5.
6.
Symbol
Dim. (mm)
a
1.35
b
0.20
c
0.50
d
15.40
e
15.40
The drawings are not to scale.
All dimensions are in millimeters.
All drawings are subject to change without notice.
The PCB Land Pattern drawing is in compliance with IPC-7351B.
Stencil thickness 0.125 mm.
For detailed pin-positioning, see Figure 4.3 (p. 66) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 71) .
6.3 Errata
Please see the errata document for EFM32GG880 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 1.30
May 23rd, 2014
Removed "preliminary" markings
Updated HFRCO figures.
Corrected single power supply voltage minimum value from 1.85V to 1.98V.
Updated Current Consumption information.
Updated Power Management information.
Updated GPIO information.
Updated LFRCO information.
Updated HFRCO information.
Updated ULFRCO information.
Updated ADC information.
Updated DAC information.
Updated OPAMP information.
Updated ACMP information.
Updated VCMP information.
Added AUXHFRCO information.
7.2 Revision 1.21
November 21st, 2013
Updated figures.
Updated errata-link.
Updated chip marking.
Added link to Environmental and Quality information.
Re-added missing DAC-data.
7.3 Revision 1.20
September 30th, 2013
Added I2C characterization data.
Added SPI characterization data.
Added EBI characterization data.
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Corrected the DAC and OPAMP2 pin sharing information in the Alternate Functionality Pinout section.
Corrected GPIO operating voltage from 1.8 V to 1.85 V.
Updated that the EM2 current consumption test was carried out with only one RAM block enabled.
Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
Updated Environmental information.
Updated trademark, disclaimer and contact information.
Other minor corrections.
7.4 Revision 1.10
June 28th, 2013
Updated power requirements in the Power Management section.
Removed minimum load capacitance figure and table. Added reference to application note.
Other minor corrections.
7.5 Revision 1.00
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Other minor corrections.
7.6 Revision 0.98
May 25th, 2012
Corrected EM3 current consumption in the Electrical Characteristics section.
7.7 Revision 0.96
February 28th, 2012
Added reference to errata document.
Corrected LQFP100 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.8 Revision 0.95
September 28th, 2011
Flash configuration for Giant Gecko is now 1024KB or 512KB. For flash sizes below 512KB, see the
Leopard Gecko Family.
Corrected operating voltage from 1.8 V to 1.85 V.
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Added rising POR level to Electrical Characteristics section.
Updated Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup.
Added Gain error drift and Offset error drift to ADC table.
Added Opamp pinout overview.
Added reference to errata document.
Corrected LQFP100 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.9 Revision 0.91
March 21th, 2011
Added new alternative locations for EBI and SWO.
Corrected slew rate data for Opamps.
7.10 Revision 0.90
February 4th, 2011
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 7
2.3. Memory Map ................................................................................................................................. 9
3. Electrical Characteristics ........................................................................................................................... 10
3.1. Test Conditions ............................................................................................................................. 10
3.2. Absolute Maximum Ratings ............................................................................................................. 10
3.3. General Operating Conditions .......................................................................................................... 10
3.4. Current Consumption ..................................................................................................................... 12
3.5. Transition between Energy Modes .................................................................................................... 12
3.6. Power Management ....................................................................................................................... 13
3.7. Flash .......................................................................................................................................... 14
3.8. General Purpose Input Output ......................................................................................................... 14
3.9. Oscillators .................................................................................................................................... 22
3.10. Analog Digital Converter (ADC) ...................................................................................................... 27
3.11. Digital Analog Converter (DAC) ...................................................................................................... 37
3.12. Operational Amplifier (OPAMP) ...................................................................................................... 38
3.13. Analog Comparator (ACMP) .......................................................................................................... 42
3.14. Voltage Comparator (VCMP) ......................................................................................................... 44
3.15. EBI ........................................................................................................................................... 44
3.16. LCD .......................................................................................................................................... 48
3.17. I2C ........................................................................................................................................... 49
3.18. USART SPI ................................................................................................................................ 50
3.19. Digital Peripherals ....................................................................................................................... 51
4. Pinout and Package ................................................................................................................................. 53
4.1. Pinout ......................................................................................................................................... 53
4.2. Alternate Functionality Pinout .......................................................................................................... 57
4.3. GPIO Pinout Overview ................................................................................................................... 65
4.4. Opamp Pinout Overview ................................................................................................................. 65
4.5. LQFP100 Package ........................................................................................................................ 66
5. PCB Layout and Soldering ........................................................................................................................ 68
5.1. Recommended PCB Layout ............................................................................................................ 68
5.2. Soldering Information ..................................................................................................................... 70
6. Chip Marking, Revision and Errata .............................................................................................................. 71
6.1. Chip Marking ................................................................................................................................ 71
6.2. Revision ...................................................................................................................................... 71
6.3. Errata ......................................................................................................................................... 71
7. Revision History ...................................................................................................................................... 72
7.1. Revision 1.30 ............................................................................................................................... 72
7.2. Revision 1.21 ............................................................................................................................... 72
7.3. Revision 1.20 ............................................................................................................................... 72
7.4. Revision 1.10 ............................................................................................................................... 73
7.5. Revision 1.00 ............................................................................................................................... 73
7.6. Revision 0.98 ............................................................................................................................... 73
7.7. Revision 0.96 ............................................................................................................................... 73
7.8. Revision 0.95 ............................................................................................................................... 73
7.9. Revision 0.91 ............................................................................................................................... 74
7.10. Revision 0.90 .............................................................................................................................. 74
A. Disclaimer and Trademarks ....................................................................................................................... 75
A.1. Disclaimer ................................................................................................................................... 75
A.2. Trademark Information ................................................................................................................... 75
B. Contact Information ................................................................................................................................. 76
B.1. ................................................................................................................................................. 76
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32GG880 Memory Map with largest RAM and Flash sizes ........................................................................ 9
3.1. Typical Low-Level Output Current, 2V Supply Voltage .................................................................................. 16
3.2. Typical High-Level Output Current, 2V Supply Voltage ................................................................................. 17
3.3. Typical Low-Level Output Current, 3V Supply Voltage .................................................................................. 18
3.4. Typical High-Level Output Current, 3V Supply Voltage ................................................................................. 19
3.5. Typical Low-Level Output Current, 3.8V Supply Voltage ............................................................................... 20
3.6. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................... 21
3.7. Calibrated LFRCO Frequency vs Temperature and Supply Voltage ................................................................ 24
3.8. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature .............................................. 25
3.9. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature .............................................. 25
3.10. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 25
3.11. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 26
3.12. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 26
3.13. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 26
3.14. Integral Non-Linearity (INL) ................................................................................................................... 32
3.15. Differential Non-Linearity (DNL) .............................................................................................................. 32
3.16. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 33
3.17. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 34
3.18. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 35
3.19. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 36
3.20. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 36
3.21. ADC Temperature sensor readout ......................................................................................................... 37
3.22. OPAMP Common Mode Rejection Ratio ................................................................................................. 40
3.23. OPAMP Positive Power Supply Rejection Ratio ........................................................................................ 40
3.24. OPAMP Negative Power Supply Rejection Ratio ...................................................................................... 41
3.25. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V ..................................................................... 41
3.26. OPAMP Voltage Noise Spectral Density (Non-Unity Gain) .......................................................................... 41
3.27. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 43
3.28. EBI Write Enable Timing ....................................................................................................................... 44
3.29. EBI Address Latch Enable Related Output Timing ..................................................................................... 45
3.30. EBI Read Enable Related Output Timing ................................................................................................. 46
3.31. EBI Read Enable Related Timing Requirements ........................................................................................ 47
3.32. EBI Ready/Wait Related Timing Requirements .......................................................................................... 47
3.33. SPI Master Timing ............................................................................................................................... 50
3.34. SPI Slave Timing ................................................................................................................................ 51
4.1. EFM32GG880 Pinout (top view, not to scale) ............................................................................................. 53
4.2. Opamp Pinout ...................................................................................................................................... 65
4.3. LQFP100 ............................................................................................................................................. 66
5.1. LQFP100 PCB Land Pattern ................................................................................................................... 68
5.2. LQFP100 PCB Solder Mask .................................................................................................................... 69
5.3. LQFP100 PCB Stencil Design ................................................................................................................. 70
6.1. Example Chip Marking (top view) ............................................................................................................. 71
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 7
3.1. Absolute Maximum Ratings ..................................................................................................................... 10
3.2. General Operating Conditions .................................................................................................................. 10
3.3. Environmental ....................................................................................................................................... 11
3.4. Current Consumption ............................................................................................................................. 12
3.5. Energy Modes Transitions ...................................................................................................................... 13
3.6. Power Management ............................................................................................................................... 13
3.7. Flash .................................................................................................................................................. 14
3.8. GPIO .................................................................................................................................................. 14
3.9. LFXO .................................................................................................................................................. 22
3.10. HFXO ................................................................................................................................................ 23
3.11. LFRCO .............................................................................................................................................. 23
3.12. HFRCO ............................................................................................................................................. 24
3.13. AUXHFRCO ....................................................................................................................................... 27
3.14. ULFRCO ............................................................................................................................................ 27
3.15. ADC .................................................................................................................................................. 27
3.16. DAC .................................................................................................................................................. 37
3.17. OPAMP ............................................................................................................................................. 38
3.18. ACMP ............................................................................................................................................... 42
3.19. VCMP ............................................................................................................................................... 44
3.20. EBI Write Enable Timing ....................................................................................................................... 45
3.21. EBI Address Latch Enable Related Output Timing ..................................................................................... 45
3.22. EBI Read Enable Related Output Timing ................................................................................................. 46
3.23. EBI Read Enable Related Timing Requirements ........................................................................................ 47
3.24. EBI Ready/Wait Related Timing Requirements .......................................................................................... 47
3.25. LCD .................................................................................................................................................. 48
3.26. I2C Standard-mode (Sm) ...................................................................................................................... 49
3.27. I2C Fast-mode (Fm) ............................................................................................................................ 49
3.28. I2C Fast-mode Plus (Fm+) .................................................................................................................... 50
3.29. SPI Master Timing ............................................................................................................................... 50
3.30. SPI Slave Timing ................................................................................................................................ 51
3.31. Digital Peripherals ............................................................................................................................... 51
4.1. Device Pinout ....................................................................................................................................... 53
4.2. Alternate functionality overview ................................................................................................................ 57
4.3. GPIO Pinout ........................................................................................................................................ 65
4.4. LQFP100 (Dimensions in mm) ................................................................................................................. 67
5.1. QFP100 PCB Land Pattern Dimensions (Dimensions in mm) ......................................................................... 68
5.2. QFP100 PCB Solder Mask Dimensions (Dimensions in mm) ......................................................................... 69
5.3. QFP100 PCB Stencil Design Dimensions (Dimensions in mm) ....................................................................... 70
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 42
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 44
3.3. Total LCD Current Based on Operational Mode and Internal Boost ................................................................. 48
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