PD - 95386A DIGITAL AUDIO MOSFET IRLR9343PbF IRLU9343PbF IRLU9343-701PbF Features Advanced Process Technology l Key Parameters Optimized for Class-D Audio Amplifier Applications l Low RDSON for Improved Efficiency l Low Qg and Qsw for Better THD and Improved Efficiency l Low Qrr for Better THD and Lower EMI l 175°C Operating Junction Temperature for Ruggedness l Repetitive Avalanche Capability for Robustness and Reliability l Multiple Package Options l Lead-Free l Key Parameters VDS RDS(ON) typ. @ VGS = -10V RDS(ON) typ. @ VGS = -4.5V Qg typ. TJ max -55 93 150 31 175 V m: m: nC °C D D-Pak IRLR9343 I-Pak IRLU9343 I-Pak Leadform 701 IRLU9343-701 Refer to page 10 for package outline G S Description This Digital Audio HEXFET® is specifically designed for Class-D audio amplifier applications. This MosFET utilizes the latest processing techniques to achieve low on-resistance per silicon area. Furthermore, Gate charge, body-diode reverse recovery and internal Gate resistance are optimized to improve key Class-D audio amplifier performance factors such as efficiency, THD and EMI. Additional features of this MosFET are 175°C operating junction temperature and repetitive avalanche capability. These features combine to make this MosFET a highly efficient, robust and reliable device for Class-D audio amplifier applications. Absolute Maximum Ratings Parameter VDS VGS ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C PD @TC = 100°C TJ TSTG Max. Units Drain-to-Source Voltage -55 V Gate-to-Source Voltage Continuous Drain Current, VGS @ -10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current ±20 -20 A Power Dissipation Power Dissipation 79 39 W 0.53 -40 to + 175 W/°C °C ––– N -14 -60 c Linear Derating Factor Operating Junction and Storage Temperature Range Clamping Pressure h Thermal Resistance RθJC RθJA RθJA g Parameter Junction-to-Case Junction-to-Ambient (PCB Mounted) Junction-to-Ambient (free air) g gj Typ. Max. Units ––– ––– 1.9 50 °C/W ––– 110 Notes through are on page 10 www.irf.com 1 12/07/04 IRLR/U9343PbF & IRLU9343-701PbF Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Min. Typ. Max. Units BVDSS ∆ΒVDSS/∆TJ RDS(on) Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Parameter -55 ––– ––– -52 ––– ––– Static Drain-to-Source On-Resistance ––– ––– 93 150 105 170 V VGS = 0V, ID = -250µA mV/°C Reference to 25°C, ID = -1mA mΩ VGS = -10V, ID = -3.4A VGS = -4.5V, ID = -2.7A VGS(th) Gate Threshold Voltage Gate Threshold Voltage Coefficient -1.0 ––– ––– -3.7 ––– ––– VDS = VGS, ID = -250µA V mV/°C Drain-to-Source Leakage Current ––– ––– ––– ––– -2.0 -25 µA VDS = -55V, VGS = 0V VDS = -55V, VGS = 0V, TJ = 125°C IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage ––– ––– ––– ––– -100 100 nA VGS = -20V VGS = 20V gfs Forward Transconductance Total Gate Charge 5.3 ––– ––– 31 ––– 47 S Gate-to-Source Charge Gate-to-Drain Charge ––– ––– 7.1 8.5 ––– ––– VDS = -25V, ID = -14A VDS = -44V VGS = -10V Gate Charge Overdrive Turn-On Delay Time ––– ––– 15 9.5 ––– ––– Rise Time Turn-Off Delay Time ––– ––– 24 21 ––– ––– Fall Time Input Capacitance ––– ––– 9.5 660 ––– ––– Output Capacitance Reverse Transfer Capacitance ––– ––– 160 72 ––– ––– LD Effective Output Capacitance Internal Drain Inductance ––– ––– 280 4.5 ––– ––– LS Internal Source Inductance ––– 7.5 ––– ∆VGS(th)/∆TJ IDSS Qg Qgs Qgd Qgodr td(on) tr td(off) tf Ciss Coss Crss Coss Conditions e e ID = -14A See Fig. 6 and 19 VDD = -28V, VGS = -10V ns e ID = -14A RG = 2.5Ω VGS = 0V pF VDS = -50V ƒ = 1.0MHz, See Fig.5 VGS = 0V, VDS = 0V to -44V Between lead, nH 6mm (0.25in.) from package and center of die contact f Avalanche Characteristics Parameter EAS IAR EAR Single Pulse Avalanche Energy i Avalanche Current Repetitive Avalanche Energy d Typ. Max. Units ––– 120 mJ See Fig. 14, 15, 17a, 17b i A mJ Diode Characteristics Parameter IS @ TC = 25°C Continuous Source Current ISM VSD trr Qrr 2 Min. Typ. Max. Units ––– ––– -20 (Body Diode) Pulsed Source Current ––– ––– -60 (Body Diode) Diode Forward Voltage Reverse Recovery Time ––– ––– ––– 57 -1.2 86 V ns Reverse Recovery Charge ––– 120 180 nC c Conditions MOSFET symbol A showing the integral reverse D G p-n junction diode. TJ = 25°C, IS = -14A, VGS = 0V TJ = 25°C, IF = -14A di/dt = 100A/µs e S e www.irf.com IRLR/U9343PbF & IRLU9343-701PbF 100 100 10 BOTTOM VGS -15V -12V -10V -8.0V -5.5V -4.5V -3.0V -2.5V TOP -I D, Drain-to-Source Current (A) -I D, Drain-to-Source Current (A) TOP 1 -2.5V ≤ 60µs PULSE WIDTH Tj = 25°C 10 BOTTOM 1 -2.5V ≤ 60µs PULSE WIDTH Tj = 175°C 0.1 0.1 0.1 1 10 0.1 100 Fig 1. Typical Output Characteristics 10 100 Fig 2. Typical Output Characteristics 100.0 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) -I D, Drain-to-Source Current (Α) 1 -VDS, Drain-to-Source Voltage (V) -VDS, Drain-to-Source Voltage (V) T J = 25°C TJ = 175°C 10.0 1.0 VDS = -25V ≤ 60µs PULSE WIDTH 0.1 0.0 5.0 10.0 15.0 ID = -14A VGS = -10V 1.5 1.0 0.5 -60 -40 -20 -V GS, Gate-to-Source Voltage (V) 10000 20 40 60 80 100 120 140 160 180 Fig 4. Normalized On-Resistance vs. Temperature 20 -V GS, Gate-to-Source Voltage (V) VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 1000 Ciss Coss Crss 100 0 T J , Junction Temperature (°C) Fig 3. Typical Transfer Characteristics C, Capacitance (pF) VGS -15V -12V -10V -8.0V -5.5V -4.5V -3.0V -2.5V ID= -14A 16 VDS= -44V VDS= -28V VDS= -11V 12 8 4 FOR TEST CIRCUIT SEE FIGURE 19 0 10 1 10 100 -VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs.Drain-to-Source Voltage www.irf.com 0 10 20 30 40 50 QG Total Gate Charge (nC) Fig 6. Typical Gate Charge vs.Gate-to-Source Voltage 3 IRLR/U9343PbF & IRLU9343-701PbF 1000 -I D, Drain-to-Source Current (A) -I SD, Reverse Drain Current (A) 100.0 T J = 175°C 10.0 T J = 25°C 1.0 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 100µsec 10 Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 10msec 1 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1 2.0 10 100 1000 -VDS , Drain-toSource Voltage (V) -VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 2.5 -VGS(th) Gate threshold Voltage (V) 20 16 -ID , Drain Current (A) 1msec 12 8 4 2.0 ID = -250µA 1.5 0 1.0 25 50 75 100 125 150 175 -75 -50 -25 T J , Junction Temperature (°C) 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 10. Threshold Voltage vs. Temperature Fig 9. Maximum Drain Current vs. Case Temperature Thermal Response ( Z thJC ) 10 1 D = 0.50 0.20 0.10 0.05 0.1 τJ 0.02 0.01 R1 R1 τJ τ1 R2 R2 τC τ2 τ1 τ2 τ Ri (°C/W) 1.162 0.7370 τi (sec) 0.000512 0.002157 Ci= τi/Ri Ci= i/Ri 0.01 SINGLE PULSE ( THERMAL RESPONSE ) Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc 0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 4 www.irf.com 500 600 EAS, Single Pulse Avalanche Energy (mJ) RDS(on), Drain-to -Source On Resistance ( mΩ) IRLR/U9343PbF & IRLU9343-701PbF ID = -14A 500 400 300 200 T J = 125°C 100 T J = 25°C 0 ID -4.0A -5.5A BOTTOM -14A TOP 400 300 200 100 0 4.0 6.0 8.0 10.0 25 -VGS, Gate-to-Source Voltage (V) 50 75 100 125 150 175 Starting T J, Junction Temperature (°C) Fig 12. On-Resistance Vs. Gate Voltage Fig 13. Maximum Avalanche Energy Vs. Drain Current 1000 Allowed avalanche Current vs avalanche pulsewidth, tav assuming ∆ Tj = 25°C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax -Avalanche Current (A) Duty Cycle = Single Pulse 100 0.01 10 0.05 0.10 1 0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 tav (sec) Fig 14. Typical Avalanche Current Vs.Pulsewidth 140 TOP Single Pulse BOTTOM 1% Duty Cycle ID = -14A EAR , Avalanche Energy (mJ) 120 100 80 60 40 20 0 25 50 75 100 125 150 175 Starting T J , Junction Temperature (°C) Fig 15. Maximum Avalanche Energy Vs. Temperature www.irf.com Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 17a, 17b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25°C in Figure 14, 15). t av = Average time in avalanche. D = Duty cycle in avalanche = tav ·f ZthJC(D, tav) = Transient thermal resistance, see figure 11) PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC Iav = 2DT/ [1.3·BV·Zth] EAS (AR) = PD (ave)·tav 5 IRLR/U9343PbF & IRLU9343-701PbF D.U.T Driver Gate Drive - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop InductorInductor Curent Current ISD Ripple ≤ 5% * Reverse Polarity of D.U.T for P-Channel * VGS = 5V for Logic Level Devices Fig 16. Peak Diode Recovery dv/dt Test Circuit for P-Channel HEXFET® Power MOSFETs L VDS V DS D.U.T RG VDD A IAS -V -20V GS tp VGS DRIVER D.U.T. RG 0.01Ω RD + VDD -10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 15V Fig 17a. Unclamped Inductive Test Circuit Fig 18a. Switching Time Test Circuit I AS td(on) tr t d(off) tf VGS 10% 90% tp VDS V(BR)DSS Fig 17b. Unclamped Inductive Waveforms Fig 18b. Switching Time Waveforms Id Vds Vgs L DUT 0 1K VCC Vgs(th) Qgs1 Qgs2 Fig 19a. Gate Charge Test Circuit 6 Qgd Qgodr Fig 19b Gate Charge Waveform www.irf.com IRLR/U9343PbF & IRLU9343-701PbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: T HIS IS AN IRFR120 WIT H ASS EMBLY LOT CODE 1234 ASSEMBLED ON WW 16, 1999 IN T HE ASSEMBLY LINE "A" PART NUMBER INT ERNAT IONAL RECT IFIER LOGO Note: "P" in as s embly line position indicates "Lead-Free" IRFU120 12 916A 34 ASSEMBLY LOT CODE DAT E CODE YEAR 9 = 1999 WEEK 16 LINE A OR PART NUMBER INT ERNAT IONAL RECT IFIER LOGO IRFU120 12 ASSEMBLY LOT CODE www.irf.com 34 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 16 A = ASSEMBLY SIT E CODE 7 IRLR/U9343PbF & IRLU9343-701PbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRFU120 WIT H AS SEMBLY LOT CODE 5678 ASS EMBLED ON WW 19, 1999 IN THE AS SEMBLY LINE "A" INTERNAT IONAL RECT IFIER LOGO PART NUMBER IRFU120 919A 56 78 ASS EMBLY LOT CODE Note: "P" in as sembly line pos ition indicates "Lead-F ree" DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRF U120 56 AS S EMBLY LOT CODE 8 78 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = AS S EMBLY S IT E CODE www.irf.com IRLR/U9343PbF & IRLU9343-701PbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.3 ( .641 ) 15.7 ( .619 ) 12.1 ( .476 ) 11.9 ( .469 ) FEED DIRECTION TRL 16.3 ( .641 ) 15.7 ( .619 ) 8.1 ( .318 ) 7.9 ( .312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481. www.irf.com 9 IRLR/U9343PbF & IRLU9343-701PbF I-Pak Leadform Option 701 Package Outline Dimensions are shown in millimeters (inches) Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 1.24mH, RG = 25Ω, IAS = -14A. Pulse width ≤ 400µs; duty cycle ≤ 2%. This only applies for I-Pak, LS of D-Pak is measured between lead and center of die contact Rθ is measured at TJ of approximately 90°C. Contact factory for mounting information Limited by Tjmax. See Figs. 14, 15, 17a, 17b for repetitive avalanche information When D-Pak mounted on 1" square PCB (FR-4 or G-10 Material) . For recommended footprint and soldering techniques refer to application note #AN-994 Refer to D-Pak package for Part Marking, Tape and Reel information. Data and specifications subject to change without notice. This product has been designed for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.12/04 10 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/