IDT ICS85320AMIT Lvcmos/lvttl-to-differential 3.3v, 2.5v lvpecl translator Datasheet

ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL
3.3V, 2.5V LVPECL TRANSLATOR
GENERAL DESCRIPTION
FEATURES
The ICS85320I is a LVCMOS / LVTTL-to-DifferenICS
tial 3.3V, 2.5V LVPECL translator and a member
HiPerClockS™
of the HiPerClocks™ family of High Performance
Clocks Solutions from IDT. The ICS85320I has a
single ended clock input. The single ended clock
input accepts LVCMOS or LVTTL input levels and translates
them to 3.3V or 2.5V LVPECL levels. The small outline 8-pin
SOIC package makes this device ideal for applications where
space, high performance and low power are important.
• One differential 2.5V/3.3V LVPECL output
• LVCMOS/LVTTL CLK input
• CLK accepts the following input levels: LVCMOS or LVTTL
• Maximum output frequency: 267MHz
• Part-to-part skew: 275ps (maximum)
• Additive phase jitter, RMS: 0.05ps (typical)
• 3.3V operating supply voltage
(operating range 3.135V to 3.465V)
• 2.5V operating supply voltage
(operating range 2.375V to 2.625V)
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
CLK
PIN ASSIGNMENT
Q
nQ
nc
Q
nQ
nc
1
2
3
4
8
7
6
5
VCC
CLK
nc
VEE
ICS85320I
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 4, 6
nc
Unused
Type
No connect.
Description
2,3
Q, nQ
Output
Differential output pair. LVPECL interface levels.
5
V EE
Power
Negative supply pin.
7
CLK
Input
8
VCC
Power
Pullup
LVCMOS / LVTTL clock input.
Positive supply pin.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
Test Conditions
Minimum
2
Typical
Maximum
Units
ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
Inputs, VI
-0.5V to VCC + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
VCC
Positive Supply Voltage
IEE
Power Supply Current
Minimum
Typical
Maximum
Units
3.135
2.375
3.3
3.465
V
2.5
2.625
V
25
mA
Maximum
Units
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VIH
Input High Voltage
CLK
2
VCC + 0.3
V
VIL
Input Low Voltage
CLK
-0.3
1.3
V
IIH
Input High Current
CLK
VCC = VIN = 3.465V
5
µA
IIL
Input Low Current
CLK
VCC = VIN = 3.465V
-150
µA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Maximum
Units
VIH
Input High Voltage
CLK
Test Conditions
Minimum
1.6
Typical
VCC + 0.3
V
VIL
Input Low Voltage
CLK
-0.3
0.9
V
IIH
Input High Current
CLK
VCC = VIN = 2.625V
5
µA
IIL
Input Low Current
CLK
VCC = VIN = 2.625V
-150
µA
TABLE 3D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 0.9
V
VOL
Output Low Voltage; NOTE 1
VCC - 2.0
VCC - 1.7
V
VSWING
Peak-to-Peak Output Voltage Swing
0.6
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
TABLE 4A. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tPD
t sk(pp)
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Par t-to-Par t Skew; NOTE 2, 3
tR, tF
Output Rise/Fall Time
t jit
Test Conditions
ƒ ≤ 267MHz
Integration Range:
12KHz - 20MHz
20% to 80%
Minimum
Typical
0.8
Maximum
Units
267
MHz
1.4
ns
0.05
200
ps
275
ps
70 0
ps
o dc
Output Duty Cycle
45
55
%
NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VCC = 2.5V±5%, TA = -40°C TO 85°C
Symbol
Parameter
fMAX
Output Frequency
tPD
t sk(pp)
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Par t-to-Par t Skew; NOTE 2, 3
tR, tF
Output Rise/Fall Time
t jit
Test Conditions
Minimum
ƒ ≤ 267MHz
Integration Range:
12KHz - 20MHz
0.8
20% to 80%
200
Typical
Maximum
Units
215
MHz
1. 7
ns
0.05
ps
375
ps
700
ps
o dc
Output Duty Cycle
45
55
%
NOTE 1: Measured from VCC/2 point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
0
-10
Input/Output Additive Phase Jitter
-20
@ 156.25MHz (12KHz to 20MHz)
= 0.05ps typical
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
PARAMETER MEASUREMENT INFORMATION
2V
2V
VCC
Qx
SCOPE
VCC
LVPECL
Qx
SCOPE
LVPECL
nQx
nQx
VEE
VEE
-1.3V ± 0.165V
-0.5V ± 0.125V
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
Part 1
nQx
80%
80%
Qx
VSW I N G
Part 2
nQy
Clock
Outputs
20%
20%
tF
tR
Qy
t sk(o)
OUTPUT RISE/FALL TIME
PART-TO-PART SKEW
nCLK
nQ
CLK
Q
t PW
t
nQ
Q
odc =
tPD
PERIOD
t PW
x 100%
t PERIOD
PROPAGATION DELAY
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal distortion. Figures 1A and 1B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
125Ω
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 1A. LVPECL OUTPUT TERMINATION
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
84Ω
FIGURE 1B. LVPECL OUTPUT TERMINATION
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 2A and Figure 2B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground
level. The R3 in Figure 2B can be eliminated and the termination
is shown in Figure 2C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 2B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 2C. 2.5V LVPECL TERMINATION EXAMPLE
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
APPLICATION SCHEMATIC EXAMPLE
Figure 3 shows an example of ICS85320I application schematic.
In this example, the device is operated at VCC=3.3V. The decoupling
capacitor should be located as close as possible to the power
pin. For LVPECL output termination, only two terminations
examples are shown in this schematic. For more termination
approaches, please refer to the LVPECL Termination Application
Note.
Zo = 50 Ohm
Zo = 50 Ohm
R2
50
VCC = 3.3V
R1
50
U1
1
2
3
4
nc
Q
nQ
nc
Vcc
Clk
nc
Vee
8
7
6
5
R3
50
Clk_in
85320
VCC
(U1-8)
VCC = 3.3V
C1
10uf
C2
0.1uF
R4
133
R6
133
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R5
82.5
R7
82.5
Optional Termination
FIGURE 3. ICS85320I APPLICATION SCHEMATIC EXAMPLE
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85320I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85320I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 86.6mW + 30.2mW = 116.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.117W * 103.3°C/W = 97.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θ JA FOR 8-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT
AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 1.0V
(VCC_MAX - VOH_MAX) = 1.0V
•
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX - VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/R ] * (VCC_MAX - VOH_MAX) =
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(VOL_MAX – (VCC_MAX - 2V))/R ] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/R ] * (VCC_MAX - VOL_MAX) =
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
153.3°C/W
112.7°C/W
128.5°C/W
103.3°C/W
115.5°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85320I is: 269
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 7. PACKAGE DIMENSIONS
SYMBOL
Millimeters
MINIMUN
N
A
MAXIMUM
8
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
1.27 BASIC
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
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LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS85320AMI
85320AMI
8 lead SOIC
tube
-40°C to 85°C
ICS85320AMIT
85320AMI
8 lead SOIC
2500 tape & reel
-40°C to 85°C
ICS85320AMILF
85320AIL
8 lead "Lead-Free" SOIC
tube
-40°C to 85°C
ICS85320AMILFT
85320AIL
8 lead "Lead-Free" SOIC
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
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ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
REVISION HISTORY SHEET
Rev
A
Table
Page
1
14
Description of Change
Features Section - added lead-free bullet.
Ordering Information Table - corrected standard marking and, added lead-free
par t number, marking, and note.
Updated datasheet layout.
IDT ™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR
15
Date
11/13/06
ICS8532AMI REV A NOVEMBER 13, 2006
ICS85320I
LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR
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Integrated Device Technology, Inc.
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Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
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321 Kingston Road
Leatherhead, Surrey
KT22 7TU
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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