Revised August 2000 MM74HC240 Inverting Octal 3-STATE Buffer General Description Features The MM74HC240 3-STATE buffer utilizes advanced silicon-gate CMOS technology. It possesses high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the advantage of CMOS circuitry, i.e., high noise immunity and low power consumption. It has a fanout of 15 LS-TTL equivalent inputs. ■ Typical propagation delay: 12 ns ■ 3-STATE outputs for connection to system buses ■ Wide power supply range: 2–6V ■ Low quiescent supply current: 80 µA (74 Series) ■ Output current: 6 mA The MM74HC240 is an inverting buffer and has two active LOW enables (1G and 2G). Each enable independently controls 4 buffers. All inputs are protected from damage due to static discharge by diodes to VCC and ground. Ordering Code: Order Number MM74HC240WM MM74HC240SJ MM74HC240MTC MM74HC240N Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table 1G 1A 1Y 2G 2A 2Y L L H L L H L H L L H L H L Z H L Z H H Z H H Z H = HIGH Level L = LOW Level Z = HIGH Impedance Top View © 2000 Fairchild Semiconductor Corporation DS005020 www.fairchildsemi.com MM74HC240 Inverting Octal 3-STATE Buffer September 1983 MM74HC240 Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±35 mA DC VCC or GND Current, per pin (ICC) ±70 mA Storage Temperature Range (TSTG) Min Max Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V −40 +85 °C (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times −65°C to +150°C Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Symbol VIH VIL Parameter ns 500 ns VCC = 6.0V 400 ns Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C. (Note 4) Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V 2.0V 0.5 0.5 0.5 V 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Maximum LOW Level Input Voltage VOH 1000 Note 2: unless otherwise specified all voltages are referenced to ground. 260°C DC Electrical Characteristics (tr, tf) VCC = 2.0V VCC = 4.5V Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) Units Minimum HIGH Level VI N = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V |IOUT| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA 6.0V ±0.5 ±5 ±10 µA 6.0V 8.0 80 160 µA VIN = VIH or VIL IIN Maximum Input Current IOZ Maximum 3-STATE VIN = VIH or VIL Output Leakage VOUT = VCC or GND Current G = VIH, G = VIL ICC Maximum Quiescent VIN = VCC or GND Supply Current IOUT = 0 µA Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. 3 www.fairchildsemi.com MM74HC240 Absolute Maximum Ratings(Note 1) MM74HC240 AC Electrical Characteristics VCC = 5V, TA = 25°C, tr = tf = 6 ns Conditions Typ Guaranteed Limit Units tPHL, tPLH Symbol Maximum Propagation Delay CL = 45 pF 12 18 ns tPZH, tPZL Maximum Enable Delay RL = 1 kΩ to Active Output CL = 45 pF 14 28 ns Maximum Disable Delay RL = 1 kΩ from Active Output CL = 5 pF 13 25 ns tPHZ, tPLZ Parameter AC Electrical Characteristics VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified) Symbol Parameter tPHL, tPLH Maximum Propagation Delay tPZH, tPZL Maximum Output Enable TIme tPHZ, tPLZ Maximum Output Disable Time Conditions Capacitance (Note 5) TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units 2.0V 55 100 126 149 ns CL = 150 pF 2.0V 80 150 190 224 ns CL = 50 pF 4.5V 12 20 25 30 ns CL = 150 pF 4.5V 22 30 38 45 ns CL = 50 pF 6.0V 11 17 21 25 ns CL = 150 pF 6.0V 28 26 32 38 ns RL = 1 kΩ CL = 50 pF 2.0V 75 150 189 224 ns CL = 150 pF 2.0V 100 200 252 298 ns CL = 50 pF 4.5V 15 30 38 45 ns CL = 150 pF 4.5V 20 40 50 60 ns CL = 50 pF 6.0V 13 26 32 38 ns CL = 150 pF 6.0V 17 34 43 51 ns RL = 1 kΩ 2.0V 75 150 189 224 ns CL = 50 pF 4.5V 15 30 38 45 ns 6.0V 13 Rise and Fall Time Power Dissipation Typ CL = 50 pF tTLH, tTHL Maximum Output CPD TA = 25°C VCC 26 32 38 ns 2.0V 60 75 90 ns 4.5V 12 15 18 ns 6.0V 10 13 15 ns (per buffer) G = VIH 12 G = VIL 50 pF pF CIN Maximum Input Capacitance 5 10 10 10 pF COUT Maximum Output Capacitance 10 20 20 20 pF Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic current consumption, IS = CPD VCC f + I CC. www.fairchildsemi.com 4 MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC240 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC240 Inverting Octal 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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