Holtek HT82K68E Multimedia keyboard encoder 8-bit otp mcu Datasheet

HT82K68E
Multimedia Keyboard Encoder 8-Bit OTP MCU
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Operating voltage: 2.2V~5.5V
· 2.4V LVR by option (default disable)
· 32/34 bidirectional I/O lines
· HALT function and wake-up feature reduce power
consumption
· One 8-bit programmable timer counter with overflow
· Six-level subroutine nesting
interrupts
· Crystal or RC oscillator
· Bit manipulation instructions
· Watchdog Timer
· 16-bit table read instructions
· 3K´16 program EPROM
· 63 powerful instructions
· 160´8 data RAM
· All instructions in 1 or 2 machine cycles
· One external interrupt pin (shared with PC2)
· 20/28-pin SOP, 48-pin SSOP package
General Description
Windows 95, Windows 98 or Windows 2000
environment. A HALT feature is included to reduce
power consumption.
The HT82K68E is an 8-bit high performance peripheral
interface IC, designed for multiple I/O products and multimedia applications. It supports interface to a low speed
PC with multimedia keyboard or wireless keyboard in
Rev. 2.00
1
July 10, 2007
HT82K68E
Block Diagram
S T A C K 0
S T A C K 1
S T A C K 2
S T A C K 3
P ro g ra m
R O M
P C 2
In te rru p t
C ir c u it
S T A C K 4
S T A C K 5
P ro g ra m
C o u n te r
IN T C
S Y S C L K /4
T M R
T M R C
In s tr u c tio n
R e g is te r
M P 0
M P 1
M
8 b it
U
S Y S C L K /4
X
W D T S
D A T A
M e m o ry
W D T P r e s c a le r
W D T
M
U
X
R C
In s tr u c tio n
D e c o d e r
P E C
M U X
A L U
T im in g
G e n e ra to r
P O R T E
P E
P D C
S T A T U S
P O R T D
P D
S h ifte r
P C C
P O R T C
P C
O S C 2
O S
R E
V D
V S
S
C 1
S E T
D
A C C
P B C
P A C
P A
Rev. 2.00
P O R T B
P B
2
P O R T A
O S C
P E 0 ~ P E 4
P D 0 ~ P D 7
P C 0 ~ P C 7
P B 0 ~ P B 7
P A 0 ~ P A 7
July 10, 2007
HT82K68E
Pin Assignment
P B 5
1
4 8
P B 6
P B 4
2
4 7
P B 7
P A 3
3
4 6
P A 4
P A 2
4
4 5
P A 5
P A 1
5
4 4
P A 6
P A 0
6
4 3
P A 7
P B 3
7
4 2
N C
P B 2
8
4 1
N C
P B 1
9
4 0
N C
P B 0
1 0
3 9
N C
P B 5
1
2 8
P B 6
N C
1 1
3 8
O S C 2
P B 4
2
2 7
P B 7
N C
1 2
3 7
O S C 1
P A 3
3
2 6
P A 4
P D 7
1 3
3 6
V D D
P A 2
4
2 5
P A 5
P D 6
1 4
3 5
R E S E T
P A 3
1
2 0
P A 4
P A 1
5
2 4
P A 6
P D 5
1 5
3 4
P E 4 (L E D )
P A 2
2
1 9
P A 5
P A 0
6
2 3
P A 7
P D 4
1 6
3 3
P D 3
P A 1
3
1 8
P A 6
P B 3
7
2 2
O S C 2
V S S
1 7
3 2
P D 2
P A 0
4
1 7
P A 7
P B 2
8
2 1
O S C 1
P E 2 (L E D )
1 8
3 1
P D 1
P B 1
5
1 6
O S C 2
P B 1
9
2 0
V D D
P E 3 (L E D )
1 9
3 0
P D 0
P B 0
6
1 5
O S C 1
P B 0
1 0
1 9
R E S E T
P C 0
2 0
2 9
P C 7
V S S
7
1 4
V D D
V S S
1 1
1 8
P C 7
P C 1
2 1
2 8
P C 6
P E 2
8
1 3
R E S E T
P C 1
1 2
1 7
P C 6
P C 2
2 2
2 7
P C 5
P C 0
9
1 2
P C 3
P C 2
1 3
1 6
P C 5
P E 0
2 3
2 6
P C 4
P C 1
1 0
1 1
P C 2
P C 3
1 4
1 5
P C 4
P E 1
2 4
2 5
P C 3
H T 8 2 K 6 8 E
2 0 S O P -A
H T 8 2 K 6 8 E
2 8 S O P -A
H T 8 2 K 6 8 E
4 8 S S O P -A
Pin Description
Pin Name
I/O
Mask
Option
Description
PA0~PA7
I/O
Wake-up
Pull-high
or None
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input
by mask option. Software* instructions determine the CMOS output or Schmitt Trigger input with or without 12K pull-high resistor.
PB0~PB7
I/O
Pull-high
or None
Bidirectional 8-bit input/output port. Software* instructions determine the output or
Schmitt Trigger input with or without pull-high resistor.
PC0
I/O
Wake-up
Pull-high
or None
This pin is an I/O port. NMOS open drain output with pull-high resistor and can be
used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up input by mask option.
PC1
I/O
Wake-up
Pull-high
or None
This pin is an I/O port. NMOS open drain output with pull-high resistor and can be
used as DATA or CLOCK line of PS2. This pin can be configured as a wake-up input by mask option.
PC2~PC3
I/O
Wake-up
Pull-high
or None
Bidirectional 2-bit input/output port. Each bit can be configured as a wake-up input
by mask option. Software* instructions determine the CMOS output or Schmitt
Trigger input with or without pull-high resistor.
PC2 also as external interrupt input pin. PE0 determine whether rising edge or falling edge of PC2 to trigger the INT circuit.
PC4~PC7
I/O
Pull-high
or None
Bidirectional 4-bit input/output port. Software* instructions determine the CMOS
output or Schmitt Trigger input with or without pull-high resistor.
PD0~PD7
I/O
Pull-high
or None
Bidirectional 8-bit input/output port. Software* instructions determine the CMOS
output or Schmitt Trigger input with or without pull-high resistor.
Rev. 2.00
3
July 10, 2007
HT82K68E
I/O
Mask
Option
Description
PE0~PE1
I/O
Pull-high
or None
Bidirectional input/output port. Software* instruction determine the CMOS output
or Schmitt Trigger input with or without pull-high resistor.
If PE0 output 1, rising edge of PC2 trigger INT circuit.
PE0 output 0, falling edge of PC2 trigger INT circuit.
PE2
O
This pin is a CMOS output structure. The pad can function as LED (SCR) drivers
for the keyboard. IOL=18mA at VOL=3.4V
PE3
O
This pin is a CMOS output structure. The pad can function as LED (NUM) drivers
for the keyboard. IOL=18mA at VOL=3.4V
PE4
O
This pin is a CMOS output structure. The pad can function as LED (CAP) drivers for
the keyboard. IOL=18mA at VOL=3.4V
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
RESET
I
¾
Chip reset input. Active low. Built-in power-on reset circuit to reset the entire chip.
Chip can also be externally reset via RESET pin
OSC1
OSC2
I
O
Pin Name
Note:
OSC1, OSC2 are connected to an RC network or a crystal for the internal system
Crystal or RC clock. In the case of RC operation, OSC2 is the output terminal for the 1/4 system
clock; A 110kW resistor is connected to OSC1 to generate a 2 MHZ frequency.
*: Software means the HT-IDE (Holtek Integrated Development Environment) can be configured by mask option.
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+6.0V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
Operating Temperature ..........................-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
VDD
Operating Voltage
IDD1
Operating Current (Crystal OSC)
Ta=25°C
Test Conditions
VDD
Conditions
¾
¾
3V
No load, fSYS= 6MHz
5V
IDD2
3V
Operating Current (RC OSC)
No load, fSYS= 6MHz
5V
ISTB1
3V
Standby Current (WDT enabled)
No load, system HALT
5V
ISTB2
3V
Standby Current (WDT Disabled)
No load, system HALT
5V
VIL1
VIH1
Rev. 2.00
Input Low Voltage for I/O Ports
(Schmitt)
Input High Voltage for I/O Ports
(Schmitt)
Min.
Typ.
Max.
Unit
2.2
¾
5.5
V
¾
0.7
1.5
mA
¾
2
5
mA
¾
0.5
1.5
mA
¾
2
5
mA
¾
¾
8
mA
¾
¾
15
mA
¾
¾
3
mA
¾
¾
6
mA
3V
¾
0
¾
0.9
V
5V
¾
0
¾
1.5
V
3V
¾
2.1
¾
3
V
5V
¾
3.5
¾
5
V
4
July 10, 2007
HT82K68E
Symbol
VIL2
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
¾
0
¾
0.7
V
5V
¾
0
¾
1.3
V
3V
¾
2.4
¾
3
V
5V
¾
4.0
¾
5
V
¾
¾
2.4
¾
V
VDD
Conditions
3V
Input Low Voltage (RESET)
VIH2
Input High Voltage (RESET)
VLVR
Low Voltage Reset
¾
IOL
I/O Port Sink Current of PA, PB, PC,
PD, PE0~1
5V
VOL= 0.5V
16
25
¾
mA
IOH1
I/O Port Source Current of PA, PB,
PC2~7 PD, PE0~1
5V
VOH= 4.5V
-8
-16
¾
mA
IOH2
I/O Port Source Current of PE2~4
5V
VOH= 4.5V
-2.5
-4
¾
mA
ILED
LED Sink Current (SCR, NUM, CAP)
5V
VOL=3.4V
10
18
24
mA
tPOR
Power-on Reset Time
5V
R=100kW, C=0.1mF
ms
Internal Pull-high Resistance of PA,
PB, PC, PD, PE Port
3V
5V
RPH
50
100
150
¾
30
60
90
kW
¾
15
30
45
kW
Internal Pull-high Resistance of DATA,
CLK
3V
¾
4
9
15
kW
5V
¾
2
4.7
8
kW
Df/f
Frequency Variation
5V
Crystal
¾
¾
±1
%
Df/f1
Frequency Variation
5V
RC
¾
¾
±20
%
RPH1
A.C. Characteristics
Symbol
fSYS1
Parameter
Ta=25°C
Test Conditions
Max.
Unit
¾
¾
6
¾
MHz
¾
¾
6
¾
MHz
3V
5V
3V
OSC resistor 40kW
4.8
6
7.2
MHz
5V
OSC resistor 40kW
4.8
6
7.2
MHz
System Clock (RC OSC)
tWDTOSC
3V
¾
45
90
180
ms
5V
¾
35
78
130
ms
Watchdog Oscillator Period
3V
tWDT1
Watchdog Time-out Period (RC)
tWDT2
Watchdog Time-out Period
(System Clock)
¾
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
Note:
Typ.
Conditions
System Clock (Crystal OSC)
fSYS2
Min.
VDD
12
23
45
ms
9
19
35
ms
Without WDT prescaler
¾
1024
¾
tSYS
¾
1
¾
¾
ms
¾
1024
¾
tSYS
1
¾
¾
ms
Without WDT prescaler
5V
Power-up or
wake-up from HALT
¾
tSYS= 1/fSYS
Rev. 2.00
5
July 10, 2007
HT82K68E
Functional Description
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
Execution Flow
The HT82K68E system clock is derived from either a
crystal or an RC oscillator. The system clock is internally
divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are
required to complete the instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be within
256 locations.
Program Counter - PC
The 12-bit program counter (PC) controls the sequence
in which the instructions stored in the program ROM are
executed and its contents specify a maximum of 4096
addresses.
Once a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized with
3072´16 bits, addressed by the program counter and table pointer.
T 1
S y s te m
T 2
T 3
Program Memory - ROM
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
O S C 2 ( R C o n ly )
( N M O S o p e n d r a in o u tp u t)
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
External interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer counter overflow
0
0
0
0
0
0
0
0
1
0
0
0
@3
@2
@1
@0
Skip
Loading PCL
Program Counter+2
*11
*10
*9
*8
@7
@6
@5
@4
Jump, call branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Note: *11~*0: Program counter bits
#11~#0: Instruction code bits
Rev. 2.00
S11~S0: Stack register bits
@7~@0: PCL bits
6
July 10, 2007
HT82K68E
0 0 0 H
0 0 8 H
The TBLH is read only and cannot be restored. If the
main routine and the ISR (Interrupt Service Routine)
both employ the table read instruction, the contents of
the TBLH in the main routine are likely to be changed
by the table read instruction used in the ISR. Errors
can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the location must be placed in TBLP. All table related instructions need 2 cycles to complete the operation. These
areas may function as normal program memory depending upon the requirements.
D e v ic e in itia liz a tio n p r o g r a m
T im e r /e v e n t c o u n te r in te r r u p t s u b r o u tin e
n 0 0 H
P ro g ra m
R O M
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
B F F H
1 6 b its
N o te : n ra n g e s fro m
0 to B
Program Memory
Certain locations in the program memory are reserved
for special usage:
Stack Register - STACK
· Location 000
This area is reserved for the initialization program. After chip reset, the program always begins execution at
location 000H.
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into six levels and is neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledgement, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
· Location 004H
Location 004H is reserved for external interrupt service program. If the PC2 (external input pin) is activated, the interrupt is enabled, and the stack is not full,
the program begins execution at location 004H. The
pin PE0 determine whether the rising or falling edge of
the PC2 to activate external interrupt service program.
· Location 008H
This area is reserved for the timer counter interrupt
service program. If timer interrupt results from a timer
counter overflow, and if the interrupt is enabled and
the stack is not full, the program begins execution at
location 008H.
Data Memory - RAM
The data memory is designed with 184 ´ 8 bits. It is divided into two functional groups: special function registers and general purpose data memory (160´8). Most of
them are read/write, but some are read only.
· Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m]
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, the remaining 1 bit is read as 0. The
Table Higher-order byte register (TBLH) is read only.
Instruction(s)
The special function registers include the Indirect Addressing register 0 (00H), the Memory Pointer register 0
(MP0;01H), the Indirect Addressing register 1 (02H), the
Memory Pointer register 1 (MP1;03H), the Accumulator
(ACC;05H), the Program Counter Lower-byte register
(PCL;06H), the Table Pointer (TBLP;07H), the Table
Higher-order byte register (TBLH;08H), the Watchdog
Timer option Setting register (WDTS;09H), the Status register (STATUS;0AH), the Interrupt Control register
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
0
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table location bits
Rev. 2.00
7
July 10, 2007
HT82K68E
0 0 H
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
pointed to by MP0 (01H) and MP1 (03H) respectively.
Reading location 00H or 02H indirectly will return the result 00H. Writing indirectly results in no operation.
The function of data movement between two indirect addressing registers is not supported. The memory pointer
registers, MP0 and MP1, are 8-bit registers which can
be used to access the data memory by combining corresponding indirect addressing registers.
0 4 H
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
Accumulator
The accumulator is closely related to the ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data
operations. The data movement between two data
memory locations must pass through the accumulator.
0 C H
0 D H
T M R
0 E H
T M R C
0 F H
1 0 H
S p e c ia l P u r p o s e
D a ta M e m o ry
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P E
1 B H
1 C H
P E C
2 0 H
6 0 H
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operation.
The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
also changes the status register.
: U n u s e d .
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
R e a d a s ² 0 0 ²
Status Register - Status
The 8-bit status register (0AH) contains the zero flag (Z),
carry flag (C), auxiliary carry flag (AC), overflow flag
(OV), power down flag (PDF) and watch dog time-out
flag (TO). The status register not only records the status
information but also controls the operation sequence.
F F H
RAM Mapping
(INTC;0BH), the timer counter register (TMR;0DH), the
timer counter control register (TMRC;0EH), the I/O registers (PA;12H, PB;14H, PC;16H, PD;18H, PE;1AH) and
the I/O control registers (PAC;13H, PBC;15H, PCC;17H,
PDC;19H, PEC;1BH). The remaining space before the
60H is reserved for future expanded usage and reading
these locations will get the result 00H. The general purpose data memory, addressed from 60H to FFH, is used
for data and control information under instruction command.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flags. It should be noted
that operations related to the status register may give
different results from those intended. The TO and PDF
flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and
clearing the Watchdog Timer.
All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data
memory can be set and reset by the SET [m].i and CLR
[m].i instructions, respectively. They are also indirectly
accessible through Memory pointer registers
(MP0;01H, MP1;03H).
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of status
are important and if the subroutine can corrupt the status register, precaution must be taken to save it properly.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] and [02H] can access the data memory
Rev. 2.00
8
July 10, 2007
HT82K68E
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or if no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is
set by executing a HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set
by a WDT time-out.
6, 7
¾
Unused bit, read as ²0²
Status (0AH) Register
Interrupt
program which corrupt the desired control sequence, the
contents should be saved in advance.
The HT82K68E provides an internal timer counter interrupt and an external interrupt shared with PC2. The interrupt control register (INTC;0BH) contains the
interrupt control bits to set not only the enable/disable
status but also the interrupt request flags.
The internal timer counter interrupt is initialized by setting the timer counter interrupt request flag (T0F; bit 5 of
INTC), which is normally caused by a timer counter
overflow. When the interrupt is enabled, and the stack is
not full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further interrupts.
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be prevented from becoming full.
The external interrupt is shared with PC2. The external
interrupt is activated, the related interrupt request flag
(EIF; bit4 of INTC) is then set. When the interrupt is enabled, the stack is not full, and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will also be
cleared to disable other interrupts.
The external interrupt (PC2) can be triggered by a high
to low transition, or a low to high transition of the PC2,
which is dependent on the output level of the PE0.
When PE0 is output high, the external interrupt is triggered by a low to high transition of the PC2. When PE0
is output low, the external interrupt is triggered by a high
to low transition of PC2.
All these kinds of interrupt have the wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack followed by
a branch to a subroutine at the specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register and Status
register (STATUS) are altered by the interrupt service
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1= enabled; 0= disabled)
1
EEI
Control the external interrupt
2
ET0I
Controls the timer counter interrupt (1= enabled; 0= disabled)
3
¾
Unused bit, read as ²0²
4
EIF
External interrupt flag
5
T0F
Internal timer counter request flag (1= active; 0= inactive)
6, 7
¾
Unused bit, read as ²0²
INTC (0BH) Register
Rev. 2.00
9
July 10, 2007
HT82K68E
V
During the execution of an interrupt subroutine, other interrupt acknowledgements are held until the RETI instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, a RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
O S C 1
O S C 2
C r y s ta l O s c illa to r
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced
on the latter of the two T2 pulses, if the corresponding
interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit.
Interrupt Source
04H
Timer counter overflow
08H
O S C 2
R C
O s c illa to r
If an RC oscillator is used, an external resistor between
OSC1 and VDD is needed and the resistance must range
from 20kW to 47kW. The system clock, divided by 4, is
available on OSC2, which can be used to synchronize
external logic. The RC oscillator provides the most cost
effective solution. However, the frequency of the oscillation may vary with VDD, temperature and the chip itself
due to process variations. It is, therefore, not suitable for
timing sensitive operations where accurate oscillator frequency is desired.
The timer counter interrupt request flag (T0F), external
interrupt request (EIF) enable timer counter bit (ET0I),
enable external interrupt bit (EEI) and enable master
interrupt bit (EMI) constitute an interrupt control register (INTC) which is located at 0BH in the data memory.
EMI, ET0I and EEI, are used to control the enabling/disabling of interrupts. These bits prevent the
requested interrupt from being serviced. Once the interrupt request flags (T0F) are set, they will remain in
the INTC register until the interrupts are serviced or
cleared by a software instruction.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift needed for oscillator, no other external components
are needed. Instead of a crystal, the resonator can also
be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1
and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the
system enters the power down mode, the system clock is
stopped, but the WDT oscillator still works for a period of
approximately 78ms. The WDT oscillator can be disabled
by mask option to conserve power.
It is suggested that a program does not use the ²CALL
subroutine² within the interrupt subroutine. Because
interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications,
if only one stack is left and enabling the interrupt is not
well controlled, once the ²CALL subroutine² operates in
the interrupt subroutine it will damage the original control sequence.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask options. This
timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by
mask option. If the Watchdog Timer is disabled, all the executions related to the WDT results in no operation.
Oscillator Configuration
There are two oscillator circuits in HT82K68E. Both are
designed for system clocks; the RC oscillator and the
Crystal oscillator, which are determined by mask options. No matter what oscillator type is selected, the
signal provides the system clock. The HALT mode
stops the system oscillator and resists the external signal to conserve power.
S y s te m
fS Y S /4
(N M O S O p e n
D r a in O u tp u t)
System Oscillator
Vector
External interrupt 1
D D
O S C 1
Once the internal WDT oscillator (RC oscillator normally
with a period of 78ms) is selected, it is first divided by 256
c lo c k /4
W D T
O S C
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
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HT82K68E
· The contents of the on–chip RAM and registers re-
(8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be realized.
Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS)
can give different time-out periods. If WS2, WS1, WS0
are all equal to 1, the division ratio is up to 1:128, and the
maximum time-out period is 2.6 seconds.
main unchanged.
· WDT and WDT prescaler will be cleared and recount
again (if the WDT clock has come from the WDT oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, interrupt, and external falling edge signal
on port A and port C [0:3] or a WDT overflow. An external reset causes a device initialization and the WDT
overflow performs a ²warm reset². Examining the TO
and PDF flags, the reason for chip reset can be determined. The PDF flag is cleared when system power-up
or executing the CLR WDT instruction and is set when
the HALT instruction is executed. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and stack pointer, the others
keep their original status.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation
the WDT logic can be restarted by external logic. The
high nibble and bit 3 of the WDTS are reserved for user
defined flags, which can be used to indicate some specified status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
On the other hand, awakening from an external interrupt
(PC2), two sequences may happen. If the interrupt is
disabled or the interrupt is enabled but the stack is full,
the program will resume execution at the next instruction. But if the interrupt is enabled and the stack is not
full, the regular interrupt response takes place.
The port A or port C [0:3] wake-up can be considered as
a continuation of normal execution. Each bit in port A
can be independently selected to wake up the device by
mask option. Awakening from an I/O port stimulus, the
program will resume execution of the next instruction.
WDTS (09H) Register
Once a wake-up event occurs, and the system clock comes from a crystal, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, the
HT82K68E will insert a dummy period after the
wake-up. If the system clock comes from an RC oscillator, it continues operating immediately. If the wake-up
results in next instruction execution, this will execute immediately after the dummy period is completed.
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. An overflow in the
HALT mode, initializes a ²warm reset² only when the program counter and stack pointer are reset to zero. To
clear the contents of the WDT (including the WDT
prescaler ), three methods are adopted; external reset
(a low level to RESET), software instruction(s), or a HALT
instruction. There are two types of software instructions;
CLR WDT and CLR WDT1/CLR WDT2. Of these two
types of instruction, only one can be active depending
on the mask option - ²CLR WDT times selection option².
If the ²CLR WDT² is selected (ie. CLR WDT times equal
one), any execution of the CLR WDT instruction will
clear the WDT. In case ²CLR WDT1² and ²CLR WDT2²
are chosen (ie. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise,
the WDT may reset the chip because of the time-out.
To minimize power consumption, all I/O pins should be
carefully managed before entering the HALT status.
Reset
There are three ways in which a reset can occur:
· RESET reset during normal operation
· RESET reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm reset
that just resets the program counter and stack pointer,
leaving the other circuits to remain in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish between different ²chip resets².
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
· The system oscillator will turn off but the WDT oscilla-
tor keeps running (if the WDT oscillator is selected).
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HT82K68E
V D D
TO
PDF
RESET Conditions
0
0
RESET reset during power-up
u
u
RESET reset during normal operation
0
1
RESET wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
tS
R E S E T
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
V
Note: ²u² means unchanged
To guarantee that the system oscillator has started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system powers up or when it awakes from the HALT state.
D D
R E S E T
When a system power-up occurs, the SST delay is
added during the reset period. But when the reset comes from the RESET pin, the SST delay is disabled.
Any wake-up from HALT will enable the SST delay.
Reset Circuit
The functional unit chip reset status is shown below.
Program Counter
H A L T
000H
W D T
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer counter
Off
Input/output ports
Input mode
Stack Pointer
Points to the top of the stack
W D T
T im e - o u t
R e s e t
W a rm
R e s e t
R E S E T
S S T
1 0 -s ta g e
R ip p le C o u n te r
O S C 1
C o ld R e s e t
P o w e r - o n D e te c tio n
Reset Configuration
Timer Counter
A timer counter (TMR) is implemented in the
HT82K68E. The timer counter contains an 8-bit programmable count-up counter and the clock may come
from the system clock divided by 4.
counter to FFH. Once overflow occurs, the counter is
reloaded from the timer counter preload register and
generates the interrupt request flag (TF; bit 5 of INTC) at
the same time.
Using the internal instruction clock, there is only one reference time-base.
To enable the counting operation, the timer ON bit
(TON; bit 4 of TMRC) should be set to 1. In the case of
timer counter OFF condition, writing data to the timer
counter preload register will also reload that data to the
timer counter. But if the timer counter is turned on,
data written to it will only be kept in the timer counter
preload register. The timer counter will still operate until
overflow occurs. When the timer counter (reading TMR)
is read, the clock will be blocked to avoid errors. As
clock blocking may results in a counting error, this must
be taken into consideration by the programmer.
There are two registers related to the timer counter;
TMR ([0DH]), TMRC ([0EH]). Two physical registers are
mapped to TMR location; writing TMR makes the starting value be placed in the timer counter preload register
and reading TMR gets the contents of the timer counter.
The TMRC is a timer counter control register, which defines some options.
In the timer mode, once the timer counter starts counting, it will count from the current contents in the timer
Bit No.
Label
0~3
¾
4
TON
5
¾
6
7
TM0
TM1
Function
Unused bit, read as "0"
To enable/disable timer counting (0= disabled; 1= enabled)
Unused bit, read as "0"
10= Timer mode (internal clock)
TMRC (0EH) Register
Rev. 2.00
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July 10, 2007
HT82K68E
The state of the registers is summarized in the following table:
Register
WDT Time-out
RESET Reset
(Normal Operation) (Normal Operation)
Reset
(Power On)
RESET Reset
(HALT)
WDT Time-out
(HALT)
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H*
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
TMR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
Program
Counter
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PEC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
S y s te m
C lo c k /4
T M 1
T M 0
T O N
D a ta B u s
T M 1
T M 0
T im e r C o u n te r
P r e lo a d R e g is te r
T im e r
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
R e lo a d
O v e r flo w
to In te rru p t
Timer Counter
Rev. 2.00
13
July 10, 2007
HT82K68E
Input/Output Ports
After a chip reset, these input/output lines stay at high
levels or floating (mask option). Each bit of these input/output latches can be set or cleared by the SET [m].i
or CLR [m].i (m=12H, 14H, 16H, 18H or 1AH) instruction.
There are 32 bidirectional input/output lines in the
HT82K68E, labeled from PA to PE, which are mapped to
the data memory of [12H], [14H], [16H], [18H] and [1AH]
respectively. All these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction MOV A,[m] (m=12H, 14H,
16H, 18H or 1AH). For output operation, all data is
latched and remains unchanged until the output latch is
rewritten.
Some instructions first input data and then follow the
output operations. For example, the SET [m].i, CLR
[m].i, CPL [m] and CPLA [m] instructions read the entire
port states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PEC) to control the input/output configuration. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor (mask option) structures can be reconfigured dynamically (i.e.,
on-the-fly) under software control. To function as an
input, the corresponding latch of the control register must
write ²1². The pull-high resistance will exhibit automatically
if the pull-high option is selected. The input source(s) also
depend(s) on the control register. If the control register bit
is ²1², input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal
bus. The latter is possible in ²read-modify-write² instruction. For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H, 15H,
17H, 19H and 1BH.
Each line of port A and port C [0:3] has the capability to
wake-up the device.
PC2 is shared with the external interrupt pin, PE2~PE4
is defined as CMOS output pins only. PE0 can determine whether the high to low transition, or the low to
high transition of PC2 to activate the external subroutine, when PE0 output high, the low to high transition of
PC2 to trigger the external subroutine, when PE0 output
low, the high to low transition of PC2 to trigger the external subroutine.
PE2~PE4 is configured as CMOS output only and is
used to drive the LED. PC0, PC1 is configured as
NMOS open drain output with 4.6kW pull-high resistor
such that it can easy to use as DATA or CLOCK line of
PS2 keyboard application.
V
D a ta B u s
D
W r ite C o n tr o l R e g is te r
Q
C K
S
Q
V
C h ip R e s e t
P A
P B
P C
P D
P E
Q
D
C K
S
Q
M
R e a d I/O
S y s te m W a k e -u p
( P A & P C 0 ~ P C 3 o n ly )
W e a k
P u ll- u p
M a s k O p tio n
R e a d C o n tr o l R e g is te r
W r ite I/O
D D
D D
U
0 ~
0 ~
0 ~
0 ~
0 ~
P A
P B
P C
P D
P E
7
7
4
7
7
X
M a s k O p tio n
Input/Output Ports
Rev. 2.00
14
July 10, 2007
HT82K68E
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR such as changing a battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
V
O P R
5 .5 V
The LVR includes the following specifications:
V
2 .2 V
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
· The LVR uses the ²OR² function with the external
0 .9 V
RES signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V
L V R
2 .4 V
· The low voltage (0.9V~VLVR) has to remain in their
VOPR is the voltage range for proper chip
operation at 4MHz system clock.
Note:
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
*1
R e s e t
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the
reset mode.
Rev. 2.00
15
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HT82K68E
ROM Code Option
The following shows six kinds of ROM code option in the HT82K68E. All the ROM code options must be defined to ensure proper system function.
No.
ROM Code Option
1
OSC type selection. This option is to decide if an RC or Crystal oscillator is chosen as system clock. If the
Crystal oscillator is selected, the XST (Crystal Start-up Timer) default is activated, otherwise the XST is disabled.
2
WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable
the WDT.
3
CLRWDT times selection. This option defines the way to clear the WDT by instruction. ²One time² means
that the CLR WDT instruction can clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR
WDT2 instructions have been executed, only then will the WDT be cleared.
4
Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA and PC [0:3] only)
all have the capability to wake-up the chip from a HALT.
5
Pull-high selection. This option is to decide whether the pull-high resistance is visible or not in the input mode
of the I/O ports. Each bit of an I/O port can be independently selected.
6
LVR enable/disable. User can configure whether enable or disable the circuit by configuration option.
Application Circuits
RC Oscillator for Multiple I/O Applications
V
D D
F .B .
0 .1 m F
1 0 m .
V
V
V D D
P A
P A
P A
P A
P A
P A
P A
P A
P B
P B
P B
P B
P B
P B
P B
P B
P D
P D
P D
P D
P D
P D
P D
P D
P C
P C
D D
4 0 k W
fS Y S /4
(N M O S O p e n
D r a in O u tp u t)
V
O S C 1
O S C 2
D D
4 7 k W
IN 4 1 4 8
R E S E T
0 .1 m F
V
D D
C A P
N U M
S C R
C L K
D A T A
Crystal Oscillator or Ceramic Resonator for
Multiple I/O Applications
C L K
D A T A
C 0
7
0
6
5
4
3
2
1
0
7
6
5
4
3
2
C 2
0 .1 m F
R e s e rv e fo r
R e s o n a to r
C 3
C 4
V D D
P A
P A
P A
P A
P A
P A
P A
P A
P B
P B
P B
P B
P B
P B
P B
P B
P D
P D
P D
P D
P D
P D
P D
P D
P C
P C
O S C 1
C 5
C 6
C 7
O S C 2
R 0
R 1
V
R 2
D D
R 3
R 4
R 5
4 7 k W
IN 4 1 4 8
R 6
R E S E T
7
R 7
6
7
6
5
4
3
2
1
0
0 .1 m F
R 8
R 9
R 1 0
R 1 1
R 1 2
R 1 3
R 1 4
R 1 5
R 1 6
R 1 7
V
D D
C A P
N U M
S C R
C L K
D A T A
H T 8 2 K 6 8 E
Rev. 2.00
F .B .
1 0 m F
C 1
1
D D
C L K
D A T A
C 0
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
C 1
1
C 2
C 3
C 4
C 5
C 6
C 7
R 0
R 1
R 2
R 3
R 4
R 5
R 6
7
R 7
6
7
6
5
4
3
2
1
0
R 8
R 9
R 1 0
R 1 1
R 1 2
R 1 3
R 1 4
R 1 5
R 1 6
R 1 7
H T 8 2 K 6 8 E
16
July 10, 2007
HT82K68E
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 2.00
17
July 10, 2007
HT82K68E
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 2.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
18
July 10, 2007
HT82K68E
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
19
July 10, 2007
HT82K68E
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
20
July 10, 2007
HT82K68E
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
21
July 10, 2007
HT82K68E
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
22
July 10, 2007
HT82K68E
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
23
July 10, 2007
HT82K68E
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
24
July 10, 2007
HT82K68E
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
25
July 10, 2007
HT82K68E
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
26
July 10, 2007
HT82K68E
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
27
July 10, 2007
HT82K68E
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
28
July 10, 2007
HT82K68E
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
29
July 10, 2007
HT82K68E
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
July 10, 2007
HT82K68E
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 2.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
31
July 10, 2007
HT82K68E
Package Information
20-pin SOP (300mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Rev. 2.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
490
¾
510
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
32
July 10, 2007
HT82K68E
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 2.00
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
33
July 10, 2007
HT82K68E
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
2 4
1
C
C '
G
H
D
F
E
Symbol
Rev. 2.00
a
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
613
¾
637
D
85
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
34
July 10, 2007
HT82K68E
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 20W
Symbol
Description
A
Reel Outer Diameter
B
Reel Inner Diameter
Dimensions in mm
330±1.0
62±1.5
13.0+0.5
-0.2
C
Spindle Hole Diameter
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 2.00
35
July 10, 2007
HT82K68E
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
32.2+0.3
-0.2
T2
Reel Thickness
38.2±0.2
Rev. 2.00
330±1.0
36
July 10, 2007
HT82K68E
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 20W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0+0.3
-0.1
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.8±0.1
B0
Cavity Width
13.3±0.1
K0
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
0.3±0.05
C
Cover Tape Width
21.3
SOP 28W (300mil)
Symbol
W
Description
Dimensions in mm
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
11.5±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 2.00
21.3
37
July 10, 2007
HT82K68E
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32.0±0.3
P
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
2.0 Min.
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
12.0±0.1
B0
Cavity Width
16.20±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 2.00
0.35±0.05
25.5
38
July 10, 2007
HT82K68E
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 2.00
39
July 10, 2007