Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD13385F5 SLPS612 – OCTOBER 2016 CSD13385F5 12-V N-Channel FemtoFET™ MOSFET 1 Features • • • 1 • • • • . Low On Resistance Low Qg and Qgd Ultra-Small Footprint – 1.53 mm × 0.77 mm Low Profile – 0.35-mm Height Integrated ESD Protection Diode – Rated > 4-kV HBM – Rated > 2-kV CDM Lead and Halogen Free RoHS Compliant Product Summary TA = 25°C TYPICAL VALUE UNIT VDS Drain-to-Source Voltage 12 V Qg Gate Charge Total (4.5 V) 3.9 nC Qgd Gate Charge Gate-to-Drain RDS(on) VGS(th) Drain-to-Source On Resistance 0.39 nC VGS = 1.8 V 26 VGS = 2.5 V 18 VGS = 4.5 V 15 Threshold Voltage 0.8 mΩ V Device Information(1) DEVICE QTY CSD13385F5 3000 MEDIA PACKAGE SHIP 7-Inch Reel Femto 1.53-mm × 0.77-mm SMD Lead Less Tape and Reel 2 Applications CSD13385F5T • • (1) For all available packages, see the orderable addendum at the end of the data sheet. Optimized for Industrial Load Switch Applications Optimized for General Purpose Switching Applications 250 Absolute Maximum Ratings TA = 25°C 3 Description This 12-V, 15-mΩ, N-Channel FemtoFET™ MOSFET technology is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing a significant reduction in footprint size. VALUE UNIT VDS Drain-to-Source Voltage 12 V VGS Gate-to-Source Voltage 8 V ID IDM PD . . V(ESD) . TJ, Tstg . Continuous Drain Current(1) 4.3 Continuous Drain Current(2) 7.1 (1)(3) Pulsed Drain Current 41 Power Dissipation(1) 0.5 Power Dissipation(2) 1.4 Human-Body Model (HBM) 4 Charged-Device Model (CDM) 2 Operating Junction, Storage Temperature –55 to 150 A A W kV °C (1) Min Cu, typical RθJA = 245°C/W. (2) Max Cu, typical RθJA = 90°C/W. (3) Pulse duration ≤ 100 μs, duty cycle ≤ 1%. . Typical Part Dimensions Top View G 0.35 mm S 0.77 mm 1.53 mm D 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD13385F5 SLPS612 – OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 1 1 1 2 3 7 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Receiving Notification of Documentation Updates.... Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 Mechanical Dimensions ............................................ 8 7.2 Recommended Minimum PCB Layout...................... 9 7.3 Recommended Stencil Pattern ................................. 9 Device and Documentation Support.................... 7 4 Revision History 2 DATE REVISION NOTES October 2016 * Initial release. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD13385F5 CSD13385F5 www.ti.com SLPS612 – OCTOBER 2016 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 9.6 V 50 µA IGSS Gate-to-source leakage current VDS = 0 V, VGS = 8 V 25 µA VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA V RDS(on) Drain-to-source on resistance gfs Transconductance 12 V 0.8 1.2 VGS = 1.8 V, IDS = 0.1 A 0.5 26 50 VGS = 2.5 V, IDS = 0.9 A 18 23 VGS = 4.5 V, IDS = 0.9 A 15 19 VDS = 1.2 V, IDS = 0.9 A 11.3 mΩ S DYNAMIC CHARACTERISTICS Ciss Input capacitance VGS = 0 V, VDS = 6 V, ƒ = 1 MHz 519 674 pF Coss Output capacitance 305 396 pF Crss Reverse transfer capacitance 29 38 pF RG Series gate resistance 20 Qg Gate charge total (4.5 V) 3.9 Qgd Gate charge gate-to-drain 0.39 nC Qgs Gate charge gate-to-source 0.74 nC Qg(th) Gate charge at Vth 0.46 nC Qoss Output charge 2.5 nC td(on) Turnon delay time 7 ns tr Rise time 10 ns td(off) Turnoff delay time 33 ns tf Fall time 10 ns VDS = 6 V, IDS = 0.9 A VDS = 6 V, VGS = 0 V VDS = 6 V, VGS = 4.5 V, IDS = 0.9 A, RG = 2 Ω Ω 5.0 nC DIODE CHARACTERISTICS VSD Diode forward voltage ISD = 0.9 A, VGS = 0 V 0.67 1.0 V 5.2 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC RθJA (1) (2) Junction-to-ambient thermal resistance (1) MIN TYP 90 Junction-to-ambient thermal resistance (2) 245 MAX UNIT °C/W Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD13385F5 3 CSD13385F5 SLPS612 – OCTOBER 2016 www.ti.com 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise stated) 20 10 18 9 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) Figure 1. Transient Thermal Impedance 16 14 12 10 8 6 4 VGS = 1.8 V VGS = 2.5 V VGS = 4.5 V 2 8 7 6 5 4 3 2 TC = 125°C TC = 25°C TC = -55°C 1 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VDS - Drain-to-Source Voltage (V) 0.9 1 0 0.2 D002 0.4 0.6 0.8 1 1.2 1.4 VGS - Gate-to-Source Voltage (V) 1.6 1.8 D003 VDS = 5 V Figure 2. Saturation Characteristics 4 Submit Documentation Feedback Figure 3. Transfer Characteristics Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD13385F5 CSD13385F5 www.ti.com SLPS612 – OCTOBER 2016 Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise stated) 1000 4 3.5 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 4.5 3 2.5 2 1.5 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 100 1 0.5 10 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 Qg - Gate Charge (nC) ID = 0.9 A 3.2 3.6 0 4 2 D004 4 6 8 VDS - Drain-to-Source Voltage (V) Figure 4. Gate Charge D005 Figure 5. Capacitance 50 1 45 RDS(on) - On-State Resistance (m:) VGS(th) - Threshold Voltage (V) 12 VDS = 6 V 1.1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 -75 10 TC = 25°C, I D = 0.9 A TC = 125°C, I D = 0.9 A 40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 175 0 1 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) D006 7 8 D007 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage 10 1.4 VGS = 1.8 V VGS = 4.5 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 1.5 1.3 1.2 1.1 1 0.9 0.8 0.7 -75 TC = -55°C TC = -40°C TC = 25°C TC = 125°C TC = 150°C 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 175 0 0.1 D008 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VSD - Source-to-Drain Voltage (V) 0.9 1 D009 ID = 0.9 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD13385F5 5 CSD13385F5 SLPS612 – OCTOBER 2016 www.ti.com Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise stated) 100 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 100 10 1 100 ms 10 ms 0.1 0.1 1 ms 100 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25qC TC = 125qC 10 1 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D010 D011 Single pulse, typical RθJA = 290°C/W Figure 10. Maximum Safe Operating Area (SOA) Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 TA - Ambient Temperature (°C) 150 175 D012 Typical RθJA = 245°C/W Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD13385F5 CSD13385F5 www.ti.com SLPS612 – OCTOBER 2016 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.3 Trademarks FemtoFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD13385F5 7 CSD13385F5 SLPS612 – OCTOBER 2016 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Mechanical Dimensions 0.77 0.69 A B PIN 1 INDEX AREA 1.53 1.45 C 0.35 MAX SEATING PLANE 3 0.5 (R0.05) TYP 1 1 3X 3X 0.40 0.38 0.16 0.14 0.015 TOP B (1) All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994). (2) This drawing is subject to change without notice. (3) This package is a PB-free solder land design. A Table 1. Pin Configuration 8 POSITION DESIGNATION Pin 1 Gate Pin 2 Source Pin 3 Drain Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD13385F5 CSD13385F5 www.ti.com SLPS612 – OCTOBER 2016 7.2 Recommended Minimum PCB Layout 3X (0.39) (0.05) MIN ALL AROUND 1 (R0.05) TYP 3X (0.15) SYMM SOLDER MASK OPENING TYP (0.5) 3 SYMM (1) METAL UNDER SOLDER MASK TYP All dimensions are in millimeters. 7.3 Recommended Stencil Pattern 3X (0.39) 1 3X (0.2) (R0.05) TYP 2X (0.15) SYMM (0.15) (0.525) 3 SYMM (1) SOLDER MASK EDGE TYP All dimensions are in millimeters. Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Product Folder Links: CSD13385F5 9 PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD13385F5 ACTIVE PICOSTAR YJK 3 3000 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 150 4V CSD13385F5T ACTIVE PICOSTAR YJK 3 250 Green (RoHS & no Sb/Br) Call TI Level-1-260C-UNLIM -55 to 150 4V (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2016 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) CSD13385F5 PICOST AR YJK 3 3000 178.0 8.4 CSD13385F5T PICOST AR YJK 3 250 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 0.92 1.68 0.42 4.0 8.0 Q1 0.92 1.68 0.42 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Oct-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD13385F5 PICOSTAR YJK 3 3000 220.0 220.0 35.0 CSD13385F5T PICOSTAR YJK 3 250 220.0 220.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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