Winbond I5216SD 8 to 16 minute voice record/playback system with integrated codec Datasheet

I5216 SERIES
Advanced Information
PRELIMINARY
8 TO 16 MINUTE VOICE RECORD/PLAYBACK SYSTEM WITH
INTEGRATED CODEC
GENERAL DESCRIPTION
The ChipCorder I5216 is an 8 to 16 minute Voice and Data Record and Playback system with
integrated Voice band CODEC. The device works on a single 2.7V to 3.3V supply, and has fully
integrated system functions, including: AGC, microphone preamplifier, speaker driver, memory and
CODEC. The CODEC meets the PCM conformance specification of the G.714 recommendation. Its µLaw and A-law compander meets the specification of the ITU-T G.711 recommendation.
FEATURES
•
Single Supply 2.7 to 3.3 Volt operation
•
Voice and digital data record and playback system on a single chip
•
Industry-leading sound quality
•
Low voltage operation
•
Message management
•
Fully integrated system functions
•
Flexible architecture
•
Nonvolatile message storage
•
Configurable ChipCorder sampling rates of 4 kHz, 5.3kHz, 6.4 kHz and 8kHz
•
8, 10, 12 and 16 minutes duration
•
External or internal Voice recorder clock
• I2C
serial interface (400kHz)
•
Configurable analog paths
•
2.2V Microphone Bias Pin
•
100 year message retention (typical)
100K analog record cycles (typical)
• 10K digital record cycles (typical)
• Full-duplex (not in I2S mode) single channel speech CODEC with :
o External 13.824 MHz, 27.648 MHz, 20.48 MHz or 40.96 MHz master clock
o I2S and PCM digital audio interface ports
o Serial transfer data rate from 64 to 3072 Kbps
o Short and Long frame sync formats
o 2s complement and signed magnitude data format
o Complete µ-Law and A-Law companding
o Linear 14 bit ∆Σ PCM CODEC-filter for A/D and D/A converter
o 8 kHz or 44.1 kHz – 48 kHz digital audio sampling rate options
•
o Analog receive and transmit gain adjust
o Configurable setup through the I2C interface
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Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
TABLE OF CONTENTS
GENERAL DESCRIPTION .......................................................................................................1
FEATURES.............................................................................................................................. 1
PIN LAYOUT & DESCRIPTIONS ............................................................................................ 4
I5216 BLOCK DIAGRAMS....................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................ 8
SPEECH/SOUND QUALITY....................................................................................... 8
DURATION ................................................................................................................. 8
FLASH STORAGE...................................................................................................... 9
MICROCONTROLLER INTERFACE.......................................................................... 9
PROGRAMMING ........................................................................................................ 9
APPLICATIONS....................................................................................................................... 9
INTERNAL REGISTERS ....................................................................................................... 14
MEMORY ORGANIZATION .................................................................................................. 17
OPERATION MODES............................................................................................................ 17
2
I C PORT ............................................................................................................................... 17
2
I C SLAVE ADDRESS ........................................................................................................... 18
2
I C OPERATION DEFINITIONS ............................................................................................ 19
2
I C CONTROL REGISTERS.................................................................................................. 21
COMMAND BYTE.................................................................................................................. 21
FUNCTION BITS ................................................................................................................... 21
REGISTER BITS.................................................................................................................... 22
OPCODE SUMMARY ............................................................................................................ 22
DATABYTES.......................................................................................................................... 24
POWER-UP SEQUENCE..................................................................................................... 25
SET MASTER CLOCK DIVISION RATIO............................................................................. 25
PLAYBACK MODE ..................................................................................... ......................... 26
RECORD MODE...................................................................................................... ............ 26
FEED THROUGH MODE ........................................................................................ ............ 26
CALL RECORD ....................................................................................................... ............ 30
MEMO RECORD ..................................................................................................... ............ 31
MEMO & CALL PLAYBACK..................................................................................... ............ 32
MESSAGE CUEING ................................................................................................ ............ 34
ANALOG MODE ...................................................................................................... ............ 34
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Publication Release Date: November 30, 2001
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PRELIMINARY
AUTO MUTE & AUTO GAIN FUNCTIONS ............................................................. ............ 37
VOLUME CONTROL DESCRIPTION ..................................................................... ............ 38
SPEAKER & AUX OUT DESCRIPTION .................................................................. ............ 39
MICROPHONE INPUTS .......................................................................................... ............ 40
DIGITAL MODE ....................................................................................................... ............ 41
WRITING DATA.................................................................................................................... 41
READING DATA ................................................................................................................... 41
ERASING DATA ................................................................................................................... 41
EXAMPLE COMMAND SEQUENCES ................................................................................. 42
PIN DETAILS ........................................................................................................................ 45
DIGITAL I/O PINS.................................................................................................... 45
ANALOG I/O PINS................................................................................................... 48
AUXILIARY OUTPUT .............................................................................................. 49
AUXILIARY INPUT .................................................................................................. 50
POWER & GROUND PINS ..................................................................................... 51
SAMPLE LAYOUT FOR PDIP ................................................................................. 52
ELECTRICAL CHARACTERISTICS..................................................................................... 53
ABSOLUTE MAXIMUM RATINGS FOR PACKAGED PARTS................................ 53
ABSOLUTE MAXIMUM RATINGS FOR DIE........................................................... 53
OPERATING CONDITIONS FOR PACKAGED PARTS ......................................... 53
OPERATING CONDITIONS FOR DIE .................................................................... 54
GENERAL PARAMETERS ................................................................................................... 54
TIMING PARAMETERS........................................................................................................ 55
ANALOG PARAMETERS ..................................................................................................... 57
2
I C INTERFACE TIMING ...................................................................................................... 60
CODEC PARAMETERS ....................................................................................................... 61
TIMING DIAGRAMS ............................................................................................................. 62
2
I C SERIAL INTERFACE TECHNICAL INFORMATION ...................................................... 69
2
I S SERIAL INTERFACE TECHNICAL INFORMATION ...................................................... 73
DEVICE PHYSICAL DIMENSIONS ...................................................................................... 77
DIE BONDING PHYSICAL LAYOUT .................................................................................... 80
ORDERING INFORMATION…………………………………………………………................. 82
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Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
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PRELIMINARY
ISD5216 Pin Layout
VSSA
SDI
SDIO
RAC
INT
MCLK
VCCD
VCCD
SCL
A1
SDA
A0
VSSD
VSSD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ISD5216
I5216
WS
SCK
NC
AUX OUT
AUX IN
VCCA
SP+
VSSA
SPACAP
MICBS
MICMIC+
VSSA
VCCD
1
28
VCCD
SCL
2
27
MCLK
A1
3
26
INT
SDA
4
25
RAC
A0
5
24
SDIO
VSSD
6
23
SDI
VSSD
7
22
VSSA
VSSA
8
21
WS
MIC+
9
20
SCK
MIC-
ISD5216
I5216
10
19
NC
MICBS
11
18
AUX OUT
ACAP
12
17
AUX IN
SP-
13
16
VCCA
VSSA
14
15
SP+
28 -PIN TSOP
PDIP/SOIC
PDIP
VCCD
1
28
VCCD
SCL
2
27
MCLK
A1
3
26
INT
SDA
4
25
RAC
VSSD
5
24
SDIO
23
VSSA
SDI
I5216
VSSD
6
A0
7
22
MICBS
8
21
NC
MIC-
9
20
AUX OUT
MIC+
10
19
SCK
VSSA
11
18
WS
ACAP
12
17
AUX IN
SP-
13
16
VCCA
VSSA
14
15
SP+
SOIC
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Publication Release Date: November 30, 2001
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PRELIMINARY
PIN DESCRIPTION
Pin Name
Pin No.
Pin No.
Pin No.
RAC
28-pin
TSOP
4
28-pin
PDIP
25
28-pin
SOIC
25
/INT
5
26
26
MCLK
6
27
27
SCL
9
2
2
SDA
11
4
4
A0
A1
MIC+
MICMICBS
ACAP
SP+
SP-
12
10
16
17
18
19
22
20
5
3
9
10
11
12
15
13
7
3
10
9
8
12
15
13
AUX IN
24
17
17
AUX OUT
25
18
20
SDI
SDIO
WS
SCK
VCCD
2
3
28
27
7,8
23
24
21
20
1,28
22
24
18
19
1,28
VSSD
VSSA
VCCA
13,14
1,15,21
23
6,7
8,14,22
16
5,6
11,14,23
16
NC
26
19
21
1
Functionality
Row Address Clock; an open drain output. The RAC pin goes LOW
1
TRACLO before the end of each row of memory, and returns HIGH
at exactly the end of each row of memory.
Interrupt Output; an open drain output indicating that a set EOM bit
has been found during Playback, or that the chip is in an Overflow
(OVF) condition. This pin remains LOW until a Read Status
command is executed.
This pin allows the internal clock of the Voice record/playback
system to be externally driven for enhanced timing precision. This
pin is grounded for most applications. It is required for the CODEC
operation.
2
Serial Clock Line is part of the I C serial bus. It is used to clock the
2
data into and out of the I C interface.
2
Serial Data Line is part of the I C serial bus. Data is passed
between devices on the bus over this line.
2
Input pin that supplies the LSB for the I C Slave Address.
2
Input pin that supplies the LSB +1 bit for the I C Slave Address.
Differential positive Input to the microphone amplifier.
Differential negative Input to the microphone amplifier.
Microphone Bias Voltage
AGC Capacitor connection. Required for the on-chip AGC amplifier.
Differential Positive Speaker Driver Output.
Differential Negative Speaker Driver Output. When the speaker
outputs are in use, the AUX OUT output is disabled.
Auxiliary Input. This is one of the gain adjustable analog inputs for
the device.
Auxiliary Output. This is one the analog outputs for the device.
When this output is in use, the SP+ and SP- outputs are disabled.
Serial Digital Audio PCM Input.
2
Serial Digital Audio PCM Output or I S Input/Output.
2
Digital audio PCM Frame sync (FS) or I S Word Sync (WS).
2
Digital audio PCM or I S Serial Clock.
Positive Digital Supply pins. These pins carry noise generated by
internal clocks in the chip. They must be carefully bypassed to
Digital Ground to ensure correct device operation.
Digital Ground pins.
Analog Ground pins.
Positive Analog Supply pin. This pin supplies the low level audio
sections for the device. It should be carefully bypassed to Analog
Ground to ensure correct device operation.
No Connection
See parameters section of the datasheet.
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Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
BLOCK DIAGRAMS
I5216 Block Diagram
2.2V Voltage
reference
MICBS
1
MICROPHONE
(AGPD)
MIC IN
1
(AGPD)
AGCCAP
2
FILTO
1
ARRAY
( S1M0
S1M1 )
(INS0)
AUX IN
AMP
1
DAO
(AXPD)
( AXG0
AXG1)
MIC+
MIC-
ARRAY
1
1 (FLS0)
(
) 2(
FLD0
FLD1
)
(AMT0)
SUM2
Program/Read Control
(DIGITAL)
VOL
2 x 64-bit reg.
ARRAY OUT
(ANALOG)
AUX
OUT
AMP
FILTO
Array I/O Mux
A/D
CTRL
( S2M0
S2M1)
2
2 x 64 S/H
1 (CKD2)
Σ
AUX IN
(FLPD)
Multilevel
Storage Array
(ANALOG)
)
1
2
Internal
Clock
OSPD
CKDV
SUM2
Low Pass
Filter
Auto mute
Auto gain
SUM2
Summing
AMP
FILTO
ARRAY OUT
(DIGITAL)
Output MUX
(
S1S0
S1S1
SUM1
SUM1
2
2
÷2
MCLK
Σ
SUM1 MUX
SUM1 MUX
1.0 / 1.4 / 2.0 / 2.8
AUX IN
AUX IN
SUM1
Summing
AMP
INP
Filter
MUX
AGC
MIC -
Input Source MUX
MIC+
SPEAKER
Spkr.
AMP
DAO
INP
SUM2
INP
DAO
2
SUM2
µ-Law / A-Law /
Linear 14 bit
CODEC
(ADPD
)
DAPD
2
VSSA
1 (VLPD)
3
2
( OPS0
OPS1 )
( )
VOL0
VOL1
VOL2
( OPA0
OPA1 )
( VLS0
VLS1 )
2
Power Conditioning
VCCA
Volume
Control
Vol MUX
CODEC
Mux
( )
VSSA
SP+
SP-
2
SUM1
CDI0
CDI1
AUX OUT
VSSD
VSSD
VCCD
Device Control
PCM / I2S Interface
VCCD
WS
SCK
SDIO
SDI
SCL
SDA
INT
RAC
A0
5/22/01
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Publication Release Date: November 30, 2001
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A1
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I5216 CODEC DIAGRAM
µ/A-Law
Expander
or linear
(
)
Digital
Smoothing
Interpolation Filter
14 bit
Digital
Σ∆
Demodulator
( MUTE )
(
Digital
Anti-Aliasing
Decimation Filter
( MUTE )
1
1
(DAPD)
Anti
Aliasing
Filter
1
CIG0
CIG1
CIG2
)
(
1
(ADPD)
HPF0
HSR0
(
COG0
COG1
COG2
)
1 bit
)
2
)
µ/A-Law
Compressor
or linear
SDIO
SDI
8 bits or 16
bits
Digital
PLL
WS
(CKD2)
1
1
SCK
(HSR0)
1
LAW0
LAW1
2
(
Sample frequency
14 bit
PCM / I2S Interface
WS
3
1
8 bits or 16
bits
(I2S0)
ANALOG OUT
3
Digital
High pass
Filter
15 bit
Analog
Σ∆
Modulator
SC
AMP
DAO
1 bit D/A
& SC
Filter
1 bit
2
0.8/1/1.2/1.25/1.4/1.6/1.8/2
ANALOG IN
LAW0
LAW1
14 bit
÷2
MCLK
5/8/01
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Publication Release Date: November 30, 2001
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FUNCTIONAL DESCRIPTION
O
The I5216 ChipCorder Product provides high quality, fully integrated, single-chip Record/Playback
solutions for 8- to 16-minute messaging applications that are ideal for use in PBX systems, cellular
phones, automotive communications, GPS/navigation systems, and other portable products. The I5216
product is an enhancement to the ISD5116 architecture, providing: 1) A full duplex Voice CODEC with
2
µ-Law and A-Law compander, with I S and PCM interface ports; 2) A 2.2V microphone bias supply for
reduced noise coupling. This supply can also be used to power down the external microphone with the
system.
Analog functions and audio gating have also been integrated into the I5216 product to allow for easy
interfacing with integrated chip sets on the market. Audio paths have been designed to enable full
duplex conversation record, voice memo and answering machine (including outgoing message
playback).
Logic Interface Options of 2.0V and 3.0V are supported by the I5216 to accommodate both portable
communication (2.0- and 3.0-volt required) and automotive product customers (5.0-volt required).
Like other ChipCorder products, the I5216 integrates the sampling clock, anti-aliasing and smoothing
filters, and multi-level storage array on a single chip. For enhanced voice features, the I5216 eliminates
external circuitry by integrating automatic gain control (AGC), a power amplifier/speaker driver, volume
control, summing amplifiers, analog switches, and a Voice CODEC. Input level adjustable amplifiers
are also included, providing a flexible interface for multiple applications.
Recordings are stored in on-chip nonvolatile memory cells, providing zero-power message storage.
This unique, single-chip solution is made possible through Winbond’s patented multilevel storage
technology. Voice and audio signals are stored directly into solid-state memory in their natural,
uncompressed form, providing superior quality voice and music reproduction.
SPEECH/SOUND QUALITY
The I5216 ChipCorder product can be configured, via software, to operate at 4.0, 5.3, 6.4, and 8.0 kHz
sampling frequencies, allowing the user a choice of speech quality options. Increasing the duration
decreases the sampling frequency and bandwidth, which affects sound quality. The "Input Sample
Duration" table below compares filter pass band and product durations.
DURATION
To meet end-system requirements, the I5216 device is a single-chip solution, which provides 8 to 16
minutes of voice record and playback, depending on the sample rates defined by the customer's
software.
INPUT SAMPLE RATE TO DURATION INPUT SAMPLE
Rate (kHz)
Duration1
(Minutes)
Typical Filter Pass Band (kHz)
8.0
8 min 3 sec
3.7
6.4
10 min 4 sec
2.9
5.3
12 min 9 sec
2.5
4.0
16 min 6 sec
1.8
1. Minus any pages selected for digital storage
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Publication Release Date: November 30, 2001
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I5216 SERIES
Advanced Information
PRELIMINARY
FLASH STORAGE
One of the benefits of Winbond’s ChipCorder technology is the use of on-chip nonvolatile memory,
which provides zero-power message storage. A message is retained for up to 100 years (typically)
without power. In addition, the device can be re-recorded over 10,000 times (typically) for digital
messages and over 100,000 times (typically) for analog messages.
A new feature has been added that allows for the allocation of memory space in the I5216, to either
digital or analog storage, when recording. When making a recording, if a section is assigned for digital
or analog data storage, the system microcontroller stores this information in the Message Address
Table.
MICROCONTROLLER INTERFACE
2
The I5216 is controlled through an I C 2-wire interface. This synchronous serial port allows commands,
configurations, address data, and digital data to be loaded to the device, while allowing status, digital
data and current address information to be read back from the device. In addition to the serial
interface, two other pins can be connected to the microcontroller for enhanced interface: the RAC
timing pin and the INT\ pin for interrupts to the controller. Communications with all of the internal
registers is through the serial bus, as well as digital memory Read and Write operations.
PROGRAMMING
The I5216 series is also ideal for playback-only applications, whereas single or multiple messages may
2
be played back when desired. Playback is controlled through the I C port. Once the desired message
configuration is created, duplicates can easily be generated via a Winbond or third-party programmer.
For more information on available application tools and programmers, please see the Winbond web
site at http://www.winbond-usa.com/.
APPLICATIONS
The I5216 is a single chip solution for voice and analog storage that also includes the capability to
store digital information in the memory array. The array may be divided between analog and digital
storage, as the user chooses, when configuring the device.
Looking at the block diagram on the following page, one can see that the I5216 may be very easily
designed into a cellular phone. Placing the device between the microphone and the existing baseband
chip takes care of the transmit path. The SDI/SDIO of the baseband chip is connected to the SDIO/SDI
2
of the I5216. Two pins are needed for the I C digital control and digital information for storage.
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Publication Release Date: November 30, 2001
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PRELIMINARY
INT
SCL
SDA
Starting at the MICROPHONE inputs, the input signal at the MICROPHONE inputs can be routed in
the following ways:
•
directly through the Voice band CODEC of the I5216 chip, then through the SDIO pin, to output
the digital PCM signal.
•
through the AGC amplifier, before it is routed to the voice band CODEC.
•
through the AGC amplifier to the storage array
•
through the AGC amplifier and mixed with an analog voice band CODEC signal coming from
the digital SDI pin
In addition, if the phone is inserted into a "hands-free" car kit, then the signal from the pickup
microphone in the car can be passed through to the same places from the AUX IN pin and the phone's
microphone is switched off. In this scenario, the other party's voice from the phone would be played
into the PCM IN input and passed through to the AUX OUT pin that would drive the car kit's
loudspeaker.
Depending upon whether one desires recording one side (simplex) or both sides (duplex) of a
conversation, the various paths will also be switched through to the low pass filter (for antialiasing) and
into the storage array. Later, the cell phone owner can play back the messages from the array. When
this happens, the Array Output MUX is connected to the volume control, through the Output MUX, to
the Speaker Amplifier. For applications other than a cell phone, the audio paths can be switched into
many different and flexible configurations. Some examples follow.
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TRANSFORMER APPLICATION
To Microcontroller
I2C interface and
Vcc
Address setting
.1µF
.1µF
3
4
5
6
7
8
9
1.5kΩ
.1µF
Electret Microphone
10
11
12
13
14
WM-54B Panasonic
.1µF
1.5kΩ
1
2
28
27
MCLK
26
VCCD
VCCD
SCL
4.7KΩ
4.7KΩ
INT
A1
25
SDA
RAC
A0
SDIO 24
23
VSSD ISD521
VSSA 22
VSSA
WS 21
MIC+
SCK 20
MICNC 19
18
MICBS
AUX OUT
ACAP
AUX IN 17
16
VCCA
SP15
VSSD
SDI
SP+
VSSA
1µF
13.824 MHz
Vcc
Vcc
PCM OUT
PCM IN
8 KHz
2.048 MHz
TO AUXILIARY INPUT
.1µF
.1µF
PDIP
600Ω
N=1
TIP
N=1
RING
600Ω
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Publication Release Date: November 30, 2001
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HANDSET APPLICATION
To Microcontroller
I2C interface and
Vcc
Address setting
.1µF
.1µF
1.5kΩ
.1µF
1
2
3
4
5
6
7
8
9
Electret Microphone
10
11
12
13
14
WM-54B Panasonic
.1µF
1.5kΩ
VCCD
VCCD
26
RAC 25
SDIO 24
23
SDI
A1
4.7KΩ
4.7KΩ
INT
SDA
A0
VSSD
VSSD
28
MCLK 27
SCL
13.824 MHz
Vcc
Vcc
PCM OUT
PCM IN
22
21
20
SCK
19
VSSA
ISD521
VSSA
8 KHz
WS
MIC+
MIC-
2.048 MHz
NC
AUX OUT 18
MICBS
17
VCCA 16
SP+ 15
ACAP
TO RINGER
AUX IN
SP
VSSA
.1µF
AUXILIARY INPUT
.1µF
PDIP
RECEIVE
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CAR STEREO APPLICATION
To Microcontroller
I2C interface and
Vcc
Address setting
.1µF
.1µF
4
5
6
1.5kΩ
7
8
.1µF
9
10
11
12
13
14
Electret Microphone
WM-54B Panasonic
.1µF
1.5kΩ
1
2
3
VCCD 28
MCLK 27
VCCD
SCL
26
RAC 25
24
SDIO
23
4.7KΩ
4.7KΩ
INT
A1
SDA
A0
VSSD
SDI
VSSD
VSSA
ISD521
VSSA
WS
MIC+
SCK
MIC-
NC
MICBS
AUX OUT
ACAP
AUX IN
SP-
VCCA
VSSA
SP+
22
21
20
19
18
17
16
15
20.48 MHz
Vcc
Vcc
I2S SERIAL I/O
48 KHz
3.072 MHz
.1µF
1µF
PDIP
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Publication Release Date: November 30, 2001
Revision A1
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PRELIMINARY
INTERNAL REGISTERS
The following tables provide a general illustration of the bits. There are three configuration registers:
CFG0, CFG1 and CFG2. Thus, there are six 8-bit bytes to be loaded during the set-up of the device.
CFG0
Bit no.
Signal
Description
D0 (LSB)
VLPD
Power down the Volume Control.
D1
OPA0
Power down Speaker driver and/or Auxiliary output.
D2
OPA1
Power down Speaker driver and/or Auxiliary output.
D3
OPS0
Select speaker output multiplexer.
D4
OPS1
Select speaker output multiplexer.
D5
CDI0
Analog to digital converter input selector.
D6
CDI1
Analog to digital converter input selector.
D7
AMT0
Compress the filter signal.
D8
OSPD
Power down the internal ChipCorder oscillator.
D9
INS0
Select Microphone input or Auxiliary input.
D10
AXPD
Power down Auxiliary input amplifier.
D11
AXG0
Auxiliary input amplifier gain setting.
D12
AXG1
Auxiliary input amplifier gain setting.
D13
CIG0
Input gain setting for the Analog to digital converter.
D14
CIG1
Input gain setting for the Analog to digital converter.
D15 (MSB)
CIG2
Input gain setting for the Analog to digital converter.
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CFG1
Bit no.
Signal
Description
D0 (LSB)
AGPD
Power down the Microphone AGC
D1
FLPD
Power down the Filter
D2
FLD0
Set the duration and sample rate of the ChipCorder
D3
FLD1
Set the duration and sample rate of the ChipCorder
D4
FLS0
Select the filter input signal
D5
S2M0
Select Sum Amplifier 2 input
D6
S2M1
Select Sum Amplifier 2 input
D7
S1M0
Select Sum Amplifier 1 input
D8
S1M1
Select Sum Amplifier 1 input
D9
S1S0
Select Sum Amplifier 1 multiplexer
D10
S1S1
Select Sum Amplifier 1 multiplexer
D11
VOL0
Volume Control Setting
D12
VOL1
Volume Control Setting
D13
VOL2
Volume Control Setting
D14
VLS0
Select Volume Control input
D15 (MSB)
VLS1
Select Volume Control input
-15
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
CFG2
Bit no.
Signal
Description
D0 (LSB)
ADPD
Power down the Analog to Digital converter
D1
DAPD
Power down the Digital to Analog converter
D2
LAW0
Select digital µ-Law or A-Law input/output format
D3
LAW1
Select digital µ-Law or A-Law input/output format
D4
I2S0
Select the I2S interface
D5
HSR0
Enable the high sample rate mode
D6
HPF0
Enable High Pass Filter
D7
MUTE
Mute the CODEC A/D and D/A path
D8
CKDV
Divide MCLK by 2560 or 1728 for 8 kHz ChipCorder sample rate
D9
COG0
Output gain setting for the Digital to Analog converter
D10
COG1
Output gain setting for the Digital to Analog converter
D11
COG2
Output gain setting for the Digital to Analog converter
D12
CKD2
Divide MCLK frequency by 2 or 1
D13
-
Reserved
D14
-
Reserved
D15 (MSB)
-
Reserved
-16
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
MEMORY ORGANIZATION
The I5216 memory array is arranged as 1888 rows (or pages) of 2048 bits, for a total memory of
3,866,624 bits. The primary addressing for the 2048 pages is handled by 11 bits of address data in the
analog mode. At the 8 kHz sample rate, each page contains 256 milliseconds of audio. Thus, at 8 kHz
there is actually room for 8 minutes and 3 seconds of audio.
A memory page is 2048 bits organized as thirty-two 64-bit "blocks" when used for digital storage. The
contents of a page are either analog or digital. This is determined by instruction (op code) at the time
the data is written. A record of what is analog and what is digital, and where, is stored by the system
microcontroller in the message address table (MAT). The MAT is a table kept in the microcontroller
memory that defines the status of each message “block.” It can be stored back into the I5216 if the
power fails or the system is turned off. Use of this table allows for efficient message management.
Segments of messages can be stored wherever there is available space in the memory array. [This
is explained in detail for the Winbond I5008 in Applications Note #No.9 and will similarly be in a later
Note for the I5216.]
When a page is used for analog storage, the same 32 blocks are present, but there are 8 EOM (Endof-Message) markers. This means that for each 4 blocks there is an EOM marker at the end. Thus,
when recording, the analog recording will stop at any one of eight positions. At 8 kHz, this results in a
resolution of 32 msec when ENDING an analog recording. Beginning an analog recording is limited to
the 256 msec resolution provided by the 11-bit address. A recording does not immediately stop when
the Stop command is issued, but continues until the 32-millisecond block is filled. Then a bit is placed
into the EOM memory to develop the interrupt that signals a message is finished playing in the
Playback mode.
2
Digital data is sent and received, serially, over the I C interface. The data is serial-to-parallel converted
and stored in one of two alternating (commutating) 64-bit shift registers. When an input register is full,
it becomes the register that is parallel written into the array. The prior write register becomes the new
serial input register. A mechanism is built in to ensure there is always a register available for storing
new data.
Storing data in the memory is accomplished by accepting data, one byte at a time, and issuing an
acknowledgement. If data is coming in faster than it can be written, then the chip will not issue an
acknowledgement to the host microcontroller until it is ready.
The read mode is the opposite of the write mode. Data is read into one of two 64-bit registers from the
2
array and serially sent to the I C port. (See Digital Mode on page 41 for details).
OPERATION MODES DESCRIPTION
2
I C PORT
Important note: The content contained herein of the rest of this datasheet assumes that the
2
2
reader is familiar with the I C serial interface. Additional information on I C may be found in
2
the I C section of this document. If you are not familiar with this serial protocol, please read
the I2C section to familiarize yourself with it. A significant amount of additional information on
2
I C can also be found on the Philips web page at http://www.philips.com/.
-17
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
I2C SLAVE ADDRESS
The I5216 has a 7 bit slave address of <100 00xy> where x and y are equal to the state, respectively,
of the external address pins A1 and A0. Because all data bytes are required to be 8 bits, the LSB of the
address byte is the Read/Write selection bit that tells the slave whether to transmit or receive data.
Therefore, there are eight possible slave addresses for the I5216
A1
A0
Slave Address
R/W\
Bit
HEX Value
0
0
<100 00 00>
0
80
0
1
<100 00 01>
0
82
1
0
<100 00 10>
0
84
1
1
<100 00 11>
0
86
0
0
<100 00 00>
1
81
0
1
<100 00 01>
1
83
1
0
<100 00 10>
1
85
1
1
<100 00 11>
1
87
2
To use more than four I5216 devices in an application requires some external switching of the I C link.
-18
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
I2C OPERATION DEFINTIONS
There are many control functions used to operate the I5216. Among them are the following.
2
Conventions used in I C Data
Transfer Diagrams
READ STATUS COMMAND: The read status command is a read
request from the Host processor to the I5216 without delivering a
Command Byte. The Host supplies all of the clocks (SCL). In each
case, the entity sending the data drives the data line (SDA). The Read
2
Status Command is executed by the following I C sequence.
S
= START Condition
P
= STOP Condition
2
1. Host executes I C START
2. Send Slave Address with R/W bit = “1” (Read) 81h.
DATA = 8 bit data transfer
3. Slave responds back to Host an Acknowledge (ACK), followed
by 8 bit Status word.
R
= “1” in the R/W bit
4. Host sends an Acknowledge (ACK) to Slave.
5. Wait for SCL to go HIGH.
W
6. Slave responds with Upper Address byte of internal address
register.
A
= “0” in the R/W bit
= ACK (Acknowledge)
7. Host sends an ACK to Slave.
N
8.
Wait for SCL to go high.
9.
Slave responds with Lower Address byte of internal address
register.
2
= No ACK
SLAVE ADDRESS
10. Host sends a NO ACK to Slave, then executes I C STOP
= 7 bit Slave
Address
The Box color indicates the
direction of data flow
= Host to Slave (Gray)
= Slave to Host (White)
2
Note: The processor could have sent an I C STOP after the Status
Word data transfer, and thus aborted the transfer of the Address bytes
A graphical representation of this operation is found below. See the caption box above for more
explanation.
S
SLAVE ADDRESS
R
A
DATA
A
DATA
High
Status
-19
A
Addr.
DATA
Low
N
P
Addr.
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
LOAD COMMAND BYTE REGISTER (Single Byte Load)
A single byte may be written to the Command Byte Register in order to power up the device, start or
stop Analog Record (if no address information is needed), or perform a Message Cueing function. The
Command Byte Register is loaded as follows:
S
2
SLAVE ADDRESS
1.
Host executes I C START.
2.
Send Slave Address with R/W bit = “0” (Write) [80h].
3.
Slave responds back with an ACK.
4.
Wait for SCL to go HIGH.
5.
Host sends a command byte to Slave.
6.
Slave responds with an ACK.
7.
Wait for SCL to go HIGH.
8.
Host executes I C STOP.
W
A
DATA
A
Command Byte
2
LOAD COMMAND BYTE REGISTER (Address Load):
For the normal addressed mode the Registers are loaded as follows:
2
1.
Host executes I C START.
2.
Send Slave Address with R/W bit = “0” (Write).
3.
Slave responds back with an ACK.
4.
Wait for SCL to go HIGH.
5.
Host sends a byte to Slave - (Command Byte).
6.
Slave responds with an ACK.
7.
Wait for SCL to go HIGH.
8.
Host sends a byte to Slave - (High Address Byte).
9.
Slave responds with an ACK.
10. Wait for SCL to go HIGH.
11. Host sends a byte to Slave - (Low Address Byte).
12. Slave responds with an ACK.
13. Wait for SCL to go HIGH.
2
14. Host executes I C STOP.
S
SLAVE ADDRESS
W
A
DATA
Command
A
DATA
High
-20
A
DATA
Addr.
Low
A
P
Addr.
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
I2C CONTROL REGISTERS
The I5216 is controlled by loading commands to, or reading commands from the internal command,
configuration and address registers. The Command byte sent is used to start and stop recording, write
or read digital data and perform other functions necessary for the operation of the device.
COMMAND BYTE
Control of the I5216 is implemented through an 8-bit command byte that is sent after the 7-bit device
address and the 1-bit Read/Write selection bit. The 8 bits are:
Global power up bit
DAB bit: determines whether device is performing an analog or digital function
3 function bits: these determine which function the device is to perform in conjunction with the
DAB bit.
3 register address bits: these determine if and when data is to be loaded to a register
Power Up Bit
C7
C6
C5
C4
C3
C2
C1
C0
PU
DAB
FN2
FN1
FN0
RG2
RG1
RG0
Function Bits
Register Bits
FUNCTION BITS
The command byte function bits are detailed
in the table to the right. C6, the DAB bit,
determines
whether
the
device
is
performing an analog or digital function. The
other bits are decoded to produce the
individual commands. Note that not all
decode combinations are currently used;
they are reserved for future use. Out of 16
possible codes, the I5216 uses 7 for normal
operation. The other 9 are No Ops.
Function
Command Bits
C6
C5
C4
C3
DAB
FN2
FN1
FN0
0
0
0
0
STOP (or do nothing)
0
1
0
1
Analog Play
0
0
1
0
Analog Record
0
1
1
1
Analog MC
1
1
0
0
Digital Read
1
0
0
1
Digital Write
1
0
1
0
Erase (row)
-21
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
REGISTER BITS
The register load may be used to modify
a command sequence (such as load an
address) or used with the null command
sequence to load a configuration or test
register. Not all registers are accessible to
the user. [The remaining three codes are
No Ops.]
RG2
RG1
RG0
C2
C1
C0
0
0
0
No action
0
0
1
Load Address
0
1
0
Load CFG0
0
1
1
Load CFG1
1
0
1
Load CFG2
Function
OPCODE SUMMARY
OpCode Command Description
2
The following commands are used to access the chip through the I C port:
Play: analog play command.
Record: analog record command.
Message Cue: analog message cue command.
Enter Digital mode.
Read: digital read command.
Write: digital write command.
Erase: digital page and block erase command.
Exit Digital mode.
Power up: global power up/down bit. (C7).
Load address: load address register (is incorporated in play, record, read and write
commands).
Load CFG0: load configuration register 0.
Load CFG1: load configuration register 1.
Load CFG2: load configuration register 2.
Read STATUS: Read the interrupt status and address register, including a hardwired device
ID.
-22
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
OPCODE COMMAND BYTE TABLE
Pwr
Function Bits
Register Bits
OPCODE
HEX
PU
DAB
FN2
FN1
FN0
RG2
RG1
RG0
COMMAND BIT NUMBER
CMD
C7
C6
C5
C4
C3
C2
C1
C0
POWER UP
80
1
0
0
0
0
0
0
0
POWER DOWN
00
0
0
0
0
0
0
0
0
STOP (DO NOTHING) STAY ON
80
1
0
0
0
0
0
0
0
STOP (DO NOTHING) STAY OFF
00
0
0
0
0
0
0
0
0
LOAD ADDRESS
81
1
0
0
0
0
0
0
1
LOAD CFG0
82
1
0
0
0
0
0
1
0
LOAD CFG1
83
1
0
0
0
0
0
1
1
LOAD CFG2
85
1
0
0
0
0
1
0
1
RECORD ANALOG
90
1
0
0
1
0
0
0
0
RECORD ANALOG @ ADDR
91
1
0
0
1
0
0
0
1
PLAY ANALOG
A8
1
0
1
0
1
0
0
0
PLAY ANALOG @ ADDR
A9
1
0
1
0
1
0
0
1
MSG CUE ANALOG
B8
1
0
1
1
1
0
0
0
MSG CUE ANALOG @ ADDR
B9
1
0
1
1
1
0
0
1
ENTER DIGITAL MODE
C0
1
1
0
0
0
0
0
0
ERASE DIGITAL PAGE
D1
1
1
0
1
0
0
0
1
WRITE DIGITAL
C8
1
1
0
0
1
0
0
0
WRITE DIGITAL @ ADDR
C9
1
1
0
0
1
0
0
1
READ DIGITAL
E0
1
1
1
0
0
0
0
0
READ DIGITAL @ ADDR
E1
1
1
1
0
0
0
0
1
EXIT DIGITAL MODE
40
0
1
0
0
0
0
0
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
READ STATUS REGISTER
1
-23
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
1
See Playback and Stop Cycle on page 62 for details.
DATABYTES
2
In the I C write mode, the device can accept data sent after the command byte. If a register load option
is selected, the next two bytes are loaded into the selected register. The format of the data is MSB first,
2
as specified by the I C standard. Thus to load DATA<15:0> into the device, DATA<15:8> is sent first,
the byte is acknowledged, and DATA<7:0> is sent next. The address register consists of two bytes.
The format of the address is as follows:
ADDRESS<15:0> = PAGE_ADDRESS<10:0>, BLOCK_ADDRESS<4:0>
If an analog function is selected, the block address bits must be set to 00000. Digital Read and Write
are block addressable.
When the device is polled with the Read Status command, it will return three bytes of data. The first
byte is the status byte, the next is the upper address byte and the last is the lower address byte. The
status register is one byte long and its bit function is:
STATUS<7:0> = EOM, OVF, READY, PD, PRB, DEVICE_ID<2:0>
The lower address byte will always return the block address bits as zero, either in digital or analog
mode.
The functions of the bits are:
BIT#
NAME
FUNCTION
7
EOM
Indicates whether an EOM interrupt has occurred.
6
OVF
Indicates whether an overflow interrupt has occurred.
5
READY
Indicates the internal status of the device – if READY is LOW no new
commands should be sent to device.
4
PD
Device is powered down if PD is HIGH.
3
PRB
Play/Record mode indicator. HIGH=Play/LOW=Record.
DEVICE_ID
An internal device ID. This is 001 for the I5216.
2
1
0
It is good practice to read the status register after a Write or Record operation to ensure that the
device is ready to accept new commands. Depending upon the design and the number of pins
available on the controller, the polling overhead can be reduced. If INT\ and RAC are tied to the
microcontroller, the controller does not have to poll as frequently to determine the status of the I5216
-24
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
POWER-UP SEQUENCE
This sequence prepares the I5216 for an operation to follow, and waits for the Tpud time before
sending the next command sequence.
2
1. Send I C Start.
2. Send one byte 10000000 {Slave Address, R/W = 0} 80h.
3. Slave ACK.
4. Wait for SCL High.
5. Send one byte 10000000 {Command Byte = Power Up} 80h.
6. Slave ACK.
7. Wait for SCL High.
2
8. Send I C Stop.
SET MASTER CLOCK DIVISION RATIO
The I5216 product has two Master Clock configuration bits that allow four possible Master Clock
frequencies. The Master Clock Division ratios can be set by bits CKD2 and CKDV. These are bits D12
and D8 of CFG2, respectively. The combination of these bits, with the sample rate bit HSR0, also sets
the CODEC sample frequency.
Master Clock Possible Settings
FMCLK
HSR0 (D5)
(CFG2)
CKD2 (D12)
(CFG2)
CKDV (D8)
(CFG2)
FSCODEC
13.824 MHz
0
0
0
8 kHz
20.48 MHz
0
0
1
11.852 kHz*
27.648 MHz
0
1
0
8 kHz
40.96 MHz
0
1
1
11.852 kHz*
13.824 MHz
1
0
0
32 kHz*
20.48 MHz
1
0
1
44.1 - 48 kHz
27.648 MHz
1
1
0
32 kHz*
40.96 MHz
1
1
1
44.1-48 kHz
*not tested
-25
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
PLAYBACK MODE
The command sequence for an analog Playback operation can be handled several ways. One
technique is to do a Load Address (81h), which requires sending a total of four bytes, followed by a
Play Analog, which is a Command Byte (A8h) preceded by the Slave Address Byte. This is a total of six
bytes plus the times for Start, ACK, and Stop.
Another approach for an analog Playback operation is via a single four byte exchange, which consists
of the Slave Address (80h), the Command Byte (A9h) for Play Analog @ Address, and the two address
bytes.
RECORD MODE
The command sequence for an Analog Record is a four byte sequence consisting of the Slave
Address (80h), the Command Byte (91h) for Record Analog @ Address, and the two address bytes.
2
(See I C Interface on page 17 for more detail.)
FEED THROUGH MODE
SDIO
1
(I2S0)
(LAW1,LAW0)
3
Spkr.
AMP
AMP
DAO-
3
(DAPD,HSR0,MUTE) (COG2,COG1,COG0)
SUM2VOLFILTO-
SP+
SP-
2
(OPA1,O PA0)
2
(OPS1,O PS0)
µ/A-Law
Compressor
2
(LAW1,LAW0)
Input
GAIN
ADC
4
(ADPD,HSR0,HPF0,MUTE)
3
(CIG2,CIG1,CIG0)
CODEC In Mux
PCM Interface
SCK
2
Output
GAIN
DAC
MUX
WS
µ/A-Law
Expander
SPEAKER
Output
SDI
FILTO+
VOL+
SUM2+
DAO+
SUM2+
INP+
MIC+
MIC INPSUM2-
2
(CDI1,CDI0)
This diagram shows the part of the I5216 block diagram that is used in Feed Through Mode. The rest of the chip
will be powered down to conserve power. Note that the Microphone and Speaker +/– paths are differential
- 26 -
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
FEED THROUGH MODE
The previous examples were dependent upon the device already being powered up and the various
paths being set through the device for the desired operation. To set up the device for the various paths
requires loading the three 16-bit Configuration Registers with the correct data. For example, in the
Feed Through Mode, the device only needs to be powered up and a few paths selected. This mode
enables the I5216 to connect to a cellular or cordless baseband phone chip set without affecting the
audio source or destination. There are two paths involved: the transmit path and the receive path. The
transmit path connects the Winbond chip’s microphone source through to the digital audio input on the
baseband chip set. The receive path connects the baseband chip set’s digital output through to the
speaker driver on the Winbond chip. This allows the Winbond chip to substitute for Analog to Digital
and Digital to Analog conversion, and incidentally gain access to the audio, both to and from the
baseband chip set.
To setup the environment described above, a series of commands need to be sent to the I5216. First,
the chip needs to be powered up as described in Power-Up Sequence on page 25. Then the
Configuration Registers need to be filled with the specific data to connect the desired paths. In the
case of the Feed Through Mode, most of the chip can remain powered down. The Feed Through
Mode diagram illustrates the affected paths
To select the Feed Through mode, the following control bits must be configured in the I5216 configuration register
To set up the transmit path:
1. Select the FTHRU path through the CODEC INPUT MUX—Bits CDI1 and CDI0 control the
state of the CODEC INPUT MUX. These are the D6 and D5 bits, respectively, of Configuration
Register 0 (CFG0) and they should be set to ONE and ZERO, respectively, to select the
FTHRU path.
2. Power up the ADC—Bit ADPD controls the power up state of ADC. This is bit D0 of CFG2 and
it should be a ZERO to power up the ADC.
3. Set the CODEC input gain. The input gain setting will depend on the input level at the MIC+/pins and can be set by the CODEC INPUT GAIN Bits CIG2, CIG1 and CIG0. These are the
D15, D14 and D13 bits, respectively, of Configuration Register 0 (CFG0). The input gain can
be set according to the following table. (Table A)
4. Enable the High Pass Filter, if desired, in the low sample rate mode. This can be done by
setting bit HPF0 to ONE. This is bit D6 of CFG2.
5. Select the low or high sample rate mode by setting bit HSR0. This is bit D5 of CFG2. HSR0
needs to be set to ONE for the high sample rate mode.
6. Set the MUTE bit if desired. This bit can be set temporarily to reduce power up ‘pops’ or to set
the system on hold. This bit is D7 of CFG2 and needs to be set to ONE in order to mute the
signal.
7. Set the digital data format through bits LAW1 and LAW0. These are bits D3 and D2 of CFG2,
respectively. The data format can be chosen according to the following table. (Table B).
2
8. Set the interface mode to PCM-interface by setting bit I S0 to ZERO. This will also enable full
duplex mode. This bit is bit D4 of CFG2.
9. Set the Master Clock division ratios as described in Set Master Clock Division Ratio on page
25.
- 27
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
Table A
Table B
CIG2
CIG1
CIG0
GAIN
0
0
0
0.80
0
0
1
1.00
0
1
0
1.20
0
1
1
1.25
1
0
0
1.40
1
0
1
1.60
1
1
0
1.80
1
1
1
2.00
Table C
LAW
1
LAW
0
Data format
0
0
Two’s complement
0
1
A-Law
1
0
µ-Law
1
1
Table D
HSRO
Sample Rate Mode
HPF0
High Pass Filter
0
Low
0
Bypassed
1
High
1
Enabled
Table E
Table F
ADPD
CODEC ADC
DAPD
CODEC DAC
0
Power Up
0
Power Up
1
Power Down
1
Power Down
Table G
2
Table H
I S0
CONDITION
MUTE
CONDITION
0
PCM Interface
0
Power Up
1
Mute CODEC ADC & DAC
1
2
I S Interface
- 28
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
To set up the receive path:
Set up the CODEC output gain amplifier for the correct gain—Bits COG0, COG1 and COG2 control the
gain settings of this amplifier. These are bits D9, D10 and D11, respectively, of CFG2. The table below
will help determine the setting
COG2
COG1
COG0
GAIN (dB)
0
0
0
0
0
0
1
+2
0
1
0
+4
0
1
1
+6
1
0
0
-8
1
0
1
-6
1
1
0
-4
1
1
1
-2
1. Power up the DAC—Bit DAPD controls the power up state of the DAC. This is bit D1 of CFG2
and should be a ZERO to power up the DAC.
2. Select the DAC path through the OUTPUT MUX—Bits OPS0 and OPS1 control the state of
the OUTPUT MUX. These are bits D3 and D4, respectively, of CFG0 and they should be set to
the state where D3 is ONE and D4 is ZERO to select the DAC path.
3. Power up the Speaker Amplifier—Bits OPA0 and OPA1 control the state of the Speaker and
AUX amplifiers. These are bits D1 and D2, respectively, of CFG0. They should be set to the
state where D1 is ONE and D2 is ZERO. This powers up the Speaker Amplifier and configures
it for a higher gain setting (for use with a piezo speaker element) and also powers down the
AUX output stage.
2
4. Set the Master Clock configuration bits and bits HSR0, MUTE, HPF0, I S0, LAW1 and LAW0
as described in the previous sections.
The status of the rest of the functions in the I5216 chip must be defined before the configuration
registers settings are updated:
1. Power down the Volume Control Element—Bit VLPD controls the power up state of the Volume
Control. This is bit D0 of CFG0 and it should be set to a ONE to power down this stage.
2. Power down the internal oscillator—Bit PDOS controls the power up state of the internal
ChipCorder oscillator. This is bit D8 of CFG0 and it should be set to a ONE to power down this
oscillator
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Advanced Information
PRELIMINARY
3. Power down the AUX IN amplifier—Bit AXPD controls the power up state of the AUX IN input
amplifier. This is bit D10 of CFG0 and it should be set to a ONE to power down this stage.
4. Power down the SUM1 and SUM2 Mixer amplifiers—Bits S1M0 and S1M1 control the SUM1 mixer
and bits S2M0 and S2M1 control the SUM2 mixer. These are bits D7 and D8 in CFG1, and bits D5
and D6 in CFG1, respectively. All four bits should be set to a ONE in order to power down these
two amplifiers.
5. Power down the FILTER stage—Bit FLPD controls the power up state of the FILTER stage in the
device. This is bit D1 in CFG1 and should be set to a ONE to power down the stage.
6. Power down the AGC amplifier—Bit AGPD controls the power up state of the AGC amplifier. This
is bit D0 in CFG1 and should be set to a ONE to power down this stage.
7. Don’t Care bits—All other bits are not used in Feed Through Mode. Their bits may be set to either
level. In this example, we will set all the "Don’t Care" bits to a ZERO.
The following example shows the setup for a full-duplex feed-through path at 8 kHz sampling rate. The
twos complement data format is enabled. The High Pass filter is also enabled. The Master Clock input
is running at 13.824MHz.
CFG0=0010 0101 0100 1011 (hex 254B)
and
CFG1=0000 0001 1110 0011 (hex 01E3).
and
CFG2=0000 0000 0100 0000 (hex 0040).
Since three registers are being loaded, CFG0 is loaded, followed by the loading of CFG1 and CFG2.
These three registers must be loaded in this order. The internal set up for these registers will take
effect synchronously, with the rising edge of SCL.
CALL RECORD
The call record mode adds the ability to record the incoming phone call. In most applications, the I5216
would first be set up for Feed Through Mode as described above. When the user wishes to record the
incoming call, the set up of the chip is modified to add that ability. For the purpose of this
explanation, we will use the 6.4 kHz ChipCorder sample rate during recording.
The block diagram of the I5216 shows that the Multilevel Storage array is always driven from the
SUM2 SUMMING amplifier. The path traces back from there, through the LOW PASS Filter, the
FILTER MUX, the SUM1 SUMMING amplifier, the SUM1 MUX, back to the origin CODEC. Feed
Through Mode has already powered up the CODEC, so we only need to power up and enable the path
to the Multilevel Storage array from that point:
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Advanced Information
PRELIMINARY
1. Select the CODEC path through the SUM1 MUX—Bits S1S0 and S1S1 control the state of the
SUM1 MUX. These are bits D9 and D10, respectively, of CFG1 and they should be set to the state
where both D9 and D10 are ZERO to select the CODEC path.
2. Select the SUM1 MUX input (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1 control
the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of CFG1 and
they should be set to the state where D7 is ONE and D8 is ZERO to select the SUM1 MUX (only)
path.
3. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state
of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1 SUMMING amplifier path.
4. Deselect the signal compression-Bit AMT0 controls the signal compression. This is bit D7 of CFG0
and it must be set to ZERO.
5. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
6. Select the 6.4 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample
rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 6.4
kHz sample rate, D2 must be set to ONE and D3 set to ZERO.
7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier—Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6, respectively, of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
The configuration settings in the call record mode are:
CFG0=0100 0100 0000 1011 (hex 440B).
CFG1=0000 0000 1100 0101 (hex 00C5).
CFG2=0000 0000 0100 0000 (hex 0040).
MEMO RECORD
The Memo Record mode sets the chip up to record from the local microphone into the chip’s Multilevel
Storage Array. A connected cellular telephone or cordless phone chip set may remain powered down
since they are not active in this mode. The path to be used is microphone input to AGC amplifier, then
through to the INPUT SOURCE MUX, to the SUM1 SUMMING amplifier. From there, the path goes
through the FILTER MUX, the LOW PASS FILTER, the SUM2 SUMMING amplifier, then to the
MULTILEVEL STORAGE ARRAY. In this example, we will select the 5.3 kHz sample rate. The rest of
the chip may be powered down.
1. Power up the AGC amplifier Bit AGPD controls the power up state of the AGC amplifier. This is bit
D0 of CFG1 and must be set to ZERO to power up this stage.
2. Select the AGC amplifier through the INPUT SOURCE MUX—Bit INS0 controls the state of the
INPUT SOURCE MUX. This is bit D9 of CFG0 and must be set to a ZERO to select the AGC amplifier.
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Advanced Information
PRELIMINARY
3. Select the INPUT SOURCE MUX (only) to the S1 SUMMING amplifier—Bits S1M0 and S1M1
control the state of the SUM1 SUMMING amplifier. These are bits D7 and D8, respectively, of
CFG1 and they should be set to the state where D7 is ZERO and D8 is ONE to select the INPUT
SOURCE MUX (only) path.
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the state
of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the SUM1
SUMMING amplifier path.
5. Deselect the signal compression-Bit AMT0 controls the signal compression. This is bit D7 of CFG0
and it must be set to ZERO.
6. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
7. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample
rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 5.3
kHz sample rate, D2 must be set to ZERO and D3 set to ONE.
8. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier – BITS S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6, respectively, of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
9. Power up the Internal Oscillator—Bit OSPD controls the power up state of the Internal Oscillator.
This is bit D8 of CFG0 and it must be set to ZERO to power up the Internal Oscillator.
To set up the chip for Memo Record, the configuration registers are set up as follows:
CFG0=0000 0100 0000 0001 (hex 0401).
CFG1=0000 0001 0100 1000 (hex 0148).
CFG2=0000 0000 0000 0011 (hex 0003).
Only those portions necessary for this mode are powered up.
MEMO AND CALL PLAYBACK
This mode sets the chip up for local playback of messages that were recorded earlier. The playback
path is from the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS
FILTER stage. From there, the audio path goes through the SUM2 SUMMING amplifier to the
VOLUME MUX, through the VOLUME CONTROL then to the SPEAKER output stage. We will assume
that we are driving a piezo speaker element and that this audio was previously recorded at 8 kHz. All
unnecessary stages will be powered down.
1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX—Bit FLS0, the state
of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the MULTILEVEL
STORAGE ARRAY.
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Advanced Information
PRELIMINARY
2. Power up the LOW PASS FILTER—Bit FLPD controls the power up state of the LOW PASS
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and sample
rate to be used during record and playback. These are bits D2 and D3 of CFG1. To enable the 8.0
kHz sample rate, D2 and D3 must be set to ZERO.
4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and S2M1
control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6, respectively, of
CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to select the LOW
PASS FILTER (only) path.
5. Select the SUM2 SUMMING amplifier path through the VOLUME MUX—Bits VLS0 and VLS1
control the VOLUME MUX stage. These bits are D14 and D15, respectively, of CFG1. They should
be set to the state where D14 is ONE and D15 is ZERO to select the SUM2 SUMMING amplifier.
6. Power up the VOLUME CONTROL LEVEL—Bit VLPD controls the power-up state of the VOLUME
CONTROL attenuator. This is Bit D0 of CFG0. This bit must be set to a ZERO to power-up the
VOLUME CONTROL.
7. Select a VOLUME CONTROL LEVEL—Bits VOL0, VOL1 and VOL2 control the state of the VOLUME CONTROL LEVEL. These are bits D11, D12, and D13, respectively, of CFG1. A binary count
of 000 through 111 controls the amount of attenuation through that stage. In most cases, the
software will select an attenuation level according to the desires of the product user. In this
example, we will assume the user wants an attenuation of –12 dB. For that setting, D11 should be
set to ONE, D12 should be set to ONE, and D13 should be set to a ZERO.
8. Select the VOLUME CONTROL path through the OUTPUT MUX—These are bits D3 and D4,
respectively, of CFG0. They should be set to the state where D3 is ZERO and D4 is a ZERO to
select the VOLUME CONTROL.
9. Power up the SPEAKER amplifier and select the HIGH GAIN mode—Bits OPA0 and OPA1 control
the state of the speaker (SP+ and SP–) and AUX OUT outputs. These are bits D1 and D2 of
CFG0. They must be set to the state where D1 is ONE and D2 is ZERO to power-up the speaker
outputs in the HIGH GAIN mode and to power-down the AUX OUT.
10. Power up the Internal Oscillator—Bit OSPD controls the power up state of the Internal Oscillator.
This is bit D8 of CFG0 and it must be set to ZERO to power up the Internal Oscillator.
To set up the chip for Memo or Call Playback, the configuration registers are set up as follows:
CFG0=0010 0100 0010 0010 (hex 2422).
CFG1=0101 1001 1101 0001 (hex 59D1).
CFG2=0000 0000 0000 0011 (hex 0003).
Only those portions necessary for this mode are powered up.
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Advanced Information
PRELIMINARY
MESSAGE CUEING
Message cueing allows the user to skip through messages, without having to know the actual physical
location of each message. This operation is used during playback. In this mode, the messages are
skipped 512 times faster than in normal playback mode. This operation will stop when an EOM marker
is reached. Then, the internal address counter will be pointing to the next message.
ANALOG MODE
AUX IN DESCRIPTION
The AUX IN is an additional audio input to the Winbond I5216, such as from the microphone circuit in a
mobile phone “car kit.” This input has a nominal 700 mV p-p level at its minimum gain setting (0 dB).
(See Aux In Amplifier Gain Settings table on page 50.) Additional gain is available in 3 dB steps
2
(controlled by the I C serial interface) up to 9 dB.
INTERNAL TO THE DEVICE
Rb
CCOUP=0.1 µF
Ra
AUX
IN
Input
AUX IN
Input Amplifier
NOTE: fCUTOFF=
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1
2πRaCCOUP
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
I5216 ANALOG STRUCTURE (Left Half) DESCRIPTION
INP
AUX IN
Input Source MUX
AGC AMP
Σ
SUM1 MUX
( S1M0
S1M1 )
SUM1
2
FILTO
SUM1 MUX
1
(INS0)
SUM1
Summing
AMP
INP
ARRAY
DAC OUT
S1M1
S1M0
0
0
0
1
SUM1 MUX ONLY
1
0
INP Only
1
1
POWER DOWN
S1S1
S1S0
SOURCE
0
0
AGC AMP
0
1
ARRAY
AUX IN AMP
1
0
FILTO
1
1
N?C
2
( S1S0
)
S1S1
INSO
0
1
SOURCE
BOTH
SOURCE
DAC OUT (DAO)
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
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CFG1
CFG2
I5216 SERIES
Advanced Information
PRELIMINARY
I5216 ANALOG STRUCTURE (Right Half) DESCRIPTION
FLPD
CONDITION
0
Power Up
1
Power Down
FLD1
FLD0
SAMPLE
RATE
0
0
8 KHz
3.7 KHz
FLS0
0
1
6.4 KHz
2.9 KHz
1
0
5.3 KHz
2.5 KHz
1
1
4.0 KHz
1.8 KHz
S2M1
S2M0
0
0
SOURCE
0
1
AUX IN ONLY
1
0
FILTO ONLY
1
1
Power Down
BOTH
FILTER
PASS BAND
SOURCE
AMT0
Signal Output
0
SUM1
0
Uncompressed
1
ARRAY
1
Compressed
OSPD
Condition
CKD2
Condition
CKDV
Condition
0
Power Up Internal
Oscillator
0
Divide Master Clock
frequency by 1
0
Divide Master Clock
frequency by 1728
1
Power Down
Internal Oscillator
1
Divide Master Clock
frequency by 2
1
Divide Master Clock
frequency by 2560
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
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CFG1
CFG2
I5216 SERIES
Advanced Information
PRELIMINARY
AUTO MUTE AND AUTO GAIN FUNCTIONS
During playback, the signal passes through the Automatic Attenuator before it is filtered. The
Automatic Attenuator will attenuate all signals at the noise level in order to reduce the noise during
quiet pauses.
During record, low level input signals are brought up by the Auto Gain function if the configuration bit
D7 of CFG0 (AMT0) is set. This improves the signal to noise ratio of recorded low level input signals. If
the configuration bit CFG0<7> (AMT0) is set to ZERO, all input levels are recorded with the same gain
setting. The attack and release time of the Auto Gain and Auto Mute functions is set by the capacitor
on the ACAP pin. The AGC cannot be used if the Auto Gain or Auto Mute function is enabled.
Tattack ≈ 0,1504 x Vpeak
Trelease ≈ 6.58 x Vpeak
Expand
Compress
0
Gain
(dB)
12
Gain
(dB)
0
-12
0
@ Cattcap=4.7 µF
Vpp
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0
Vpp
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Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
VOLUME CONTROL DESCRIPTION
VLPD
VLS1 VLS0 SOURCE
CONDITION
0
Power Up
1
Power Down
VOL2
VOL1
VOL0
ATTENUATION
0
0
0
0 dB
0
0
1
4 dB
0
1
0
8 dB
0
0
DAC OUT
0
1
1
12 dB
0
1
SUM2
1
0
0
16 dB
1
0
SUM1
1
0
1
20 dB
1
1
INP
1
1
0
24 dB
1
1
1
28 dB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
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CFG0
CFG1
CFG2
I5216 SERIES
Advanced Information
PRELIMINARY
SPEAKER AND AUX OUT DESCRIPTION
OPS1
OPS0
0
0
SOURCE
OPA1
OPA0 SPKR DRIVE
VOL
0
0
Power Down
AUX OUT
Power Down
0
1
DAC OUT
0
1
3.6 VP-P @ 150 Ω
Power Down
1
0
FILTO
1
0
23.5 mWatt @ 8 Ω
Power Down
1
1
SUM2
1
1
Power Down
1 VP-P Max @ 5 KΩ
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
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CFG0
CFG1
CFG2
I5216 SERIES
Advanced Information
PRELIMINARY
MICROPHONE INPUTs
The microphone inputs transfer the voice signal to the on-chip AGC preamplifier, or directly to the
CODEC INPUT MUX, depending on the selected path. The AGC circuit has a range of 45 dB in order
to deliver a nominal 694 mV p-p into the storage array from a typical electret microphone output of 2 to
20 mV p-p. The input impedance is typically 10kΩ.
The MICBS pin provides a 2.2V bias voltage for the external microphone only when the AGC is
powered up. Using this regulated bias voltage results in less supply noise coupling into the MIC+ and
MIC- pins compared to the situation in which the external microphone is powered up through the power
supply. It also saves current during power down.
The ACAP pin provides the capacitor connection for setting the parameters of the microphone AGC
circuit. It should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because
the capacitor is also used in the playback mode for the AutoMute circuit or when signal compression is
chosen (AMT0 set). The AutoMute circuit reduces the amount of noise present in the output during
quiet pauses. Tying the ACAP pin to ground gives maximum gain. Tying it to VCCA gives minimum
gain for the AGC amplifier, but cancels the AutoMute function.
2.2V Voltage
2.2V
Voltage
reference
reference
MICBS
(AGPD)
MICROPHONE
CDI1
CDI0
0
0
INP
0
1
SUM2
1
0
MIC
1
1
No Input
AGPD
MIC+
CODEC ADC
INPUT
1
MIC IN
MIC IN
AGC
MIC -
CONDITION
0
Power Up
1
Power Down
1
(AGPD)
AGCCAP
IN
P
SU
M2
+
SU
IN
M2
P+
CODEC INPUT MUX
CDI0 2
CDI1
(
CODEC ADC IN
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
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CFG0
CFG1
CFG2
I5216 SERIES
Advanced Information
PRELIMINARY
DIGITAL MODE
In the Digital Mode, it is important to understand that each group of digital operations must be
preceded by the Digital Mode command (0XC0) and followed by the Exit Digital Mode command
(0X40). No delay is required after these commands. Note that after any of these operations is
completed, the device is powered down. Therefore, it will be required to issue the normal Power-Up
command (0X80h) with a power-up delay (Tpud) before any analog operations can be performed
following digital commands.
WRITING DATA
The Digital Write function allows the user to select a portion of the array to be used as digital memory.
The partition between analog and digital memory is left up to the user. A page can only be either Digital
or Analog, but not both. The minimum addressable block of memory in the digital mode is 1 block, or
64 bits, when reading or writing. The address sent to the device is the 11-bit row (or page) address
with the 5-bit scan (or block) address. However, one must send a Digital Erase before attempting to
change digital data on a page. This means that even when changing only one of the 32 blocks, all 32
will need to be rewritten to the page.
2
After the address is entered, the data is sent in one-byte packets followed by an I C acknowledge
generated by the chip. Data for each block is sent MSB first. The data transfer is ended when the
2
master generates an I C STOP condition. If only a partial block of data is sent before the STOP
condition, zero is “written” in the remaining bytes; that is, they are left at the erase level. An erased
page (row) will be read as all zeros. The device can buffer up to two blocks of data.
If the device is unable to accept more data due to the internal write process, the SCL line will be held
LOW indicating, to the master, to halt data transfer. If the device encounters an overflow condition, it
2
will respond by generating an interrupt condition and an I C Not Acknowledge signal after the last valid
byte of data. Once data transfer is terminated, the device needs up to two cycles (64 us) to complete
its internal write cycle before another command is sent. If an active command is sent before the
internal cycle is finished, the I5216 will hold SCL LOW until the current command is finished.
READING DATA
2
The Digital Read command utilizes the combined I C command format. That is, a command is sent to
the chip using the write data direction. Then the data direction is reversed by sending a repeated start
condition and the slave address with R/W set to one. After this, the slave device (I5216) begins to send
data to the master until the master generates a Not Acknowledge. If the part encounters an overflow
condition, the INT pin is pulled LOW. No other communication with the master is possible due to the
master generating ACK signals.
As with Digital Write, Digital Read can be done a “block” at a time. Thus, only 64 bits need to be read
in each Digital Read command sequence.
ERASING DATA
The Digital Erase command can only erase an entire page at a time. This means that the D0 or D1
command only needs to include the 11-bit page address; the 5-bit for block address are left at 00000.
Once a page has been erased, each block may be written separately, 64 bits at a time. But, if a block
has been previously written, then the entire page of 2048 bits must be erased in order to re-write (or
change) a block.
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Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
A sequence might look like:
- read the entire page
- store it in RAM
- change the desired bit(s)
- erase the page
- write the new data from RAM to the entire page
EXAMPLE COMMAND SEQUENCES
Graphical representations of these operations follow each description.
WRITE DIGITAL DATA: A single byte may be written to the Command Byte Register in order to
power up the device, start or stop Analog Record (if no address information is needed), or do a
Message Cueing function. For the normal digital addressed mode, the Registers are loaded as
follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
2
Host executes I C START.
Send Slave Address with R/W bit = “0” (Write).
Slave responds back with an ACK.
Wait for SCL HIGH.
Send Digital Mode command – 0X80h, 0XC0h
Slave responds with an ACK.
Wait for SCL HIGH.
Send Slave Address command – 0X80h
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends a byte to Slave - (Command Byte = 00C9h).
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends a byte to Slave - (High Address Byte).
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends a byte to Slave - (Low Address Byte).
Slave responds with an ACK
Wait for SCL HIGH.
Host sends a byte to Slave - (First 8 bits of digital information).
Slave responds with an ACK.
Wait for SCL HIGH.
Steps 19, 20 and 21 are repeated until last byte is sent and acknowledged.
2
Send Exit Digital Mode Command – 0X80h, 0X40hHost executes I C STOP.
S
SLAVE ADDRESS
W
A
Command
- 42
C9h
A
DATA
A
DATA
A
P
High
Addr.
Low
Addr.
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
READ DIGITAL DATA: For a normal digital read, the Registers are loaded as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
S
2
Host executes I C START.
Send Slave Address with R/W bit = “0” (Write).
Slave responds back with an ACK.
Wait for SCL HIGH.
Send Digital Mode command – 0X80h, 0XC9h
Slave responds with an ACK.
Wait for SCL HIGH
Host sends a byte to Slave - (Command Byte = E1).
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends a byte to Slave - (High Address Byte).
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends a byte to Slave - (Low Address Byte).
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends repeat START.
Host sends Slave Address with R/W bit = 1 (Reverses Data Direction).
Slave responds with an ACK.
Wait for SCL HIGH.
Slave sends a byte to Host - (First 8 bits of digital information).
Host responds with an ACK.
Wait for SCL HIGH.
Steps 20, 21 and 22 are repeated until last byte is sent and a NO ACK is returned.
Host sends Slave Address with R/W bit = 0 (Reverses Data Direction)
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends Exit Digital Mode command. – 0X40
Slave responds with an ACK.
Wait for SCL HIGH
2
Host executes I C STOP.
SLAVE ADDRESS
W
A
E1
Command
A
DATA
High
- 43
A
DATA
Addr.
Low
N
P
Addr.
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
ERASE DIGITAL DATA: To erase digital information the following is done:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
2
Host executes I C START.
Send Slave Address with R/W bit = “0” (Write).
Slave responds back with an ACK.
Wait for SCL HIGH.
Send Digital Mode command – 0X80h, 0XC0h
Slave responds with an ACK.
Wait for SCL HIGH.
Send Slave Address command – 0X80h
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends a Digital Erase command to Slave - (Command Byte = 0XD1h).
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends a byte to Slave - (High Address Byte = 0000h).
Slave responds with an ACK.
Wait for SCL HIGH.
Host sends a byte to Slave - (Low Address Byte = 0XA0h). Erase row 5 in this example.
Slave responds with an ACK
Wait for SCL HIGH.
2
Host executes I C STOP.
Host waits for RAC\ to go LOW and then back HIGH.
2
Host executes I C START.
Send Exit Digital Mode Command – 0X80h, 0X40h
Slave responds with an ACK.
Wait for SCL HIGH
2
Host executes I C STOP.
Erase starts on falling
edge of Slave
acknowledge
S
SLAVE ADDRESS
W
A
D1h
Command Byte
"N" RAC cycles
Last erased row
Note 3.
Note 4.
A
DATA
A
High Addr. Byte
S
DATA
A
P
Note 2
Low Addr. Byte
SLAVE ADDRESS
W
A
80h
A
P
Command Byte
- 44
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
Notes:
1. Erase operations must be addressed on a Row boundary. The 5 LSB bits of the Low
Address Byte will be ignored.
2
2. I C bus is released while erase proceeds. Other devices may use the bus until it is time
to execute the STOP command that causes the end of the Erase operation.
3. Host processor must count RAC cycles to determine where the chip is in the erase
process, one row per RAC cycle. RAC pulses LOW for 0.25 microsecond at the end of
each erased row. The erase of the “next” row begins with the rising edge of RAC. See
the Digital Erase RAC timing diagram on page 46.
4. When the erase of the last desired row begins, the following STOP command (Command
Byte = 80 hex) must be issued. This command must be completely given, including
receiving the ACK from the Slave before the RAC pin goes HIGH .25 microseconds before
the end of the row.
PIN DETAILS
DIGITAL I/O PINS:
SCL (SERIAL CLOCK LINE)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor to
Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged over
the Serial Data Line.
SDA (SERIAL DATA LINE)
2
The Serial Data Line carries the data between devices on the I C interface. Data must be valid on this
line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is a bidirectional line requiring a pull-up resistor to Vcc.
RAC (ROW ADDRESS CLOCK)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency
the duration of this period is 256 ms. there are 1888 pages of memory in the Winbond I5216 device.
RAC stays HIGH for 248 ms and goes LOW for the remaining 8 ms before it reaches the end of the
page.
1 ROW
RAC Waveform
During 8 KHz Operation
256 msec
TRAC
- 45
8 msec
TRACLO
Publication Release Date: November 30, 2001
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I5216 SERIES
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PRELIMINARY
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing
mode. See the Timing Parameters table on page 55 for RAC timing information at other sample rates.
When a record command is first initiated, the RAC pin remains HIGH for an extra TRACLO period in
order to load sample and hold circuits internal to the device. The RAC pin can be used for message
management techniques.
1 ROW
RAC Waveform
During Message Cueing
500 usec
TRAC
15.6 us
TRACLO
RAC Waveform
During Digital Erase
1.25 µsec
.25 µsec
INT (Interrupt)
INT is an open drain output pin. The Winbond I5216 Interrupt pin goes LOW and stays LOW when an
Overflow (OVF) or End of Message (EOM) marker is detected. Each operation that ends in an EOM or
OVF generates an interrupt, including the message cueing cycles. The interrupt is cleared by a READ
STATUS instruction that gives a status byte out the SDA line.
MCLK (Master Clock Input)
The Master clock input for the Winbond I5216 product has an internal pull-down device. Normally, the
Winbond I5216 ChipCorder section is operated at one of four internal rates selected for its internal
oscillator by the Sample Rate Select bits. If the internal oscillator is powered down (configuration bit
OSPD set to ONE), the device is clocked through the MCLK pin as shown in the section I5216 Analog
Structure (right half) description on page 36.
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Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
Master Clock Input Table for ChipCorder Section
FMCLK
FLD1
FLD0
CKD2
CKDV
Sample Rate
Filter Knee
13.824 MHz
0
0
0
0
8.0 kHz
3.7 kHz
20.48 MHz
0
0
0
1
8.0 kHz
3.7 kHz
27.648 MHz
0
0
1
0
8.0 kHz
3.7 kHz
40.96 MHz
0
0
1
1
8.0 kHz
3.7 kHz
13.824 MHz
0
1
0
0
6.4 kHz
2.9 kHz
20.48 MHz
0
1
0
1
6.4 kHz
2.9 kHz
27.648 MHz
0
1
1
0
6.4 kHz
2.9 kHz
40.96 MHz
0
1
1
1
6.4 kHz
2.9 kHz
13.824 MHz
1
0
0
0
5.3 kHz
2.5 kHz
20.48 MHz
1
0
0
1
5.3 kHz
2.5 kHz
27.648 MHz
1
0
1
0
5.3 kHz
2.5 kHz
40.96 MHz
1
0
1
1
5.3 kHz
2.5 kHz
13.824 MHz
1
1
0
0
4.0 kHz
1.8 kHz
20.48 MHz
1
1
0
1
4.0 kHz
1.8 kHz
27.648 MHz
1
1
1
0
4.0 kHz
1.8 kHz
40.96 MHz
1
1
1
1
4.0 kHz
1.8 kHz
Because the anti-aliasing and smoothing filters track the Sample Rate Select bits, one must, for
optimum performance, maintain the external clock at one of the four possible frequencies shown in the
table for Analog Structure (Right Half) description on page 36 AND set the Sample Rate Configuration
bits to one of the four values in order to properly set the filters to their correct cutoff frequency as
described in Analog Structure (Right Half) description on page 36. The duty cycle on the input clock is
not critical when CKD2 is set to ONE, as the clock is immediately divided by two (internally). If the
MCLK is not used, this input should be connected to VSSD.
A0, A1 (Address Pins)
These two pins are normally strapped for the desired address that the Winbond I5216 will have on the
2
I C serial interface. If there are four of these devices on the bus, then each must be strapped
differently in order to allow the master device to address them individually. The possible addresses
range from 80h to 87h, depending upon whether the device is being written to, or read from, by the
host.
The Winbond I5216 has a 7-bit slave address of which only A0 and A1 are pin programmable. The
eighth bit (LSB) is the R/W bit. Thus, the address will be 1000 0xy0 or 1000 0xy1
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Publication Release Date: November 30, 2001
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I5216 SERIES
Advanced Information
PRELIMINARY
ANALOG I/O PINS
MIC+, MIC-
(Microphone Input +/-)
The microphone input transfers the voice signal to the on-chip AGC preamplifier or directly to the
CODEC A/D INPUT MUX, depending on the selected path. The AGC circuit has a range of 45 dB in
order to deliver a nominal 694 mV p-p into the storage array from a typical electric microphone output
of 2 to 20 mV p-p. The input impedance is typically 20 kΩ differential and 13.3 kΩ differential when the
CODEC INPUT MUX MICIN path is selected.
MICROPHONE INPUT
1.5kΩ
2.2V Voltage
reference
MICBS
.1µF
1
MIC+
Electret Microphone
WM-54B Panasonic
(AGPD)
Ra=10kΩ
MIC IN
AGC
MIC -
1
(AGPD)
4.7µF
SUM2+
INP+
INP-
1.5kΩ
SUM2-
AGCCAP
.1µF
CODEC INPUT MUX
2
(CDI0
CDI1 )
Rc=40kΩ
CODEC ADC IN
f
− 3 dB
=
1
2 ⋅ π ⋅ Ra ⋅ CCOUPLE
ACAP (AGC Capacitor)
This pin provides the capacitor connection for setting the parameters of the microphone AGC circuit. It
should have a 4.7 µF capacitor connected to ground. It cannot be left floating. This is because the
capacitor is also used in the playback mode for the AutoMute circuit or when signal compression is
chosen (AMT0 is set to ONE). This circuit reduces the amount of noise present in the output during
quiet pauses. Tying this pin to ground gives maximum gain. Tying it to VCCA gives minimum gain for the
AGC amplifier, but cancels the AutoMute function.
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I5216 SERIES
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PRELIMINARY
SP +, SP-
(Speaker +/-)
This is the speaker differential output circuit. It is designed to drive an 8Ω speaker connected across
the speaker pins, up to a maximum of 23.5 mW RMS power. This stage has two selectable gains, 1.32
and 1.6, which can be chosen through the configuration registers. These pins are biased to approximately 1.2 VDC and, if used single-ended, must be capacitively coupled to their load. Do NOT
ground the unused pin.
AUX OUT (Auxiliary Output)
The AUX OUT is an additional audio output pin to be used, for example, to drive the speaker circuit in
a “car kit.” It drives a minimum load of 5 kΩ and up to a maximum of 1 V p-p. The AC signal is
superimposed on approximately 1.2 VDC bias and must be capacitively coupled to the load.
OPS1
OPS0
0
0
SOURCE
OPA1
OPA0 SPKR DRIVE
AUX OUT
VOL
0
0
Power Down
Power Down
Power Down
0
1
DAC OUT
0
1
3.6 VP-P @ 150 Ω
1
0
FILTO
1
0
23.5 mWatt @ 8 Ω
Power Down
1
1
SUM2
1
1
Power Down
1 VP-P Max @ 5 KΩ
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CIG2
CIG1
CIG0
AXG1
AXG0
AXPD
INS0
OSPD
AMT0
CDI1
CDI0
OPS1
OPS0
OPA1
OPA0
VLPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0
VOL2
VOL1
VOL0
S1S1
S1S0
S1M1
S1M0
S2M1
S2M0
FLS0
FLD1
FLD0
FLPD
AGPD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
X
X
CKD2
COG2
COG1
COG0
CKDV
MUTE
HPF0
HSR0
I2S0
LAW1
LAW0
DAPD
ADPD
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Publication Release Date: November 30, 2001
Revision A1
CFG0
CFG1
CFG2
I5216 SERIES
Advanced Information
PRELIMINARY
AUX IN (Auxiliary Input)
The AUX IN is an additional audio input to the Winbond I5216, such as from the microphone circuit in a
mobile phone “car kit.” This input has a nominal 694 mV p-p level at its minimum gain setting (0 dB).
(See Aux In Amplifier Gain Settings Table below). Additional gain is available in 3 dB steps (controlled
2
by the I C interface) up to 9 dB.
AUX IN INPUT MODES
Internal to the device
Rb
AUX IN
Input
AUX IN
Input Amplifier
Gain
Setting
00
01
10
11
Resistor Ratio
(Rb/Ra)
40.1 / 40.1
47.0 / 33.2
53.5 / 26.7
59.2 / 21
AXPD
0
1
Condition
Power Up
Power Down
Gain
1.0
1.414
2.0
2.82
(1)
Gain
(dB)
0
3
6
9
AUX IN AMPLIFIER GAIN SETTINGS
0TLP Input
(2)
VP-P
0.694
0.491
0.347
0.245
CFG0
AXG1
0
0
1
1
Gain
AXG0
0
1
0
1
(1)
1.00
1.41
2.00
2.82
Array
In/Out VP-P
Speaker
(3)
Out VP-P
0.694
0.694
0.694
0.694
0.694
0.694
0.694
0.694
1.
Gain from AUX IN to ARRAY IN
2.
0TLP Input is the reference Transmission Level Point that is used for testing. This level is typically 3
dB below clipping
3.
Differential
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Publication Release Date: November 30, 2001
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I5216 SERIES
Advanced Information
PRELIMINARY
POWER AND GROUND PINS
VCCA, VCCD (Voltage Inputs)
To minimize noise, the analog and digital circuits in the Winbond I5216 device use separate power
busses. These +3 V busses lead to separate pins. Tie the VCCD pins together as close as possible, and
decouple both supplies as near to the package as possible.
VSSA, VSSD (Ground Inputs)
The Winbond I5216 series utilizes separate analog and digital ground busses. The analog ground
(VSSA) pins should be tied together as close to the package as possible, and connected through a lowimpedance path to power supply ground. The digital ground (VSSD) pin should be connected through a
separate low impedance path to power supply ground. These ground paths should be large enough to
ensure that the impedance between the VSSA pins and the VSSD pin is less than 3Ω. The backside of
the die is connected to VSSD through the substrate resistance. In a chip-on-board design, the die attach
area must be connected to VSSD.
NC (No Connect)
These pins should not be connected to the board at any time. Connection of these pins to any signal,
ground or VCC, may result in incorrect device behavior or cause damage to the device.
- 51 -
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
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PRELIMINARY
SAMPLE PC LAYOUT FOR PDIP
The PDIP package is illustrated from the top. PC board traces and the three chip capacitors are on the
bottom side of the board.
Note 2
1
C1
V
C
C
D
C2
MCLK
V
S
S
D
Note 3
Note 1
VSSA
(Digital Ground)
C1=C2=C3=0.1 uF chip Capacitors
Note 1: VSSD traces should be kept
separated back to the VSS supply feed
point.
Note 2: VCCD traces should be kept
separated back to the VCC supply feed
point.
Note 3: The Digital and Analog grounds
tie together at the power supply. The
VCCA and VCCD supplies will also need
filter capacitors (typ. 50 to 100 uF).
C3
To
VCCA
Analog Ground
- 52
Note 3
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ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Packaged Parts) (1)
Condition
Value
0
Junction temperature
150 C
Storage temperature range
-65 C to +150 C
Voltage Applied to any pin
(VSS - 0.3V) to (VCC + 0.3V)
Voltage applied to any pin (Input current limited to +/-20 mA)
(VSS – 1.0V) to (VCC + 1.0V)
Lead temperature (soldering
300 C
0
0
0
– 10 seconds)
VCC - VSS
-0.3V to +5.5V
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
ABSOLUTE MAXIMUM RATINGS (Die) (1)
Condition
Value
0
Junction temperature
150 C
Storage temperature range
-65 C to +150 C
Voltage Applied to any pad
(VSS - 0.3V) to (VCC + 0.3V)
VCC - VSS
-0.3V to +5.5V
0
0
1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute
maximum ratings may affect device reliability. Functional operation is not implied at these conditions.
OPERATING CONDITIONS (Packaged Parts)
Condition
Value
Commercial operating temperature range
(1)
0
0 C to +70 C
(1)
-20 C to +70 C
(1)
-40 C to +85 C
Extended operating temperature
Industrial operating temperature
Supply voltage (VCC)
(2)
Ground voltage (VSS)
1.
Case temperature
0
0
0
0
0
+2.7V to +3.3V
(3)
0V
2.
VCC = VCCA = VCCD
- 53
3.
VSS = VSSA = VSSD
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Revision A1
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PRELIMINARY
OPERATING CONDITIONS (Die)
Condition
Value
(1)
0
Die operating temperature range
Supply voltage (VCC)
Ground voltage (VSS)
1.
0 C to +50 C
(2)
+2.7V to +3.3V
(3)
Case temperature
0
0V
2.
VCC = VCCA = VCCD
3.
VSS = VSSA = VSSD
General Parameters
Min
(2)
Typ
(1)
Max
(2)
Symbol
Parameters
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
SCL, SDA, SDIO Output Low
Voltage
0.4
V
IOL = 3 mA
VOL1
RAC, INT Output Low Voltage
0.4
V
IOL = 1 mA
VOH
Output High Voltage
V
IOL = -10 µA
ICC
VCC Current (Operating)
VCC x
0.2
VCC x 0.8
Units
Conditions
V
V
VCC – 0.4
(3)
- Playback & A/D + D/A
30
50
mA
No Load
- Record & A/D + D/A
36
56
mA
No Load
- CODEC A/D + D/A
20
30
mA
No Load
ISB
VCC Current (Standby)
1
10
µA
(3)
IIL
Input Leakage Current
+/-1
µA
(3)
(3)
1. Typical values: TA = 25°C and Vcc = 3.0 V.
2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
3. VCCA and VCCD summed together.
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Publication Release Date: November 30, 2001
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PRELIMINARY
TIMING PARAMETERS
Symbol
Parameters
FS
Sampling Frequency
FCF
TREC
TPLAY
TPUD
TSTOP OR PAUSE
Min
(2)
Typ
(1)
Max
(2)
Units
Conditions
8.0
kHz
(5)
6.4
kHz
(5)
5.3
kHz
(5)
4.0
kHz
(5)
8.0 kHz (sample rate)
3.7
kHz
Knee Point
(3)(7)
6.4 kHz (sample rate)
2.9
kHz
Knee Point
(3)(7)
5.3 kHz (sample rate)
2.5
kHz
Knee Point
(3)(7)
4.0 kHz (sample rate)
1.8
kHz
Knee Point
(3)(7)
8.0 kHz (sample rate)
8.05
min
(6)
6.4 kHz (sample rate)
10.06
min
(6)
5.3 kHz (sample rate)
12.15
min
(6)
4.0 kHz (sample rate)
16.1
min
(6)
8.0 kHz (sample rate)
8.05
min
(6)
6.4 kHz (sample rate)
10.06
min
(6)
5.3 kHz (sample rate)
12.15
min
(6)
4.0 kHz (sample rate)
16.1
min
(6)
8.0 kHz (sample rate)
1
msec
6.4 kHz (sample rate)
1
msec
5.3 kHz (sample rate)
1
msec
4.0 kHz (sample rate)
1
msec
8.0 kHz (sample rate)
32
msec
6.4 kHz (sample rate)
40
msec
5.3 kHz (sample rate)
48
msec
4.0 kHz (sample rate)
64
msec
Filter Knee
Record Duration
Playback Duration
Power-Up Delay
Stop or Pause
Record or Play
- 55
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Advanced Information
PRELIMINARY
TIMING PARAMETERS (CONT’D)
Symbol
Parameters
TRAC
RAC Clock Period
TRACLO
TRACM
TRACML
Min
Typ
(1)
Max
(2)
Units
Conditions
8.0 kHz (sample rate)
256
msec
(9)
6.4 kHz (sample rate)
320
msec
(9)
5.3 kHz (sample rate)
386
msec
(9)
4.0 kHz (sample rate)
512
msec
(9)
8.0 kHz (sample rate)
8
msec
6.4 kHz (sample rate)
10
msec
5.3 kHz (sample rate)
12.1
msec
4.0 kHz (sample rate)
16
msec
8.0 kHz (sample rate)
500
msec
6.4 kHz (sample rate)
625
msec
5.3 kHz (sample rate)
750
msec
4.0 kHz (sample rate)
1000
msec
15.6
msec
19.5
msec
23.4
msec
31.2
msec
RAC Clock Low Time
RAC Clock Period
Message Cueing Mode
in
RAC Clock Low Time in
Message Cueing Mode
8.0 kHz (sample rate)
6.4 kHz (sample rate)
5.3 kHz (sample rate)
4.0 kHz (sample rate)
THD
(2)
Total Harmonic Distortion
AUX IN to ARRAY,
1
2
ARRAY to SPKR
1
2
- 56
%
%
@1 KHz at 0TLP,
sample rate = 5.3
KHz
Publication Release Date: November 30, 2001
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Advanced Information
PRELIMINARY
ANALOG PARAMETERS
MICROPHONE INPUT (14)
Symbol
Parameters
VMIC+/-
MIC +/- Input Voltage
VMIC (0TLP)
MIC +/- input reference
transmission level point
(0TLP)
AMIC (GT)
MIC +/- Gain Tracking
RMIC
Microphone input resistance
AAGC
Microphone AGC Amplifier
Range
VMICBS
Microphone Bias Voltage
RMICBS
MICBS Output Resistance
Min
(2)
Typ
( 1)(14)
Max
(2)
Units
Conditions
mV
Peak-to-Peak
(4)(8)
208
mV
Peak-to-Peak
(4)(10)
+/-0.1
dB
1 kHz, +3 to –40 dB
0TLP Input
10
kΩ
MIC- and MIC+ pins
dB
Over 3-300 mV Range
2.2
V
IMICBS = 0.0 mA
700
Ω
300
6
40
AUX IN (14)
Symbol
Parameters
Min
(2)
Typ
Max
(2)
Units
Conditions
(1)(14)
VAUX IN
AUX IN Input Voltage
VAUX IN (0TLP)
AUX IN (0TLP) Input
Voltage
AAUX IN (GA)
AUX IN Gain Accuracy
AAUX IN (GT)
AUX IN Gain Tracking
RAUX IN
AUX IN Input Resistance
1.0
V
Peak-to-Peak (0 dB
gain setting)
mV
Peak-to-Peak (0 dB
gain setting)
dB
(11)
+/-0.1
dB
1000 Hz, +3 to –45 dB
0TLP Input, 0 dB setting
10 to 100
kΩ
Depending on AUX IN
Gain
694.2
-0.5
- 57
+0.5
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PRELIMINARY
SPEAKER OUTPUTS (14)
(2)
Symbol
Parameters
Min
VSPHG
SP+/- Output Voltage (High
Gain Setting)
RSPLG
SP+/- Output Load Imp.
(Low Gain)
8
RSPHG
SP+/- Output Load Imp.
(High Gain)
70
CSP
SP+/- Output Load Cap.
VSPAG
SP+/- Output Bias Voltage
(Analog Ground)
VSPDCO
Speaker Output DC Offset
PSRR
Power Supply Rejection
Ratio
FR
Frequency Response (3003400 Hz)
-0.25
POUTLG
Power Output (Low Gain
Setting)
23.5
Typ
(1)(14)
Max
(2)
3.6
150
100
1.2
Units
Conditions
V
Peak-to-Peak,
differential load = 150Ω,
OPA1, OPA0 = 01
Ω
OPA1, OPA0 = 10
Ω
OPA1, OPA0 = 01
pF
VDC
+/-100
-55
+0.25
mV
DC
With CODEC D/A IN to
Speaker.
dB
Measured with a 1 kHz,
100 map sine wave
input at VCC and VCC
pins
dB
With 0TLP input to AUX
(12)
IN, 6 dB setting
mW
RMS
Differential load at 8Ω
Units
Conditions
AUX OUT (14)
Symbol
Parameters
VAUX OUT
AUX OUT – Maximum
Output Swing
RL
Minimum Load Impedance
CL
Maximum Load
Capacitance
VBIAS
AUX OUT
Min
(2)
Typ
(1)(14)
Max
(2)
1.0
5
5kΩ Load
KΩ
100
1.2
- 58
V
pF
VDC
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PRELIMINARY
VOLUME CONTROL (14)
Symbol
Parameters
AOUT
Output Gain
Absolute Gain
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Min
(2)
Typ
(1)(14)
Max
(2)
-28 to 0
-0.5
+0.5
Units
Conditions
dB
8 steps of 4 dB,
referenced to output
dB
AUX IN 1.0 kHz 0TLP,
6 dB gain setting
measured differentially
at SP+/-
Typical values: TA = 25°C and Vcc = 3.0V.
All min/max limits are guaranteed by Winbond via electrical testing or characterization.
Not all specifications are 100 percent tested.
Low-frequency cut off depends upon the value of external capacitors (see Pin
Descriptions).
Differential input mode. Nominal differential input is 208 mV p-p. (0TLP)
Sampling frequency can vary as much as –6/+4 percent over the industrial temperature
and voltage ranges. For greater stability, an external clock can be utilized (see Pin
Descriptions).
Playback and Record Duration can vary as much as –6/+4 percent over the industrial
temperature and voltage ranges. For greater stability, an external clock can be utilized
(see Pin Descriptions).
Filter specification applies to the low pass filter.
For optimal signal quality, this maximum limit is recommended.
When a record command is sent, TRAC = TRAC + TRACLO on the first page addressed.
The maximum signal level at any input is defined as 3.17 dB higher than the reference
transmission level point. (0TLP) This is the point where signal clipping may begin.
Measured at 0TLP point for each gain setting. See AUX IN table.
0TLP is the reference test level through inputs and outputs. See AUX IN table.
Referenced to 0TLP input at 1 kHz, measured over 300 to 3,400 Hz bandwidth.
For die, only typical values are applicable.
- 59
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PRELIMINARY
I2C INTERFACE TIMING
STANDARD-MODE
PARAMETER
FAST-MODE
SYMBOL
MIN.
MAX.
MIN.
MAX.
UNIT
fSCL
0
100
0
400
kHz
tHD; STA
4.0
-
0.6
-
ns
LOW period of the SCL clock
tLOW
4.7
-
1.3
-
ns
HIGH period of the SCL clock
tHIGH
4.0
-
0.6
-
ns
tSU; STA
4.7
-
0.6
-
ns
tSU; DAT
250
-
100
SCL clock frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
Set-up time
condition
for
a
repeated
START
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
-
tr
1000
(1)
-
ns
20 + 0.1Cb
(2)
300
ns
20 + 0.1Cb
(2)
300
ns
tf
-
300
tSU; STO
4.0
-
0.6
-
ns
Bus-free time between a STOP and
START condition
tBUF
4.7
-
1.3
-
ns
Capacitive load for each bus line
Cb
-
400
-
400
pF
Noise margin at the LOW level for each
connected device (including hysteresis)
VnL
0.1 VDD
-
0.1 VDD
-
V
Noise margin at the HIGH level for each
connected device (including hysteresis)
VnH
0.2 VDD
-
0.2 VDD
-
V
Set-up time for STOP condition
1.
2
2
A Fast-mode I C-interface device can be used in a Standard-mode I C-interface system, but the
requirement tSU;DAT > 250 ns must then be met. This will automatically be the case if the device does
not stretch the LOW period of the SCL signal.
If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line; tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode
2
I C -interface specification) before the SCL line is released.
2.
Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times
are allowed.
- 60
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PRELIMINARY
CODEC PARAMETERS
The internal CODEC meets the specification of the ITU-T G.714 recommendation in 8 kHz sampling
mode. This specification is verified, using the MIC+/- and SPEAKER+/- pins as analog input and
output.
The CODEC µ/A-Law Compander meets the specification of the ITU-T G.711 µ/A-Law companding
recommendation
Symbol
Parameters
LABS
Absolute level
TXMAX
Max. Transmit level
fch1
Min
Units
Conditions
Vrms
0 dBm0 = -2.5dBm @ 600 Ω
2
Vpp
Mic+/Mic- differential
High pass filter cut-off
frequency
300
Hz
@WS=8kHz,
MCLK=13.824MHz
fcl1
Low pass filter cut-off
frequency
3400
Hz
@WS=8kHz,
MCLK=13.824MHz
fcl2
Low pass filter cut-off
frequency
4686
5037
5100
Hz
@ WS=44.1kHz – 48kHz,
MCLK=20.48MHz
∆fMCLK
Master clock frequency
accuracy
-500
0
+500
ppm
DMCLK
Master Clock Duty Cycle
48
50
52
%
- 61
Typ
Max
Publication Release Date: November 30, 2001
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PRELIMINARY
TIMING DIAGRAMS
I2C TIMING DIAGRAM
STOP
START
t
t
t
f
r
SU;DAT
SDA
SCL
t
t
f
HIGH
t
t
LOW
SU;STO
t
SCLK
PLAYBACK AND STOP CYCLE
tSTOP
tSTART
SDA
PLAY AT ADDR
STOP
SCL
DATA CLOCK PULSES
STOP
AUX IN
AUX OUT
- 62
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PRELIMINARY
EXAMPLE OF POWER UP COMMAND
- 63
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PRELIMINARY
I2S TIMING DIAGRAMS
- 64
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PRELIMINARY
I2S PARAMETERS (all values in nano seconds)
Parameter
Bit Clock period T
Transmitter
Receiver
Lower Limit
Upper Limit
Lower Limit
Upper Limit
MIN
MIN
MIN
MIN
MAX
MAX
325
MAX
114
114
Low time tLC
114
114
Rise time tRC
MAX
325
High time tHC
49
Delay tdtr
Hold time thtr
NOTES
260
100
Set-up time tsr
65
Hold time thr
0
PCM TIMING DIAGRAMS
- 65
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PRELIMINARY
PCM TIMING DIAGRAMS (CONT’D)
- 66
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PRELIMINARY
PCM TIMING DIAGRAMS (CON’TD)
- 67
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PRELIMINARY
PCM PARAMETERS
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Bit Clock Frequency
1/TSCK
SCK
64
---
3072
kHz
Bit Clock Duty Cycle
DC
SCK
---
50
---
%
Word Sync. Frequency
1/TWSl
WS @ low rate
---
8000
---
Hertz
Word Sync. Frequency
1/TWSh
WS @ high rate
44.1
---
48
kHz
TIR
SCK,SDI,SDIO,WS
---
---
50
nsec
TIF
SCK,SDI,SDIO,WS
---
---
50
nsec
THLD
SCK low to WS
low
50
---
---
nsec
TXS
SCK to WS
20
---
---
nsec
TSX
WS to SCK
100
---
---
nsec
TRS
SCK to WS
20
---
---
nsec
TSR
WS to SCK
100
---
---
nsec
Setup Time for SDI valid
TSTSDI
---
20
---
---
nsec
Hold Time for SDI valid
THDSDI
---
50
---
---
nsec
Output Delay Time for
SDIO valid
TDV
SCK to SDIO
10
---
120
nsec
Output Delay Time for
SDIO High Impedance
TDHI
SCK to SDIO
10
---
120
nsec
Rise Time
Fall Time
nd
Hold Time for 2
of Bit clock
cycle
Transmit Sync. Timing
Receive Sync. Timing
- 68
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I2C SERIAL INTERFACE TECHNICAL INFORMATION
CHARACTERISTICS OF THE I2C SERIAL INTERFACE
2
The I C interface is for bi-directional, two-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a
positive supply via a pull-up resistor. Data transfer may be initiated only when the interface bus is not
busy.
BIT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable
during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted as
a control signal.
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the interface bus is not busy. A HIGH-to-LOW transition
of the data line while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition
of the data line while the clock is HIGH is defined as the stop condition (P)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
2
Bit transfer on the I C-bus
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Definition of START and STOP conditions
- 69
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PRELIMINARY
SYSTEM CONFIGURATION
A device generating a message is a ‘transmitter’; a device receiving a message is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices that are controlled by the master are
the ‘slaves’.
ACKNOWLEDGE
The number of data bytes transferred between the start and stop conditions from transmitter to
receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is
a HIGH level signal put on the interface bus by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. In addition, a master receiver must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so
that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (setup and hold times must be taken into consideration). A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the last byte that has been clocked out of the
slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a
stop condition.
LCD
DRIVER
MICRO CONTROLLER
STATIC
RAM OR
EEPROM
SDA
SCL
GATE
ARRAY
ISD 5116
MBC645
2
Example of an I C-bus configuration using two microcontrollers
Data output by
DATA OUTPUT
transmitter
BY TRANSMITTER
Not acknowlwedge
not acknowledge
Data output by
DATA OUTPUT
receiver
BY RECEIVER
acknowledge
Not acknowlwedge
SCL from Master
SCL FROM
MASTER
1
7
2
2
8
8
9
9
S
clockpulse
pulse
Clock
forfor
acknowledgement
acknowledgement
START
condition
Start condition
MBC602
2
Acknowledge on the I C-bus
Acknowledge on the I 2C-bus
- 70
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PRELIMINARY
I2C PROTOCOL
2
Since the I C protocol allows multiple devices on the bus, each device must have an address. This
address is known as a “Slave Address”. A Slave Address consists of 7 bits, followed by a single bit that
indicates the direction of data flow. This single bit is 1 for a Write cycle, which indicates the data is
being sent from the current bus master to the device being addressed. This single bit is a 0 for a Read
cycle, which indicates that the data is being sent from the device being addressed to the current bus
master.
2
Before any data is transmitted on the I C interface, the current bus master must address the slave it
st
wishes to transfer data to or from. The Slave Address is always sent out as the 1 byte following the
Start Condition sequence. An example of a Master transmitting an address to a ISD5216 slave is
shown below. In this case, the Master is writing data to the slave and the R/W bit is “0”, i.e. a Write
cycle. All the bits transferred are from the Master to the Slave, except for the indicated Acknowledge
bits.
Master Transmits to Slave Receiver (Write) Mode
acknowledgement
from slave
S
SLAVE ADDRESS
Start Bit
W A
acknowledgement
from slave
COMMAND BYTE
A
acknowledgement
from slave
High ADDR. BYTE
A
acknowledgement
from slave
Low ADDR. BYTE
A
P
Stop Bit
R/W
A common procedure in the ISD5116 is the reading of the Status Bytes. The Read Status condition in
the ISD5216 is triggered when the Master addresses the chip with its proper Slave Address,
immediately followed by the R/W bit set to a “0” and without the Command Byte being sent. This is an
example of the Master sending to the Slave, immediately followed by the Slave sending data back to
the Master. The “N” not-acknowledge cycle from the Master ends the transfer of data from the Slave.
Master Reads from Slave immediately after first byte (Read Mode)
acknowledgement
from slave
From Slave
S
SL AVE ADDRESS
R
A
From Slave
STATUS W ORD
A
High ADDR. BYTE
From Slave
A
Low ADDR BYTE
N
P
From Master
Start Bit
From
Master
R/W
From
Master
acknowledgement
from Master
- 71
acknowledgement
from Master
Stop Bit
From
Master
not-acknowledged
from Master
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PRELIMINARY
Another common operation in the ISD5216 is the reading of digital data from the chip’s memory array
2
at a specific address. This requires the I C interface Master to first send an address to the ISD5116
2
Slave device, and then receive data from the Slave in a single I C operation. To accomplish this, the
data direction R/W bit must be changed in the middle of the command. The following example shows
the Master sending the Slave address, then sending a Command Byte and 2 bytes of address data to
the ISD5216, and then immediately changing the data direction and reading some number of bytes
from the chip’s digital array. An unlimited number of bytes can be read in this operation. The “N” notacknowledge cycle from the Master forces the end of the data transfer from the Slave. The following
example details the transfer explained in the section on page 41 of this datasheet.
Master Reads from the Slave after setting data address in Slave
(Write data address, READ Data)
acknowledgement
from slave
S
SLAVE ADDRESS
Start Bit
From
Master
W A
acknowledgement
from slave
COMMAND BYTE
A
acknowledgement
from slave
High ADDR. BYTE
A
acknowledgement
from slave
Low ADDR. BYTE
A
R/W
From
Master
acknowledgement
from slave
From Slave
S
SLAVE ADDRESS
R
A
8 BITS of DATA
From Slave
A
8 BITS of DATA
From Slave
A
8 BITS of DATA
N
P
From Master
Start Bit
From
Master
R/W
From
Master
acknowledgement
from Master
acknowledgement
from Master
Stop Bit
From
Master
not-acknowled
from Master
- 72
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I2S SERIAL INTERFACE TECHNICAL INFORMATION
2
THE I BUS
As shown in the following figure, the bus has three lines:
• continuous serial clock (SCK)
• word select (WS)
• serial data (SD)and the device generating SCK and WS is the master.
Simple System Configurations and Basic Interface Timing
SERIAL DATA
Serial data is transmitted in two’s complement with the MSB first. The MSB is transmitted first because
the transmitter and receiver may have different word lengths. It isn’t necessary for the transmitter to
know how many bits the receiver can handle, nor does the receiver need to know how many bits are
being transmitted.
When the system word length is greater than the transmitter word length, the word is truncated (least
significant data bits are set to ‘0’) for data transmission. If the receiver is sent more bits than its word
length, the bits after the LSB are ignored. On the other hand, if the receiver is sent fewer bits than its
word length, the missing bits are set to zero internally. And so, the MSB has a fixed position, whereas
the position of the LSB depends on the word length. The transmitter always sends the MSB of the next
word one clock period after the WS changes.
- 73
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Serial data sent by the transmitter may be synchronized with either the trailing (HIGH-to-LOW) or the
leading (LOW-to-HIGH) edge of the clock signal. However, the serial data must be latched into the
receiver on the leading edge of the serial clock signal, and so there are some restrictions when
transmitting data that is synchronized with the leading edge (see figure below ).
Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able
to match the performance of the transmitter.
- 74
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WORD SELECT
The word select line indicates the channel being transmitted:
• WS = 0; channel 1 (left)
• WS = 1; channel 2 (right)
WS may change either on a trailing or leading edge of the serial clock, but it doesn’t need to be
symmetrical. In the slave, this signal is latched on the leading edge of the clock signal. The WS line
changes one clock period before the MSB is transmitted. This allows the slave transmitter to derive
synchronous timing of the serial data that will be set up for transmission. Furthermore, it enables the
2
receiver to store the previous word and clear the input for the next word (see figure Timing for I S
Transmitter on previous page.)
TIMING
2
In the I S format, any device can act as the system master by providing the necessary clock signals. A
slave will usually derive its internal clock signal from an external clock input. This means, taking into
account the propagation delays between master clock and the data and/or word-select signals, that the
total delay is simply the sum of:
• the delay between the external (master) clock and the slave’s
internal clock; and
• the delay between the internal clock and the data and/or
word-select signals.
For data and word-select inputs, the external to internal clock delay is of no consequence because it
2
only lengthens the effective set-up time (see figure Timing for I S Transmitter on previous page.) The
major part of the time margin is to accommodate the difference between the propagation delay of the
transmitter, and the time required to set up the receiver.
All timing requirements are specified relative to the clock period or to the minimum allowed clock
period of a device. This means that higher data rates can be used in the future.
Timing for I2S Receiver
T
= clock period
TR = minimum allowed clock period for transmitter
T > TR
Note that the specifications are defined by the transmitter speed. The specification of the receiver has to be able
to match the performance of the transmitter.
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I5216 SERIES
Advanced Information
PRELIMINARY
S Parameters (all values in nanoseconds)
Parameter
Bit Clock period T
Transmitter
Receiver
Lower Limit
Upper Limit
Lower Limit
Upper Limit
MIN
MIN
MIN
MIN
MAX
MAX
325
MAX
114
114
Low time tLC
114
114
Rise time tRC
MAX
325
High time tHC
49
Delay tdtr
Hold time thtr
NOTES
260
100
Set-up time tsr
65
Hold time thr
0
Voltage Level Specification
Output Levels
V L < 0.4V
V H > 2.4V both levels able to drive one standard TTL input (I IL = –1.6mA and I IH = 0.04mA).
Input Levels
V IL = 0.8V
V IH = 2.0V
Note: At present, TTL is considered a standard for logic levels. As other IC (LSI) technologies become
popular, other levels will also be supported.
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I5216 SERIES
Advanced Information
PRELIMINARY
DEVICE PHYSICAL DIMENSIONS
PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS
A
B
G
28
27
26
25
24
23
22
21
20
19
18
17
16
15
2
3
4
5
6
7
8
9
10
11
12
13
14
F
C
E
D
J
H
I
PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE E DIMENSIONS
INCHES
M ILLIM ETERS
M in
Nom
M ax
M in
Nom
M ax
A
0.520
0.528
0.535
13.20
13.40
13.60
B
0.461
0.465
0.469
11.70
11.80
11.90
C
0.311
0.315
0.319
7.90
8.00
8.10
D
0.002
0.006
0.05
E
0.007
0.009
0.011
0.17
0.22
0.27
0.041
0.95
1.00
0.0217
F
G
0.037
0
I
0
0.020
J
0.004
H
0.039
0
3
0.022
0.15
0.55
0
0
6
0.028
0
0.50
0.008
0.10
- 77
0
3
0.55
1.05
0
6
0.70
0.21
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS
28 27 26 25 24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
G
C
B
D
F
E
H
PLASTIC SMALL OUTLINE INTEGRATED CIRCUIT (SOIC) DIMENSIONS
INCHES
MILLIMETERS
Min
Nom
Max
Min
Nom
Max
A
0.701
0.706
0.711
17.81
17.93
18.06
B
0.097
0.101
0.104
2.46
2.56
2.64
C
0.292
0.296
0.299
7.42
7.52
7.59
D
0.005
0.009
0.0115
0.127
0.22
0.29
E
0.014
0.016
0.019
0.35
0.41
0.48
0.050
F
1.27
G
0.400
0.406
0.410
10.16
10.31
10.41
H
0.024
0.032
0.040
0.61
0.81
1.02
Note:
Lead coplanarity to be within 0.004 inches.
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I5216 SERIES
Advanced Information
PRELIMINARY
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Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
DIE BONDING PHYSICAL LAYOUT
I5216 DEVICE PIN/PAD LOCATIONS WITH RESPECT TO DIE CENTER IN MICRON (µM)
PIN
Pin Name
X Axis
Y Axis
VSSD
VSS Digital Ground
-1880.70
4721.30
VSSD
VSS Digital Ground
-1709.10
4721.30
AD0
Address 0
-1407.20
4721.30
SDA
Serial Data Address
-1066.00
4721.30
AD1
Address 1
-743.70
4721.30
SCL
Serial Clock Line
-428.60
4721.30
VCCD
VCC Digital Supply Voltage
-156.50
4721.30
VCCD
VCC Digital Supply Voltage
58.90
4721.30
External Clock Input
246.80
4721.30
INT
Interrupt
554.10
4720.50
RAC
Row Address Clock
1029.00
4721.30
SDIO
Serial Data Input Output
1362.60
4721.30
SDI
Serial Data Input
1679.50
4721.30
VSSA
VSS Analog Ground
1840.55
4721.30
-2027.80
-4716.20
MCLK
VSSA
“
“
“
MIC+
Non-inverting Microphone Input
-1824.20
-4716.20
MIC-
Inverting Microphone Input
-1628.60
-4716.20
MICBS
Microphone Bias Voltage
-1327.95
-4716.20
ACAP
AGC/AutoMute Cap
-905.70
-4716.20
SP-
Speaker Negative
-373.50
-4716.20
VSSA
VSS Analog Ground
-39.90
-4716.20
VSSA
VSS Analog Ground
50.10
-4716.20
SP+
Speaker Positive
383.70
-4716.20
VCCA
VCC Analog Supply Voltage
717.30
-4716.20
VCCA
VCC Analog Supply Voltage
807.30
-4716.20
Auxiliary Input
1073.00
-4716.20
Auxiliary Output
1325.95
-4716.20
SCK
Serial Data Clock
1634.65
-4716.20
WS
Word Select
1896.25
-4716.20
AUX IN
AUX OUT
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Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
I5216 SERIES BONDING PHYSICAL LAYOUT
VSSD
VSSD
A0
SDA
A1
SCL
V CCD
V CCD
(1)
MCLK
(UNPACKAGED DIE)
INT
RAC
SDIO SDI VSSA
I5216 Series
Die Dimensions
I5216 Series
X: 4380 µm
Die Dimensions
X: µm
4380µm
Y: 9880
Y:
(3)
9880µm
988
I5216
(3)
Die Thickness
Die Thickness
292.1µm + 12.7µm
292.1
+ 12.7 µm
Pad µm Opening
90 x 90µm
Pad Opening (min)
3.5 x 3.5 mils
90x 90 µm
3.5 x 3.5 mils
VSSA MIC+ MIC - MICBS ACAP
SP-
VSSA(2)
SP+ VCCA (2) AUXIN AUXOUT SCK
WS
1.
The backside of die is internally connected to Vss. It MUST NOT be connected to any other
potential or damage may occur.
2.
Double bond recommended.
This figure reflects the current die thickness. Please contact Winbond as this thickness may change
in the future.
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I5216 SERIES
Advanced Information
PRELIMINARY
ORDERING INFORMATION
WINBOND PART NUMBER DESCRIPTION
I5216-_ _
Product Family
I5216 Product
(8- to 16-minute durations)
Special Temperature Field:
Blank
=
Commercial Packaged (0°C to +70°C)
or
Commercial Die (0°C to +50°C)
D
=
Extended (–20°C to +70°C)
I
=
Industrial (–40°C to +85°C)
Package Type:
E
=
28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1
S
=
28-Lead 0.300-Inch Plastic Small Outline Package (SOIC)
P
=
28-Lead
X
=
Die
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0.600-Inch Plastic Dual Inline Package (PDIP)
Publication Release Date: November 30, 2001
Revision A1
I5216 SERIES
Advanced Information
PRELIMINARY
When ordering I5216 series devices, please refer to the following valid part numbers.
Part Number
I5216E
I5216ED
I5216EI
I5216S
I5216SD
I5216SI
I5216P
I5216X
Chip scale package is available upon customer’s request.
For the latest product information, access Winbond’s worldwide website at http://www.winbondusa.com
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
11F, No. 115, Sec. 3,
Min-Sheng East. Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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