LMV712-N, LMV712-N-Q1 www.ti.com SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 LMV712-N, LMV712-N-Q1 Low Power, Low Noise, High Output, RRIO Dual Operational Amplifier with Independent Shutdown Check for Samples: LMV712-N, LMV712-N-Q1 FEATURES APPLICATIONS • • • • • • • • 1 2 • • • • • • • • • • • • (Typical Unless Otherwise Noted) LMV712-N is available in Automotive AECQ100 Grade 1 version 5MHz GBP Slew Rate 5V/µs Low Noise 20nV/√Hz Supply Current 1.22mA/Channel VOS< 3mV Max Ensured 2.7V and 5V Specifications Temperature Range -40°C to 125°C Rail-to-Rail Inputs and Outputs Unity Gain Stable Small Package: 10-Pin WSON, 10-Pin VSSOP and 10-Bump DSBGA 1.5µA Shutdown ICC 2.2µs Turn On Power Amplifier Control Loop Cellular Phones Portable Equipment Wireless LAN Radio Systems Cordless Phones DESCRIPTION The LMV712-N duals are high performance BiCMOS operational amplifiers intended for applications requiring Rail-to-Rail inputs combined with speed and low noise. They offer a bandwidth of 5MHz and a slew rate of 5 V/µs and can handle capacitive loads of up to 200pF without oscillation. The LMV712-N is ensured to operate from 2.7V to 5.5V and offers two independent shutdown pins. This feature allows disabling of each device separately and reduces the supply current to less than 1µA typical. The output voltage rapidly ramps up smoothly with no glitch as the amplifier comes out of the shutdown mode. The LMV712-N with the shutdown feature is offered in space saving 10-Bump DSBGA and 10-Pin WSON packages. It is also offered in 10-Pin VSSOP package. These packages are designed to meet the demands of small size, low power, and low cost required by cellular phones and similar battery operated portable electronics. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001–2014, Texas Instruments Incorporated LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 www.ti.com Typical Application Circuit Figure 1. P.A. Control Loop These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) (3) Human Body Model 1.5kV Machine Model 150V Differential Input Voltage ±Supply Voltage (V+) +0.4V to (V−) −0.4V Voltage at Input/Output Pin Supply Voltage (V+ - V−) 6V Output Short Circuit V+ (4) − (4) Output Short Circuit V Current at Input Pin ±10mA Current at Output Pin ±50mA Storage Temp Range −65°C to 150°C Junction Temperature TJMAX (5) 150°C Soldering specification for WSON SnPb: Infrared or Convection (20sec) 235°C Soldering specification for all other packages: see product folder at www.ti.com and http://www.ti.com/lit/SNOA549 (1) (2) (3) (4) (5) 2 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Shorting circuit output to either V+ or V− will adversely affect reliability. The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 LMV712-N, LMV712-N-Q1 www.ti.com SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 Recommended Operating Conditions (1) Supply Voltage 2.7V to 5.5V Temperature Range −40°C ≤ TJ ≤ 85°C LMV712 −40°C ≤ TJ ≤ 125°C LMV712-Q1 Thermal Resistance 10-Pin VSSOP 235°C/W 10-Pin WSON 53.4°C/W 10-Bump DSBGA 196°C/W (1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. 2.7V Electrical Characteristics Unless otherwise specified, all limits ensured for V+ = 2.7V, V − = 0V, VCM = 1.35V and TA = 25°C and RL > 1MΩ. Boldface limits apply at the temperature extremes (−40°C ≤T J ≤85°C for LMV712 and −40°C ≤T J ≤125°C for LMV712-Q1). Symbol Parameter VOS Input Offset Voltage IB Input Bias Current CMRR PSRR Condition Common Mode Rejection Ratio Power Supply Rejection Ratio CMVR Common Mode Voltage Range ISC Output Short Circuit Current Typ Max VSSOP WSON 0.4 3 3.2 DSBGA 3 7 9 LMV712 5.5 115 130 LMV712-Q1 5.5 3740 VCM = 0.85V and VCM = 1.85V Min (1) (2) 0V ≤ VCM ≤ 2.7V 50 45 75 2.7V ≤ V+ ≤ 5V, VCM = 0.85V 70 68 90 2.7V ≤ V+ ≤ 5V, VCM = 1.85V 70 68 90 For CMRR ≥ 50dB −0.3 2.9 3 Sourcing VO = 0V 15 12 25 Sinking VO = 2.7V 25 22 50 2.62 2.60 2.68 RL = 10kΩ to 1.35V 0.01 VO Output Swing RL = 600Ω to 1.35V VO(SD) 2.52 2.50 Output Voltage in Shutdown On Mode IS Supply Current per Channel Shutdown Mode (1) (2) (1) Units mV pA dB dB dB −0.2 V mA mA V 0.12 0.15 2.55 V V 0.05 0.23 0.30 V 10 200 mV 1.22 1.7 1.9 mA 0.12 1.5 2.0 uA All limits are ensured by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 3 LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 www.ti.com 2.7V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for V+ = 2.7V, V − = 0V, VCM = 1.35V and TA = 25°C and RL > 1MΩ. Boldface limits apply at the temperature extremes (−40°C ≤T J ≤85°C for LMV712 and −40°C ≤T J ≤125°C for LMV712-Q1). Symbol AVOL Parameter Large Signal Voltage Gain Condition Min (1) Sourcing RL = 10kΩ VO = 1.35V to 2.3V LMV712 80 76 LMV712-Q1 69 Sinking RL = 10kΩ VO = 0.4V to 1.35V LMV712 80 76 LMV712-Q1 69 Sourcing RL = 600Ω VO = 1.35V to 2.2V LMV712 80 76 LMV712-Q1 64 Sinking RL = 600Ω VO = 0.5V to 1.35V LMV712 80 76 LMV712-Q1 VSD Shutdown Pin Voltage Range GBWP Gain-Bandwidth Product SR Slew Rate φm Phase Margin en Input Referred Voltage Noise On Mode Shutdown Mode Max (1) 115 Units dB 115 113 dB 113 97 dB 97 100 dB 62 100 2.0 to 2.7 V 0 to 0.8 0 to 1 V 5 MHz 5 V/µs f = 1kHz 60 Deg 20 nV/√Hz 2.2 Turn-On Time from Shutdown TON (3) (2) 2.4 to 2.7 (3) Turn-On Time from Shutdown Typ 4 4.6 6 8 DSBGA μs μs Number specified is the slower of the positive and negative slew rates. 5V Electrical Characteristics Unless otherwise specified, all limits ensured for V+ = 5V, V − = 0V, VCM = 2.5V and TA = 25°C and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter VOS Input Offset Voltage IB Input Bias Current Condition VCM = 0.85V and VCM = 1.85V Min Typ Max VSSOP WSON 0.4 3 3.2 DSBGA 3 7 9 5.5 115 130 (1) LMV712 (2) LMV712-Q1 CMRR (1) (2) 4 Common Mode Rejection Ratio (1) Units mV pA 3600 0V ≤ VCM ≤ 5V 50 45 80 dB All limits are ensured by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 LMV712-N, LMV712-N-Q1 www.ti.com SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for V+ = 5V, V − = 0V, VCM = 2.5V and TA = 25°C and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol PSRR CMVR ISC Parameter Condition Typ 70 68 90 70 68 90 (1) 2.7V ≤ V+ ≤ 5V, VCM = 0.85V Power Supply Rejection Ratio Min + 2.7V ≤ V ≤ 5V, VCM = 1.85V For CMRR ≥ 50dB Common Mode Voltage Range Output Short Circuit Current (2) −0.3 5.2 5.3 Sourcing VO = 0V 20 18 35 Sinking VO = 5V 25 21 50 4.92 4.90 4.98 RL = 10kΩ to 2.5V 0.01 VO Output Swing 4.82 4.80 RL = 600Ω to 2.5V VO(SD) Output Voltage in Shutdown On Mode IS Supply Current per Channel Shutdown Mode AVOL Large Signal Voltage Gain Sourcing RL = 10kΩ VO = 2.5V to 4.6V LMV712 80 76 LMV712-Q1 69 Sinking RL = 10kΩ VO = 0.4V to 2.5V LMV712 80 76 LMV712-Q1 69 Sourcing RL = 600Ω VO = 2.5V to 4.6V LMV712 80 76 LMV712-Q1 69 Sinking RL = 600Ω VO = 0.4V to 2.5V LMV712 80 76 LMV712-Q1 VSD Shutdown Pin Voltage Range GBWP Gain-Bandwidth Product SR Slew Rate φm Phase Margin en Input Referred Voltage Noise (3) Max (1) Units dB dB −0.2 V V mA mA V 0.12 0.15 4.85 V V 0.05 0.23 0.30 V 10 200 mV 1.17 1.7 1.9 mA 0.12 1.5 2.0 uA 130 dB 130 130 dB 130 110 dB 110 107 dB 69 107 On Mode 4.5 to 5 3.5 to 5 Shutdown Mode 0 to 0.8 0 to 1.5 V 5 MHz 5 V/µs (3) f = 1kHz V 60 Deg 20 nV/√Hz Number specified is the slower of the positive and negative slew rates. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 5 LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 www.ti.com 5V Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for V+ = 5V, V − = 0V, VCM = 2.5V and TA = 25°C and RL > 1MΩ. Boldface limits apply at the temperature extremes. Symbol Parameter Condition Min (1) Turn-On Time for Shutdown TON Turn-On Time for Shutdown 6 6 8 DSBGA Typ Max Units 1.6 4 4.6 μs (2) (1) μs Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 LMV712-N, LMV712-N-Q1 www.ti.com SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 Typical Performance Characteristics Unless otherwise specified, VS = +5V, single supply, TA = 25°C. Supply Current Per Channel vs. Supply Voltage Supply Current vs. Supply Voltage (Shutdown) 1.5 0.6 85°C 1.3 0.5 25°C IS (µA) IS (mA) 1.1 -40°C 0.4 0.9 0.3 0.7 0.5 2.7 3.0 3.5 4.0 4.5 0.2 2.7 3.0 5.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 2. Figure 3. VOS vs. VCM IB vs. VCM Over Temp 5.0 100 0 +85°C -200 +70°C 10 -40°C -600 IBIAS (pA) VOS (µV) -400 25°C +50°C 1 +25°C -800 0°C 0.1 85°C -25°C -1000 -40°C 0.01 -1200 0 1 2 3 4 5 0 3 4 5 Figure 4. Figure 5. Output Positive Swing vs. Supply Voltage, RL = 600Ω Output Negative Swing vs. Supply Voltage, RL = 600Ω 100 140 90 VOUT FROM GND (mV) 25°C 85°C 120 + VOUT FROM V (mV) 2 VCM (V) 160 100 80 -40°C 60 40 2.7 1 VCM (V) 25°C 85°C 80 70 60 -40°C 50 3.0 3.5 4.0 4.5 5.0 40 2.7 VS (V) 3.0 3.5 4.0 4.5 5.0 VS (V) Figure 6. Figure 7. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 7 LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VS = +5V, single supply, TA = 25°C. Sourcing Current vs. Output Voltage, VS = 2.7V Sourcing Current vs. Output Voltage, VS = 5V 35 30 85°C 85°C 30 25 25 ISOURCE (mA) ISOURCE (mA) 25°C 20 -40°C 15 10 -40°C 25°C 20 15 10 5 5 0 -0.3 0 0.2 0.7 1.2 1.7 2.2 0 2.7 1 + 2 3 4 VOUT FROM V (V) VOUT (V) Figure 8. Figure 9. Sinking Current vs. Output Voltage, VS = 2.7V Sinking Current vs. Output Voltage, VS = 5V 90 70 85°C 85°C 80 60 70 50 25°C 60 25°C 40 ISINK (mA) ISINK (mA) 5 30 -40°C 20 -40°C 50 40 30 20 10 10 0 0 -10 -0.3 -10 0.2 0.7 1.7 1.2 VOUT (V) 2.2 0 2.7 1 2 3 4 5 VOUT (V) Figure 10. Figure 11. PSRR vs. Frequency VS = 2.7V PSRR vs. Frequency VS = 5V 100 100 90 90 80 80 NEGATIVE NEGATIVE 70 PSRR (dB) PSRR (dB) 70 60 50 40 POSITIVE 30 60 50 40 POSITIVE 30 20 20 10 10 0 0 10 100 1k 10k 100k 1M 10 Figure 12. 8 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 LMV712-N, LMV712-N-Q1 www.ti.com SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 Typical Performance Characteristics (continued) Unless otherwise specified, VS = +5V, single supply, TA = 25°C. CMRR vs. Frequency CMRR vs. Frequency 100 100 VS = 2.7V 90 90 dVCM = 0.2V TO 1.2V 80 80 70 CMRR (dB) 60 50 40 60 50 40 30 30 20 20 10 10 0 0 10 100 1k 10k dVCM = 2V TO 3V 10 1M 100k VS = 5V 100 1k FREQUENCY (Hz) Open Loop Frequency Response vs. RL Open Loop Frequency Response vs. RL 80 VS = 2.7V VS = 5V 70 60 60 10k: 50 RL = 10k: 600: 90 20 60 40 RL = 600: RL = 600: 30 90 60 20 10 30 10 30 0 0 0 0 10k: -10 -20 1k 10k 100k RL = 10k: -10 1M -20 1k 10M 10k FREQUENCY (Hz) 80 70 100k 1M 10M FREQUENCY (Hz) Figure 16. Figure 17. Open Loop Frequency Response vs. CL Open Loop Frequency Response vs. CL 80 VS = 2.7V VS = 5V 70 CL = 0pF CL = 0pF 60 90 50 60 50 60 30 CL = 100pF 30 20 0 CL = 1000pF CL = 1000pF 10 0 -20 1k 100k CL = 100pF 30 30 0 CL = 1000pF 20 CL = 1000pF 0 CL = 100pF -10 CL = 0pF 10k 40 10 CL = 100pF -10 GAIN (dB) 90 PHASE (Deg) 60 40 PHASE (Deg) 600: 30 GAIN (dB) 50 PHASE (Deg) GAIN (dB) 1M Figure 15. 80 GAIN (dB) 100k Figure 14. 70 40 10k FREQUENCY (Hz) PHASE (Deg) CMRR (dB) 70 1M 10M -20 1k FREQUENCY (Hz) CL = 0pF 10k 100k 1M 10M FREQUENCY (Hz) Figure 18. Figure 19. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 9 LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, VS = +5V, single supply, TA = 25°C. Voltage Noise vs. Frequency Voltage Noise vs. Frequency 1000 1000 INPUT VOLTAGE NOISE (nV/ Hz) INPUT VOLTAGE NOISE (nV/ Hz) VS = 2.7V VCM = 1.35V VSD = 2.7V 100 10 VS = 5V VCM = 2.5V VSD = 5V 100 10 1 1 1 10 100 1k FREQUENCY (Hz) 10k 1 100k 100 1k FREQUENCY (Hz) 10k 100k Figure 21. Non-Inverting Large Signal Pulse Response, VS = 2.7V Non-Inverting Large Signal Pulse Response, VS = 5V OUTPUT OUTPUT (1V/div) (1V/div) INPUT INPUT Figure 20. TIME (500ns/div) TIME (500ns/div) Figure 23. Non-Inverting Small Signal Pulse Response, VS = 2.7V Non-Inverting Small Signal Pulse Response, VS = 5V OUTPUT OUTPUT (50mV/div) (50mV/div) INPUT INPUT Figure 22. TIME (500ns/div) TIME (500ns/div) Figure 24. 10 10 Figure 25. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 LMV712-N, LMV712-N-Q1 www.ti.com SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 Typical Performance Characteristics (continued) Unless otherwise specified, VS = +5V, single supply, TA = 25°C. INPUT Inverting Large Signal Pulse Response, VS = 5V OUTPUT OUTPUT (1V/div) (1V/div) INPUT Inverting Large Signal Pulse Response, VS = 2.7V TIME (500ns/div) Figure 26. Figure 27. Inverting Small Signal Pulse Response, VS = 2.7V Inverting Small Signal Pulse Response VS = 5V (50mV/div) OUTPUT OUTPUT (50mV/div) INPUT INPUT TIME (500ns/div) TIME (500ns/div) TIME (500ns/div) Figure 28. Figure 29. Turn on Time Response VS = 5V Input Common Mode Capacitance vs. VCM VS = 5V SHUTDOWN PULSE 30 26 CCM TO GROUND FMEAS = 1MHz FOLLOWER CONFIG 24 VOUT FOLLOWS VIN (VCM) OUTPUT VOLTAGE CDIFF (pF) (2V/div) 28 22 20 18 16 14 12 10 0 TIME (2µs/div) 1 2 3 4 5 VCM (V) Figure 30. Figure 31. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 11 LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 www.ti.com APPLICATION INFORMATION Theory Of Operation The LMV712-N dual op amp is derived from the LMV711 single op amp. Figure 32 contains a simplified schematic of one channel of the LMV712-N. V + VBIAS IP MP3 Q2 MP1 IN MP2 + MP4 Q1 MN2 IN - CLASS AB CONTROL OUT MN3 MN1 Q3 Q4 Q6 Q5 IN V MN4 VBIAS - SD BIAS CONTROL Figure 32. Rail-to-Rail input is achieved by using in parallel, one NMOS differential pair (MN1 and MN2) and one PMOS differential pair (MP1 and MP2). When the common mode input voltage (VCM) is near V+, the NMOS pair is on and the PMOS pair is off. When VCM is near V−, the NMOS pair is off and the PMOS pair is on. When VCM is between V+ and V−, internal logic decides how much current each differential pair will get. This special logic ensures stable and low distortion amplifier operation within the entire common mode voltage range. Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LMV712-N becomes a function of VCM. VOS has a crossover point at 1.4V above V−. Refer to the "VOS vs. VCM" curve in the Typical Performance Characteristics section. Caution should be taken in situations where input signal amplitude is comparable to VOS value and/or the design requires high accuracy. In these situations, it is necessary for the input signal to avoid the crossover point. The current coming out of the input differential pairs gets mirrored through two folded cascode stages (Q1, Q2, Q3, Q4) into the "class AB control" block. This circuitry generates voltage gain, defines the op amp's dominant pole and limits the maximum current flowing at the output stage. MN3 introduces a voltage level shift and acts as a high impedance to low impedance buffer. The output stage is composed of a PMOS and a NPN transistor in a common source/emitter configuration, delivering a rail-to-rail output excursion. The MN4 transistor ensures that the LMV712-N output remains near V− when the amplifier is in shutdown mode. Shutdown Pin The LMV712-N offers independent shutdown pins for the dual amplifiers. When the shutdown pin is tied low, the respective amplifier shuts down and the supply current is reduced to less than 1µA. In shutdown mode, the amplifier's output level stays at V−. In a 2.7V operation, when a voltage between 1.5V to 2.7V is applied to the shutdown pin, the amplifier is enabled. As the amplifier is coming out of the shutdown mode, the output waveform ramps up without any glitch. This is demonstrated in Figure 33. 12 Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 OUTPUT VOLTAGE (2V/div) SHUTDOWN PULSE www.ti.com TIME (2µs/div) Figure 33. A glitch-free output waveform is highly desirable in many applications, one of which is power amplifier control loops. In this application, the LMV712-N is used to drive the power amplifier's power control. If the LMV712-N did not have a smooth output ramp during turn on, it would directly cause the power amplifier to produce a glitch at its output. This adversely affects the performance of the system. To enable the amplifier, the shutdown pin must be pulled high. It should not be left floating in the event that any leakage current may inadvertently turn off the amplifier. Printed Circuit Board Consideration To properly bypass the power supply, several locations on a printed circuit board need to be considered. A 6.8µF or greater tantalum capacitor should be placed at the point where the power supply for the amplifier is introduced onto the board. Another 0.1µF ceramic capacitor should be placed as close as possible to the power supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be bypassed with a 0.1µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V− pins need to be bypassed. It is good practice to use a ground plane on a printed circuit board to provide all components with a low inductive ground connection. Surface mount components in 0805 size or smaller are recommended in the LMV712-N application circuits. Designers can take advantage of the DSBGA, VSSOP and WSON miniature sizes to condense board layout in order to save space and reduce stray capacitance. Capacitive Load Tolerance The LMV712-N can directly drive 200pF in unity-gain without oscillation. The unity-gain follower is the most sensitive configuration to capacitive loading. Direct capacitive loading reduces the phase margin of amplifiers. The combination of the amplifier's output impedance and the capacitive load induces phase lag. This results in either an under-damped pulse response or oscillation. To drive a heavier capacitive load, Figure 34 can be used. Figure 34. In Figure 34, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO resistor value, the more stable VOUT will be. But the DC accuracy is degraded when the RISO gets bigger. If there were a load resistor in Figure 34, the output voltage would be divided by RISO and the load resistor. Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 13 LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 www.ti.com The circuit in Figure 35 is an improvement to the one in Figure 34 because it provides DC accuracy as well as AC stability. In this circuit, RF provides the DC accuracy by using feed-forward techniques to connect VIN to RL. CF and RISO serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Increased capacitive drive is possible by increasing the value of CF. This in turn will slow down the pulse response. Figure 35. Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR (silicon controlled rectifier) effects. The input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMV712-N is designed to withstand 150mA surge current on all the pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the pins. In addition, like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins will also inhibit latchup susceptibility. 14 Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 LMV712-N, LMV712-N-Q1 www.ti.com SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 CONNECTION DIAGRAMS *Connect thermal pad to V- or leave floating 10 -IN A 9 2 3 - + OUT B + + +IN A V V 8 - -IN B 4 OUT A 1 -IN A 2 +IN A 3 7 5 6 SD A - +IN B V SD B SD A 10 V - + + 4 5 - 1 OUT A - + 9 OUT B 8 -IN B 7 +IN B 6 SD B Figure 36. 10-Pin VSSOP (Top View) Figure 37. 10-Pin WSON (Top View) A2 + V A2 + V A1 OUT A A3 OUTB A3 OUTB A1 OUT A B1 -INA B 3 -INB B 3 -INB B1 -INA C1 +INA C3 +INB C 3 +INB C1 +INA D1 SDA D3 SDB D3 SDB D1 SDA - - V D2 V D2 Figure 38. 10-Bump DSBGA (Top View) Figure 39. 10-Bump DSBGA (Bottom View) Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 15 LMV712-N, LMV712-N-Q1 SNOS534I – FEBRUARY 2001 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY Changes from Revision H (Feb 2013) to Revision I • Page Added Q1 part ...................................................................................................................................................................... 1 Changes from Revision G (February 2013) to Revision H • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: LMV712-N LMV712-N-Q1 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMV712LD/NOPB ACTIVE WSON NGY 10 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 A62 LMV712LDX/NOPB ACTIVE WSON NGY 10 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 A62 LMV712MM NRND VSSOP DGS 10 1000 TBD Call TI Call TI -40 to 85 A61 LMV712MM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A61 LMV712MMX NRND VSSOP DGS 10 TBD Call TI Call TI -40 to 85 A61 LMV712MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A61 LMV712Q1MM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AUA LMV712Q1MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AUA LMV712TL/NOPB ACTIVE DSBGA YPA 10 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 AU2A LMV712TLX/NOPB ACTIVE DSBGA YPA 10 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 AU2A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2015 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF LMV712-N, LMV712-N-Q1 : • Catalog: LMV712-N • Automotive: LMV712-N-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device LMV712LD/NOPB Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant WSON NGY 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMV712LDX/NOPB WSON NGY 10 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMV712MM VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV712MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV712MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV712Q1MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV712Q1MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LMV712TL/NOPB DSBGA YPA 10 250 178.0 8.4 1.68 2.13 0.76 4.0 8.0 Q1 LMV712TLX/NOPB DSBGA YPA 10 3000 178.0 8.4 1.68 2.13 0.76 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 2-Sep-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV712LD/NOPB WSON NGY 10 1000 213.0 191.0 55.0 LMV712LDX/NOPB WSON NGY 10 4500 367.0 367.0 35.0 LMV712MM VSSOP DGS 10 1000 210.0 185.0 35.0 LMV712MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LMV712MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LMV712Q1MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LMV712Q1MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LMV712TL/NOPB DSBGA YPA 10 250 210.0 185.0 35.0 LMV712TLX/NOPB DSBGA YPA 10 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NGY0010A LDA10A (Rev B) www.ti.com MECHANICAL DATA YPA0010 0.600 ±0.075 D E TLP10XXX (Rev D) D: Max = 2.048 mm, Min =1.987 mm E: Max = 1.565 mm, Min =1.504 mm 4215069/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2015, Texas Instruments Incorporated