E-CMOS EC9223NNQ1R Multi-channel tft lcd supply Datasheet

Multi-Channel TFT LCD Supply
EC9223
General Description
TheEC9223 is an integrated power supply solution optimized for small to medium size thin- film transistor (TFT)
liquid crystal displays (LCD’s). The boost converter operates at a fixed frequency of 1.2MHz. The integrated Nchannel FET has a current limit of 1.8A. The positive and negative charge pumps provide regulated TFT LCD
gate-on and gate-off supplies. Both outputs can be adjusted by external resistive voltage dividers.
The integrated operational amplifier is typically used for LCD VCOM driving; the output can sink or source up to
150mA short-circuit current. A built-in voltage detector generates a reset signal when the input voltage drops
below 2.6V. The reset signal is active low and has a 123ms blanking time during power-on. The EC9223 is
available in a thin 16-pin 3x3 mm WQFN green package.
Features
QFN-16 Pin Configuration
2.5V to 5.5V input supply
Active-high Enable Control
Current-mode boost regulator
- 1.2MHz switching frequency
- Integrated 20V/1.8A 700mΩ FET
- Fast transient response to pulsed load
- High efficiency up to 90%
- Adjustable high-accuracy output voltage(±1%)
VGH positive charge pump
VGL negative charge pump
Integrated unity-gain VCOM buffer
- ±150mA output current limit
- 12V/us slew rate
- 12MHz Bandwidth
Low-voltage detection circuit
Soft-start and timed delay fault latch for all outputs
Thermal shutdown
Thin 3x3 mm 16-lead WQFN package
Applications
TFT LCD for Notebooks
Tablet Personal Computer Display
Car Navigation Display
Portable equipment
E-CMOS Corp. (www.ecmos.com.tw)
1/13
5E26N-Rev. F001
EC9223
Multi-Channel TFT LCD Supply
PIN DESCRIPTION
Number
Name
Pin Description
Negative charge pump driver output.
1
DRVN
2
REF
3
AGND
Reference output. All power outputs are disabled until REF exceeds its UVLO
threshold.
Analog ground.
4
RSTnn
Voltage detector output. RSTnn is an active-low open-drain output.
5
EN
6
OPAI
Unity-gain buffer input pin.
7
OPAO
Unity-gain buffer output pin.
8
AVDD
Charge pump and unity-gain buffer supply.
9
PGND
Boost converter power ground (source of the internal NMOS switch).
10
LX
Boost converter switching node (drain of the internal NMOS switch).
11
VIN
Supply for PWM, reference and other circuits.
12
FB
Boost converter feedback voltage input.
13
COMP
14
FBP
15
DRVP
16
FBN
-
TP
Enable control input pin. This pin has a 4uA pull-down current source.
Boost converter error amplifier compensation node.
Positive charge pump feedback input.
Positive charge pump driver output.
Negative charge pump feedback input.
Thermal Pad, connect to AGND.
Ordering Information
EC9223 NN XX X
R:Tape & Reel
Q1:WQFN
Part Number
Package
Marking
EC9223NNQ1R
WQFN 16L
9223
LLLLL
E-CMOS Corp. (www.ecmos.com.tw)
Marking Information
1. LLLLL:Lot No
5E26N-Rev. F001
2/13
Multi-Channel TFT LCD Supply
EC9223
Function Block Diagram
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
3/13
Multi-Channel TFT LCD Supply
EC9223
Typical Application Diagram
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
4/13
EC9223
Multi-Channel TFT LCD Supply
Absolute Maximum Ratings
Input Supply Voltage, VIN
-0.3V to 6.5V
Voltages on EN, RSTnn
-0.3V to 6.5V
Voltages on AVDD, LX
-0.3V to 22V
Voltages on FB, FBP, FBN, COMP, REF
-0.3V to (VIN+0.3V)
Voltages on DRVP, DRVN, OPAI, OPAO
-0.3V to (AVDD+0.3V)
Storage temperature range
-65°C to 150°C
Lead temperature (soldering, 10s maximum)
260°C
ESD, Human body mode
2kV
ESD, Machine mode
200V
Note1: All voltages are referenced to ground with PGND and AGND pins grounded.
Note2: “ABSOLUTE MAXIMUM RATINGS” indicate limits beyond which permanent damage to the device
may occur. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those indicated under "Recommended Operating Conditions" is not implied. For
guaranteed specifications and test conditions, see the “ELECTRICAL SPECIFICATIONS”.
Recommended Operation Conditions
Junction temperature range
-40°C to 125°C
Ambient temperature range
-40°C to 85°C
Power Dissipation Ratings
Package
16-ld QFN
Thermal Resistance,
Power Rating
Power Rating
Power Rating
ΘJA
(TA < 25 °C )
(25 < TA < 85 °C )
(TA = 85°C )
103°C /W
1.25W
(125 - TA) / 103 W
0.39W
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
5/13
EC9223
Multi-Channel TFT LCD Supply
Electrical Specifications
(VIN=3.3V, AVDD = 8.5V, TA=25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
2.5
--
5.5
V
System Supply
Input Supply Voltage
VIN
VIN Under Voltage Lockout
Threshold
VIN Under
Voltage Lockout
VUVLO
VIN rising
1.8
2.0
2.2
V
VUVLO
Hysteresis
--
0.1
--
V
Threshold
VIN Quiescent current
IQ
VFB = 1.35V, LX no switching
--
0.3
--
mA
VIN Quiescent current
IQ
VFB = 1.15V, LX switching
--
0.8
--
mA
EN Threshold
VIH
2
--
--
EN Threshold
VIL
--
--
0.8
Thermal shutdown
TSHDN
--
150
--
℃
1.188
1.2
1.212
V
V
Main Boost Regulator
FB Regulation Voltage
VFB
FB Fault Trip Level
Falling edge
0.95
V
FB Load Regulation
0< ILOAD < full
-1
%
FB Line Regulation
VIN = 2.5 to 5.5V
0.15
0.25
%/V
FB Input Bias Current
VFB = 1.25V
0
40
nA
-40
FB Transconductance
Gm
∆I=±5uA at COMP, FB = COMP
70
uA/V
FB Voltage Gain
AV
FB to COMP
1500
V/V
LX Current Limit
LX On-Resistance
VFB =1.1V, duty cycle = 75%
Rds_LX
LX Leakage Current
1.4
1.8
ILX = 200mA
0.7
VLX = 19V, TA = +25°C
0.1
Current-Sense Transresistance
2.2
Ω
10
0.35
Maximum Duty Cycle
DUTY
Soft-Start Period
TSS1
85
90
A
uA
V/A
94
7
%
ms
Reference
REF OUTPUT Voltage
VREF
IREF=50uA
REF Load Regulation
IREF
REF Line Regulation
1.176
1.20
1.224
V
0<ILOAD <100uA
1
5
mV
IREF = 100uA
VIN=2.5V to 5.5V
2
5
mV
1200
1500
KHz
Oscillator and Timing
Frequency
FOSC
Duration to Trigger Fault
Condition
900
FB or FBP or FBN below
threshold
E-CMOS Corp. (www.ecmos.com.tw)
100
ms
5E26N-Rev. F001
6/13
EC9223
Multi-Channel TFT LCD Supply
Positive Charge-Pump Regulator
AVDD Supply Range
VAVDD
Operating Frequency
FOSC_CP
FBP Regulation Voltage
VFBP
FBP Input Bias Current
IFBP_BIAS
DRVP P-Ch On-Resistance
RDRVPP
DRVP N-Ch On-Resistance
RDRVPN
FBP Fault Trip Level
Soft-Start Period
6
16
600
VFBP =1.5V, TA = +25°C
V
KHz
1.176
1.2
1.224
V
-40
-
40
nA
VAVDD=10V,IDRVP=20mA
Falling edge
TSS2
20
Ω
20
Ω
0.95
V
5
ms
Negative Charge-Pump Regulator
AVDD Supply Range
VAVDD
Operating Frequency
FOSC_CP
FBN Regulation Voltage
VFBN
FBN Input Bias Current
IFBN_BIAS
DRVN P-Ch On-Resistance
RDRVNP
6
16
600
VFBN = 0V, TA = +25°C
V
KHz
210
240
270
mV
-40
-
40
nA
20
Ω
20
Ω
0.45
V
5
ms
VAVDD=10V,IDRVN=20mA
DRVN N-Ch On-Resistance
RDRVNN
FBN Fault Trip Level
Soft-Start Period
Rising edge
TSS3
Operational Amplifier
AVDD Supply Range
VAVDD
6
AVDD Supply Current
IAVDD
VOPAI= VAVDD/2, no load
Input Offset Voltage
VOS
VOPAI =VAVDD/2, TA = +25°C
-15
Input Bias Current
IBIAS
VOPAI =VAVDD/2, TA = +25°C
-100
0
VAVDD
V
Input Common-Mode Voltage
Range
Output-Voltage-Swing High
1.2
mA
15
mV
100
nA
VAVDD - VAVDD 20
5
mV
OPAO IOUT = 5 mA
VAVDD - VAVDD 200
150
mV
VOH
OPAO IOUT = -100µA
5
20
mV
OPAO IOUT = -5 mA
150
200
mV
VOL
Slew Rate
SR
VOPAO 20% to 80% with
CL=10pF, RL=10k
-3dB Bandwidth
BW
CL=10pF, RL=10k
ISCC
0
V
OPAO IOUT = 100µA
Output-Voltage-Swing Low
Short-Circuit Current
0.6
16
8
12
V/us
12
MHz
VOPAI=VAVDD/2 , short output to
GND (sourcing)
100
150
mA
VOPAI=VAVDD/2 , short output to
AVDD (sinking)
100
150
mA
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
7/13
EC9223
Multi-Channel TFT LCD Supply
Low-Voltage Detector
Reset Threshold
VRST_TH
Falling edge at VIN
VRST_HYST
RSTnn Output Voltage
VRST
Reset Blanking Time
TBLK
2.6
V
100
mV
ISINK = 1mA
0.4
120
V
ms
Application Information
The EC9223 offers an all-in-one solution for TFT LCD. The chip includes a high-efficiency boost converter with a
20V/1.8A on-chip N-channel transistor for biasing of the LCD, a regulated positive charge pump, a regulated
negative charge pump, and a unity-gain VCOM buffer. A voltage detector circuit generates a reset signal when
the input voltage falls below 2.6V.
TFT LCD Boost Converter (AVDD)
The LCD panel AVDD supply is generated from a high-efficiency PWM boost converter operating with current
mode control, and the switching frequency is 1.2MHz. During the on-period, TON, the synchronous FET
connects one end of the inductor to ground, therefore increasing the inductor current. After the FET turns off, the
inductor switching node, LX, is charged to a positive voltage by the inductor current. The freewheeling diode
turns on and the inductor current flows to the output capacitor. The converter operates in the continuous
conduction mode (CCM) when the average input current IIN is at least one-half of the inductor peak- to-peak
ripple current, ∆ILPP.
The output voltage, AVDD, is determined by the duty cycle, D, of the power FET on-time and the input voltage,
VIN.
The average load current, ILOAD, can be calculated from the power conservation law.
η ×VIN × I IN = AVDD × I LOAD
where η is the power conversion efficiency. For a lower load current, the inductor current would decay to zero during the freewheeling period and the output node would be disconnected from the inductor for the remaining portion of the switching
period. The converter would operate in the discontinuous conduction mode (DCM). Current mode control is well known for its
robustness and fast transient response. An inner current feedback loop sets the on-time and the duty cycle such that the
current through the inductor equals to the current computed by the compensator. This loop acts within one switching cycle. A
slope compensation ramp is added to suppress sub-harmonic oscillations. An outer voltage feedback loop subtracts the
voltage on the FB pin from the internal reference voltage and feeds the difference to the compensator operational
transconductance (Gm) amplifier. This amplifier is compensated by an external R-C network to allow the user to optimize the
transient response and loop stability for the specific application conditions.
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
8/13
Multi-Channel TFT LCD Supply
EC9223
Compensation
This current mode boost converter has a current sense loop and a voltage feedback loop. The current sense
loop does not need any compensation. The voltage feedback loop is compensated by an external series R-C
network RCOMP and CCOMP from COMP pin to ground. RCOMP sets the high-frequency loop gain and the
unity gain bandwidth of the loop which determines the transient response. CCOMP together with RCOMP determine
the phase margin which relates to loop stability.
Output Capacitor Selection
The output voltage ripple due to converter switching is determined by the output capacitor total capacitance,
COUT, and the output capacitor total effective series resistance, ESR.
The first ripple component can be reduced by increasing COUT. Changing COUT may require adjustment of
compensation R and C in order to provide adequate phase margin and loop bandwidth.
The second ripple component can be reduced by selecting low-ESR ceramic capacitors and using several
smaller capacitors in parallel instead of just one large capacitor.
Inductor Selection
To prevent magnetic saturation of the inductor core the inductor has to be rated for a maximum current larger
than IPK in a given application. Since the chip provides current limit protection of 1.8A (typ) it is generally
recommended that the inductor be rated at least for 1.8A. Selection of the inductor requires trade-off between
the physical size (footprint x height) and its electrical properties (current rating, inductance, resistance). Within a
given footprint and height, an inductor with larger inductance typically comes with lower current rating and often
larger series resistance. Larger inductance typically requires more turns on the winding, a smaller core gap or a
core material with a larger relative permeability. An inductor with a larger physical size has better electrical
properties than a smaller inductor.
It is desirable to reduce the ripple current ∆ILPP in order to reduce voltage noise on the input and output
capacitors. In practice, the inductor is often much larger than the capacitors and it is easier and cheaper to
increase the size of the capacitors. The ripple current ∆ILPP is then chosen the largest possible while at the
same time not degrading the maximum input and output current that the converter can operate with before
reaching the current limit of the chip or the rated current of the inductor.
For example, ∆ILPP could be set to 20% of IMAX.
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
9/13
Multi-Channel TFT LCD Supply
EC9223
Positive Charge Pump (VGH)
The positive charge pump is used to generate the TFT LCD gate on voltage. The output voltage, VGH, can be set by an
external resistive divider. Voltage VFBP is 1.2V. A single stage charge pump can produce an output voltage less than
approximately twice the charge pump input voltage AVDD. The output voltage VGH is regulated as the following equation.
The negative charge pump is used to generate the TFT LCD gate off voltage. The output voltage, VGL, is set
with an external resistive divider from its output to REF with the midpoint connected to FBN. The error amplifier
compares the feedback signal from FBN with an internal reference 240mV. The output voltage VGL is regulated
as the following equation. VREF is 1.2V.
VCOM Buffer
The VCOM buffer generates the bias supply for the back plane of an LCD screen which is capacitively coupled to
the pixel drive voltage. The purpose of the VCOM buffer is to hold the bias voltage steady while pixel voltage
changes dynamically. The buffer is designed to sustain up to ±75mA of output current. In transients, it can
deliver up to 150mA at which point the over current protection circuit limits the output current. Excessive current
draw over a period of time may cause the chip temperature to rise and set off the over temperature protection
circuit.
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
10/13
EC9223
Multi-Channel TFT LCD Supply
Under Voltage Protection
During normal operation (after completing the soft start sequence) EC9223 constantly monitors feedback pins FB, FBP and
FBN. A fault condition occurs if FB falls below 0.95V or FBP falls below 0.95V or FBN rises above 0.45V. If any of the fault
conditions persist for longer than 100ms, the chip sets a fault latch and shuts down. To turn the power supplies back on
requires cycling of VIN supply below the UVLO level or toggling the EN pin low and high. This will clear the fault latch and
restore normal operation.
Over Current Protection
The EC9223 has Over-Current Protection (OCP) that limits the peak inductor current in every switching cycle. It
prevents large current from damaging the inductor and diode. Once the inductor current exceeds the current limit,
the internal switch turns off immediately and shortens the duty cycle. The output voltage drops if the over-current
condition occurs. Current limit is affected by the input voltage, duty cycle, and inductor value.
Thermal-Overload Protection
The EC9223 boost converter provides Thermal-overload Protection to prevents excessive power dissipation
from overheating the IC. When the junction temperature exceeds TJ = 150°C, a thermal sensor activates the
fault protection, which shuts down all outputs. To resume normal operation the chip internal temperature must
drop at least by 15°C. In addition, either the inpu t supply must be cycled below the UVLO level or the EN pin
must be toggled low and high to clear the fault latch.
Voltage Detector Circuit
The internal voltage detector circuit monitors the chip input voltage VIN. The chip can either drive RSTnn pin low
or leave it floating. While floating, RSTnn is pulled high by an external pull up resistor. When VIN drops below
2.6V the chip pulls RSTnn pin low. In order to release RSTnn the VIN voltage must rise above 2.7V. The voltage
detector circuit is disabled and RSTnn is floating while the chip is disabled and for 123ms from the time the chip
is enabled (VIN>UVLO and EN is high).
Start-Up and Power-Off Control
The EC9223 employs EN pin to control the whole chip. Pulling EN high enables this device. When EN goes high,
once reference voltage is ready, the boost convertor starts operating. To limit the supply inrush current during
start up conditions, an internal soft-start circuitry is implemented. The soft-start circuitry will slowly ramp up the
output voltage during soft-start period, the soft-start period is 7ms for AVDD and 5ms for VGH and VGL. The
EC9223 shuts down to reduce the supply current when EN is low. In this mode, all the internal blocks turn off,
and the n-channel MOSFET is turned off as well. The boost convertor’s output is connected to VIN by the
external inductor and rectifier diode.
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
11/13
Multi-Channel TFT LCD Supply
EC9223
Startup Sequence
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
12/13
Multi-Channel TFT LCD Supply
EC9223
Package Information
(WQFN-16 3x3 mm)
E-CMOS Corp. (www.ecmos.com.tw)
5E26N-Rev. F001
13/13
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