NB3N3010B 3.3V, 12.288 MHz Audio Oversampling Clock Generator for USB Applications http://onsemi.com Description MARKING DIAGRAMS* 8 VDD 1 A L Y W M G 4 = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. GND CFILT 8 1 DFN8 MN SUFFIX CASE 506AA • Accepts 8 kHz or 4 kHz Reference Input Derived from USB Start−of−Frame Generates 12.288 MHz Frequency−Locked to the Reference Fully Integrated Frequency−Lock−Loop with Internal Loop Filter Low Skew Dual LVCMOS Outputs Very Low Phase Noise Preserves Codec Noise Floor Internal Voltage Regulator Supply Voltage Required: +3.3 V $5% Temperature Range: 0°C to +85°C These are Pb−Free Devices 3010B ALYW G SOIC−8 D SUFFIX CASE 751 Features • • • • • • • • 8 1 XX M G G The NB3N3010B is a precision, low noise clock multiplier that generates an output frequency of 12.288 MHz. This is accomplished by using Frequency−Locked−Loop (FLL) techniques where a 4 kHz reference input is multiplied by 3072, or an 8 kHz input by 1536. The frequency multiplier is selected by the S0 pin. The two LVCMOS output drivers are disabled to a logic Low with the ENABLEn pin set HIGH. The NB3N3010B operates from a single +3.3 V supply, and is available in the SOIC−8 pin package, and optionally in a DFN8 package. The operating temperature range is from 0°C to +85°C. The NB3N3010B device provides the optimum combination of low cost, flexibility, and high performance. This makes it ideal for applications such as oversampling A−to−D and D−to−A converters from a low reference frequency, such as a USB start−of−frame (SOF) pulse. 5 4 CLK_A +1.8 V Linear Regulator 6 REF Tolerant Frequency Detector 3 CLK_B Frequency Generator Loop Filter Output Buffers 7 Divider 1 ENABLEn 2 S0 Figure 1. NB3N3010B Simplified Diagram © Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 0 1 Publication Order Number: NB3N3010B/D NB3N3010B ENABLEn 1 8 VDD S0 2 7 CLKB REF 3 6 CLKA GND 4 5 CFILT NB3N3010B Figure 2. Pinout SOIC−8 / DFN8 (Top View) Table 1. PIN DESCRIPTION Pin Symbol I/O Description 1 ENABLEn LVTTL/ LVCMOS Input Low active Output Enable; Defaults HIGH when left open; Internal pull−up resistor to VDD. 2 S0 LVTTL/ LVCMOS Input Frequency Select Input. See input frequency select Table 2 for details. Defaults HIGH when left open. Internal pull−up resistor to VDD. 3 REF Input 4 GND Power Supply 5 CFILT Analog 6 CLKA LVCMOS Output Clock output, copy A (12.288 MHz) 7 CLKB LVCMOS Output Clock output, copy B (12.288 MHz) 8 VDD Power Supply Reference Clock input Negative Supply Voltage; Ground 0 V. This pin provides GND return path to the VDD supply. Connection for external filter capacitor for internal +1.8 V regulator; see Figure 4. Positive Supply Voltage, +3.3 V $5% http://onsemi.com 2 NB3N3010B Table 2. ATTRIBUTES Characteristic ESD Protection Value Human Body Model Machine Model > 4 kV 400 V RPU − ENABLEn Input Pull−up Resistor RPU − SO Input Pull−up Resistor 48 kW 48 kW Moisture Sensitivity (Note 1) Flammability Rating Pb−Free Oxygen Index: 28 to 34 Level 1 UL 94 V−0 @ 0.125 in Transistor Count 12039 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Condition 1 Condition 2 Rating Unit Positive Power Supply GND = 0 V 4.6 V VI Input Voltage (VIN) GND = 0 V −0.3 V to VDD + 0.3 V V TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range −40 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) (Note 2) SOIC−8 41 to 44 °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN−8 (2x2) DFN−8 (2x2) 129 84 °C/W qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN−8 (2x2) 35−40 °C/W Tsol Wave Solder 265 °C Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). Table 4. DC CHARACTERISTICS VDD = 3.3 V $5%, GND = 0 V, TA = 0°C to +85°C, Note 3. Symbol VDD Characteristic Power Supply Voltage Min Typ Max Unit 3.13 3.3 3.47 V IDDOEL Power Supply Current (operating, i.e. ENABLEn is LOW) Outputs Unloaded 21 35 mA IDDOEH Power Supply Current (standby, i.e. ENABLEn is HIGH) 415 600 uA VIH Input HIGH Voltage (REF, ENABLEn, S0) 2.0 VDD + 0.3 V VIL Input LOW Voltage (REF, ENABLEn, S0) GND − 0.3 0.8 V VOH Output HIGH Voltage (CLKA, CLKB) , IOH = −12 mA VOL Output LOW Voltage (CLKA, CLKB), IOL = 12 mA 2.4 V 0.4 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. CFILT capacitor must be installed; see Figure 4. http://onsemi.com 3 NB3N3010B Table 5. AC CHARACTERISTICS VDD = 3.3 V $5%, GND = 0 V, TA = 0°C to +85°C (Note 4) Symbol Characteristic fout Output Clock Frequency: CLKA & CLKB fOUT = 8 kHz x 1536 fOUT = 4 kHz x 3072 fREF Reference Input Frequency tjit(per)−ref Min Typ Max Unit MHz S0 = 1 S0 = 0 12.25728 12.25728 12.288 12.288 12.31872 12.31872 S0 = 1 S0 = 0 7.98 3.99 8 4 8.02 4.01 kHz 250 ns 68000 136000 ns Reference Input Period Jitter (pk−pk) tREFH Reference Input Pulse Width (high) tCLKH CLKA, CLKB output width, high 13 ns tCLKL CLKA, CLKB output width, low 13 ns tr CLKA, CLKB rise time 10% − 90% tf CLKA, CLKB fall time 90% − 10% S0 = 1 S0 = 0 33 33 4 ns 4 ns tjit(per) CLKA, CLKB period jitter (over 10k cycles) peak−to−peak RMS 250 20 ps tjit(cc) CLK_A, CLKB cycle−to−cycle jitter (1k cycles) peak−to−peak RMS 300 35 ps tsk(LH) CLKA to CLKB output skew (low−to−high transitions) 700 ps tsk(HL) CLKA to CLKB output skew (high−to−low transitions) 700 ps 10 ms 100 ms Power Valid to ENABLEn ENABLEn to CLKA/CLKB 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Outputs loaded with 15 pF max to ground. CFILT capacitor must be installed; see Figure 4. 5. Maximum time required after power is applied to the MCLK FLL until it is ready to accept ENABLEn active. http://onsemi.com 4 NB3N3010B APPLICATION INFORMATION Output Enable − ENABLEn Figure 1 shows the simplified block diagram of the NB3N3010B device. The primary function of the NB3N3010B is to accept a selectable 4 kHz or 8 kHz input reference clock, REF, and then multiply it to 12.288 MHz output frequency. A Low active output enable input pin, ENABLEn, is provided. When the ENABLEn input is High inactive, both clock outputs are driven to a logic Low. The NB3N3010B implements a delay, specified as ENABLEn to Output Delay in the AC Specifications, from the assertion of ENABLEn to the first rising edges on the clock outputs. This delay insures that CLKA and CLKB output pulses are within specification before the output drivers are enabled. When ENABLEn transitions from Low to High (de−asserts), the current cycle of the clock outputs completes normally then the outputs will be held Low. The ENABLEn signal is asynchronous to either the REF input or CLK_x outputs. Frequency Select − SO Either of two expected input REF frequencies, 4 kHz or 8 kHz, will be multiplied by the FLL to achieve 12.288 MHz at the low−skew CLKA and CLKB outputs by selecting the S0 pin; see Table 6. The pulse high time (THI) of the input reference signal may vary widely depending on the application. See AC specifications for details. Table 6. INPUT FREQUENCY SELECT AND OUTPUT ENABLE FUNCTIONS ENABLEn* S0* fREF FLL Multiplier CLKA & CLKB Frequency 0 L 4 kHz 3072 12.288 MHz 0 H 8 kHz 1536 12.288 MHz 1 x x x Disabled Low *Defaults High when left open. Typical Power On Sequence 1. Power On 2. Reference Clock present; must be switching before ENABLEn goes High. 3. Output Enable, ENABLEn, High−to−Low VDD Valid VDD Valid to ENABLEn VDD ENABLEn 4 kHz or 8 kHz Outputs Enabled REF 400 Clock Cycles @ 8 kHz 200 Clock Cycles @ 4 kHz ~50 ms, typ ENABLEn to Output 12.288 MHz CLKA/B Figure 3. ENABLEn Timing Diagram http://onsemi.com 5 Completed Clock Outputs Then Low NB3N3010B CFILT for 1.8 V Regulator A low noise 1.8 V LDO/Regulator is integrated to provide a clean supply for the CLKA/CLKB output buffers. The LDO requires a decoupling capacitor in the range of 220 nF to 270 nF for compensation and high frequency PSR, and should be located near the device. The purpose of this design technique is to isolate the high switching noise of the digital outputs from the relatively sensitive internal analog phase−locked loop. CFILT 1.8 V Regulator 220 − 270 nF Figure 4. CFILT Capacitor tREF tREFH Tjitter−REF REF Figure 5. REF Input Timing Diagram Tper Tcyc tMCLKL Tjitter−PER Tjitter−cyc 80% 20% CLK A, CLK B tMCLKH Tf Figure 6. Clock Output Timing Diagram VDD 0.1 mF CLKA Bypass Capacitor Close to Pin HiZ Probe 15 pF CLKB HiZ Probe 15 pF GND Figure 7. Test Circuit http://onsemi.com 6 Tf NB3N3010B ORDERING INFORMATION Package Shipping† NB3N3010BDG SOIC−8 (Pb−Free) 98 Units / Rail NB3N3010BDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NB3N3010BMNG* DFN−8 (Pb−Free) TBD Units / Rail NB3N3010BMNR4G* DFN−8 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *To order other package and voltage variants, please contact your ON Semiconductor sales representative. http://onsemi.com 7 NB3N3010B PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X S M J SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NB3N3010B PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA−01 ISSUE E D A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 ÇÇ ÇÇ PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C DETAIL A E OPTIONAL CONSTRUCTIONS ÉÉ ÉÉ EXPOSED Cu TOP VIEW A DETAIL B 0.10 C DIM A A1 A3 b D D2 E E2 e K L L1 MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION 0.08 C (A3) NOTE 4 SIDE VIEW DETAIL A A1 D2 1 4 C 8X SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 RECOMMENDED SOLDERING FOOTPRINT* L 1.30 PACKAGE OUTLINE 8X 0.50 E2 0.90 K 8 5 e/2 e 8X b 1 0.10 C A B 0.05 C 2.30 8X NOTE 3 0.30 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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