GS840H18/32/36AT/B-180/166/150/100 TQFP, BGA Commercial Temp Industrial Temp 256K x 18, 128K x 32, 128K x 36 4Mb Sync Burst SRAMs Features • FT pin for user-configurable flow through or pipelined operation • Single Cycle Deselect (SCD) operation • 3.3 V +10%/–5% core power supply • 2.5 V or 3.3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipelined mode • Byte Write (BW) and/or Global Write (GW) operation • Common data inputs and data outputs • Clock control, registered, address, data, and control • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC standard 100-lead TQFP or 119-Bump BGA package • Pb-Free 100-lead TQFP package available Functional Description Applications The GS840H18/32/36A is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS840H18/32/36A is available in a JEDEC standard 100-lead TQFP or 119-Bump BGA package. Controls Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated 180 MHz–100 MHz 3.3 V VDD 3.3 V and 2.5 V I/O internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the BGA). Holding the FT mode pin/bump low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined mode, activating the rising-edge-triggered Data Output Register. SCD Pipelined Reads The GS840H18/32/36A is an SCD (Single Cycle Deselect) pipelined synchronous SRAM. DCD (Dual Cycle Deselect) versions are also available. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS840H18/32/36A operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to de-couple output noise from the internal circuit. Parameter Synopsis Pipeline 3-1-1-1 Flow Through 2-1-1-1 Rev: 1.11 10/2004 tCycle tKQ IDD tKQ tCycle IDD –180 5.5 ns 3.0 ns 335 mA 8 ns 9 ns 210 mA –166 6.0 ns 3.5 ns 310 mA 8.5 ns 10 ns 190 mA –150 6.6 ns 3.8 ns 280 mA 10 ns 12 ns 165 mA –100 10 ns 4.5 ns 190 mA 12 ns 15 ns 135 mA 1/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 A A E1 E2 NC NC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS840H18A 100-Pin TQFP Pinout (Package T) NC NC NC VDDQ A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS NC NC DQB DQB VSS VDDQ DQB DQB FT VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 256K x 18 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.11 10/2004 2/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS840H32A 100-Pin TQFP Pinout (Package T) NC DQC DQC VDDQ NC DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA NC LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 32 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.11 10/2004 3/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 A A E1 E2 BD BC BB BA E3 VDD VSS CK GW BW G ADSC ADSP ADV A A GS840H36A 100-Pin TQFP Pinout (Package T) DQPC DQC DQC VDDQ DQPB DQB DQB VDDQ VSS DQB DQB DQB DQB VSS VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA DQA DQA VSS VDDQ DQA DQA DQPA LBO A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A VSS DQC DQC DQC DQC VSS VDDQ DQC DQC FT VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 128K x 36 10 71 Top View 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Rev: 1.11 10/2004 4/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 TQFP Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BW I Byte Write—Writes all enabled bytes; active low BA, BB I Byte Write Enable for DQA, DQB Data I/’s; active low BC , BD I Byte Write Enable for DQC, DQD Data I/Os; active low CK I Clock Input Signal; active high GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply NC - No Connect Rev: 1.11 10/2004 5/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 GS840H18A Pad Out—119-Bump BGA—Top View (Package B) Rev: 1.11 10/2004 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC E2 A ADSC A E3 NC C NC A A VDD A A NC D DQB NC VSS NC VSS DQPA NC E NC DQB VSS E1 VSS NC DQA F VDDQ NC VSS G VSS DQA VDDQ G NC DQB BB ADV NC NC DQA H DQB NC VSS GW VSS DQA NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQB VSS CK VSS NC DQA L DQB NC NC NC BA DQA NC M VDDQ DQB VSS BW VSS NC VDDQ N DQB NC VSS A1 VSS DQA NC P NC DQPB VSS A0 VSS NC DQA R NC A LBO VDD FT A NC T NC A A NC A A ZZ U VDDQ NC NC NC NC NC VDDQ 6/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 GS840H32A Pad Out—119-Bump BGA—Top View (Package B) Rev: 1.11 10/2004 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC E2 A ADSC A E3 NC C NC A A VDD A A NC D DQC NC VSS NC VSS NC DQB E DQC DQC VSS E1 VSS DQB DQB F VDDQ DQC VSS G VSS DQB VDDQ G DQC DQC BC ADV BB DQB DQB H DQC DQC VSS GW VSS DQB DQB J VDDQ VDD NC VDD NC VDD VDDQ K DQD DQD VSS CK VSS DQA DQA L DQD DQD BD NC BA DQA DQA M VDDQ DQD VSS BW VSS DQA VDDQ N DQD DQD VSS A1 VSS DQA DQA P DQD NC VSS A0 VSS NC DQA R NC A LBO VDD FT A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC NC VDDQ 7/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 GS840H36A Pad Out—119-Bump BGA—Top View (Package B) Rev: 1.11 10/2004 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B NC E2 A ADSC A E3 NC C NC A A VDD A A NC D DQC DQPC VSS NC VSS DQPB DQB E DQC DQC VSS E1 VSS DQB DQB F VDDQ DQC VSS G VSS DQB VDDQ G DQC2 DQC BC ADV BB DQB DQB2 H DQC DQC VSS GW VSS DQB DQB J VDDQ VDD NC VDD NC VDD VDDQ K DQD DQD VSS CK VSS DQA DQA L DQD DQD BD NC BA DQA DQA M VDDQ DQD VSS BW VSS DQA VDDQ N DQD DQD VSS A1 VSS DQA DQA P DQD DQPD VSS A0 VSS DQPA DQA R NC A LBO VDD FT A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC NC VDDQ 8/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 BGA Pin Description Symbol Type Description A 0, A 1 I Address field LSBs and Address Counter Preset Inputs A I Address Inputs DQA DQB DQC DQD I/O Data Input and Output pins BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/O’s; active low CK I Clock Input Signal; active high BW I Byte Write—Writes all enabled bytes; active low GW I Global Write Enable—Writes all bytes; active low E 1, E 3 I Chip Enable; active low E2 I Chip Enable; active high G I Output Enable; active low ADV I Burst address counter advance enable; active low ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low ZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active low VDD I Core power supply VSS I I/O and Core Ground VDDQ I Output driver power supply NC - No Connect Rev: 1.11 10/2004 9/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 GS840H18/32/36A Block Diagram Register A0–An D Q A0 A0 D0 A1 Q0 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q Register D 36 Q BB 36 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D Q Register E1 E3 E2 D Q Register D Q FT G ZZ 1 Power Down DQx1–DQx9 Control Note: Only x36 version shown for simplicity. Rev: 1.11 10/2004 10/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ State Function L Linear Burst H or NC Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB Note: There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Linear Burst Sequence Interleaved Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 Note: The burst counter wraps to initial state on the 5th clock. Rev: 1.11 10/2004 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. 11/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte A H L L H H H 2, 3 Write byte B H L H L H H 2, 3 Write byte C H L H H L H 2, 3, 4 Write byte D H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Rev: 1.11 10/2004 12/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Synchronous Truth Table Operation Address Used State Diagram Key5 E1 E2 Deselect Cycle, Power Down None X H X X Deselect Cycle, Power Down None X L F Deselect Cycle, Power Down None X L Read Cycle, Begin Burst External R Read Cycle, Begin Burst External Write Cycle, Begin Burst ADV W3 DQ4 L X X High-Z L X X X High-Z F H L X X High-Z L T L X X X Q R L T H L X F Q External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CW H X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D ADSP ADSC Write Cycle, Suspend Burst Current H X X H H T D Notes: 1. X = Don’t Care, H = High, L = Low. 2. E = T (True) if E2 = 1 and E3 = 0; E = F (False) if E2 = 0 or E3 = 1. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as “Q” in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.11 10/2004 13/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low. 2. The upper portion of the diagram assumes active use of only the Enable (E1, E2, E3) and Write (BA, BB, BC, BD, BW and GW) control inputs and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.11 10/2004 14/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.11 10/2004 15/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins –0.5 to 4.6 V VDDQ Voltage in VDDQ Pins –0.5 to 4.6 V VI/O Voltage on I/O Pins –0.5 to VDDQ +0.5 (≤ 4.6 V max.) V VIN Voltage on Other Input Pins –0.5 to VDD +0.5 (≤ 4.6 V max.) V IIN Input Current on Any Pin +/–20 mA IOUT Output Current on Any I/O Pin +/–20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature –55 to 125 o TBIAS Temperature Under Bias –55 to 125 o C C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 3.3 V Supply Voltage VDD3 3.0 3.3 3.6 V 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 3.3 V VDDQ I/O Supply Voltage VDDQ3 3.0 3.3 3.6 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V Notes Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.11 10/2004 16/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 VDDQ3 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 2.0 — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.8 V 1 VDDQ I/O Input High Voltage VIHQ 2.0 — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.8 V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ2 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD — VDD + 0.3 V 1 VDD Input Low Voltage VIL –0.3 — 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD — VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ –0.3 — 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA –40 25 85 °C 2 Notes: 1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. Rev: 1.11 10/2004 17/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 50% tKC VDD + 2.0 V VSS 50% 50% VDD VSS – 2.0 V 50% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. AC Test Conditions Parameter Conditions Input high level VDD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50Ω 30pF* VDDQ/2 * Distributed Test Jig Capacitance Rev: 1.11 10/2004 18/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA ZZ Input Current IIN1 VDD ≥ VIN ≥ VIH 0 V ≤ VIN ≤ VIH –1 uA –1 uA 1 uA 100 uA FT, SCD, ZQ Input Current IIN2 VDD ≥ VIN ≥ VIL 0 V ≤ VIN ≤ VIL –100 uA –1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V — Output High Voltage VOH3 IOH = –8 mA, VDDQ = 3.135 V 2.4 V — Output Low Voltage VOL IOL = 8 mA — 0.4 V Operating Currents -180 -150 -100 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C 0 to 70°C –40 to 85°C Unit IDD Pipeline 335 345 310 320 280 290 190 200 mA IDD Flow Through 210 220 190 200 165 175 135 145 mA ISB Pipeline 20 30 20 30 20 30 20 30 mA ISB Flow Through 20 30 20 30 20 30 20 30 mA IDD Pipeline 55 65 50 60 50 60 40 50 mA IDD Flow Through 40 50 40 50 35 45 35 45 mA Parameter Test Conditions Symbol Operating Current Device Selected; All other inputs ≥VIH or ≤ VIL Output open Standby Current ZZ ≥ VDD – 0.2 V Deselect Current Device Deselected; All other inputs ≥ VIH or ≤ VIL Rev: 1.11 10/2004 -166 19/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 AC Electrical Characteristics Pipeline Flow Through Parameter Symbol Clock Cycle Time -180 -166 -150 -100 Unit Min Max Min Max Min Max Min Max tKC 5.5 — 6.0 — 6.7 — 10 — ns Clock to Output Valid tKQ — 3.0 — 3.5 3.8 — 4.5 ns Clock to Output Invalid tKQX 1.5 — 1.5 — — 1.5 — 1.5 — ns Clock to Output in Low-Z 1 tLZ 1.5 — 1.5 — 1.5 — 1.5 — ns Clock Cycle Time tKC 9.0 — 10.0 — 12.0 — 15.0 — ns Clock to Output Valid tKQ — 8.0 — 8.5 — 10.0 — 12.0 ns Clock to Output Invalid tKQX 3.0 — 3.0 — 3.0 — 3.0 — ns Clock to Output in Low-Z tLZ1 3.0 — 3.0 — 3.0 — 3.0 — ns Clock HIGH Time tKH 1.3 — 1.3 — 1.3 — 1.3 — ns Clock LOW Time tKL 1.5 — 1.5 — 1.5 — 1.5 — ns Clock to Output in High-Z tHZ1 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns G to Output Valid tOE — 3.2 — 3.5 — 3.8 — 5 ns G to output in Low-Z 1 tOLZ 0 — 0 — 0 — 0 — ns G to output in High-Z tOHZ1 — 3.2 — 3.5 — 3.8 — 5 ns Setup time tS 1.5 — 1.5 — 1.5 — 2.0 — ns Hold time tH 0.5 — 0.5 — 0.5 — 0.5 — ns ZZ setup time tZZS2 5 — 5 — 5 — 5 — ns ZZ hold time tZZH2 1 — 1 — 1 — 1 — ns ZZ recovery tZZR 20 — 20 — 20 — 20 — ns Notes: 1. These parameters are sampled and are not 100% tested 2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.11 10/2004 20/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Pipeline Mode Timing Begin Read A Cont Cont Single Read Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Single Write tKL tKH tKC Deselect Burst Read CK ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An A B C tS GW tS tH BW tH tS Ba–Bd tS Deselected with E1 tH E1 masks ADSP E1 tS tH E2 and E3 only sampled with ADSP and ADSC E2 tS tH E3 G tS tOE DQa–DQd Rev: 1.11 10/2004 tOHZ Q(A) tKQ tH D(B) tKQX tLZ tHZ Q(C) 21/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+1) Q(C+2) Q(C+3) © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Flow Through Mode Timing Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect tKL tKH tKC CK ADSP Fixed High tS tH tS tH ADSC initiated read ADSC tS tH ADV tS tH A0–An A B C tS tH GW tS tH BW tS tH Ba–Bd tS Deselected with E1 tH E1 tS tH E2 and E3 only sampled with ADSC E2 tS tH E3 G tH tS tOE DQa–DQd Rev: 1.11 10/2004 tOHZ Q(A) D(B) tKQ tLZ tHZ tKQX Q(C) Q(C+1) Q(C+2) 22/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q(C+3) Q(C) © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Sleep Mode Timing Diagram tKH tKC tKL CK Setup Hold ADSP ADSC tZZR tZZS tZZH ZZ Application Tips Single and Dual Cycle Deselect SCD devices force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. Rev: 1.11 10/2004 23/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 GS840H18/32/36A Output Driver Characteristics 120.0 100.0 Pull Down Drivers 80.0 60.0 40.0 20.0 VDDQ I Out (mA) I Out 0.0 VOut VSS -20.0 -40.0 -60.0 Pull Up Drivers -80.0 -100.0 -120.0 -140.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.6V PD HD Rev: 1.11 10/2004 3.3V PD HD 3.1V PD HD 3.1V PU HD 3.3V PU HD 24/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 3.6V PU HD © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 TQFP Package Drawing (Package T) L Min. Nom. Max A1 Standoff 0.05 0.10 0.15 A2 Body Thickness 1.35 1.40 1.45 b Lead Width 0.20 0.30 0.40 c Lead Thickness 0.09 — 0.20 D Terminal Dimension 21.9 22.0 22.1 D1 Package Body 19.9 20.0 20.1 E Terminal Dimension 15.9 16.0 16.1 E1 Package Body 13.9 14.0 14.1 e Lead Pitch — 0.65 — L Foot Length 0.45 0.60 0.75 L1 Lead Length — 1.00 — Y Coplanarity θ Lead Angle e D D1 Description b A1 A2 0.10 — Y 0° c Pin 1 Symbol L1 θ 7° E1 E Notes: 1. All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 1.11 10/2004 25/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Package Dimensions—119-Bump FPBGA (Package B, Variation 1) Pin #1 Corner BOTTOM VIEW A1 Ø0.10S C Ø0.30S C AS B S Ø0.60~0.90 (119x) 1 2 3 4 5 6 7 Ø1.00(3x) REF 20.32 22±0.20 19.50 B 0.70 REF 1.27 7.62 12.00 14±0.20 C Rev: 1.11 10/2004 SEATING PLANE 0.50~0.70 2.06.±0.13 0.15 C 0.90±0.10 0.15 C A 0.20(4x) 0.56±0.05 A B C D E F G H J K L M N P R T U 1.27 A B C D E F G H J K L M N P R T U 7 6 5 4 3 2 1 26/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs Speed2 T 3 (MHz/ns) A Org Part Number1 Type Package 256K x 18 GS840H18AT-180 Pipeline/Flow Through TQFP 180/8 C 256K x 18 GS840H18AT-166 Pipeline/Flow Through TQFP 166/8.5 C 256K x 18 GS840H18AT-150 Pipeline/Flow Through TQFP 150/10 C 256K x 18 GS840H18AT-100 Pipeline/Flow Through TQFP 100/12 C 128K x 32 GS840H32AT-180 Pipeline/Flow Through TQFP 180/8 C 128K x 32 GS840H32AT-166 Pipeline/Flow Through TQFP 166/8.5 C 128K x 32 GS840H32AT-150 Pipeline/Flow Through TQFP 150/10 C 128K x 32 GS840H32AT-100 Pipeline/Flow Through TQFP 100/12 C 128K x 36 GS840H36AT-180 Pipeline/Flow Through TQFP 180/8 C 128K x 36 GS840H36AT-166 Pipeline/Flow Through TQFP 166/8.5 C 128K x 36 GS840H36AT-150 Pipeline/Flow Through TQFP 150/10 C 128K x 36 GS840H36AT-100 Pipeline/Flow Through TQFP 100/12 C 256K x 18 GS840H18AT-180I Pipeline/Flow Through TQFP 180/8 I 256K x 18 GS840H18AT-166I Pipeline/Flow Through TQFP 166/8.5 I 256K x 18 GS840H18AT-150I Pipeline/Flow Through TQFP 150/10 C 256K x 18 GS840H18AT-100I Pipeline/Flow Through TQFP 100/12 C 128K x 32 GS840H32AT-180I Pipeline/Flow Through TQFP 180/8 I 128K x 32 GS840H32AT-166I Pipeline/Flow Through TQFP 166/8.5 I 128K x 32 GS840H32AT-150I Pipeline/Flow Through TQFP 150/10 C 128K x 32 GS840H32AT-100I Pipeline/Flow Through TQFP 100/12 C 128K x 36 GS840H36AT-180I Pipeline/Flow Through TQFP 180/8 I 128K x 36 GS840H36AT-166I Pipeline/Flow Through TQFP 166/8.5 I 128K x 36 GS840H36AT-150I Pipeline/Flow Through TQFP 150/10 C 128K x 36 GS840H36AT-100I Pipeline/Flow Through TQFP 100/12 C 256K x 18 GS840H18AGT-180 Pipeline/Flow Through Pb-free TQFP 180/8 C 256K x 18 GS840H18AGT-166 Pipeline/Flow Through Pb-free TQFP 166/8.5 C 256K x 18 GS840H18AGT-150 Pipeline/Flow Through Pb-free TQFP 150/10 C 256K x 18 GS840H18AGT-100 Pipeline/Flow Through Pb-free TQFP 100/12 C 128K x 32 GS840H32AGT-180 Pipeline/Flow Through Pb-free TQFP 180/8 C Status 128K x 32 GS840H32AGT-166 Pipeline/Flow Through Pb-free TQFP 166/8.5 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840H32AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.11 10/2004 27/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs (Continued) Speed2 T 3 (MHz/ns) A Org Part Number1 Type Package 128K x 32 GS840H32AGT-150 Pipeline/Flow Through Pb-free TQFP 150/10 C 128K x 32 GS840H32AGT-100 Pipeline/Flow Through Pb-free TQFP 100/12 C 128K x 36 GS840H36AGT-180 Pipeline/Flow Through Pb-free TQFP 180/8 C 128K x 36 GS840H36AGT-166 Pipeline/Flow Through Pb-free TQFP 166/8.5 C 128K x 36 GS840H36AGT-150 Pipeline/Flow Through Pb-free TQFP 150/10 C 128K x 36 GS840H36AGT-100 Pipeline/Flow Through Pb-free TQFP 100/12 C 256K x 18 GS840H18AGT-180I Pipeline/Flow Through Pb-free TQFP 180/8 I 256K x 18 GS840H18AGT-166I Pipeline/Flow Through Pb-free TQFP 166/8.5 I 256K x 18 GS840H18AGT-150I Pipeline/Flow Through Pb-free TQFP 150/10 C 256K x 18 GS840H18AGT-100I Pipeline/Flow Through Pb-free TQFP 100/12 C 128K x 32 GS840H32AGT-180I Pipeline/Flow Through Pb-free TQFP 180/8 I 128K x 32 GS840H32AGT-166I Pipeline/Flow Through Pb-free TQFP 166/8.5 I 128K x 32 GS840H32AGT-150I Pipeline/Flow Through Pb-free TQFP 150/10 C 128K x 32 GS840H32AGT-100I Pipeline/Flow Through Pb-free TQFP 100/12 C 128K x 36 GS840H36AGT-180I Pipeline/Flow Through Pb-free TQFP 180/8 I 128K x 36 GS840H36AGT-166I Pipeline/Flow Through Pb-free TQFP 166/8.5 I 128K x 36 GS840H36AGT-150I Pipeline/Flow Through Pb-free TQFP 150/10 C 128K x 36 GS840H36AGT-100I Pipeline/Flow Through Pb-free TQFP 100/12 C 256K x 18 GS840H18AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C 256K x 18 GS840H18AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C 256K x 18 GS840H18AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C 256K x 18 GS840H18AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C 128K x 32 GS840H32AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C 128K x 32 GS840H32AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C 128K x 32 GS840H32AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C 128K x 32 GS840H32AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C 128K x 36 GS840H36AB-180 Pipeline/Flow Through 119 BGA (var. 1) 180/8 C 128K x 36 GS840H36AB-166 Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 C 128K x 36 GS840H36AB-150 Pipeline/Flow Through 119 BGA (var. 1) 150/10 C 128K x 36 GS840H36AB-100 Pipeline/Flow Through 119 BGA (var. 1) 100/12 C Status 256K x 18 GS840H18AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840H32AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.11 10/2004 28/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 Ordering Information for GSI Synchronous Burst RAMs (Continued) Speed2 T 3 (MHz/ns) A Org Part Number1 Type Package 256K x 18 GS840H18AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I 256K x 18 GS840H18AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 C 256K x 18 GS840H18AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 C 128K x 32 GS840H32AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I 128K x 32 GS840H32AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I 128K x 32 GS840H32AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 C 128K x 32 GS840H32AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 C 128K x 36 GS840H36AB-180I Pipeline/Flow Through 119 BGA (var. 1) 180/8 I 128K x 36 GS840H36AB-166I Pipeline/Flow Through 119 BGA (var. 1) 166/8.5 I 128K x 36 GS840H36AB-150I Pipeline/Flow Through 119 BGA (var. 1) 150/10 C Status 128K x 36 GS840H36AB-100I Pipeline/Flow Through 119 BGA (var. 1) 100/12 C Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS840H32AT-8T. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipelined mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.11 10/2004 29/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology GS840H18/32/36AT/B-180/166/150/100 4Mb Burst Datasheet Revision History Rev. Code: Old; New GS84018/32/36 Rev 1.02c 5/ 1999; GS84018/32/36 8/1999D Types of Changes Page /Revisions;Reason Format or Content Format/Typos Content Format/Typos GS84018/32/36 8/ 1999;GS84018/32/36 9/ 1999E Content • Document/Continued changing to new format. • • Took “E” out of 840HE...in Core and Interface Voltages. • Pin outs/New small caps format. • Timing Diagrams/New format. • Block Diagrams/New small caps format. • Pin outs/x32 & x36 TQFP/Changed pin 72 from DQA3 to DQB3. • Pin Description/Rearranged Address Inputs to match order on TQFP Pinout. • TQFP Package Diagram/Corrected Dimension D Max from 20.1 to 22.1. GS84018/32/36 9/ 1999E;GS84018/32/36 • GS84018/32/3610-11/ 1999;GS84018/32/362/ 2000G Format • New GSI Logo • Took “Pin” out of heading for consistency. GS84018/32/362/2000G; 840H18A_r1_04 Content 840H18A_r1_04; 840H18A_r1_05 Content 840H18A_r1_05; 840H18A_r1_06 Content • Corrected all part order numbers • Updated pin description table • Updated BGA pin description table to meet JEDEC standard • Updated table on page 1 • Updated Operating Currents table on page 18 • Updated AC Electrical Characteristics table on page 19 • Added 150 MHz and 100 MHz • Updated format to comply with Technical Publications standards 840H18A_r1_06; 840H18A_r1_07 Content/Format 840H18A_r1_07; 840E18_r1_08 Content 840H18A_r1_08; 840H18_r1_09 Content 840H18A_r1_09; 840H18A_r1_10 Content • Updated format • Matched current numbers to NBT parts • Removed Preliminary banner 840H18A_r1_10; 840H18A_r1_11 Content • Added Pb-free TQFP information • Added variation number to 119 BGA information Rev: 1.11 10/2004 • Reduced IDD by 20 mA in table on page 1 and Operating Currents table • Removed 200 MHz references from entire datasheet 30/30 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 1999, GSI Technology