INNOVASIC IA188EM-PQF100I 8/16-bit microcontroller Datasheet

IA186EM/IA188EM
8/16-Bit Microcontrollers
Data Sheet
Copyright ! 2004
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Contents
Features......................................................................................................................................................4
Description ...............................................................................................................................................5
Bus Interface and Control ................................................................................................................7
Peripheral Control and Registers ..................................................................................................7
Clock and Power Management ....................................................................................................49
System Clocks..........................................................................................................................................49
Power-Save Mode ....................................................................................................................................50
Initialization and Reset.............................................................................................................................50
Reset Configuration Register ...................................................................................................................50
Chip-Selects .............................................................................................................................................50
Chip-Select Timing ..................................................................................................................................50
Ready and Wait-State Programming........................................................................................................50
Chip-Select Overlap .................................................................................................................................51
Upper Memory Chip Select .....................................................................................................................52
Low Memory Chip Select ........................................................................................................................52
Midrange Memory Chip Selects ..............................................................................................................52
Peripheral Chip Selects ............................................................................................................................52
Refresh Control ........................................................................................................................................53
Interrupt Control ......................................................................................................................................53
Interrupt Types .....................................................................................................................................54
Interrupt Table Notes ...........................................................................................................................55
Timer Control...........................................................................................................................................55
Direct Memory Access (DMA)................................................................................................................56
DMA Operation .......................................................................................................................................56
DMA Channel Control Registers .........................................................................................................56
DMA Priority .......................................................................................................................................57
Asynchronous Serial Port ...............................................................................................................58
Synchronous Serial Port ..................................................................................................................58
Programmable I/O (PIO) ................................................................................................................59
Pin Descriptions ..................................................................................................................................60
Instruction Set Summary ................................................................................................................71
Key to Abbreviations Used Instruction Summary Table .........................................................................85
Absolute Maximum Ratings .........................................................................................................90
DC Characteristics Over Commercial Operating Ranges ..............................................90
AC Characteristics Over Commercial Operating Ranges (40 MHz) ...........................................................91
Waveforms .............................................................................................................................................94
Alphabetic Key to Waveform Parameters................................................................................................94
Numeric Key to Waveform Parameters ...................................................................................................95
Read Cycle Timing ..................................................................................................................................97
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Write Cycle ..............................................................................................................................................98
Write Cycle Timing .................................................................................................................................99
PSRAM Read Cycle...............................................................................................................................100
PSRAM Read Cycle Timing..................................................................................................................101
PSRAM Write Cycle..............................................................................................................................102
PSRAM Write Cycle Timing .................................................................................................................103
PSRAM Refresh Cycle ..........................................................................................................................104
PSRAM Refresh Cycle ..........................................................................................................................104
Interrupt Acknowledge Cycle ................................................................................................................105
Interrupt Acknowledge Cycle Timing ...................................................................................................106
Software Halt Cycle ...............................................................................................................................107
Software Halt Cycle Timing ..................................................................................................................107
Clock – Active Mode .............................................................................................................................108
Clock – Power-Save Mode ....................................................................................................................108
Clock Timing .........................................................................................................................................108
srdy – Synchronous Ready.....................................................................................................................109
ardy - Asynchronous Ready ..................................................................................................................109
Peripherals..............................................................................................................................................109
Ready and Peripheral Timing.................................................................................................................109
Reset 1....................................................................................................................................................110
Reset 2....................................................................................................................................................110
Bus Hold Entering..................................................................................................................................111
Bus Hold Leaving ..................................................................................................................................111
Reset and Bus Hold Timing ...................................................................................................................111
Synchronous Serial Interface .................................................................................................................112
Synchronous Serial Interface Timing ....................................................................................................112
IA186EM 100-Pin PQFP ...........................................................................................................................113
IA186EM TQFP 100-Pin ...........................................................................................................................116
IA188EM 100-Pin PQFP ...........................................................................................................................119
IA188EM 100-Pin TQFP ...........................................................................................................................122
Physical Dimensions ..................................................................................................................................125
PQFP 100 ...............................................................................................................................................125
TQFP 100 .............................................................................................................................................127
Ordering Information......................................................................................................................128
Errata .......................................................................................................................................................129
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Please Note
Included in the Ordering Information section on page 128 of this manual are enhanced RoHS-compliant
versions of the IA186 and IA188 family of microcontrollers. However, standard packaged or non RoHScompliant versions of the IA186 and IA188 microcontrollers are still available.
Features
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Pin-for-pin compatible with AMD# Am186EM/188EM devices
All features are retained, including:
" PLL allowing same crystal/system clock frequency
" 8086/8088 instruction set with additional 186 instruction set extensions
" Programmable interrupt controller
" Two DMA channels
" Three 16-bit timers
" Programmable chip select logic and wait-state generator
" Dedicated watch dog timer
" Two independent asynchronous serial ports (UARTs)
o DMA capability
o Hardware flow control
o 7-, 8-, or 9-bit data capability
" Pulse Width Demodulator feature
" Up to 32 programmable I/O pins (PIO)
Pseudo-static/dynamic RAM controller
Fully static CMOS design
40 MHz operation at industrial operating conditions
+5 VDC power supply
Available packages:
o 100-pin Thin Quad Flat Pack (TQFP)
o 100-pin Plastic Quad Flat Pack (PQFP)
The IA186EM/188EM is a form, fit and function replacement for the original Advanced Micro Devices#
Am186EM/188EM family of microcontrollers. Innovasic produces replacement ICs using its MILESTM,
or Managed IC Lifetime Extension System cloning technology. This technology produces replacement
ICs far more complex than "emulation" while ensuring they are compatible with the original IC.
MILESTM captures the design of a clone so it can be produced even as silicon technology advances.
MILESTM also verifies the clone against the original IC so that even the "undocumented features" are
duplicated.
This data sheet contains preliminary information for the IA186EM/188EM. The complete data sheet
which documents all necessary engineering information about the IA186EM/188EM including functional
and I/O descriptions, electrical characteristics, and applicable timing will be available when the device
nears completion.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Description
The IA186EM/188EM family of microcontrollers replaces obsolete AMD# Am186EM/188EM devices,
allowing customers to retain existing board designs, software compilers/assemblers and emulation tools,
thereby avoiding expensive redesign efforts.
The IA186EM/188EM microcontrollers are an upgrade for the 80C186/188 microcontroller designs, with
integrated peripherals to provide increased functionality and reduce system costs. The Innovasic devices
are created to satisfy requirements of embedded products designed for telecommunications, office
automation and storage and industrial controls.
A block diagram of the IA186EM/188EM microcontroller is depicted in Figure 1. The IA186EM/188EM
microcontroller consists of the following functional blocks, with brief discussions of each afterwards.
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Bus Interface and Control
Peripheral Control and Registers
Chip Selects and Control
Programmable I/O
Clock and Power Management
Direct Memory Access (DMA)
Interrupt Controller
Timers
Asynchronous Serial Ports
Synchronous Serial Interface.
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IA186EM/IA188EM
Data Sheet
Vcc
gnd
s2_n - s0_n
As of Production Version -03
dt/r_n
hlda
srdy
den_n/ds_n
ardy
s6/clkdiv2_n
hold
uzi_n
8/16-BIT Microcontrollers
a[19:0]
Clock and
Power Management
ad[15:0]
ale
den_n
clkouta
clkoutb
Bus Interface & Control
wr_n
wlb_n
whb_n
rd_n
drq0
Direct Memory Access
drq1
res_n
int4
int3/inta1_n/irq
Peripheral Control and
Registers
Interrupt Controller
int1/select_n
int0
nmi
Timers
lcs_n/once0_n
mcs3_n/rfsh_n
ucs_n/once1_n
pcs5_n/a1
pcs6_n/a2
mcs2_n - mcs0_n
int2/inta0_n
tmrin0
tmrout0
tmrin1
tmrout1
Chip Selects and Control
txd0
Asynchronous Serial
Port
pcs3_n - pcs0_n
rxd0
cts0_n/enrx0_n
rts0_n/rtr0_n
sclk
pio[31:0]
Synchronous Serial Port
Programmable I/O
sden0
sden1
sdata
Instruction Decode
and Execution
Figure 1. IA186/88EM Block Diagram
NOTE
See pin descriptions for pins that share other functions with PIO pins.
pwd, int5, int6, rts1_n/rtr1_n, and cts1_n/enrx1_n are multiplexed with int2_n/inta0_n, drq0_n,
drq0_n, pcs3_n, and pcs2_n respectively.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Bus Interface and Control
Bus Interface and Control (BIC) manages all accesses to external memory and external peripherals. These
peripherals may be mapped either in memory space or I/O space. The BIC supports both multiplexed and
non-multiplexed bus operations. Multiplexed address and data are provided on the ad [15:0] bus, while a
non-multiplexed address is provided on the a [19:0] bus. The A bus provides address information for the
entire bus cycle (t1-t4), while the ad bus provides address information only during the first (t1) phase of
the bus cycle. For more details regarding bus cycles, see the AC waveforms at the end of this datasheet.
The IA186EM microcontroller provides two signals that serve as byte write enables: write high byte
(whb_n) and write low byte (wlb_n). Obviously, the IA188EM microcontroller requires only a single
write byte (wb_n) signal to support its 8-bit data bus. whb_n is the logical OR of the bhe_n and wr_n.
wlb_n is the logical OR of ad0 and wr_n. wlb_n is the logical OR of ad0 and wr_n. wb_n is low
whenever a byte is written to the IA188EM data bus ad[7:0].
The byte write enables are driven in conjunction with the non-multiplexed address bus a[19:0] to
facilitate meeting the timing requirements of common SRAMs.
The BIC also provides support for Pseudo-Static RAM (PSRAM) devices. PSRAM is supported in the
lower chip select (lcs_n) area only. In order to support PSRAM, the Chip Selects and Control (CSC) must
be appropriately programmed. For details regarding this operation, see Chip Selects.
Peripheral Control and Registers
The on-chip peripherals in the IA186EM/188EM microcontroller are controlled from a 256-byte block of
internal registers. Although these registers are actually located in the peripherals they control, they are
addressed within a single 256-byte block of I/O spaced and are therefore treated as a functional unit for
the purposes of this document.
A map of these registers is depicted in Table 1.
All write operations performed on the IA188EM should be 8-bit writes, which will still result in 16-bit
data transfers to the Peripheral Control Block (PCB) register even if the named register is an 8-bit register.
Any read performed to the PCB registers should be word reads. Code written with these points in mind
will run correctly on both the IA186EM and IA188EM.
However, unpredictable behavior will result in both the IA186EM and IA188EM processors if unaligned
read and write accesses are performed.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Register Name
Peripheral Control Block Registers
Offset
PCB Relocation Register
Reset Configuration Register
Processor Release Level Register
Power-Save Control Register
FEh
F6h
F4h
F0h
Enable RCU Register
Clock Prescaler Register
Memory Partition Register
E4h
E2h
E0h
DMA Registers
DMA1 Control Register
DMA1 Transfer Count Register
DMA1 Destination Address High Register
DMA1 Destination Address Low Register
DMA1 Source Address High Register
DMA1 Source Address Low Register
DMA0 Control Register
DMA0 Transfer Count Register
DMA0 Destination Address High Register
DMA0 Destination Address Low Register
DMA0 Source Address High Register
DMA0 Source Address Low Register
DAh
D8h
D6h
D4h
D2h
D0h
CAh
C8h
C6h
C4h
C2h
C0h
Chip-Select Registers
pcs_n and mcs_n Auxiliary Register
Mid-Range Memory Chip-Select Register
Peripheral Chip-Select Register
Low-Memory Chip-Select Register
Upper-Memory Chip-Select Register
A8h
A6h
A4h
A2h
A0h
Asynchronous Serial Port Register
Serial Port Baud Rate Divisor Register
Serial Port Receive Register
Serial Port Transmit Register
Serial Port Status Register
Serial Port Control Register
88h
86h
84h
82h
80h
PIO Registers
PIO Data 1 Register
PIO Direction 1 Register
PIO Mode 1 Register
PIO Data 0 Register
PIO Direction 0 Register
PIO Mode 0 Register
7Ah
78h
76h
74h
72h
70h
As of Production Version -03
Register Name
Timer Registers
Offset
Timer 2 Mode & Control Register
Timer 2 Max Count Compare A Register
Timer 2 Count Register
Timer 1 Mode & Control Register
Timer 1 Max Count Compare B Register
Timer 1 Max Count Compare A Register
Timer 1 Count Register
Timer 0 Mode & Control Register
Timer 0 Max Count Compare B Register
Timer 0 Max Count Compare A Register
Timer 0 Count Register
66h
62h
60h
5Eh
5Ch
5Ah
58h
56h
54h
52h
50h
Interrupt Registers
Serial Port 0 Interrupt Control Register
Watchdog Timer Control Register
INT4 Interrupt Control Register
INT3 Interrupt Control Register
INT2 Interrupt Control Register
INT1 Interrupt Control Register
INT0 Interrupt Control Register
DMA1 Interrupt Control Register
DMA0 Interrupt Control Register
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
In-Service Register
Priority Mask Register
Interrupt Mask Register
Poll Status Register
Poll Register
End-of-Interrupt (EOI) Register
Interrupt Vector Register
44h
42h
40h
3Eh
3Ch
3Ah
38h
36h
34h
32h
30h
2Eh
2Ch
2Ah
28h
26h
24h
22h
20h
Synchronous Serial Port Register
Synchronous Serial Receive Register
Synchronous Serial Transmit 0 Register
Synchronous Serial Transmit 1 Register
Synchronous Serial Enable Register
Synchronous Serial Status Register
Table 1. Map of Peripheral Control Registers
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18h
16h
14h
12h
10h
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
RELREG (0feh) - The Peripheral Control Block RELocation REGister maps the entire Peripheral
Control Block Register Bank to either I/O or memory space. In addition, RELREG contains a bit which
places the Interrupt Controller in either Master or Slave mode.
The RELREG contains 20ffh at reset.
15
14
RES
S/Mn
13
12
11
10
9
8
7
RES IO/Mn
6
5
4
3
2
1
0
RA [19:8]
RES (bit 15) - Reserved.
S/Mn (bit 14) – A 1 in this bit places the Interrupt Controller into slave mode. When set to zero, the
Interrupt Controller is in master mode.
RES (bit 13) - Reserved.
IO/Mn (bit 12)- A 1 in this bit maps the Peripheral Control Block Register Bank into IO space. When
set to zero, the Peripheral Control Block is mapped into memory space.
RA [19:8] (bits 11-0) – Sets the base address (upper 12 bits) of the Peripheral Control Block Register
Bank. RA [7:0} default to zero. Note that when bit 12 (IO/M_n) is a 1, RA [19:16] are ignored.
RESCON (0f6h) - The RESet CONfiguration Register latches user-defined information present at
specified pins at the rising edge of reset. This contents of this register are read-only and remain valid until
the next reset.
The RESCON contains user-defined information at reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RC [15:0]
RC [15:0] (bits 15-0) – At the rising edge of reset, the values of specified pins (ad [15:0] for the
IA186Es and {ao [15:8], ad [7:0]} for the IA188EM) are latched into this register.
PRL (0f4h) - The Processor Release Level Register contains a code corresponding to the latest processor
production release. The PRL is a Read-Only Register
The PRL contains 0400h.
15
14
13
12
11
10
9
8
7
PRL [7:0]
6
5
4
3
2
1
0
RES
PRL [7:0] (bits 15-8) – The latest Processor Release Level.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
PRL Value Processor Release Level
01h
C
02h
D
03h
E
04h
F
RES (bits 7-0) – Reserved.
PDCON (0f0h) - The Power-save CONtrol Register controls several miscellaneous system I/O and
timing functions.
The SYSCON contains 0000h at reset.
15
14
PSEN
13
RES
12
11
10
9
8
CBF CBD CAF CAD
7 6 5 4 3
RES
2
1
0
F2 F1 F0
PSEN (bit 15) – When set to 1, enables the power-save mode causing the internal operating clock to
be divided by the value in F2-F0. External interrupts or interrupts from internal interrupts
automatically clear PSEN. Software interrupts and exception do not clear PSEN. Note that the value of
PSEN is not restored upon execution of an IRET instruction.
RES (bit 14-12) – Reserved. These bits read back as zeros.
CBF (bit 11) – When set to 1, the clkoutb output follows the input crystal (PLL) frequency. When
this bit is 0, the clkoutb follows the internal clock frequency after the clock divider.
CBD (bit 10) – When set to 1, the clkoutb output is pulled low. When this bit is 0, the clkoutb is
driven as an output per the CBF bit.
CAF (bit 9) – When set to 1, the clkouta output follows the input crystal (PLL) frequency. When this
bit is 0, the clkouta follows the internal clock frequency after the clock divider.
CAD (bit 8) – When set to 1, the clkouta output is pulled low. When this bit is 0, the clkouta is driven
as an output per the CBF bit.
RES (bits 7-3) – Reserved. These bits read back as zeros.
F2-F0 (bits 2-0) – These bits control the clock divider as shown below. Note that PSEN must be 1 for
the clock divider to function.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
F2 F1 F0
Divider Factor
0
0
0
Divide by 1 (20)
0
0
1
Divide by 2 (21)
0
1
0
Divide by 4 (22)
0
1
1
Divide by 8 (23)
1
0
0 Divide by 16 (24)
1
0
1 Divide by 32 (25)
1
1
0 Divide by 64 (26)
1
1
1 Divide by 128 (27)
EDRAM (0e4h) - The Enable RCU Register provides control and status for the refresh counter.
The EDRAM register contains 0000h at reset.
15
14
13
12
11
10
9
E
0
0
0
0
0
0
8
7 6 5 4 3
2
1
0
T [8:0]
E (bit 15) – When set to 1, the refresh counter is enabled and msc3_n is configured to act as rfsh_n.
Clearing E clears the refresh counter and disables refresh requests. The refresh address is unaffected
by clearing E.
RES (bits 14-9) – Reserved. These bits read back as 0.
T [8:0] (bits 8-0) – These bits hold the current value of the refresh counter. These bits are read-only.
CDRAM (0e2h) - The Clock Prescaler Register determines the period between refresh cycles.
The CDRAM register is undefined at reset.
15
14
13
12
11
10
9
0
0
0
0
0
0
0
8
7 6 5 4 3
2
1
0
RC [8:0]
RES (bits 15-9) – Reserved. These bits read back as 0.
RC [8:0] (bits 8-0) – These bits hold the clock count interval between refresh cycles. This value
should not be set to less than 18 (12h), else there would never be sufficient bus cycles available for the
processor to execute code.
In power-save mode, the refresh counter value should be adjusted to account for the clock divider
value in SYSCON.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
MDRAM (0e0h) - The Memory Partition Register holds the A19-A13 address bits of the 20-bit base
refresh address.
The MDRAM register contains 0000h at reset.
15
14
13
12
11
10
9
M [6:0]
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
M [6:0] (bits 15-9) – Upper bits corresponding to address bits a19-a13 of the 20-Bit memory refresh
address. These bits are not available on the a19-a0 bus. When using PSRAM mode, M6-M0 must be
programmed to 0000000b.
Reserved [8:0] (bits 8-0) – Reserved. These bits read back as 0.
D1CON (0dah) - DMA CONtrol Registers.
D0CON (0cah)
DMA Control Registers control operation of the two DMA channels. The D0CON and D1CON registers
are undefined at reset, except ST that is set to 0.
15
14
13
12
11
10
9
8
DM/IOn
DDEC
DINC
SM/IOn
SDEC
SINC
TC
INT
7
6
5
4
3
2
1
0
SYN1SYN0
P
TDRQ
Res
CHG
ST
Bn/W
DM/IOn (bit 15) – Destination Address Space Select selects memory or I/O space for the destination
address. When DM/IO is set to 1, the destination address is in memory space. When set to 0, the
destination address is in I/O space.
DDEC (bit 14) – Destination Decrement automatically decrements the destination address after each
transfer when set to 1. The address is decremented by 1 or 2, depending on the byte/word bit (Bn/W,
bit 0). The address does not change if the increment and decrement bits are set to the same value (00b
or 11b).
DINC (bit 13) – Destination Increment, when set to 1, automatically increments the destination
address after each transfer. The address is incremented by 1 or 2, depending on the byte/word bit
(Bn/W, bit 0). The address does not change if the increment and decrement bits are set to the same
value (00b or 11b).
SM/IOn (bit 12) – Source Address Space Select selects memory or I/O space for the source address.
When SM/IOn is set to 1, the source address is in memory space, while when 0, the source address is
in I/O space.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
SDEC (bit 11) – Source Decrement, when set to 1, automatically decrements the destination address
after each transfer. The address is decremented by 1 or 2, depending on the byte/word bit (Bn/W, bit
0). The address does not change if the increment and decrement bits are set to the same value (00b or
11b).
SINC (bit 10) – Source Increment, when set to 1, automatically increments the destination address
after each transfer. The address is incremented by 1 or 2, depending on the byte/word bit (Bn/W, bit
0). The address does not change if the increment and decrement bits are set to the same value (00b or
11b).
TC (bit 9) – Terminal Count. The DMA decrements the transfer count for each DMA transfer. When
TC is set to 1, the source or destination synchronized DMA transfers terminate when the count reaches
0, but when TC is set to 0, source or destination synchronized DMA transfers do not terminate when
the count reaches 0. Unsynchronized DMA transfers always end when the count reaches 0,
irrespective of the setting of this bit.
INT (bit 8) – Interrupt. The DMA channel generates an interrupt request on completion of the transfer
count when this bit is set to 1. However, for an interrupt to be generated, the TC bit must also be set
to 1.
SYN1-SYN0 (bits 7-6) – Synchronization Type bits select channel synchronization as shown in the
following table. The value of these bits is ignored if TDRQ (bit 4) is set to 1. A processor reset
causes these bits to be set to 11b.
SYN1
0
0
1
1
SYN0
0
1
0
1
Sync Type
Unsynchronized
Source Synchronized
Destination Synchronized
Reserved
P (bit 5) – Relative Priority. Selects high priority for this channel relative to the other channel during
simultaneous transfers when set to 1.
TDRQ (bit 4) - Timer 2 Synchronization. Enables DMA requests from timer 2, when set to 1, but
disables DMA requests from timer 2 when set to 0.
EXT (bit 3) – Reserved.
CHG (bit 2) – Change Start Bit. This bit must be set to 1, to allow modification of the ST bit during a
write. During a write, when CHG is set to 0, ST is not changed when writing the control word. The
result of reading this bit is always 0.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
ST (bit 1) – Start/Stop DMA Channel. When the start bit is set to 1, the DMA channel is started. The
CHG bit must be set to 1 for this bit to be modified and only during the same register write. A
processor reset causes this bit to be set to 0.
Bn/W (bit 0) – Byte/Word Select. When set to 1, word transfers are selected. When set to 0, byte
transfers are selected. (The IA188EM does not support word transfers and furthermore they are not
supported if the chip selects are programmed for 8-bit transfers.)
D1TC (0d8h) - DMA Transfer Count Registers.
D0TC (0c8h)
The DMA Transfer Count registers are maintained by each DMA channel. They are decremented after
each DMA cycle. The state of the TC bit in the DMA control register has no influence on this activity.
But, if unsynchronized transfers are programmed or if the TC bit in the DMA control word is set, DMA
activity ceases when the transfer count register reaches 0.
The D0TC and D1TC registers are undefined at reset.
15
14
13
12
11
10
9
8
7
6 5 4 3
2
1
0
TC15 – TC0
TC [15:0] (bits 15-0) – DMA Transfer Count contains the transfer count for the respective DMA
channel. Its value is decremented after each transfer.
D1DSTH (0d6h) - The DMA DeSTination Address High Register.
D0DSTH (0c6h)
The 20-bit destination address consists of these four bits combined with the 16-bits of the respective
Destination Address Low Register. A DMA transfer requires that two complete 16-bit registers (high and
low registers) be used for both the source and destination addresses of each DMA channel involved.
These four registers must be initialized. Each address may be incremented or decremented independently
of the other after each transfer. The addresses are incremented or decremented by two for word transfers
and incremented or decremented by 1 for byte transfers.
The D0DSTH and D1DSTH registers are undefined at reset.
15
14
13
12
11
10
9
Reserved
8
7 6 5 4 3
2
1
0
DDA19-DDA16
Reserved [15:4] (bits 15-4) – Reserved.
DDA [19:16] (bits 3-0) – DMA Destination Address High bits are driven onto A19-A16 during the
write phase of a DMA transfer.
DIDSTL (0d4h) - DMA DeSTination Address Low Register.
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8/16-BIT Microcontrollers
As of Production Version -03
D0DSTL (0c4h)
The sixteen bits of these registers are combined with the four bits of the respective DMA Destination
Address High Register to produce a 20-bit destination address.
The D0DSTL and D1DSTL registers are undefined at reset.
15
14
13
12
11
10
9
8
7 6 5 4 3
2
1
0
DDA15 – DDA0
DDA [15:0] (bits 15-0) – DMA Destination Address Low bits are driven onto A15-A0 during the
write phase of a DMA transfer.
D1SRCH (0d2h) - DMA SouRCe Address High Register.
D0SRCH (0c2h)
The 20-bit source address consists of these four bits combined with the 16-bits of the respective Source
Address Low Register. A DMA transfer requires that two complete 16-bit registers in the peripheral
control block (high and low registers) be used for both the source and destination addresses of each DMA
channel involved. Each DMA channel requires that all four address registers be initialized. Each address
may be incremented or decremented independently of the other after each transfer. The addresses are
incremented or decremented by 2 for word transfers and incremented or decremented by 1 for byte
transfers.
The D0SRCH and D1SRCHL registers are undefined at reset.
15
14
13
12
11
10
9
8
Reserved
7 6 5 4 3
2
1
0
DSA19 –DSA16
Reserved [15:4] (bits 15-4) – Reserved
DSA [19:16] (bits 3-0) – DMA Source Address High bits are driven onto A19-A16 during the read
phase of a DMA transfer.
D1SRCL (0d0h) - DMA SouRCe Address Low Register.
D0SRCL (0c0h)
The sixteen bits of these registers are combined with the four bits of the respective DMA Source Address
High register to produce a 20-bit source address.
The D0SRCL and D1SRCL registers are undefined at reset.
15
14
13
12
11
10
9
8
7 6 5 4 3
2
1
DSA15-DSA0
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Data Sheet
8/16-BIT Microcontrollers
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DSA [15:0] (bits 15-0) – DMA Source Address Low bits are placed onto a15-a0 during the read phase
of a DMA transfer.
MPCS (0a8h) - MCS and PCS Auxiliary Register.
This register controls more than one type of chip select, making it different from the other chip select
control registers. The MPCS register contains information for the following, mcs3_n - mcs0_n as well as
pcs6_n - pcs5_n and pcs3_n - pcs0_n.
The MPCS register also contains a bit that configures the pcs6_n - pcs5_n pins as either chip selects or as
alternate sources for the A2 and A1 address bits. Either address bits a1 & a2 or pcs6_n - pcs5_n are
selected to the exclusion of the other. When programmed for address bits, these outputs can be used to
provide latched address bits for a2 & a1
pcs6_n - pcs5_n are high and not active on processor reset. An access to the MPCS register causes the
pins to activate, when the pcs6_n - pcs5_n are configured as address pins. The pcs6_n - pcs5_n pins do
not require corresponding access to the PACS register to be activated.
The value of the MPCS register is undefined at reset.
15
14
13
1
12
11
10
9
M6-M0
8
7
6
5 4 3
2
EX MS 1 1 1 R2
1
0
R1-R0
Reserved (bit 15) – Set to 1.
M [6:0] (bits14-8) MCS_n Block Size – These seven bits determine the total block size for the
MCS3_n - MCS0_n chip selects. The total block size is divided equally among the four chip selects.
The following table shows the relationship between M [6:0] and the size of the memory block.
Total Block
Size
8K
16K
32K
64K
128K
256K
512K
Individual
Select Size
2K
4K
8K
16K
32K
64K
128K
M6 – M0
0000001b
0000010b
0000100b
0001000b
0010000b
0100000b
1000000b
EX (bit7) Pin Selector – This bit determines whether the pcs6_n - pcs5_n pins are configured as chip
selects or as alternate outputs for a2 & a1. When this bit is set to 1, pcs6_n - pcs5_n are configured
as peripheral chip select pins, whereas when set to 0, pcs6_n - pcs5_n become address bit a1 and
address bit a2 respectively.
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8/16-BIT Microcontrollers
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MS (bit 6) Memory/ I/O Space Selector determines whether the pcs_n pins are active either during
memory or I/O bus cycles. When MS is set to 1, the pcs_n outputs are active for memory bus cycles,
and active for I/O bus cycles when set to 0.
Reserved (bits 5:3) – Set to 1.
R2 (bit 2) Ready Mode – This bit influences only the pcs6_n - pcs5_n chip selects. If R2 is set to 0,
external ready is required. If R2 is set to 1, external ready is ignored. In each case, the values of the
R1-R0 bits determine the number of wait states to be inserted.
R [1:0] (bits 1-0) Wait-State Value – These bits influence only the pcs6_n - pcs5_n chip selects. The
value of R1-R0 determines the number of wait states inserted into an access depending on whether its
to the PCS_n memory or I/O area. Up to three wait states can be inserted (R1 - R0 = 00b to 11b).
MMCS (0a6h) - Midrange Memory Chip Select Register.
Four chip-select pins, mcs3_n - mcs0_n, are provided for use within a user-locatable memory block. The
memory block base address can be located anywhere within the 1-Mbyte memory address space,
excluding the areas associated with the ucs_n and lcs_n chip selects (and, if mapped to memory, the
address range of the Peripheral Chip Selects, pcs6_n - pcs5_n and pcs3_n to pcs0_n). If the pcs_n chip
selects are mapped to I/O space, the mcs_n address range can overlap the pcs_n address range
Two registers program the Midrange Chip Selects. The Midrange Memory Chip Select (MMCS) register
determines the base address, the ready condition and wait states of the memory block that are accessed
through the mcs_n pins. The pcs_n and mcs_n Auxiliary (MPCS) register configures the block size. On
reset the mcs3_n - mcs0_n pins are not active. Accessing with a write both the MMCS and MPCS
registers activates these chip selects.
The mcs3_n - mcs0_n outputs assert with the multiplexed AD address bus (ad15 – ad0 or ao15 – ao8
and ad7 – ad0) rather than the earlier timing of the a19 – a0 bus unlike the ucs_n and lcs_n chip selects.
The timing is delayed for a half cycle later than that for ucs_n and lcs_n if the a19 – a0 bus is used for
address selection.
The value of the MMCS register is undefined at reset.
15
14
13
12
BA19 – BA13
11
10
9
8
7 6 5 4 3
2
1
0
1
1 1 1 1 1 R2 R1 - R0
BA [15:9] (bits 15-9) – Base Address. The value of the BA19 – BA13 determines the Base Address of
the memory block that is addressed by the mcs_n chip select pins. These bits correspond to bits a19 –
a13 of the 20-bit memory address. The remaining bits a12 – a0 of the base address are always 0.
The base address may be any integer multiple of the size of the memory clock selected in the MPCS
register. For example, if the midrange block is 32 Kbytes, the block could be located at 20000h or
28000h but not at 24000h.
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Data Sheet
8/16-BIT Microcontrollers
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If the lcs_n chip select is inactive, the base address of the midrange chip selects can be set to 00000h,
because the lcs_n chip select is defined to be 00000h but is unused. The further limitation that the
base address must be an integer multiple of the block size means that a 512K MMCS block size can
only be used with the lcs_n chip select inactive and the base address of the midrange chip selects set
to 00000h.
Reserved [8:3] (bits 8-3) - Set to 1.
R2 (bit 2) – Ready mode. This bit determines the mcs_n chip selects ready mode. When R2 is 0, an
external ready is necessary. If R2 is 1, an external ready is ignored. In each case, the number of wait
states inserted in an access is determined by the value of the R1 & R0 bits.
R [1:0] (bits 1-0) – Wait-State Value. The number of wait states inserted in an access is determined
by the value of the R1 & R0 bits. Up to three wait states can be inserted (R1 - R0 = 00b to 11b).
PACS (0a4h) - PeripherAl Chip Select Register.
The Peripheral Chip Selects are asserted over 256-byte range with the same timing as the AD address bus.
There are six chip selects, pcs6_n - pcs5_n and pcs3_n - pcs0_n, that are utilized in either the userlocatable memory or I/O blocks. The pcs4_n chip select is not implemented in the ia18xEM family of
Micro controllers. Excluding the areas utilized by the ucs_n, lcs_n, and mcs_n chip selects, the memory
block can be located anywhere within the 1-Mbyte address space. These chip selects may also be
configured to access the 64-Kbyte I/O space.
Programming the Peripheral Chip Selects uses two registers, The Peripheral Chip Select (PACS) register
and the pcs_n and mcs_n Auxiliary (MPCS) register. The PACS register establishes the base address,
configures the ready mode, and determines the number of wait states for the pcs3_n - pcs0_n outputs.
The MPCS register configures the pcs6_n – pcs5_n pins to be either chip selects or address pins a1 and
a2. When these pins are configured as chip selects, the MPCS register determines whether they are active
during memory or I/O bus cycles and determines the ready state and wait states for these output pins.
These pins are not active on reset but are activated as chip selects by writing to the two registers (PACS
and MPCS). To configure and activate them as address pins it is necessary to write to both the PACS and
MPCS registers. pcs6_n – pcs5_n can be configured for 0 to 3 wait states while pcs3_n - pcs0_n can be
programmed for 0 to 15 wait states.
The value of the PACS register is undefined at reset.
15
14
13
12
11
BA19 – BA11
10
9
8
7 6 5 4
3
2
1
0
1 1 1 R3 R2 R1 –R0
BA [19:11] (bits 15-7) - Base Address bits determine the base address and correspond to bits 19 - 11
of the 20-bit programmable base address of the peripheral chip select block. However, if the PCS_n
chip selects are mapped to I/O space, these bits must be set to 0000b, as I/O addresses are only 16 bits
wide.
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Data Sheet
8/16-BIT Microcontrollers
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PCS Address Ranges
PCSn Line
PCS0n
PCS1n
PCS2n
PCS3n
Reserved
PCS5n
PCS6n
Range
Low
High
Base Address
Base Address + 255
Base Address + 256
Base Address + 511
Base Address + 512
Base Address + 767
Base Address + 768
Base Address + 1023
N/A
N/A
Base Address + 1280
Base Address
Base Address + 1536
Base Address
Reserved [6:4] (bits 6-4) – Set to 1.
R [3] (bit 3) – Wait State Value. See the following table.
R [2] (bit 2) – Ready Mode. When 0, external ready is required. When 1, external ready is ignored.
But in each case the number of wait states is determined as in the following table.
R [1:0] (bits 1 – 0) – Wait-State Value. See following table. It should be noted that pcs6_n – pcs5_n
and pcs3_n – pcs0_n pins are multiplexed with the programmable I/O pins. And for them to function
as chip selects, the PIO mode and direction settings for these pins must be set to 0 for normal
operation.
PCS3n – PCS0n Wait–State Encoding
R3
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
R0
0
1
0
1
0
1
0
1
Wait States
0
1
2
3
5
7
9
15
LMCS (0a2h) - Low Memory Chip Select Register configures the Low Memory Chip Select that has
been provided to facilitate access to the interrupt vector table located at 00000h or the bottom of memory.
The lcs_n pin is not active at reset.
The width of the data bus for the lcs_n space should be configured in the AUXCON register before
activating the lcs_n chip select pin, by any write access to the LMCS register.
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8/16-BIT Microcontrollers
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The value of the LMCS register is undefined at reset except DA, which is set to 0.
15
0
14
13
12
11
10
9
8
1
1
1
1
UB2 – UB0
7
6
5 4 3
2
DA PSE 1 1 1 R2
1
0
R1-R0
Reserved [15] (bit 15) – Set to 0
UB [2:0] (bits 14 – 12) - Upper Boundary. These bits define the upper boundary of memory accessed
by the lcs_n chip select. The following table gives the possible configurations of block size (max
512Kbytes).
LMCS Block Size Programming Values
Memory Block
Size
64K
128K
256K
512K
Ending
Address
0FFFFh
1FFFFh
3FFFFh
7FFFFh
UB2 – UB0
000b
001b
011b
111b
Reserved [11:8] (bits 11-8) - Set to 1.
DA (bit 7) Disable Address - When set to 0, the address is driven onto the address bus (ad15 – ad0)
during the address phase of a bus cycle. If DA is set to 1, the address bus is disabled, providing some
measure of power saving. This bit is set to 0 at reset.
If BHE_n/ADEN_n is held at 0 during the rising edge of res_n, then the address bus is always driven,
independent of the setting of DA.
PSE (bit 6) PSRAM Mode Enable – PSRAM support for the lcs_n chip select memory space is enabled
when the PSE is set to 1. The EDRAM, MDRAM, and CDRAM refresh control unit registers must be
configured for auto refresh before PSRAM support is enabled. Setting the enable bit (EN) in the
enable RCU register (EDRAM, offset e4h) configures the mcs3_n/rfsh_n as rfsh_n.
Reserved (bits 5-3) – Set to 1.
R2 (bit 2) - Ready Mode. When this bit is set to 0, an external ready is required. When set to 1, the
external ready is ignored. In either case, however, the value of the R1 - R0 bits determine the number
of wait states inserted.
R [1:0] (bits R1-R0) - Wait-State Value. The number of wait states inserted into an access to the
LCS_n memory area is determined by the value of these bits. This number ranges from 0 to 3 (R1 – R0
= 00b to 11b)
UMCS (0a0h) - Upper Memory Chip Select Register configures the Upper Memory Chip Select pin,
which is used for the top of memory. On reset, the first fetch takes place at memory location FFFF0h and
thus this area of memory is usually used for instruction memory. With this in mind, UCS_n defaults to an
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Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
active state at reset with a memory range of 64 Kbytes (F0000h to FFFFFh), external ready required, and
three wait states automatically inserted. The upper end of the memory range always ends at FFFFFh,
whereas the lower end of this upper memory range is programmable.
The value of the UMCS register is F03Bh at reset.
15
1
14
13
12
LB2 – LB0
11
10
9
8
7
6
5 4 3
2
0
0
0
0
DA
0
1 1 1 R2
1
0
R1-R0
Reserved [15] (bit 15) – Set to 1.
LB [2:0] (bits 14–12) – Lower Boundary. These bits determine the bottom of the memory accessed
by the ucs_n chip selects.
UMCS Block Size Programming Values
Memory
Block
Size
64K
128K
256K
512K
Starting
Address
LB2 – LB0
F0000h
E0000h
C0000h
80000h
111b
110b
100b
000b
Comments
Default
Reserved (bits 11 – 8)
DA (bit 7) – Disable Address. When set to 0, the address is driven onto the address bus (ad15 – ad0)
during the address phase of a bus cycle when ucs_n is asserted. If DA is set to 1, the address bus is
disabled, and the address is not driven on the address bus when ucs_n is asserted, providing some
measure of power saving. This bit is set to 0 at reset.
If bhe_n/aden_n is held at 0 during the rising edge of res_n, then the address bus is always driven
independent of the setting of DA.
Reserved (bit 6) – Set to 0.
Reserved (bit 5 – 3) – Set to 1.
R2 (bit 2) Ready Mode – When this bit is set to 0, an external ready is required. But when set to 1, the
external ready is ignored. In either case, however, the value of the R1 - R0 bits determine the number
of wait states inserted.
R [1:0] (bits 1-0) - Wait-State Value. The number of wait states inserted into an access to the lcs_n
memory area is determined by the value of these bits. This number ranges from 0 to 3 (R1 – R0 = 00b
to 11b).
SPBAUD (088h) - Serial Port BAUD Rate Divisor Register.
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8/16-BIT Microcontrollers
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The value in this register determines the number of internal processor cycles in one phase (half-period) of
the 32 x serial clock.
The contents of these registers must be adjusted to reflect the new processor clock frequency if powersave mode is in effect.
The baud rate divisor may be calculated from:
BAUDDIV = (Processor Frequency / (32 x baud rate)) -1
By setting the BAUDDIV to 0000h, the maximum baud rate of 1/32 of the internal processor frequency
clock is set. Setting BAUDDIV to 129 (81h) provides a baud rate of 9600 at 40MHz. The baud rate
tolerance is +4.6% and –1.9% with respect to the actual serial port baud rate, not the target baud rate.
Baud Rates
Divisor Based on CPU Clock Rate
Baud Rate
20 MHz
25 MHz
33 MHz
40 MHz
300
2082
2603
3471
4165
600
1040
1301
1735
2082
1200
519
650
867
1040
2400
259
324
433
519
4800
129
161
216
259
9600
64
80
107
129
14400
42
53
71
85
19200
31
39
53
64
625 Kbaud
0
n/a
n/a
1
781.25 Kbaud
n/a
0
n/a
n/a
1.041 Mbaud
n/a
n/a
0
n/a
1.25 Mbaud
n/a
n/a
n/a
0
7 6 5 4 3
2
The value of the SPBAUD register at reset is undefined.
15
14
13
12
11
10
9
8
1
0
BAUDDIV
BAUDDIV [15:0] (bits 15-0) – Baud Rate Divisor. Defines the divisor for the internal processor
clock.
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Data Sheet
8/16-BIT Microcontrollers
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SPRD (086h) - Serial Port Receive Data Register.
Data received over the serial port are stored in this register until read. The data are received initially by
the receive shift register (no software access) permitting data to be received while the previous data are
being read.
The RDR bit (Receive Data Ready) in the serial port status register indicates the status of the SPRD
register. Setting the RDR bit 1 indicates that there is valid data in the receive register.
The value of the SPRD register is undefined at reset.
15
14
13
12
11
10
9
8
7
6
5 4 3
Reserved
2
1
0
RDATA
Reserved (bits 15-8) – Reserved.
RDATA [7:0] (bits 7-0) – Holds valid data while the RDR bit of the status register is set.
SPTD (084h) - Serial Port Transmit Data Register.
Data is written to this register by software, with the values to be transmitted by the serial port. Double
buffering of the transmitter allows for the transmission of data from the transmit shift register (no
software access), while the next data are written into the transmit register.
The THRE bit in the Serial Port Status register indicates whether there is valid data in the SPDT register.
The THRE bit must be a 1 before writing data to this register to prevent overwriting valid data that is
already in the SPDT register.
The value of the SPTD register is undefined at reset.
15
14
13
12
11
10
9
8
7
6
5 4 3
Reserved
2
1
0
TDATA
Reserved (bits 15-8) – Reserved.
TDATA [7:0] (bits 7-0) – Holds the data to be transmitted.
SPSTS (082h) – Serial Port STatuS Register.
This register stores information concerning the current status of the port. The status bits are described
below.
The value of the SPSTS register is undefined at reset.
15
14
13
12
11
Reserved
10
9
8
7
6
5
4
3
TEMT THRE RDR BRKI
2
FER
1
0
PER OER
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8/16-BIT Microcontrollers
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Reserved (bits 15-7) – Reserved – Set to 0.
TEMT (bit 6) – Transmitter Empty. When both the transmit shift register and the transmit register are
empty, this bit is set indicating to software that it is safe to disable the transmitter.
This bit is read-only.
THRE (bit 5) – Transmit Holding Register Empty. When this bit is 1, the corresponding transmit
holding register is ready to accept data. This is a read-only bit.
RDR (bit 4) – Receive Data Ready. When this bit is 1, the respective SPRD register contains valid
data. This is a read/write bit and can be reset only by reading the corresponding Receive register.
BRKI (bit 3) –Break Interrupt. This bit indicates that a break has been received when this bit is set to
1 and causes a serial port interrupt request.
NOTE: This bit should be reset by software.
FER (bit 2) – Framing Error Detected. When the receiver samples the rxd line as low when a stop bit
is expected (line high) a framing error is generated setting this bit.
NOTE: This bit should be reset by software.
PER (bit 1) - Parity Error Detected. When a parity error is detected in either mode 1 or 3, this bit is
set.
NOTE: This bit should be reset by software.
OER (bit 0) – Overrun Error Detected. When new data overwrites valid data in the receive register
(because it hasn’t been read) an overrun error is detected setting this bit.
NOTE: This bit should be reset by software.
SPCT (080h) - Serial Port ConTrol Register.
This register controls both transmit and receive parts of the serial port.
The value of the SPCT register is 0000h at reset.
15 14 13 12
11
10
9
8
7
Reserved
TX
RX
LOOP
BRK
BRK
IE
IE
6
5
PMODE
4
3
2
1
0
WLGN
STP
TMODE
RSIE
RMODE
VAL
Reserved (bits 15-12) – Reserved. Set to 0.
TXIE (bit 11) – Transmitter Ready Interrupt Enable. This bit enables the generation of an interrupt
requests whenever the transmit holding register is empty (THRE bit 1). The respective port does not
generate interrupts when this bit is 0. Interrupts continue to be generated as long as THRE and the
TXIE are 1.
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RXIE (bit 10) – Receive Data Ready Interrupt Enable. This bit enables the generation of an interrupt
requests whenever the receive register contains valid data (RDR bit 1). The respective port does not
generate interrupts when this bit is 0. Interrupts continue to be generated as long as RDR and the
RXIE are 1.
LOOP (bit 9) – Loop-back. The serial port is placed into the loop-back mode when this bit is set.
BRK (bit 8) – Send Break. When this bit is set to 1, the txd pin is driven low, overriding any data that
may be in the course of being shifted out of the transmit shift register.
See the definitions of long and short break in the Serial Port Status register definition.
BRKVAL (bit 7) – Break Value. This is the ninth data bit transmitted when in modes 2 and 3. This bit
is cleared at each transmitted word and is not buffered. To transmit data with this bit set high, the
following procedure is recommended.
1. The TEMT bit in the serial port status register must go high.
2. Set the TB8 bit by writing it to the serial port control register.
3. Finally write the transmit character to the serial port transmit register.
Serial port 0 is a special case in that if this bit is 1, the associated pins are used for flow control
overriding the Peripheral Chip Select signals. This bit is 0 at reset.
PMODE (bits6:5) – Parity Mode. When this bit is set to 1, the txd pin is driven low overriding any
data that may be in the course of being shifted out of the transmit shift register.
See the definitions of long and short break in the Serial Port Status register definition.
WLGN (bit 4) – Word Length. The number of bits transmitted or received in a frame is determined by
the value of this bit. When this bit is 0, the number of data bits in a frame is 7 whereas when this bit is
1 the number of data bits in a frame is 8. This bit is 0 at reset.
STP (bit 3) – Stop Bits. This bit specifies the number of stop bits used to indicate the end of a frame.
When this bit is 0, the number of stop bits is 1. When it is 1, the number of stop bits is 2. This bit is 0
at reset.
TMODE (bit 2) – Transmit Mode. The transmit section of the serial port is enabled when this bit is 1
and disabled when this bit is 0.
RSIE (bit 1) – Receive Status Interrupt Enable. When an exception occurs during data reception an
interrupt request is generated if enabled by this bit (RSIE = 1). Interrupt requests are made for the
error conditions listed (BRK, OER, PER, and FER) in the serial port status register. This bit is 0 at
reset.
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RMODE (bit 0) – Receive Mode. The receive section of the serial port is enabled when this bit is 1 and
disabled when this bit is 0. This bit is 0 at reset.
PDATA1 (07ah) - PIO DATA Registers.
PDATA0 (074h),
When a PIO pin is configured as an output the value in the corresponding PIO data register bit is driven
onto the pin. On the other hand, if the PIO pin is configured as an input, the value on the pin is input into
the corresponding bit of the PIO data register.
The following table lists the default states for the PIO pins.
PIO Pin Assignments
PIO
Number
Associated Pin Name
Power-On Reset
Status
0
tmrin1
Input with pull-up
1
tmrout1
Input with pull-down
2
pcs6/A2
Input with pull-up
3
pcs5/A1
Input with pull-up
4
dt/r_n
Normal operation(c)
5
den_n/ds_n
Normal operation(c)
6
srdy
Normal operation(d)
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
PIO
Number
As of Production Version -03
Associated Pin Name
Power-On Reset
Status
7(a)
a17
Normal operation(c)
8(a)
a18
Normal operation(c)
9(a)
a19
Normal operation(c)
10
tmrout0
Input with pull-down
11
tmrin0
Input with pull-up
12
drq0
Input with pull-up
13
drq1
Input with pull-up
14
mcs0_n
Input with pull-up
15
mcs1_n
Input with pull-up
16
pcs0_n
Input with pull-up
17
pcs1_n
Input with pull-up
18
pcs2_n
Input with pull-up
19
pcs3_n
Input with pull-up
20
sclk
Input with pull-up
21
sdata
Input with pull-up
22
sden0
Input with pull- down
23
sden1
Input with pull- down
24
mcs2_n
Input with pull-up
25
mcs3_n/rfsh_n
Input with pull-up
26(a, b)
uzi
Input with pull-up
27
txd
Input with pull-up
28
rxd
Input with pull-up
s6/clkdiv2_n
Input with pull-up
30
int4
Input with pull-up
31
int2
Input with pull-up
29
(a, b)
NOTES
1. Emulators use these pins. (s2_n-s0_n, res_n, nmi, clkouta, bhe_n, ale, ad15 – ad0, and a16 – a0 are
used by emulators also.)
2. If bhe_n/aden_n (ia186EM) or rfsh2_n/aden (ia188EM) is held low during power-on reset, these pins
revert to normal operation.
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3. When used as a PIO pin, it is an input with an available pull-up option.
4. When used as a PIO pin, it is an input with an available pull-down option.
The value of the PDATA registers is undefined at reset.
PDATA 0
15
14
13
12
11
10
9
8
7
6
5 4 3
2
1
0
7
6
5 4 3
2
1
0
PDATA (15 – 0)
PDATA 1
15
14
13
12
11
10
9
8
PDATA (31 – 16)
PDATA [15:0] (bits 15-0) – PIO Data 0 Bits. This register contains the values of the bits that are
either driven on or received from the corresponding PIO pins, depending on its configuration each pin
as either an output or an input. The values of these bits correspond to those in the PIO direction
registers and PIO Mode registers.
PDATA [31:16] (bits 15-0) – PIO Data 1 Bits. This register contains the values of the bits that are
either driven on, or received from, the corresponding PIO pins depending on its configuration each pin
as either an output or an input. The values of these bits correspond to those in the PIO direction
registers and PIO Mode registers
The PIO pins can be operated as open-drain outputs by:
1. Maintaining the data constant in the appropriate bit of the PIO data register.
2. Writing the value of the data bit into the respective bit position of the PIO Direction register, so that
the output is either 0 or disabled depending on the value of the data bit.
PDIR1 (078h) - PIO DIRection Registers.
PDIR0 (072h)
Each PIO pin is configured as an input or an output by the corresponding bit in the PIO direction register.
PIO Mode and PIO Direction Settings
PIO Mode
PIO Direction
Pin function
0
0
Normal operation
0
1
PIO input with pullup/pulldown
1
0
PIO output
1
1
PIO input without pullup/pulldown
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PDIR0
The value of the PDIR0 register is FC0Fh at reset.
15
14
13
12
11
10
9
8
7
6
5 4 3
2
1
0
8
7
6
5 4 3
2
1
0
PDIR (15 – 0)
PDIR1
The value of the PDIR1 register is FFFFh at reset.
15
14
13
12
11
10
9
PDIR (31 – 16)
PDIR [15:0] (bits 15-0) – PIO Direction 0 Bits. For each bit, if the value is 1, the pin is configured
as an input and as an output if the value is 0. The values of these bits correspond to those in the PIO
data registers and PIO Mode registers.
PDIR [31:16] (bits 15-0) – PIO Direction 1 Bits. For each bit, if the value is 1, the pin is configured
as an input and as an output if the value is 0. The values of these bits correspond to those in the PIO
data registers and PIO Mode registers.
PIOMODE1 (076h) - PIO MODE Registers.
PIOMODE0 (070h)
Each PIO pin is configured as an input or an output by the corresponding bit in the PIO direction register.
The bit number of PMODE corresponds to the PIO number.
See the table PIO Mode and PIO Direction Settings in PDIR description above.
PIOMODE0
The value of the PIOMODE0 register is 0000h at reset.
15
14
13
12
11
10
9
8
7
6
5
4 3
2
1
0
5 4 3
2
1
0
PMODE (15 – 0)
PIOMODE1
The value of the PIOMODE1 register is 0000h at reset.
15
14
13
12
11
10
9
8
7
6
PMODE (31 – 16)
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PMODE [15:0] (bits 15-0) – PIO Mode 0 Bits. For each bit, if the value is 1 then the pin is
configured as an input and as an output if the value is 0. The values of these bits correspond to those
in the PIO data registers and PIO Mode registers.
PMODE [31:16] (bits 15-0) – PIO Mode 1 Bits. For each bit, if the value is 1 then the pin is
configured as an input and as an output if the value is 0. The values of these bits correspond to those
in the PIO data registers and PIO Mode registers.
T1CON (05eh) - Timer 0 and Timer 1 Mode and CONtrol Registers.
T0CON (056h)
This registers controls the operation of the Timer 1 and Timer 0 respectively.
The value of both the T0CON and T1CON registers is 0000h at reset.
15
14
13
12
EN INHn INT RIU
11
10
9
8
7
6
0
0
0
0
0
0
5
4
MC RTG
3
P
2
1
0
EXT ALT CONT
EN (bit 15) – Enable Bit. The timer is enabled when the EN bit is 1. The timer count is inhibited
when the EN bit is 0. This bit is write-only, but with the INHn bit set to 1 in the same write operation.
INHn (bit 14) – Inhibit Bit. Gates the setting of the enable (EN) bit. This bit must be set to 1 in the
same write operation that sets the enable (EN) bit. Otherwise, the EN bit will not be changed. This bit
always reads as 0.
INT (bit 13) – Interrupt Bit. An interrupt request is generated when the Count register reaches its
maximum, MC = 1, by setting the INT bit to 1. In dual maxcount mode, an interrupt request is
generated when the count register reaches the value in maxcount A or maxcount B. No interrupt
requests are generated if this bit is set to 0. If an interrupt request is generated and then the enable bit
is cleared before said interrupt is serviced, the interrupt request will remain.
RIU (bit 12) – Register in Use Bit. This bit is set to 1 when the maxcount register B is used to
compare to the timer count value. It is set to 0 when the maxcount compare A register is used.
Reserved (bits 11-6) – Set to 0.
MC (bit 5) – Maximum Count. When the timer reaches its maximum count this bit is set to 1
regardless of the interrupt enable bit. This bit is also set every time Maxcount Compare register A or
B is reached, when in dual maxcount mode. This bit may be used by software polling to monitor
timer status rather than through interrupts if desired.
RTG (bit 4) – Retrigger Bit. This pin controls the timer function of the timer input pin. When set to 1,
the count is reset by a 0 to 1 transition on timrin0 or tmrin1. When set to 0, a high input on tmrin0
or tmrin1 enables the count and a 1 holds the timer value. This bit is ignored if the external clocking
(EXT=1) bit is set.
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8/16-BIT Microcontrollers
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P (bit 3) – Prescaler Bit. P is ignored if external clocking is enabled (EXT = 1). Timer 2 prescales the
timer when P is set to 1. Otherwise, the timer is incremented on every fourth CLKOUT cycle.
EXT (bit 2) – External Clock Bit. This bit determines whether an external or internal clock is used.
EXT = 1, an external clock is used and EXT = 0, an internal is used.
ALT (bit 1) – Alternate Compare Bit. If set to 1, the timer will count to Maxcount Compare A, reset
the count register to 0, count to maxcount compare B, reset the count register to 0 and begin again at
maxcount compare A.
If set to 0, the timer will count to maxcount compare A, reset the count register to 0, and begin again
at maxcount compare A. Maxcount compare B is not used in this case.
CONT (bit 0) – Continuous Mode Bit. The timer will run continuously when this bit is set to 1. The
timer will stop after each count run and EN will be cleared if the CONT bit is set to 0. If CONT = 1
and ALT = 1, the respective timer counts to the maxcount compare A value and resets, then
commences counting to maxcount compare B value, resets and ceases counting.
T2CON (066h) - Timer 2 Mode and CONtrol Register.
This register controls the operation of the Timer 2.
The value of the T2CON register is 0000h at reset.
15
EN
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INHn INT
0
0
0
0
0
0
0
MC
0
0
0
0
CONT
EN (bit 15) – Enable Bit. The timer is enabled when the EN bit is 1. The timer count is inhibited
when the EN bit is 0. Setting this bit to 1 by writing to the T2CON register requires that the INH bit be
set to 1 during the same write. This bit is write-only, but with the INHn bit set to 1 in the same write
operation.
INHn (bit 14) – Inhibit Bit. Gates the setting of the enable (EN) bit. This bit must be set to 1 in the
same write operation that sets the enable (EN) bit. This bit always reads as 0.
INT (bit 13) – Interrupt Bit. An interrupt request is generated, by setting the INT bit to 1, when the
Count register reaches its maximum, MC = 1.
Reserved (bits 12-6) – Set to 0.
MC (bit 5) – Maximum Count. When the timer reaches its maximum count this bit is set to 1,
regardless of the interrupt enable bit. This bit may be used by software polling to monitor timer status
rather than through interrupts if desired.
Reserved (bits 4-1) – Set to 0.
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CONT (bit 0) – Continuous Mode Bit. The timer will run continuously when this bit is set to 1. The
timer will stop after each count run and EN will be cleared if this bit is set to 0.
T2COMPA (062h), - Timer Maxcount COMpare Registers.
T1COMPB (05ch)
T1COMPA (05ah)
T0COMPB (054h)
T0COMPA (052h)
These registers contain the maximum count value that is compared to the respective count register. Timer
0 and Timer 1 have two of these compare registers each.
If Timer 0 or Timer 1 or both are configured to count and compare firstly to register A and then register
B, the tmrout0 or tmrout1 signals may be used to generate various duty-cycle wave forms.
Timer 2 has only one compare register, T2COMPA.
If one of these timer maxcount compare registers is set to 0000h, the respective timer will count from
0000h to FFFFh before generating an interrupt request. For example, a timer configured in this manner
with a 40MHz clock will interrupt every 6.5536 mS.
The value of these registers is undefined at reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TC15 – TC0
TC [15:0] (bits 15-0) – Timer Compare Value. The timer will count to the value in the respective
register before resetting the count value to 0.
T2CNT (060h) - Timer CouNT Registers.
T1CNT (058h)
T0CNT (050h),
These registers are incremented by one every four internal clock cycles if the relevant timer is enabled.
The Increment of Timer 0 and Timer 1 may also be controlled by external signals tmrin0 and tmrin1
respectively, or prescaled by Timer 2.
Comparisons are made between the count registers and maxcount registers and action taken dependent on
achieving the maximum count.
The value of these registers is undefined at reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TC15 – TC0
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Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
TC [15:0] (bits 15-0) – Timer Count Value. This register has the value of the current count of the
related timer that is incremented every fourth processor clock in internal clocked mode. Alternatively,
the register is incremented each time the Timer 2 maxcount is reached if using Timer 2 as a prescaler.
Timer 0 and Timer 1 may be externally clocked by tmrin0 and tmrin1 signals.
SPICON (044h) - Serial Port Interrupt CONtrol Register.
Master Mode
This register controls the operation of the asynchronous serial port interrupt source (SPI, bit 10 in of the
Interrupt Request register)
The value of this register is 001Fh at reset.
15
14
13
12
11
10
9
8
7
6
5
Reserved
4
3
Res
MSK
2
1
0
PR2-PR0
Reserved (bits 15-5) – Set to 0.
Reserved (bit 4) – Set to1.
MSK (bit 3) – Mask. This bit, when 0, enables the serial port to cause an interrupt. When this bit is 1,
the serial port is prevented from generating an interrupt.
PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the serial port interrupt in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the following table.
Priority Level
Priority
(High) 0
1
2
3
4
5
6
(Low) 7
PR2 – PR0
000b
001b
010b
011b
100b
101b
110b
111b
WDCON (044h) – WatchDog timer interrupt CONtrol Register.
Master Mode
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These registers control the operation of the Watchdog Timer interrupt source. The value of this register is
000Fh at reset.
15
14
13
12
11
10
9
8
7
6
5
Reserved
4
3
Res
MSK
2
1
0
PR2-PR0
Reserved (bits 15-5) – Set to 0.
Reserved (bit 4) – Set to 0.
MSK (bit 3) – Mask. This bit, when 0, enables the Watchdog Timer to cause an interrupt. When this
bit is 1 prevents the Watchdog Timer from generating an interrupt.
PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the Watchdog Timer interrupt in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2
– PR0 are shown in the above table (Priority Level).
I4CON (040h) – INT4 CONtrol Register.
Master Mode
This register controls the operation of the int4 signal, which is only intended for use in fully nested mode.
The interrupt is assigned to type 10h.
The value of the I4CON register is 000Fh at reset.
15
14
13
12
11
10
9
Reserved
8
7
6
5
4
3
LTM MSK
2
1
0
PR2-PR0
Reserved (bits 15-5) – Set to 0.
LTM (bit 4) – Level-Triggered Mode. The int4 interrupt may be edge or level triggered depending on
the value of the bit. If LTM is 1, int4 is active high-level sensitive interrupt l. If LTM is 0, int4 is a
rising edge triggered interrupt. The interrupt int4 must remain active (high) until serviced.
MSK (bit 3) – Mask. The int4 signal can cause an interrupt if the MSK bit is 0. The int4 signal cannot
cause an interrupt if the MSK bit is 1.
PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupt in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
I3CON (03eh) – INT2/INT3 CONtrol Register.
I2CON (03ch),
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Master Mode
INT2 and INT3 are designated as interrupt type 0eh and 0fh respectively.
The int2 and int3 pins may be configured as the interrupt acknowledge pins inta0_n and inta1_n
respectively in cascade mode.
The value of these registers is 000Fh at reset.
15
14
13
12
11
10
9
8
7
6
Reserved
5
4
3
2
LTM MSK
1
0
PR2-PR0
Reserved (bits 15-5) – Set to 0.
LTM (bit 4) – Level-Triggered Mode The int2 or int3 interrupt may be edge or level triggered
depending on the value of this bit. If LTM is 1, int2 or int3 is an active high level-sensitive interrupt.
If LTM is 0, int2 or int3 is a rising edge triggered interrupt. The interrupt int2 or int3 must remain
active (high) until acknowledged.
MSK (bit 3) – Mask. The int2 or int3 signal can cause an interrupt if the MSK bit is 0. The int2 or
int3 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate
of this bit.
PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupt int2 or int3 in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2
– PR0 are shown in the above table (Priority Level).
I1CON (03ah) – INT0/INT1 CONtrol Register.
I0CON (038h),
(Master Mode)
IINT0 and INT1 are designated as interrupt type 0ch and 0dh respectively.
The int2 and int3 pins may be configured as the interrupt acknowledge pins inta0 and inta1 respectively,
the interrupt acknowledge signals for int0 and int1 in cascade mode.
The value of these registers is 000Fh at reset.
15
14
13
12
11
Reserved
10
9
8
7
6
5
4
3
SFNM C LTM MSK
2
1
0
PR2-PR0
Reserved (bits 15-7) – Set to 0.
SPNM (bit 6) – Special Fully Nested Mode. This bit enables fully nested mode for int0 or int1 when
set to 1.
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Data Sheet
8/16-BIT Microcontrollers
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C (bit 5) – Cascade Mode. This bit enables cascade mode for int0 or int1 when set to 1.
LTM (bit 4) – Level-Triggered Mode. The int0 or int1 interrupt may be edge or level triggered
depending on the value of the bit. If LTM is 1, int0 or int1 is an active high level-sensitive interrupt.
If LTM is 0, int0 or int1 is a rising edge triggered interrupt. The interrupt int0 or int1 must remain
active (high) until acknowledged.
MSK (bit 3) – Mask. The int0 or int1 signal can cause an interrupt if the MSK bit is 0. The int0 or
int1 signal cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a duplicate
of this bit.
PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupt int0 or int1 in
relation to other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2
– PR0 are shown in the above table (Priority Level).
TCUCON (032h) - Timer Control Unit Interrupt CONtrol Register.
Master Mode
The three timers have their interrupts assigned to types 08h, 12h, and 13h and are configured by this
register.
The value of this register is 000Fh at reset.
15
14
13
12
11
10
9
8
Reserved
7
6
5 4
3
MSK
2
1
0
PR2-PR0
Reserved (bits 15-4) – Set to 0.
MSK (bit 3) – Interrupt Mask. An interrupt source may cause an interrupt if the MSK bit is 0. The
interrupt source cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a
duplicate of this bit.
PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupt in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
T2INTCON (03ah) - Timer INTerrupt CONtrol Register.
T1INTCON (038h)
T0INTCON (032h)
Slave Mode
The three timers, Timer2, Timer1, and Timer0, each have an interrupt control register, whereas in master
mode all three are masked and prioritized in one register (TCUCON).
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The value of these registers is 000Fh at reset.
15
14
13
12
11
10
9
8
7
6
5 4
Reserved
3
2
MSK
1
0
PR2 - PR0
Reserved (bits 15-4) – Set to 0.
MSK (bit 3) – Mask. Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The
interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a
duplicate of this bit.
PR2-PR0 (bit 2-0) – Priority. These bits define the priority of the serial port interrupts in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
DMA1CON/INT6CON (036h) – DMA and INTerrupt CONtrol Register. DMA0CON/INT5CON (034h)
Master Mode
The DMA0 and DMA1 interrupts have interrupt type 0ah and 0bh respectively. These pins are
configured as external interrupts or DMA requests in the respective DMA Control register.
The value of these registers is 000Fh at reset.
15
14
13
12
11
10
9
8
7
6
Reserved
5 4
3
MSK
2
1
0
PR2 - PR0
Reserved (bits 15-4) – Set to 0.
MSK (bit 3) – Mask. Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The
interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a
duplicate of this bit.
PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the serial port interrupts in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
DMA1CON/INT6 (036h) – DMA and INTerrupt CONtrol Register.
DMA0CON/INT5 (034h)
Slave Mode
The two DMA control registers maintain their original functions and addressing that they possessed in
Master Mode. These pins are configured as external interrupts or DMA requests in the respective DMA
Control register.
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8/16-BIT Microcontrollers
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The value of these registers is 000Fh at reset.
15
14
13
12
11
10
9
8
7
6
5 4
Reserved
3
2
MSK
1
0
PR2 - PR0
Reserved (bits 15-4) – Set to 0.
MSK (bit 3) – Mask. Any of the interrupt sources may cause an interrupt if the MSK bit is 0. The
interrupt sources cannot cause an interrupt if the MSK bit is 1. The Interrupt Mask Register has a
duplicate of this bit.
PR2-PR0 (bits 2-0) – Priority. These bits define the priority of the serial port interrupts in relation to
other interrupt signals. The interrupt priority is the lowest at 7 at reset. The values of PR2 – PR0 are
shown in the above table (Priority Level).
INTSTS (030h) – INTerrupt STatuS Register.
Master Mode
The Interrupt status register contains the interrupt request status of each of the three timers, Timer2,
Timer1, and Timer0.
15
14
13
DHLT
12
11
10
9
Reserved
8
7
6
5 4
3
2
1
0
TMR2 - TMR0
DHLT (bit 15) – DMA Halt. DMA activity is halted when this bit is 1. It is set to 1 automatically
when any non-maskable interrupt occurs and is cleared to 0 when an IRET instruction is executed.
Interrupt handlers and other time critical software may modify this bit directly to disable DMA
transfers. However, the DHLT bit should not be modified by software if the timer interrupts are
enabled as the function of this register as an interrupt request register for the timers would be
compromised.
Reserved (bits 14-3)
TMR [2:0] (bit 2-0) – Timer Interrupt Request. A pending interrupt request is indicated by the
respective timer, when any of these bits is 1. (N.B. the TMR bit in the REQST register is a logical OR
of these timer interrupt requests)
Slave Mode
When nonmaskable interrupts occur the interrupt status register controls DMA operation and the interrupt
request status of each of the three timers, Timer2, Timer1, and Timer0.
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Data Sheet
8/16-BIT Microcontrollers
15
14
13
12
11
DHLT
As of Production Version -03
10
9
8
7
6
5
4
3
2
Reserved
1
0
TMR2 - TMR0
DHLT (bit 15) – DMA Halt. DMA activity is halted when this bit is 1. It is set to 1 automatically
when any non-maskable interrupt occurs and is cleared to 0 when an IRET instruction is executed.
Reserved (bits 14-3)
TMR [2:0] (bit 2-0) – Timer Interrupt Request. A pending interrupt request is indicated by the
respective timer, when any of these bits is 1. (N.B. the TMR bit in the REQST register is a logical OR
of these timer interrupt requests.)
REQST (02eh) – Interrupt REQueST Register.
Master Mode
This is a read-only register and such a read results in the status of the interrupt request bits presented to
the interrupt controller.
The REQST register is undefined on reset.
15
14
13
Reserved
12
11
10
9
8
7
6
5
4
SPI
WD
I4
I3
I2 I1 IO
3
2
D1- D0
1
0
Res
TMR
Reserved (bits 15 – 11)
SPI (bit 10) – Serial Port Interrupt Request. This is the serial port interrupt state and when enabled is
the logical OR of all the serial port 0 interrupt sources: - THRE, RDR, BRKI, FER, PER, and OER.
WD (bit 9) – Watchdog Timer Interrupt Request. This is the watchdog interrupt state and indicates
that an interrupt is pending when it is a 1.
I [4:0] (bits 8 - 4) Interrupt Requests. Setting any of these bits to 1 indicates that the relevant
interrupt has a pending interrupt.
D1-D0 (bit 3:2) DMA Channel Interrupt 6 Request. Setting either bit to 1 indicates that either the
respective DMA channel has a pending interrupt.
Reserved (bit 1)
TMR (bit 0) – Timer Interrupt Request. This is the timer interrupt state and is the logical OR of the
timer interrupt requests. Setting this bit to 1 indicates that the timer control unit has a pending
interrupt.
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Slave Mode
This is a read-only register and such a read results in the status of the interrupt request bits presented to
the interrupt controller. The status of these bits is available when this register is read.
When an internal interrupt request (D1, D0, TMR2, TMR1, or TMR0) occurs, the respective bit is set to 1.
The internally generated interrupt acknowledge resets these bits.
The REQST register contains 0000h on reset.
15
14
13
12
11
10
9
8
7
6
Reserved
5
4
3
TMR2 TMR1 D1
2
1
0
D0
Res
TMR0
Reserved (bits 15 – 6)
TMR2 (bit 5) Interrupt Requests. Setting this bit to 1 indicates that timer 2 has a pending interrupt.
TMR1 (bit 4) Interrupt Requests. Setting this bit to 1 indicates that timer 1 has a pending interrupt.
D1:D0 (bits 3:2) DMA Channel Interrupt Request. Setting either bit to 1 indicates that the respective
DMA channel has a pending interrupt.
Reserved (bit 1)
TMR0 (bit 0) – Timer0 Interrupt Request. Setting this bit to 1 indicates that timer 0 has a pending
interrupt.
INSERV (02ch) – IN-SERVice Register.
Master Mode
The interrupt controller sets the bits in this register when the interrupt is taken. Writing the corresponding
interrupt type to the End-of-Interrupt (EOI) register clears each of these bits.
When one of these bits is set, an interrupt request will not be generated by the microcontroller for the
respective source. This prevents an interrupt from interrupting itself if interrupts are enabled in the ISR.
This restriction is bypassed in fully Special Fully nested mode for the INT0 and INT1 sources.
The INSERV register contains 0000h on reset
15
14
13
Reserved
12
11
10
9
8
7
6
5
4
3
2
1
0
SPI
WD
I4
I3
I2 I1 IO D1 D0 Res TMR
Reserved (bits 15 – 11)
SPI (bit 10) – Serial Port Interrupt Request. This is the serial port 0 interrupt state.
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8/16-BIT Microcontrollers
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WD (bit 9) – Watchdog Timer Interrupt In-Service Request. This bit is the In-Service state of the
Watchdog Timer.
I [4:0] (bits 8 - 4) Interrupt Requests. Setting any of these bits to 1 indicates that the relevant
interrupt has a pending interrupt.
D1-D0 (bit 3:2) DMA Channel Interrupt In-Service. This bit is the In-Service state of the respective
DMA channel.
Reserved (bit 1)
TMR (bit 0) – Timer Interrupt Request. This is the timer interrupt state and is the logical OR of the
timer interrupt requests. Setting this bit to 1 indicates that the timer control unit has a pending
interrupt.
Slave Mode
This is a read-only register and such a read supplies the status of the interrupt request bits presented to the
interrupt controller.
When an internal interrupt request (D1, D0, TMR2, TMR1, and TMR0) occurs, the respective bit is set to
1. The internally generated interrupt acknowledge resets these bits.
The REQST register contains 0000h on reset.
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
TMR2 TMR1
3
2
1
0
D1
D0
Res
TMR0
Reserved (bits 15 – 6)
TMR2 (bit 5) Timer2 Interrupt In Service. Timer 2 is being serviced when this bit is set to 1.
TMR1 (bit 4) Timer1 Interrupt IN Service. Timer 1 is being serviced when this bit is set to 1.
D1-D0 (bit 3:2) DMA Channel Interrupt In Service. The respective DMA channel is being serviced
when this bit is set to 1.
Reserved (bit 1)
TMR0 (bit 0) – Timer Interrupt In Service. Timer 0 is being serviced when this bit is set to 1.
PRIMSK (02ah) – PRIority MaSK Register.
Master and Slave Mode
This register contains a value that sets the minimum priority level at which an interrupt can be generated
by a maskable interrupt.
The PRIMSK register contains 0007h on reset
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Data Sheet
8/16-BIT Microcontrollers
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15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
PRM2 – PRM0
Reserved (bits 15 – 3) – Set to 0.
PRM 2-PRM0 (bits 2 - 0) Priority Field Mask. This three-bit field sets the minimum priority
necessary for a maskable interrupt to generate an interrupt. Any maskable interrupt with a
numerically higher value than that contained by these three bits is masked.
Priority Level
Priority
(High) 0
1
2
3
4
5
6
(Low) 7
PR2 – PR0
0 0 0b
0 0 1b
0 1 0b
0 1 1b
1 0 0b
1 0 1b
1 1 0b
1 1 1b
Any unmasked interrupt can generate an interrupt if the priority level is set to 7. On the other hand, if
the priority level is set to say 4, only unmasked interrupts with a priority of 0 to 5 are permitted to
generate interrupts.
IMASK (028h) – Interrupt MASK Register.
Master Mode
The interrupt mask register is read/write. Setting a bit in this register is effectively the same as setting the
MSK bit in the corresponding interrupt control register. Setting a bit to 1 masks the interrupt. The
interrupt request is enabled when the corresponding bit is set to 0.
The IMASK register contains 07fdh on reset
15
14
13
12
Reserved
11
10
9
8
7
6
5
4
3
2
SPI
WD
I4
I3
I2 I1
I0
D1-D0
1
0
Res
TMR
Reserved (bits 15 – 11)
SPI (bit 10) – Serial Port Interrupt Mask. Setting this bit to 1 is an indication that the asynchronous
serial port interrupt is masked.
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8/16-BIT Microcontrollers
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WD (bit 9) – Watchdog Timer Interrupt In-Service Request. Setting this bit to 1 is an indication that
the Watchdog Timer interrupt is masked.
I [4:0] (bits 8 - 4) Interrupt Mask. Setting any of these bits to 1 is an indication that the relevant
interrupt is masked.
D1-D0 (bit 3:2) DMA Channel Interrupt Mask. Setting this bit to 1 is an indication that the respective
DMA channel interrupt is masked.
Reserved (bit 1)
TMR (bit 0) – Timer Interrupt Mask. When set to 1, it indicates that the timer control unit interrupt is
masked.
Slave Mode
The interrupt mask register is read/write. Setting a bit in this register is effectively the same as setting the
MSK bit in the corresponding interrupt control register. Setting a bit to 1 masks the interrupt request. The
interrupt request is enabled when the corresponding bit is set to 0.
The IMASK register contains 003dh on reset.
15
14
13
12
11
10
Reserved
9
8
7
6
5
4
3
TMR2 TMR1 D1
2
1
D0 Res
0
TMR0
Reserved (bits 15 – 6)
TMR2 (bit 5) Timer2 Interrupt Mask. This bit provides an indication of the state of the mask bit in
the Timer Interrupt Control register. When it is set to 1, it indicates that the interrupt request is
masked.
TMR1 (bit 4) Timer1 Interrupt Mask. This bit provides an indication of the state of the mask bit in
the Timer Interrupt Control register. When it is set to 1, it indicates that the interrupt request is
masked.
D1-D0 (bit 3:2) DMA Channel Interrupt Mask. This bit provides an indication of the state of the
mask bit in the respective DMA channel Interrupt Control register. When it is set to 1, it indicates that
the interrupt request is masked.
Reserved (bit 1)
TMR0 (bit 0) – Timer Interrupt Mask. This bit provides an indication of the state of the mask bit in
the Timer Interrupt Control register. When it is set to 1, it indicates that the interrupt request is
masked.
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Data Sheet
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POLLST (026h) – POLL STatus Register.
Master Mode
This register reflects the current state of the Poll register and can be read without affecting its contents.
However, when the Poll Register is read, it causes the current interrupt to be acknowledged and be
replaced by the next interrupt.
The poll status register is read-only.
15
14
13
12
11
IREQ
10
9
8
7
6
5
4
3
2
1
0
S4 – S0
Reserved
IREQ (bit 15) – Interrupt Request. This bit is set to 1 when an interrupt is pending. And during this
state, the S4 - S0 bits contain valid data.
Reserved (bits 14-6) Set to 0
S [4:0] (bit 4-0) – Poll Status. These bits show the interrupt type of the highest priority pending
interrupt.
The interrupt service routine does not begin execution automatically with the IS bit set. Rather, the
application software must execute the appropriate ISR.
POLL (024h) – POLL Register.
Master Mode
When the Poll Register is read, it causes the current interrupt to be acknowledged and be replaced by the
next interrupt. The poll status register reflects the current state of the Poll register and can be read without
affecting its contents.
The POLL register is read-only.
15
14
13
IREQ
12
11
10
9
Reserved
8
7
6
5
4
3
2
1
0
S4 – S0
IREQ (bit 15) – Interrupt Request. This bit is set to 1 when an interrupt is pending. And during this
state, the S4 - S0 bits contain valid data.
Reserved (bits 14-6)
S [4:0] (bit 4-0) – Poll Status. These bits show the interrupt type of the highest priority pending
interrupt.
EOI (022h) – End-Of-Interrupt Register.
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Master Mode
The In Service flags of the In-Service register are reset when a write is made to the EOI register.
The interrupt service routine (ISR) should write to the EOI to reset the IS bit, in the In-Service register,
for the interrupt before executing an IRET instruction that ends an interrupt service routine.
The specific EOI reset is the preferred method for resetting the IS bits as it is most secure.
The EOI register is write-only.
15
14
13
12
11
NSPEC
10
9
8
7
6
5
4
3
Reserved
2
1
0
S4 – S0
NSPEQ (bit 15) – Non-Specific EOI. This bit is set to 1 a non-specific EOI and when set to 0 it
indicates the specific EOI.
Reserved (bits 14-5)
S [4:0] (bit 4-0) – Source Interrupt Type. These bits show the interrupt type of the highest priority
pending interrupt.
EOI (022h) – Specific End-Of-Interrupt Register.
Slave Mode
An In Service flag of a specific priority, in the In-Service register, is reset when a write is made to the
EOI register.
A three-bit user supplied priority-level value that points to the in-service bit that is to be reset. Writing
this value to this register resets the specific bit.
The EOI register is write only and undefined at reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
L2 – L0
Reserved (bits 15-3) – Write as 0.
L[2:0] (bit 2-0) – Interrupt Type. The priority or the IS (interrupt service) bit to be reset is encoded in
these three bits. Writing to these bits caused the issuance of an EOI for the interrupt type. See Table
3 - Interrupt Types.
INTVEC (020h) –INTerrupt VECtor Register.
Slave Mode
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8/16-BIT Microcontrollers
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The CPU shifts left 2 bits (multiplies by 4) an 8-bit interrupt type, generated by the interrupt controller, to
produce an offset into the interrupt vector table.
The INTVEC register is undefined at reset.
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
T4 – T0
2
1
0
0
0
0
Reserved (bits 15-8) – Read as 0.
T [4:0] (bits 7-3) – Interrupt Type. These five bits contain the five most significant bits of the
interrupt types used for the internal interrupt type. The least significant three bits of the interrupt type
are supplied by the interrupt controller, as set by the priority level of the interrupt request.
Reserved (bits 2-0) – Read as 0.
SSR (018h) – Synchronous Serial Receive Register.
This register holds the serial data received on the SSI port.
The value of the SSR register is undefined at reset.
15
14
13
12
11
10
9
8
7
6
5
Reserved
4
3
2
1
0
2
1
0
SR7-SR0
Reserved (bits 15-8) – Reserved Bits.
SR[7:0] (bits 7-0) – Data received over the SDATA pin.
SSD0 (016h) – Synchronous Serial Transmit Registers.
SSD0 (014h)
These registers hold the data to be transmitted by the SSI ports.
The value of these registers is undefined at reset.
15
14
13
12
11
10
9
8
7
6
5
Reserved
4
3
SD7-SD0
Reserved (bits 15-8) – Reserved Bits.
SD[7:0] (bits 7-0) – Data to be transmitted over the SDATA pin.
SSC (012h) – Synchronous Serial Control Register.
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This register controls the operation of the sden1 and sden0 outputs and the baud rate of the SSI port. The
sden1 and sden0 outputs are held high when the respective bit is set to 1, but in the event that both DE1
and DE0 are set to 1 then only sden0 will be held high.
The value of the SSR register is 0000h at reset.
15
14
13
12
11
10
9
8
7
6
5
Reserved
4
SCLKDIV
3
2
RES
1
0
DE1-DE0
Reserved (bits 15-6) – Reserved Bits.
SCLKDIV (bits 5-4) – SCLK Divide. These bits set the SCLK frequency. SCLK is the result of
dividing the internal processor clock by 2, 4, 8, or 16 as in the following table.
SCLKDIV
00b
01b
10b
11b
SCLK Frequency Divider
Processor Clock /2
Processor Clock /4
Processor Clock /8
Processor Clock /16
RES (bits 3-2) – Reserved Bits.
DE1 (bit1) - SDEN1. The SDEN1 bit is held high when this bit is set to 1 and SDEN1 is held low
when this bit is set to 0.
DE0 (bit0) – SDEN0. The SDEN0 bit is held high when this bit is set to 1 and SDEN0 is held low
when this bit is set to 0.
SSS (010h) – Synchronous Serial Status Register.
This is a read only register that indicates the state of the SSI port.
The value of the SSR register is 0000h at reset.
15
14
13
12
11
10
9
Reserved
8
7
6
5
4
3
2
1
RE/TE DR/DT
0
PB
Reserved (bits 15-3) – Reserved Bits.
RE/TE (bit 2) – Receive/Transmit Error Detect. This bit is set to 1 when a read of the Synchronous
Serial Received register or a write to one of the transmit register is detected while the interface is busy
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(PB = 1). This bit is reset to 0 when the SDEN output is not active (DE1-DE0 in the SSC register are
00h).
DR/DT (bit 1) – Data Receive/Transmit Complete. This bit is set to a 1 when the transmission of data
bit 7 is completed (SCLK rising edge) during a transmit or receive operation. This bit is reset by a
read of the SSR register, when either the SSD0 or SSD1 register is written, when the SSS register is
read (unless the SSI completes an operation and sets the bit in the same cycle), or when both SDEN0
and SDEN1 become inactive.
PB (bit 0) SSI Port busy. This bit indicates that a data transmit or receive is occurring when it is set
to 1. When set to 0 it indicates that the port is ready to transmit or receive data.
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Clock and Power Management
A phase-lock-loop (PLL) and a second programmable system clock output (CLKOUTB) are included in
the clock and power management unit. The internal clock is the same frequency as the crystal but with a
duty cycle of 45% - 55 %, as a worse case, generated by the PLL obviating the need for an x2 external
clock. A power-on reset (POR) resets the PLL.
C1
C2
Crystal
X1
Recommended range of
values for C1 and C2 are:
X2
C1
=
C2
=
Am186/188EM
15pF +/- 20%
22pF +/- 20%
Figure 2. Crystal Configuration
System Clocks
If required, the internal oscillator can be driven by an external clock source that should be connected to
X1, leaving X2 unconnected.
The clock outputs clkouta and clkoutb may be enabled or disabled individually (Power-Save Control
register (PDCON) bits (11 – 8)). These clock control bits allow one clock output to run at PLL frequency
and the other to run at the power-save frequency.
Processor Internal Clock
PLL
X1,
X2
Power-Save
Divisor
(/2 to /128)
clkouta
Mux
Drive enable
Mux
Time
Delay
6 +/- 2.5nS
clkoutb
Drive enable
Figure 3. Organization of Clock
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Power-Save Mode
The operation of the CPU and peripherals operate at a slower clock frequency when in power save mode
reducing power consumption and thermal dissipation. Should an interrupt occur, the microcontroller
returns to its normal operating frequency automatically on the internal clock’s next rising edge in t3. Any
clock dependent devices should be reprogrammed for the changed in frequency during the power-save
mode period.
Initialization and Reset
res_n (Reset), the highest priority interrupt, must be held low for 1mS during power-up to initialize the
microcontroller correctly. This operation makes the device cease all instruction execution and local bus
activity. The microcontoller begins instruction execution at physical address FFFF0h when res_n
becomes inactive and after an internal processing interval with ucs_n asserted and three wait states. Reset
also sets up certain registers to predetermined values and resets the Watchdog timer.
Reset Configuration Register
The data on the address/data bus (ad15 – ad0 for the Am186EM and ao15 – ao8 and ad7 – ad0 for the
Am188EM) are written into the Reset Configuration register when reset is low. This data is system
dependent and is held in the Reset Configuration register after Reset is de-asserted. This configuration
data may be placed on the address/data bus by using weak external pull-up and pull-down resistors or
applied to the bus by an external driver, as the processor does not drive the bus during reset. It is a
method of supplying the software with some initial data after a reset; for example, option jumper
positions.
Chip Selects
Chip select generation is programmable for memories and peripherals. Programming is also available to
produce ready and wait-state generation plus latched address bits a1 and a2. For all memory and I/O
cycles, the chip-select lines are active within their programmed areas, regardless of whether they are
generated by the internal DMA unit or the CPU.
There are six chip selects outputs for memories and a further six for peripherals whether in memory or I/O
space. The memory chip-selects are able to address three memory ranges, whereas the peripheral chipselects are used to address 256-byte blocks that are offset from a programmable base address. Writing to
a chip-select register enables the related logic even in the event that the pin in question has another
function, as for example in the case that the pin is programmed to be a PIO.
Chip Select Timing
For normal timing, the ucs_n and lcs_n outputs are asserted with the non-multiplexed address bus.
Ready and Wait-State Programming
Each of the memory or peripheral chip-select lines can have a ready signal programmed that can be the
ardy or srdy signal. The chip-select control registers (UMCS, LMCS, MMCS, PACS, and MPCS) have
a single bit that selects if the external ready signal is to be used or not (R2, bit 2). R1 & R0 (bits 1-0) in
these registers control the number of wait-states that are inserted during each access to a memory or
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IA186EM/IA188EM
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Data Sheet
As of Production Version -03
peripheral location (from 0 to 3). The control registers for pcs3_n – pcs0_n utilize three bits, R3, R1 – R0
(bits 3, 1 – 0) to provide 5, 7, 9, and 15 wait-states in addition to the original values of 0 – 3 wait states.
In the case where an external ready has been selected as required, internally programmed
wait-states will always be completed before the external ready can finish or extend a bus cycle. As an
example, consider a system in which the number of wait-states to be inserted has been set to three. The
external ready pin is sampled by the processor during the first wait cycle. The access is completed after
seven cycles (4 cycles plus 3 wait-cycles) if the ready is asserted. Alternatively, if the ready is not asserted
during the first wait cycle the access is prolonged until ready is asserted and two more wait-states are
inserted followed by t4.
Chip Select Overlap
Overlapping chip selects are those configurations in which more than one chip-select is asserted for the
same physical address. For example, if PCS is configured in I/O space with LCS or any other chip select
configured for memory, address 00000h is not overlapping the chip selects. It is not recommended that
multiple chip-select signals be asserted for the same physical address, although it may be inescapable in
certain systems. If this is the case, then all overlapping chip-selects must have the same external ready
configuration and the same number of wait-states to be inserted into access cycles.
Internal signals are employed to access the peripheral control block (PCB) and these signals serve as chip
selects that are configured with no wait-states and no external ready. Therefore, the PCB can be
programmed with addresses that overlap external chip-selects only if these chip selects are configured in
the same manner.
Care should be exercised in the use of the Disable Address (DA) bit in the LMCS or UMCS registers
when overlapping an additional chip-select with either the lcs_n or ucs_n chip-selects. Setting the DA bit
to 1 prevents the address from being driven onto the AD bus for all accesses for which the respective
chip-select is active, including those accesses for which the multiple selects are active.
The mcs_n and pcs_n pins are dual-purpose pins, either as chip-selects or PIO inputs or outputs.
However, their respective ready and wait-state configurations for their chip-select function will be in
effect no matter for which function these two pins are actually programmed. This requires that even if
these pins are configured as PIO and enabled (by writing to the MMCS and MPCS registers for the
mcs_n chip-selects and to the PACS and MPCS registers for the pcs_n chip-selects), the ready and waitstate settings for these signals must agree with the settings for any over-lapping chip-selects as if they had
been configured as chip-selects.
Even though pcs4_n is not available as an external pin it has ready and wait-state logic and must therefore
follow the rules for overlapping chip-selects. pcs6_n and pcs5_n on the other hand have ready and waitstate logic that is disabled when these pins are configured as address bits a2 and a1 respectively.
If the chip-select configuration rules are not followed, the processor may hang with the appearance of
waiting for a ready signal even in a system in which ready (ardy or srdy) is always set to 1.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Upper Memory Chip Select
The ucs_n chip-select is for the top of memory. On reset, the micro controller begins fetching and
executing instructions at memory location FFFF0h. As a result, upper memory is usually utilized for
instruction memory. To this end, ucs_n is active on reset and has a memory range of 64Kbytes (F0000h
to FFFFFh) as default along with external ready required and three wait-states automatically inserted.
The lower boundary of ucs_n is programmable to provide ranges of 64Kbytes to 512Kbytes.
Low Memory Chip Select
The lcs_n chip-select is for lower memory. As the interrupt vector table is at the bottom of memory
beginning at 00000h, this pin us usually utilized for control data memory. Unlike ucs_n, this pin is
inactive on reset, but it can be activated by any read or write to the LMCS register.
Midrange Memory Chip Selects
There are four midrange chip-selects, mcs3_n-mcs0_n, which may be used in a user-located memory
block. The base address of the memory block may be located anywhere in the 1-Mbyte memory address
space with some exceptions. The memory spaces used by the ucs_n and lcs_n chip-selects are excluded,
as are the pcs6_n, pcs5_n, and pcs3_n – pcs0_n. If the pcs_n chip-selects are mapped to I/O space then
the MCS address range can overlap the PCS address range.
Both the Midrange Memory Chip Select (MMCS) register and the MCS and PCS Auxiliary register
(MPCS) registers are used to program the four midrange chip-selects. The MPCS register is used to
configure the block size, whereas the MMCS register configures the base address, the ready condition,
and the wait states of the memory block accessed by the mcs_n pin. The chip selects (mcs3_n-mcs0_n)
are activated by performing a read or write operation of the MMCS and MPCS registers. The assertion of
the MCS outputs occurs with the same timing as the multiplexed AD address bus (ad15-ad0 or ao15-ao8
and ad7-ad0). The a19-a0 may be used for address selection, but the timing will be delayed by a half
clock cycle over the timing used for the ucs_n and lcs_n.
Peripheral Chip Selects
There are six peripheral chip-selects, pcs6_n, pcs5_n, and pcs3_n – pcs0_n, that may be used within a
user-defined memory or I/O block. The base address of this user-defined memory block can be located
anywhere within the 1-Mbyte memory address space except for the spaces associated with the ucs_n,
lcs_n, and mcs_n chip selects. Or it may be programmed to the 64Kbyte I/O space. pcs4_n is not
available.
Both the Peripheral Chip Select (PACS) register and the MCS and PCS Auxiliary register (MPCS)
registers are used to program the six peripheral chip-selects, pcs6_n, pcs5_n, and pcs3_n – pcs0_n. The
PACS register sets the base address, the ready condition, and the wait states for the pcs3_n – pcs0_n
outputs.
The MPCS register configures pcs6_n and pcs5_n pins as either chip selects or address pins a1 and a2
respectively. When these pins are chip selects the MPCS register also configures them as being active
during memory or I/O bus cycles, and their ready and wait states.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
None of the pcs_n pins are active at reset. Both the Peripheral Chip Select (PACS) register and the MCS
and PCS Auxiliary register (MPCS) registers must be read or written to activate the pcs_n pins aws chip
selects.
pcs6_n and pcs5_n may be programmed to have 0 to 3 wait-states, whereas pcs3_n – pcs0_n may be
programmed to have these and 5, 7, 9, and 15 wait-states.
Refresh Control
The Refresh Control Unit (RCU) generates refresh bus cycles. The RCU generates a memory read
request after a programmable period of time to the bus interface unit.
The ENA bit in the Enable RCU register (EDRAM) enables refresh cycles, operating off the processor
internal clock. If the processor is in power-save mode, the RCU must be reconfigured for the new clock
rate.
If the hlda pin is asserted when a refresh request is initiated (indicating a bus hold condition), the
processor disables the hlda pin to allow a refresh cycle to be performed. The external circuit bus master
must deassert the hold signal for at least one clock period to permit the execution of the refresh cycle.
Interrupt Control
Interrupt requests originate from a variety of internal and external sources that are arranged by the internal
interrupt controller in priority order and presented one by one to the processor.
Six external interrupt sources, five maskable (int4-int0) and one nonmaskable (NMI), are connected to
the processor and six internal interrupt sources (three timers, two DMA channels, and the asynchronous
serial port that are not brought out to external pins).
The five external maskable interrupt request pins can be used as direct interrupt requests. However,
should more interrupts be needed, int3-int0 may be with an external interrupt controller of the 82C59A
type. By programming the internal interrupt controller to slave mode, an external 82C59A compatible
interrupt controller can be used as the system master. Interrupt nesting can be used in all cases that permit
interrupts of a higher priority to interrupt those of a lower priority.
When an interrupt is accepted, other interrupts are disabled, but may be re-enabled by setting the Interrupt
Enable Flag (IF), in the Processor Status Flags register, during the Interrupt Service Routine (ISR).
Setting IF permits interrupts of equal or greater priority to interrupt the currently running ISR.
Further interrupts from the same source will be blocked until the corresponding bit in the In-Service
register (INSERV) is cleared. Special Fully Nested mode is invoked for int0 and int1 by the SFNM bit in
the INT0 and INT1 control registerm, respectively, when this bit is set to 1. In this mode a new interrupt
may be generated by these sources regardless of the in-service bit. The following table shows the
priorities of the interrupts at power-on reset.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Interrupt Types
Interrupt Name
Divide Error Exception (1)
Trace Interrupt (2)
Non-maskable Interrupt (NMI)
Breakpoint Interrupt (1)
(1)
INT0 Detected Overflow Exception
(1)
Array Bounds Exception
Unused Opcode Exception
(1)
(1, 3)
ESC Opcode Exception
(4, 5)
Timer 0 Interrupt
(4, 5)
Timer 1 Interrupt
(4, 5)
Timer 2 Interrupt
Reserved
(5)
DMA 0 Interrupt
(5)
DMA 1 Interrupt
INT0 Interrupt
INT1 Interrupt
INT2 Interrupt
INT3 Interrupt
(6)
INT4 Interrupt
(6)
Watchdog Timer Interrupt
(6)
Asynchronous Serial Port Interrupt
Reserved
00h
01h
02h
03h
04h
05h
Vector
Table
Address
00h
04h
08h
0ch
10h
14h
06h
18h
N/A
1
07h
08h
12h
13h
09h
0ah
0bh
0ch
0dh
0eh
0fh
10h
11h
14h
15h – 1fh
1ch
20h
48h
4ch
24h
28h
2ch
30h
34h
38h
3ch
40h
44h
50h
54h – 7ch
N/A
08h
08h
08h
1
2A
2B
2C
0ah
0bh
0ch
0dh
0eh
0fh
10h
11h
14h
3
4
5
6
7
8
9
9
9
Interrupt
Type
EOI
Type
Overall
Priority
Related
Instructions
N/A
N/A
N/A
N/A
N/A
N/A
1
1A
1B
1
1
1
DIV, IDIV
All
INT3
INT0
BOUND
Undefined
Opcodes
ESC Opcodes
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Interrupt Table Notes
If the user does not change priority levels, the default priority level will be used for the interrupt sources.
1. Instruction execution generates interrupts.
2. Performed in the same manner as for the 8086 & 8088.
3. An ESC opcode causes a trap.
4. Only one IRQ is generated for the three timers so they share priority level with regard to other
sources. The timers themselves have an interrupt priority order among themselves (2A > 2B > 2C).
5. These interrupt types are programmable in Slave mode.
6. Not available in slave mode.
Timer Control
The IA186EM and IA188EM each have three 16-bit programmable timers.
Timer0 and timer1 each have an input and an output connected to external pins that permit them to count
or time events, produce variable duty-cycle waveforms or non-repetitive waveforms. Timer1 can also be
configured as a Watchdog timer.
Timer2 does not have any external connections. Therefore, it is confined to internal functions such as
real-time coding, time-delay applications, a prescaler for timer0 and timer1, or to synchronize DMA
transfers.
The Peripheral Control Block contains eleven 16-bit registers to control the programmable timers. The
present value of the timer is located in the associated timer-count register, which may be read from or
written to at any time regardless of whether the timer is in operation or not. The value of the timer-count
register is incremented by the microcontroller every time a timer event takes place.
The maximum value that each timer can reach is determined by the value stored in the associated
maximum count register. Upon reaching this maximum count value, the timer count register is reset to 0
in the same clock cycle that this count was attained, so that the timer count register does not store this
maximum value. Both timer0 and timer1 have two maximum count registers, a primary and a secondary
register, permitting each timer to alternate between two discrete maximum values.
Timer0 and timer1 can have the maximum count registers configured in one of two ways, primary only or
both primary and secondary. If only the primary is configured to operate, on reaching the maximum
count the output pin will go low for one clock period. If both the primary and secondary registers are
enabled, the output pin reflects the state of whichever of the two registers is in control at the time,
generating the required waveform that is dependent on the two values in the maximum count registers.
The timers can operate at a quarter of the internal clock frequency, as they are polled every fourth clock
period. Alternatively, an external clock can be used. However, in this case the timer output can take six
clock cycles to respond to the input.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Direct Memory Access (DMA)
Direct memory access (DMA) relieves the CPU of involvement in the transfer of data between memory
and peripherals over either one or both high-speed DMA channels. Data can be transferred from memory
to I/O, I/O to memory, memory-to-memory, or I/O-to-I/O. Furthermore, the DMA channels can be
connected to the asynchronous serial port.
The IA186EM microcontroller supports the transfer of both bytes and words, to and from, even or odd
addresses, but it does not support word transfers to memory that is configured for byte accesses. The
IA188EM does not support word transfers at all. Each data transfer will take two bus cycles (a minimum
of 8 clock cycles).
There are three sources of DMA requests for each DMA channel: the channel request pin (drq1 – drq0),
Timer2, or the system software. The two channels can be programmed to have different priorities to
facilitate the resolution of simultaneous DMA requests or to interrupt a transfer on the other channel.
DMA Operation
The Peripheral Control Block contains six registers for each DMA channel to control and specify the
operation of the channels. The six registers consist of a pair of registers to store a 20-bit source address, a
pair of registers to store a 20-bit destination address, a 16-bit transfer count register, and a 16-bit control
register.
The number of DMA transfers required is designated in the DMA Transfer Count register and can be up
to 64K bytes or words and, furthermore, will end automatically. DMA channel function is defined by the
Control registers, which along with the other 5 registers can be changed at any time, including during a
DMA transfer and are implemented immediately.
DMA Channel Control Registers
See D1CON (0dah) & D0CON (0cah) - DMA CONtrol Registers above. Briefly, these registers specify
the following:
"
Is the data destination in memory or I/O space? (Bit 15).
"
Is the destination address incremented, decremented, or unchanged after each transfer? (Bit 14 & 13).
"
Is the data source in memory or I/O space? (Bit 12).
"
Is the source address incremented, decremented, or unchanged after each transfer? (Bit 11 & 10).
"
Do DMA transfers cease upon reaching a designated count? (Bit 9).
"
Does the last transfer generate an interrupt? (Bit 8).
"
Synchronization mode. (Bits 7 & 6).
"
The relative priority of one DMA channel with respect to the other. (Bit 5).
"
Acceptance of DMA requests from Timer2. (Bit 4).
"
Byte or word transfers. (Bit 0).
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
20-bit Adder/Subtractor
As of Production Version -03
Adder Control
Logic
20
Timer Request
Request
Selection
Logic
Transfer Counter Ch. 1
Destination Address Ch. 1
Source Address Ch. 1
Transfer Counter Ch. 0
Destination Address Ch. 0
Source Address Ch. 0
DMA
Control
Logic
20
Channel Control Register 1
Channel Control Register 0
drq1
drq0
Interrupt
Request
16
Internal Address/Data Bus
Figure 4. DMA Unit
DMA Priority
DMA transfers have a higher priority than CPU transfers, with the exception of word accesses to odd
memory locations or between locked memory addresses. The CPU cannot access memory during a DMA
transfer and a DMA transfer cannot be suspended by an interrupt request. Continuous DMA activity will
thus cause interrupt latency to suffer. However, an NMI request halts any DMA activity, enabling the
CPU to respond promptly to the request.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Asynchronous Serial Port
The asynchronous serial port employs standard industry communication protocols in its implementation
of full duplex, bi-directional data transfers. The port can be the source or destination of DMA transfers.
The following features are supported:
" Full-duplex data transfers
" 7-, 8-, or 9-bit data transfers
" Odd, even, or no parity
" One or two stop bits
" Error detection provided by Parity, Framing, or Overrun errors
" Hardware handshaking is achieved with the following selectable control signals: Clear-to-send (cts_n)
o Enable receiver request (enrx_n)
o Ready to send (rts_n)
o Ready to receive (rtr_n)
"
"
"
"
"
DMA to and from the port
The port has its own maskable interrupt
The port has an independent baud rate generator
Maximum baud rate is 1/32 of the processor clock
Transmit and Receive lines are double buffered
In power-save mode the baud rate generator divide factor must be re-programmed to compensate for the
change in clock rate.
Synchronous Serial Port
The synchronous serial port allows the microcontrollers to communicate with ASICs that are required to
be programmed but have a pin shortage. The four-pin interface allows half-duplex, bi-directional data
transfer at a maximum of 20 Mbits/sec with a 40 MHz CPU clock.
The synchronous serial interface of the AI186EM/AI188EM operates as the master port in a master/slave
arrangement.
There are four pins in the synchronous serial interface for communication with the system elements.
These pins are two enables (SDEN0 and SDEN1), a clock (SCLK) and a data pin (SDATA).
In power-save mode, the baud rate generator divide factor must be re-programmed to compensate for the
change in clock rate.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Programmable I/O (PIO)
32 pins are programmable as I/O signals. The following tables list these pins with their pin name and PIO
number, first in PIO numerical order, then in pin name alphabetical order. Programming a pin as a PIO
should only be performed if the normal pin function is not required as the normal function is disabled and
no longer has any affect on the pin. A PIO pin can be programmed as an input or output with or without
either a weak pull-up or pull-down, or as an open-drain output. Following a power-on reset, the PIO pins
have default status as shown in the following tables.
PIO
No.
0
1
2
3
4
5
6
7(1)
8(1)
9(1)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26(1,2)
27
28
29(1,2)
30
31
Associated Pin
tmrin1
tmrout1
pcs6_n/a2
pcs5_n/a1
dt/r_n
den_n
srdy
a17
a18
a19
tmrout0
tmrin0
drq0
drq1
mcs0_n
mcs1_n
pcs0_n
pcs1_n
pcs2_n
pcs3_n
sclk
sdata
sden0
sden1
mcs2_n
mcs3_n/rfsh_n
uzi_n
txd
rxd
s6/clkdiv2
int4
int2
Power-On Reset
Status
Input with pull-up
Input with pull-down
Input with pull-up
Normal operation(3)
Normal operation(3)
Normal operation(3)
Normal operation(3)
Normal operation(3)
Normal operation(3)
Normal operation(3)
Input with pull-down
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Associated Pin
a17
a18
a19
den_n/ds_n
drq0
drq1
dt/r_n
int2/
int4
mcs0_n
mcs1_n
mcs2_n
mcs3_n/rfsh_n
pcs0_n
pcs1_n
pcs2_n
pcs3_n
pcs5_n/a1
pcs6_n/a2
rxd
s6/clkdiv2
sclk
sdata
sden0
sden1
srdy
tmrin0
tmrin1
tmrout0
tmrout1
txd
uzi_n
PIO No.
7
8
9
5
12
13
4
31
30
14
15
24
25
16
17
18
19
3
2
28
29
20
21
22
23
6
11
0
10
1
27
26
Power-On Reset
Status
Normal operation(3)
Normal operation(3)
Normal operation(3)
Normal operation(3)
Input with pull-up
Input with pull-up
Normal operation(3)
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up(1,2)
Input with pull-up
Input with pull-up
Input with pull-up
Input with pull-up
Normal operation(4)
Input with pull-up
Input with pull-up
Input with pull-down
Input with pull-down
Input with pull-up
Input with pull-up
NOTES
These notes apply to both tables:
1. Emulators use these pins and also s2_n-s0_n, res_n, nmi, clkouta, bhe_n ale, ad15-ad0, and a15-a0.
2. If bhe_n/aden_n (IA186EM) or rfsh_n/aden_n (IA188M) is held low during power-on reset, these
pins will revert to normal operation.
3. Input with pull-up option available when used as PIO.
4. Input with pull-down option available when used as PIO.
These default status setting may be changed as desired.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
The three most significant bits of the address bus (a19 – a17) start with their normal function on poweron reset, permitting the processor to begin fetching instructions from the boot address FFFF0h.
Furthermore, normal function is the default setting for dt/r_n, den_n, and srdy on power-on reset.
s6/clkdiv2_n and uzi_n automatically return to normal operation in the event that the ad15-ad0 bus
override is enabled. The ad15-ad0 bus override is enabled if the bhe_n/aden_n for the IA186EM, or the
rfsh2_n/aden_n for the IA188EM, is held low during power-on reset.
Pin Descriptions
a19 (pio9), a18 (pio8), a17 (pio7), a16 – a0 Address Bus (synchronous outputs with tristate)
These pins are the system’s source of non-multiplexed I/O or memory addresses and occur a half
CLKOUTA cycle before the multiplexed address/data bus (ad15-ad0 for the IA186EM or ao15_ao8 and
ad7-ad0 for the AI188EM). The address bus is tristated during a bus hold or reset.
ad15 – ad8 IA186EM Address/Data bus (level-sensitive synchronous inouts with tristate)
These pins are the system’s source of time-multiplexed I/O or memory addresses and data. The address
function of these pins can be disabled. (See bhe_n/aden_n pin description.) If the address function of
these pins is enabled, the address will be present on this bus during t1 of the bus cycle and data will be
present during t2, t3, and t4 of the same bus cycle.
If whb_n is not active, these pins are tristated during t2, t3, and t4 of the bus cycle.
The address/data bus is tristated during a bus hold or reset.
These pins can be used to load the internal Reset Configuration register (RESCON, offset 0F6h) with
configuration data during a power-on reset.
ad7 – ad0 Address/Data bus (level-sensitive synchronous inouts with tristate)
These pins are the system’s source of time-multiplexed low-order byte of the addresses for I/O or memory
and 8-bit data. The low-order address byte will be present on this bus during t1 of the bus cycle and the 8bit data will be present during t2, t3, and t4 of the same bus cycle.
The address function of these pins can be disabled. (See bhe_n/aden_n pin description.)
If wlb_n is not active, these pins are tristated during t2, t3, and t4 of the bus cycle. The address/data bus is
tristated during a bus hold or reset.
ao15 – ao8 IA188EM Address-only bus (level-sensitive synchronous outputs with tristate)
The address-only bus will contain valid high-order address bits during the bus cycle (t1, t2, t3, and t4) if the
bus is enabled.
These pins are combined with ad7-ad0 to complete the multiplexed address bus and are tristated during a
bus hold or reset condition.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
ale Address Latch Enable (synchronous output)
This signal indicates the presence of an address on the address bus (ad15-ad0 for the IA186EM or ao15ao8 and ad7-ad0 for the AI188EM), which is guaranteed to be valid on the falling edge of ale.
ardy Asynchronous Ready (level-sensitive asynchronous input)
This asynchronous signal provides an indication to the microcontroller that the addressed I/O device or
memory space will complete a data transfer. This active high signal is asynchronous with respect to
clkouta and if the falling edge of ardy is not synchronized to clkouta and additional clock cycle may be
added
ardy should be tied high to maintain a permanent assertion of the ready condition. On the other hand, if
the ardy signal is not used by the system it should be tied low, which passes control to the srdy signal.
bhe_n/aden_n IA186EM only Bus High Enable (synchronous output with tristate) /Address Enable
(input with internal pull-up)
bhe_n - bhe_n and address bit ad0 or a0 inform the system which bytes of the data bus (upper, lower, or
both) are involved in the current memory access bus cycle as shown in the following table.
bhe_n
0
0
1
1
ad0
0
1
0
1
Type of Bus Cycle
Word Transfer
High-Byte Transfer (Bits 15-8)
Low-Byte Transfer (Bits 7-0)
Refresh
bhe_n does not require latching and during bus hold and reset is tristated. It is asserted during t1 and
remains so through t3 and tw.
The high and low byte write enable functions of bhe_n and ad0 are performed by whb_n and wlb_n
respectively.
When using the ad bus, DRAM refresh cycles are indicated by bhe_n/aden_n and ad0 both being high.
During refresh cycles the a and ad busses may not have the same address during the address phase of the
ad bus cycle necessitating the use of ad0 as a determinant for the refresh cycle rather than A0.
An additional signal is utilized for PSRAM refreshes (see mcs3_n/rfsh_n pin description).
aden_n
There is a weak internal pull-up on bhe_n/aden_n obviating the need for an external pull-up and reducing
power consumption.
Holding aden_n high or letting it float during power-on reset passes control of the address function of the
ad bus (ad15-ad0) during LCS and UCS bus cycles from aden_n to the DA bit in LMCS and UMCS
registers. When the address function is selected, the memory address is placed on the a19-a0 pins.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
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Holding aden_n low during power-on reset, both the address and data are driven onto the ad bus
independently of the DA bit setting. This pin is normally sampled one clock cycle after the rising edge of
res_n.
clkouta – Clock Output A (synchronous output)
This pin is the internal clock output to the system. Bits 9, 8, and 2-0 of the Power-Save Control register
(PDCON) control the output of this pin, which may be tristated, output the crystal input frequency (X1),
or output the power save frequency (internal processor frequency after divisor). clkouta can be used as a
full speed clock source in power-save mode. The A.C. timing specifications that are clock-related refer to
clkouta, which remains active during reset and hold conditions.
clkoutb – Clock Output B (synchronous output)
This pin is an additional clock out put to the system. Bits 11, 10, and 2-0 of the Power-Save Control
register (PDCON) control the output of this pin, which may be tristated, output the PLL frequency, or
may output the power save frequency (internal processor frequency after divisor). clkoutb remains active
during reset and hold conditions.
den_n (pio5) – Data Enable Strobe ( synchronous output with tristate)
This pin provides an output enable to an external bus data bus transmitter or receiver. This signal is
asserted during I/O, memory, and interrupt acknowledge processes and is deasserted when dt/r_n
undergoes a change of state. It is tristated for a bus hold or reset.
drq1-drq (pio12-pio13) – DMA Requests (synchronous level-sensitive inputs)
drq0 – An external device that is ready for DMA channel 1 or 0 to carry out a transfer indicates to the
microcontroller this readiness on these pins. They are level triggered, internally synchronized, not
latched, and must remain asserted until dealt with.
dt/r_n (pio4) – Data Transmit or Receive (synchronous output with tristate)
The microntroller transmits data when dt/r_n is pulled high and receives data when this pin is pulled low.
It floats during a reset or bus hold condition.
gnd – Ground
Six or seven pins, depending on package, connect the microcontroller to the system ground.
hlda – Bus Hold Acknowledge (synchronous output)
This pin is pulled high to signal the system that the microntroller has ceded control of the local bus, in
response to a high on the hold signal by an external bus master, after the microcontroller has completed
the current bus cycle. The assertion of hlda is accompanied by the tristating of den_n, rd_n, wr_n,
s2_n-s0_n, ad15-ad0, s6, a19-a0, bhe_n, whb_n, wlb_n, and dt/r_n, followed by the driving high of the
chip selects ucs_n, lcs_n, mcs3_n - mcs0_n, pcs6_n – pcs5_n, and pcs3_n – pcs0_n. The external bus
master releases control of the local bus by the deassertion of hold that in turn induces the microcontroller
to deassert the hlda. The microcontroller can take control of the bus if necessary (to execute a refresh for
example), by deasserting hlda without the bus master first deasserting hold. This requires that the
external bus master be able to deassert hold to permit the microcontroller to access the bus.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
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hold – Bus Hold Request (synchronous level-sensitive input)
This pin is pulled high to signal the microcontroller that the system requires control of the local bus.
hold latency time (time between the hold and hlda) depends on the current processor activity when the
hold is received. A hold request is second only do a DMA refresh request in priority of processor activity
requests. If a hold request is received at the moment a DMA transfer starts, the hold latency can be up to
4 bus cycles. (On the IA186EM only, this happens when a word transfer is taking place from an odd to an
odd address). This means that the latency may be 16 clock cycles without wait states. Furthermore, if
lock transfers are being performed, then the latency time is increased by the during of the locked transfer.
int0 – Maskable Interrupt Request 0 (asynchronous input)
The int0 pin provides an indication that an interrupt request has occurred, and provided that int0 is not
masked, program execution will continue at the location specified by the INT0 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be
edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to
ensure that it is recognized.
int1/select_n – Maskable Interrupt Request 1/Slave Select (both are asynchronous inputs)
int1 - The int1 pin provides an indication that an interrupt request has occurred, and provided that int1 is
not masked, program execution will continue at the location specified by the INT1 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be
edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to
ensure that it is recognized.
select_n – This pin provides an indication to the microcontroller that an interrupt type has been placed on
the address/data bus when the internal Interrupt Control Unit is slaved to an external interrupt controller.
Before this occurs, however, the int0 pin must have indicated an interrupt request has occurred.
int2/inta0_n (pio31) – Maskable Interrupt Request 2 (asynchronous input) / Interrupt Acknowledge
0 (synchronous output)
int2 - The int2 pin provides an indication that an interrupt request has occurred, and provided that int2 is
not masked, program execution will continue at the location specified by the int2 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be
edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to
ensure that it is recognized. When int0 is configured to be in cascade mode, int2 changes its function to
inta0_n.
inta0_n – this function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int0 when the microcontroller’s Interrupt Control Unit is in cascade
mode. The peripheral device that issued the interrupt must provide the interrupt type.
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int3/inta1_n/irq – Maskable Interrupt Request 3 (asynchronous input) / Interrupt Acknowledge 1
(synchronous output) / Interrupt Acknowledge (synchronous output)
int3 - The int3 pin provides an indication that an interrupt request has occurred, and provided that int3 is
not masked, program execution will continue at the location specified by the int3 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be
edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to
ensure that it is recognized. When int1 is configured to be in cascade mode, int3 changes its function to
inta1_n.
inta1_n – this function indicates to the system that the microcontroller requires an interrupt type in
response to the interrupt request int1 when the microcontroller’s Interrupt Control Unit is in cascade
mode. The peripheral device that issued the interrupt must provide the interrupt type.
irq – With the Interrupt Control Unit of the microcontroller in slave mode, the signal on this pin allows
the microcontroller to output an interrupt request to the external master interrupt controller.
int4/pio30 – Maskable Interrupt Request 4 (asynchronous input)
int4 - The int4 pin provides an indication that an interrupt request has occurred, and provided that int4 is
not masked, program execution will continue at the location specified by the int4 vector in the interrupt
vector table. Although interrupt requests are asynchronous, they are synchronized internally and may be
edge- or level-triggered. The assertion of the interrupt request must be maintained until it is handled, to
ensure that it is recognized.
lcs_n/once0_n – Lower Memory Chip Select (synchronous output with internal pull-up) / ONCE
Mode Request (input)
lcs_n - The lcs_n pin provides an indication that a memory access is occurring to the lower memory
block. The size of the Lower Memory Block and its base address are programmable, with the size
adjustable up to 512 Kbytes. lcs_n is held high during bus hold.
once0_n – (ONCE – ON Circuit Emulation). This pin and its companion pin once1_n define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if both
are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE mode, all
pins are tristated and remain so until a subsequent reset. To prevent the microcontroller from entering
ONCE mode inadvertently, this pin has a weak pull-up that is only present during reset. Finally, this pin
is not tristated during bus hold.
mcs2_n – mcs0_n (no pio - pio15 – pio 14) – Midrange Memory Chip Selects (synchronous outputs
with internal pull-up)
mcs0_n - The mcs2_n and mcs0_n pins provide an indication that a memory access is in train to either
the second or third midrange memory block. The size of the Midrange Memory Block and its base
address are programmable. mcs2_n – mcs0_n are held high during bus hold and have weak pull-ups that
are only present during reset.
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IA186EM/IA188EM
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mcs3_n/rfsh_n (pio25) – Midrange Memory Chip Select (synchronous output with internal pull-up)
/ Automatic Refresh (synchronous output)
mcs3_n - The mcs3_n pin provides an indication that a memory access is in train to the fourth region of
the midrange memory block. The size of the Midrange Memory Block and its base address are
programmable. mcs3_n is held high during bus hold and has a weak pull-up that is present only during
reset.
rfsh_n – This signal is timed for auto refresh to PSRAM or DRAM devices. The refresh pulse is output
only when the PSRAM or DRAM mode bit is set (EDRAM register bit 15). This pulse is of 1.5 clock
pulse duration with the rest of the refresh cycle made up of a deassertion period such that the overall
refresh time is met. Finally, this pin is not tristated during a bus hold.
nmi – Nonmaskable Interrupt (synchronous edge-sensitive input)
This is the highest priority interrupt signal and cannot be masked, unlike int4 – int0.
Program execution is transferred to the nonmaskable interrupt vector in the interrupt vector table, upon
the assertion of this interrupt (transition from Low to High), and this interrupt is initiated at the next
instruction boundary. For recognition to be assured the nmi pin must be held high for at least a clkouta
period so that the transition from low to high is latched and synchronized internally. The interrupt will
begin at the next instruction boundary.
The NMI is not involved in the priority resolution process that deals with the maskable interrupts, and
does not have an associated interrupt flag. This allows for a new NMI request to interrupt an NMI service
routine that is already underway. The interrupt flag IF is cleared, disabling the maskable interrupts, when
an interrupt is taken by the processor. If, during the NMI service routine, the maskable interrupts are reenabled, by use of STI instruction for example, the priority resolution of maskable interrupts will be
unaffected by the servicing of the NMI. For this reason, it is strongly recommended that the NMI interrupt
service routine does not enable the maskable interrupts.
pcs3_n - pcs0_n (pio19 – pio16) – Peripheral Chip Selects 3-0 (synchronous outputs)
These pins provide an indication that a memory access is under way for the corresponding region of the
peripheral memory block (I/O or memory address space). The base address of the Peripheral memory
block is programmable. pcs3_n – pcs0_n are held high during both bus hold and reset. These outputs are
asserted with the ad address bus over a 256-byte range each.
pcs5_n/A1– Peripheral Chip Select 5 (synchronous output) / latched Address Bit 1 (synchronous
output)
pcs5_n – This signal provides an indication that a memory access is under way for the sixth region of the
peripheral memory block (I/O or memory address space). The base address of the Peripheral memory
block is programmable. pcs5_n is held high during both bus hold and reset. This output is asserted with
the ad address bus over a 256-byte range.
A1 – This pin provides and internally latched address bit 1 to the system when the EX bit (bit 7) in the
MCS_n and PCS_n auxiliary (MPCS) register is 0. It retains its previously latched value during a bus
hold.
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IA186EM/IA188EM
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pcs6_n/A2/ – Peripheral Chip Select 6 (synchronous output) / latched Address Bit 2 (synchronous
output)
pcs6_n – This signal provides an indication that a memory access is under way for the seventh region of
the peripheral memory block (I/O or memory address space). The base address of the Peripheral memory
block is programmable. pcs6_n is held high during both bus hold and reset. This output is asserted with
the ad address bus over a 256-byte range.
A2 – This pin provides and internally latched address bit 2 to the system when the EX bit (bit 7) in the
MCS_n and PCS_n auxiliary (MPCS) register is 0. It retains its previously latched value during a bus
hold.
pio31 – pio0
Programmable I/O Pins (asynchronous input/output open –drain)
32 individually programmable I/O pins are provided. See page 62.
rd_n - Read strobe (synchronous output with tristate)
This pin provides an indication to the system that a memory or I/O read cycle is under way. It will not to
be asserted before the ad bus is floated during the address to data transition. rd_n is tristated during bus
hold.
res_n - Reset (asynchronous level-sensitive input)
This pin forces a reset on the microcontroller. It has a Schmitt trigger to allow power-on reset generation
via an RC network. When this signal is asserted, the microcontroller immediately terminates its present
activity, clears its internal logic, and transfers CPU control to the reset address, FFFF0h.
res_n must be asserted for at least 1ms and may be asserted asynchronously to clkouta as it is
synchronized internally. Furthermore, Vcc must be within specification and clkouta must be stable for
more than four of its clock periods for the period that res_n is asserted.
The microcontroller starts to fetch instructions 6.5 clkouta clock periods after the deassertion of res_n.
rfsh2_n/aden_n - IA188EM only - Refresh 2 (synchronous output with tristate) / Address Enable
(input with internal pull-up)
rfsh2_n – Indicates that a DRAM refresh cycle is being performed when it is asserted low. However, this
is not valid in PSRAM mode where mcs3_n/rfsh_n is used instead.
aden_n – If this pin is held high during power-on reset, the ad bus (ao15-ao8 & ad7-ad0) is controlled
during the address portion of the LCS and UCS bus cycles by the DA bit (bit 7) in the LCS and UCS
registers. If the DA bit is 1, the address is accessed on the a19-a0 pins reducing power consumption. The
weak pull-up on this pin obviates the necessity of an external pull-up.
If this pin is held low during power-on reset, the ad bus is used for both addresses and data without regard
for the setting of the DA bits. rfsh2_n/aden_n is sampled one crystal clock cycle after the rising edge of
res_n and is tristated during bus holds and ONCE mode.
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IA186EM/IA188EM
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rxd (pio28) - Receive Data (asynchronous input)
This signal connects asynchronous serial receive data from the system to the asynchronous serial port.
s2_n-s0_n - Bus Cycle Status (synchronous outputs with tristate)
These three signals inform the system of the type of bus cycle is in progress. s2_n may be used to
indicate whether the current access is to memory or I/O, and s1_n may be used to indicate whether data is
being transmitted or received. These signals are tristated during bus hold and hold acknowledge.
The coding for these pins is shown in the following table.
s2_n
0
0
0
0
1
1
1
1
s1_n
0
0
1
1
0
0
1
1
s0_n
0
1
0
1
0
1
0
1
Bus Cycle
Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
None (passive)
s6/clkdiv2_n (pio29) - Bus Cycle Status Bit 6 (synchronous output) /Clock Divide by 2 (input with
internal pull-up)
s6 - This signal is high during the second and remaining cycle periods, i.e. t2 – t4, indicating that a DMA–
initiated bus cycle is under way. s6 is tristated during bus hold or reset.
clkdiv2_n – The microcontroller enters clock divide-by-2 mode, if this signal is held low during poweron-reset. In this mode, the PLL is disabled and the processor receives the external clock divided by 2.
Sampling of this pin occurs on the rising edge of res_n.
Should this pin be used as pio29 configured as an input, care should be taken that it is not driven low
during power-on-reset. This pin has an internal pull-up so it is not necessary to drive the pin high even
though it defaults to an input PIO.
sclk – Serial Clock (synchronous outputs with tristate)
This pin provides a slave device with a synchronous serial clock permitting synchronization of the
transmit and receive data exchanges between the slave and the microcontroller. sclk is the result of
dividing the internal clock by 2, 4, 8, or 16 dependent on the contents of the Synchronous Serial Control
(SSC) register bits 5-4. Accessing either the SSR of SSD registers activates the sclk for eight cycles.
When sclk is not active the microcontroller hold is high.
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IA186EM/IA188EM
8/16-BIT Microcontrollers
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sdata – Serial Data (synchronous inout)
This pin connects a slave device to synchronous serial transmit and receive data. The last value is
maintained on this pin when it is inactive.
sden1 - sden0 – Serial Data Enables (synchronous outputs with tristate)
These pins facilitate the transfer of data on ports 1 and 0 of the Synchronous Serial Interface (SSI). Either
sden1 or sden0 is asserted by the microcontroller at the start of the data transfer and is de-asserted it when
the transfer is completed. These pins are held low by the microcontroller when they are inactive.
srdy/pio6 - Synchronous Ready (synchronous level-sensitive input)
This signal is an active high input synchronized to clkouta and indicates to the microcontroller that a data
transfer will be completed by the addressed memory space or I/O device.
In contrast to the Asynchronous Ready (ardy), which requires internal synchronization, srdy permits
easier system timing as it already synchronized. Tying srdy high will always assert this ready condition,
whereas tying it low will give control to ardy.
tmrin0/pio11 - Timer Input 0 (synchronous edge-sensitive input)
This signal may be either a clock or control signal for the internal timer 0. The timer is incremented by
the microcontroller after it synchronizes a rising edge of tmrin0. When not used, tmrin0 must be tied
high, or when used as pio11 it is pulled up internally.
tmrin1/pio0 - Timer Input 1 (synchronous edge-sensitive input)
This signal may be either a clock or control signal for the internal timer 1. The timer is incremented by
the microcontroller after it synchronizes a rising edge of tmrin1. When not used, tmrin1 must be tied
high, or when used as pio0 it is pulled up internally.
tmrout0/pio10 - Timer Output 0 (synchronous output)
This signal provides the system with a single pulse or a continuous waveform with a programmable duty
cycle. It is tristated during a bus hold or reset.
tmrout1/pio1 - Timer Output 1 (synchronous output)
This signal provides the system with a single pulse or a continuous waveform with a programmable duty
cycle. It is tristated during a bus hold or reset.
txd/pio22 - Transmit Data (asynchronous output)
This pin provides the system with asynchronous serial transmit data from the serial port.
ucs_n/once1_n - Upper Memory Chip Select (synchronous output) / ONCE Mode Request 1 (input
with internal pull-up)
ucs_n - This pin provides an indication that a memory access is in train to the upper memory block. The
size of the Upper Memory Block and its base address are programmable, with the size adjustable up to
512 Kbytes. ucs_n is held high during bus hold.
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8/16-BIT Microcontrollers
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After power-on-reset, ucs_n is active low and program execution begins at FFFF0h with the default
configuration of the ucs_n chip select is for 64 Kbytes memory range from F0000h to FFFFFh.
once1_n – (ONCE – ON Circuit Emulation). This pin and its companion pin once0_n define the
microcontroller mode during reset. These two pins are sampled on the rising edge of res_n and if both
are asserted low the microcontroller starts in ONCE mode, else it starts normally. In ONCE mode all pins
are tristated and remain so until a subsequent reset. To prevent the microcontroller from entering ONCE
mode inadvertently, this pin has a weak pull-up that is only present during reset. Finally, this pin is not
tristated during bus hold.
uzi_n/pio26 – Upper Zero Indicate (synchronous output)
This pin allows the designer to determine if an access to the interrupt vector table is in progress by ORing
it with bits 15-10 of the address and data bus (ad15-ad10 on the AI186EM and ao15-ao10 on the
AI188EM). uzi_n is the logical OR of the inverted a19-a16 bits. It asserts in the first period of a bus
cycle and is held throughout the cycle.
At reset uzi_n should be pulled high or should be allowed to float. If this pin is pulled low at reset, the
microcontroller enters a reserved clock test mode.
vcc – Power Supply (input)
These pins supply power (+5V) to the microcontroller.
whb_n – Write High Byte - IA186EM only - (synchronous output with tristate)
This pin and wlb_n provide an indication to the system of which bytes of the data bus (upper, lower or
both) are taking part in a write cycle. whb_n is asserted with ad15_ad8 and is the logical OR of bhe_n
and wr_n. It is tristated during reset.
wlb_n/wb_n – Write Low Byte - IA186EM only - (synchronous output with tristate) / Write Byte –
IA188EM only - (synchronous output with tristate)
wlb_n - wlb_n and whb_n provide an indication to the system of which bytes of the data bus (upper,
lower, or both) are taking part in a write cycle. wlb_n is asserted with ad7_ad0 and is the logical OR of
ad0 and wr_n. It is tristated during reset.
wb_n – On the IA188EM microcontroller, wb_n provides an indication that a write to the bus is
occurring. It shares the same early timing as that of the non-multiplexed address bus, and is associated
with ad7-ad0. It is tristated during reset.
wr_n – Write Strobe (synchronous output)
This pin provides an indication to the system that the data currently on the bus is to be written to a
memory or I/O device. It is tristated during a bus hold or reset.
x1 – Crystal Input (input)
This pin and x2 are the connections for a fundamental mode or third-overtone, parallel-resonant crystal
used by the internal oscillator circuit. An external clock source for the microcontroller is connected to x1
while the x2 pin is left unconnected.
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IA186EM/IA188EM
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x2 – Crystal Input (input)
This pin and x1 are the connections for a fundamental mode or third-overtone, parallel-resonant crystal
used by the internal oscillator circuit. An external clock source for the microcontroller is connected to x1
while the x2 pin is left unconnected.
Pins Used by Emulators
The following pins are used by emulators:
a19-a0
ao15-ao8
ad7-ad0
ale
bhe_n/aden_n (on the AI186EM)
clkouta
rfsh2_n/aden_n (on the AI188EM)
rd_n
s2_n-s0_n
s6/lock_n/clkdiv2_n
uzi_n
Emulators require that s6/lock_n/clkdiv2_n and uzi_n be configured as their normal functions, i.e. as s6
and uzi_n respectively. Holding bhe_n/aden_n (AI186EM) or rfsh_n/aden_n (AI188EM) low during
the rising edge of res_n, s6 and uzi_n will be configured in their normal functions instead of as PIOs, at
reset.
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IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Instruction Set Summary
NOTE
Key to abbreviations appears at the end of the table.
Instruction
Mnemonic
AAA
AAD
AAM
AAS
Description
ASCII adjust AL after add
ASCII adjust AX before divide.
ASCII adjust AL after multiply
ASCII adjust AL after subtract
Add imm8 to AL with carry
Add imm16 to AX with carry
Add imm8 to r/m8 with carry
Add imm16 to r/m16 with carry
ADC
Add sign extended imm8 to r/m16
with carry
Add byte reg to r/m8 with carry
Add word reg to r/m16 with carry
Add r/m8 to byte reg with carry
Add r/m16 to word reg with carry
Add imm8 to AL
Add imm16 to AX
Add imm8 to r/m8
Add imm16 to r/m16
ADD
AND
Add sign extended imm8 to r/m16
Add byte reg. to r/m8
Add word reg. to r/m16
Add r/m8 to byte reg
Add r/m16 to word reg
And imm8 with AL
Opcode - Hex
byte byte byte
1
2
3-6
37
D5
0A
D4
0A
3F
14
ib
15
iw
/2
80
ib
/2
81
iw
/2
83
ib
10
/r
11
/r
12
/r
13
/r
04
ib
05
iw
/0
80
ib
/0
81
iw
/0
83
ib
00
/r
01
/r
02
/r
03
/r
24
ib
Clock Cycles
IA186
IA188
8
15
19
7
3
4
8
15
19
7
3
4
4/16
4/16
4/16
4/20
4/16
4/20
3/10
3/10
3/10
3/10
3
4
3/10
3/14
3/10
3/14
3
4
4/16
4/16
4/16
4/20
4/16
4/20
3/10
3/10
3/10
3/10
3
3/10
3/14
3/10
3/14
3
And imm16 with AX
25
iw
4
4
And imm8 with r/m8
80
/4
ib
4/16
4/16
And imm16 with r/m16
81
/4
iw
4/16
4/20
And sign-extended imm8 with
r/m16
83
/4
ib
4/16
4/20
And byte reg. with r/m8
20
/r
3/10
3/10
Flags Affected
O D I
T S Z A P C
U
U
U
U
-
-
-
U
R
R
U
U
R
R
U
R
U
U
R
U
R
R
U
R -
-
-
R R R R R
R -
-
-
R R R R R
0 -
-
-
R R U R
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
R
U
U
R
0
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
And word reg. with r/m16
21
/r
3/10
3/14
And r/m8 with byte reg
22
/r
3/10
3/10
And r/m16 with word reg
23
/r
3/10
3/14
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
Description
BOUND
Check array index against bounds
Call near, disp relative to next
instruction
Call near, reg indirect mem
Call far to full address given
Call far to address at m16:16 word
Convert byte integer to word
Clear carry flag
Clear direction flag
Clear interrupt-enable flag
Complement carry flag
Compare imm8 to AL
Compare imm16 to AX
Compare imm8 to r/m8
Compare imm16 to r/m16
Compare sign-extended imm8 to
r/m16
Compare byte reg to r/m8
Compare word reg to r/m16
Compare r/m8 to byte reg
Compare r/m16 to word reg
Compare byte ES: [DI] to byte
segment: [SI]
Compare word ES: [DI] to word
segment: [SI]
Compare byte ES: [DI] to byte DS:
[SI]
Compare word ES: [DI] to word DS:
[SI]
CS segment reg override prefix
Convert word integer to double word
Decimal adjust AL after addition
Decimal adjust AL after subtraction
Subtract 1 from r/m8
Subtract 1 from r/m16
Subtract 1 from word reg
CALL
CBW
CLC
CLD
CLI
CMC
CMP
CMPS
CMPSB
CMPSW
CS
CWD
DAA
DAS
DEC
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
62
/r
-
Clock Cycles
IA186
IA188
O D I
T S Z A P C
33-35
33-35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
0
-
-
-
-
-
-
R
R -
-
-
R R R R R
R -
-
-
R R R R R
R -
-
-
R R R R R
R -
-
-
R R R R R
U
U
-
-
-
R
R
R -
-
-
R R R R R
U -
-
-
U U U U U
-
-
-
-
E8
cw
-
15
19
FF
9A
FF
98
F8
FC
FA
F5
3C
3D
80
81
83
/2
cd
/3
ib
iw
/7
/7
/7
ib
iw
ib
13/19
23
38
2
2
2
2
2
3
4
3/10
3/10
3/10
17/27
31
54
2
2
2
2
2
3
4
3/10
3/14
3/14
38
39
3A
3B
/r
/r
/r
/r
-
3/10
3/10
3/10
3/10
3/10
3/14
3/10
3/14
A6
-
-
22
22
A7
-
-
22
26
A6
-
-
22
22
A7
-
-
22
26
2E
99
27
2F
FE
FF
48+
rw
/1
/1
-
4
4
4
3/15
3/15
3
4
4
4
3/15
3/19
3
-
29/35
29/35
-
-
-
DIV
Divide unsigned numbers
F6
DS
DS segment override prefix
3E
mod
110
r/m
-
Flags Affected
-
R
R
-
R
R
-
- - R R
R R
-
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
-
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
ENTER
ES
ESC
HLT
IDIV
IMUL
Description
Create stack frame for nested
procedure
Create stack frame for non-nested
procedure
Create stack frame for nested
procedure
ES segment reg override prefix
Escape - takes a Trap 7
Escape - takes a Trap 7
Escape - takes a Trap 7
Escape - takes a Trap 7
Escape - takes a Trap 7
Escape - takes a Trap 7
Escape - takes a Trap 7
Escape - takes a Trap 7
Suspend instruction execution
Divide Integers
AL = AX/(r/m8);
AH = remainder
Divide Integers
AX = DX : AX/(r/m16);
DX = remainder
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
iw
C8
ib
iw
C8
00
iw
C8
01
26
D8
/0
D9
/1
DA
/2
DB
/3
DC
/4
DD
/5
DE
/6
DF
/7
F4
F6
/7
-
Clock Cycles
IA186
IA188
22+16
(n-1)
26+20
(n-1)
15
19
25
29
2
44-52
/
50-58
53-61
/
59-67
25-28
/
31-34
2
44-52
/
50-58
53-61
/
63-71
25-28
/
31-34
F7
/7
-
Multiply Integers
AX=(r/m8)*Al
F6
/5
-
Multiply Integers
DX=(r/m16)*AX
F7
/5
-
34-37
/
40-43
34-37
/
44-47
Multiply Integers
(word reg) = (r/m16)*(sign-ext.
byte integer)
6B
/r
ib
-
22-25
22-25
Multiply Integers
(word reg) = (word reg)*(sign-ext.
byte integer)
6B
/r
ib
-
22-25
22-25
Multiply Integers
(word reg) = (r/m16)*(sign-ext.
byte integer)
69
/r
iw
-
29-32
29-32
Multiply Integers
(word reg) = (word reg)*(sign-ext.
byte integer)
69
/r
iw
-
29-32
29-32
Flags Affected
O D I
T S Z A P C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0 0 -
-
-
-
-
-
-
-
-
-
-
-
-
-
U -
-
-
U U U U U
R -
-
-
U U U U R
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
IN
INC
Description
Input byte from imm port to AL
Input word from imm port to AX
Input byte from port in DX to AL
Input word from port in DX to AX
Increment r/m8 by 1
Increment r/m16 by 1
Increment word reg by 1
INS
INSB
INSW
INT 3
INT
INTO
Input byte from port in DX to ES :
[DI]
Input word from port in DX to ES :
[DI]
Input byte from port in DX to ES :
[DI]
Input word from port in DX to ES :
[DI]
Generate interrupt 3 (trap to
debug)
Generate type of interrupt specified
by imm8
Generate interrupt 4 if Overflow
Flag (O) is 1
IRET
Interrupt return
JA
JNBE
JAE
JNB
JNC
JB
JC
Jump short if above (C & Z = 0)
JNAE
JBE
JNA
JCXZ
JE
JZ
Jump short if not below or equal
Jump short if above or equal(C=0)
Jump short if not below (C=0)
Jump short if not carry (C=0)
Jump short if below (C=1)
Jump short if carry (C=1)
Jump short if not above or equal
(C=1)
Jump short if below or equal
(C & Z = 0)
Jump short if not above
(C & Z = 0)
Jump short if CX reg is 0
Jump short if equal (Z=1)
Jump short if 0 (Z=1)
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
E4
ib
E5
ib
EC
ED
FE
/0
FF
/0
40+
rw
Clock Cycles
IA186
IA188
10
10
8
8
3/15
3/15
10
14
8
12
3/15
3/19
3
3
Flags Affected
O D I
T S Z A P C
-
-
-
-
-
-
-
-
-
R -
-
-
R R R R R
-
-
-
-
-
-
-
-
-
-
-
0 0 -
-
-
-
-
6C
6D
-
-
14
14
CC
-
-
45
45
CD
ib
-
47
47
CE
-
-
48, 4
48, 4
CF
-
-
28
28
77
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
73
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
72
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
76
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
E3
cb
-
15,5
15,5
-
-
-
-
-
-
-
-
-
74
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
6C
6D
Restores value of flags reg that
was stored on the stack when
the interrupt was taken
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
Description
JG
Jump short if greater (Z & S = O)
Jump short if not less or equal
(Z & S = O)
Jump short if greater or equal
(S=O)
Jump short if not less (S = O)
Jump short if less or equal
(Z & S = O)
Jump short if not greater
(Z & S = O)
Jump short direct, disp relative to
next instruction
Jump near direct, disp relative to
next instruction
Jump near indirect
Jump far direct to doubleword imm
address
Jump m16: 16 indirect and far
Jump short if not equal (Z=0)
Jump short if not zero (Z=0)
Jump short if not overflow (O=1)
Jump short if not parity (P=0)
Jump short if parity odd (P=0)
Jump short if not sign (S=0)
Jump short if overflow (O=1)
Jump short if parity (P=1)
Jump short if parity (P=1)
Jump short if sign (S=1)
Load AH with low byte of flags reg
Load DS:r16 with segment :offset
from memory
Load offset for m16 word in 16-bit
reg
Destroy procedure stack frame
Load ES:r16 with segment offset
from memory
Asserts lock_n during an
instruction execution
Load byte segment :[SI] in AL
Load word segment :[SI] in AX
JNLE
JGE
JNL
JLE
JNG
JMP
JNE
JNZ
JNO
JNP
JPO
JNS
JO
JP
JPE
JS
LAHF
LDS
LEA
LEAVE
LES
LOCK
LODS
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
Clock Cycles
Flags Affected
IA186
IA188
O D I
T S Z A P C
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
7F
cb
7D
cb
7E
cb
-
13, 4
13, 4
EB
cb
-
14
14
E9
cw
-
14
14
FF
/4
-
11/17
11/21
EA
cd
-
14
14
FF
/5
-
26
34
75
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
71
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
7B
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
79
70
cb
cb
-
13, 4
13, 4
13, 4
13, 4
-
-
-
-
-
-
-
-
-
7A
cb
-
13, 4
13, 4
-
-
-
-
-
-
-
-
-
78
9F
cb
-
-
13, 4
2
13, 4
2
C5
/r
-
18
26
-
-
-
-
-
-
-
-
-
8D
/r
-
6
6
-
-
-
-
-
-
-
-
-
C9
-
-
8
8
-
-
-
-
-
-
-
-
-
C4
/r
-
18
26
-
-
-
-
-
-
-
-
-
F0
-
-
1
1
-
-
-
-
-
-
-
-
-
AC
AD
-
-
12
12
12
16
-
-
-
-
-
-
-
-
-
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
LODSB
LODSW
LOOP
LOOPE
LOOPZ
LOOPNE
LOOPNZ
MOV
Description
Load byte DS: [SI] in AL
Load word DS: [SI] in AX
Decrement count ; jump short if
CX $ 0
Decrement count ; jump short if
CX $ 0 and Z = 1
Decrement count ; jump short if
CX $ 0 and Z = 1
Decrement count ; jump short if
CX $ 0 and Z = 0
Decrement count ; jump short if
CX $ 0 and Z = 0
Copy reg to r/m8
Copy reg to r/m16
Copy r/m8 to reg
Copy r/m16 to reg
Copy segment reg to r/m16
Copy r/m16 to segment reg
Copy byte at segment offset to AL
Copy word at segment offset to AX
Copy AL to byte at segment offset
Copy AX to word at segment offset
Copy imm8 to reg
Copy imm16 to reg
MOVS
MOVSB
MOVSW
Copy imm8 to r/m8
Copy imm16 to r/m16
Copy byte segment [SI] to ES:[DI]
Copy word segment [SI] to ES:[DI]
Copy byte DS:[SI] to ES:[DI]
Copy word DS:[SI] to ES:[DI]
AX = (r/m8) * AL
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
AC
AD
16, 6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R -
-
-
-
-
-
-
R
R -
-
-
R R R R R
12
12
12
16
16, 6
-
E1
cb
-
E0
cb
-
16, 6
16, 6
88
89
8A
/r
/r
/r
-
2/12
2/12
2/9
2/12
2/16
2/9
8B
8C
8E
A0
A1
A2
A3
B0
+rb
B8
+rw
C6
C7
A4
A5
A4
A5
/r
/sr
/sr
-
-
2/9
2/11
2/9
8
8
9
9
2/13
2/15
2/13
8
12
9
13
3
3
3
4
F6
/4
12
12
14
14
14
14
26-28
/
32-34
35-37
/
41-43
12
13
14
18
14
18
26-28
/
32-34
35-37
/
45-47
3/10
3/10
-
DX :: AX = (r/m16) * AX
F7
/4
Perform 2's complement negation
of r/m8
F6
/3
Perform 2's complement negation
of r/m16
F7
Instruction
T S Z A P C
IA188
-
/0
/0
-
/3
-
Opcode - Hex
3/10
Flags Affected
O D I
IA186
E2
MUL
NEG
Clock Cycles
3/14
Clock Cycles
Flags Affected
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Mnemonic
NOP
NOT
As of Production Version -03
OR imm8 with r/m8
80
OR imm16 with r/m16
81
OR imm8 with r/m16
83
OR byte reg with r/m8
OR word reg with r/m16
OR r/m8 with byte reg
OR r/m16 with word reg
Output AL to imm port
Output AX to imm port
Output AL to port in DX
Output AX to port in DX
Output byte DS:[SI] to port in DX
Output word DS:[SI] to port in DX
Output byte DS:[SI] to port in DX
Output word DS:[SI] to port in DX
Pop top word of stack into memory
word
Pop top word of stack into word
reg
Pop top word of stack into DS
Pop top word of stack into ES
Pop top word of stack into SS
Pop DI, SI, BP, BX, DX, CX, & AX
Pop top word of stack into
Processor Status Flags reg
Push memory word onto stack
08
09
0A
0B
E6
E7
EE
EF
6E
6F
6E
6F
byte
2
/2
/2
ib
iw
/1
ib
/1
iw
/1
ib
/r
/r
/r
/r
ib
ib
-
8F
/0
-
20
24
10
14
Description
Perform no operation
Complement each bit in r/m8
Complement each bit in r/m16
OR imm8 with AL
OR imm16 with AX
byte
1
90
F6
F7
0C
0D
OR
OUT
OUTS
OUTSB
OUTSW
POP
POPA
POPF
Push reg word onto stack
PUSH
Push sign-extended imm8 onto
stack
Push imm16 onto stack
Push CS onto stack
Push SS onto stack
Push DS onto stack
Push ES onto stack
byte
3-6
-
IA186
IA188
O D I
T S Z A P C
3
3/10
3/10
3
4
3
3/10
3/14
3
4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4/16
4/16
-
4/16
4/20
0 -
-
-
R R U R
0
-
4/16
4/20
-
3/10
3/10
3/10
3/10
9
9
7
7
3/10
3/14
3/10
3/14
9
13
7
11
-
-
-
-
-
-
-
-
-
14
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
58+
rw
1F
07
17
61
-
-
-
-
8
12
51
83
9D
-
-
8
12
FF
50+
rw
/6
-
16
20
-
-
10
14
6A
-
-
10
14
68
0E
16
1E
06
-
-
10
9
9
9
9
14
13
13
13
13
Values in word at top of stack
are copied into FLAGS reg bits
-
-
-
-
-
-
-
-
-
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
PUSHA
PUSHF
RCL
RCR
REP
INS
REP
LODS
REP
MOVS
REP
OUTS
Description
Push AX, CX, DX, BX, original SP,
BP, SI, and DI
Push Processor Status Flags reg
Rotate 9 bits of C and r/m8 left
once
Rotate 9 bits of C and r/m8 left CL
times
Rotate 9 bits of C and r/m8 left
imm8 times
Rotate 17 bits of C and r/m16 left
once
Rotate 17 bits of C and r/m16 left
CL times
Rotate 17 bits of C and r/m16 left
imm8 times
Rotate 9 bits of C and r/m8 right
once
Rotate 9 bits of C and r/m8 right
CL times
Rotate 9 bits of C and r/m8 right
imm8 times
Rotate 17 bits of C and r/m16
right once
Rotate 17 bits of C and r/m16
right CL times
Rotate 17 bits of C and r/m16
right imm8 times
Input CX bytes from port in DX to
ES : [DI]
Input CX bytes from port in DX to
ES : [DI]
Load CX bytes from segment :[SI]
in AL
Load CX words from segment :[SI]
in AX
Copy CX bytes from segments :
[SI] to ES:[DI]
Copy CX words from segments :
[SI] to ES:[DI]
Output CX bytes from DS:[SI] to
port in DX
Output CX bytes from DS:[SI] to
port in DX
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
Clock Cycles
IA186
IA188
Flags Affected
O D I
T S Z A P C
60
-
-
36
68
-
-
-
-
-
-
-
-
-
9C
-
-
9
13
-
-
-
-
-
-
-
-
-
D0
/2
-
2/15
2/15
5+n/
17+n
5+n/
17+n
5+n/
17+n
5+n/
17+n
-
-
-
-
-
-
-
-
-
2/15
2/15
5+n/
17+n
5+n/
17+n
5+n/
17+n
5+n/
17+n
2/15
2/15
5+n/
17+n
5+n/
17+n
5+n/
17+n
5+n/
17+n
-
-
-
-
-
-
-
-
-
2/15
2/15
5+n/
17+n
5+n/
17+n
5+n/
17+n
5+n/
17+n
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
D2
/2
-
D1
/2
ib
/2
D3
/2
-
C1
/2
ib
-
D0
/3
-
C0
D2
/3
-
-
/3
ib
-
D1
/3
-
D3
/3
-
75
/3
ib
-
F3
6C
-
8+8n
8+8n
F3
6D
-
8+8n
12+8n
AC
-
6+11n
6+11n
AD
-
6+11n
10+
11n
A4
-
8+8n
8+8n
C0
F3
F3
F3
F3
A5
-
8+8n
12+8n
F3
6E
-
8+8n
8+8n
F3
6F
-
8+8n
12+8n
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
Description
REP
STOS
Fill CX bytes at ES:[DI] with AL
Fill CX words at ES:[DI] with AL
Find non-matching bytes in ES:[DI]
and segment :[SI]
Find non-matching words in
ES:[DI] and segment :[SI]
Find non-AL byte starting at
ES:[DI]
Find non-AX word starting at
ES:[DI]
Find non-matching bytes in ES:DI
and segment :[SI]
Find non-matching words in ES:DI
and segment :[SI]
Find non-AL byte starting at ES:DI
Find non-AX word starting at ES:DI
Find matching bytes in ES:[DI] and
segment :[SI]
Find matching words in ES:[DI]
and segment :[SI]
Find AL byte starting at ES:[DI]
Find AX word starting at ES:[DI]
Find matching bytes in ES:DI and
segment :[SI]
Find matching words in ES:DI and
segment :[SI]
Find AL byte starting at ES:DI
Find AX word starting at ES:DI
Return near to calling procedure
REPE
CMPS
REPE
SCAS
REPZ
CMPS
REPZ
SCAS
REPNE
CMPS
REPNZ
CMPS
REPNE
SCAS
REPNZ
SCAS
RET
ROL
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
F3
AA
F3
AB
-
IA188
O D I
T S Z A P C
8+8n
8+8n
8+8n
12+8n
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
U -
-
-
-
-
-
-
R
A6
-
5+22n
5+22n
F3
A7
-
5+22n
9+22n
F3
AE
-
5+15n
5+15n
F3
AF
-
5+15n
9+15n
F3
A6
-
5+22n
5+22n
F3
A7
-
5+22n
9+22n
F3
F3
AE
AF
-
5+15n
5+15n
5+15n
9+15n
F2
A6
-
5+22n
5+22n
F2
A7
-
5+22n
9+22n
F2
F2
A6
A7
-
5+22n
5+22n
5+22n
9+22n
F2
AE
-
5+15n
5+15n
F2
AF
-
5+15n
9+15n
F2
F2
C3
AE
AF
-
5+15n
5+15n
16
5+15n
9+15n
20
data
low
data
high
22
30
18
22
25
33
2/15
5+n/
17+n
5+n/
17+n
2/15
2/15
5+n/
17+n
5+n/
17+n
2/15
CB
Return near; pop imm16
parameters
C2
Return far; pop imm16 parameters
CA
Rotate 8 bits of r/m8 left once
Rotate 8 bits or r/m8 left CL times
D0
data
low
/0
data
high
-
D2
/0
-
/0
ib
/0
data
8
-
C0
D1
Flags Affected
IA186
F3
Return far to calling procedure
Rotate 8 bits or r/m8 left imm8
times
Rotate 16 bits of r/m8 left once
Clock Cycles
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
ROL
ROR
SAHF
Description
Rotate 16 bits or r/m8 left CL
times
Rotate 16 bits or r/m8 left imm8
times
Rotate 8 bits of r/m8 right once
Rotate 8 bits or r/m8 right CL
times
Rotate 8 bits or r/m8 right imm8
times
Rotate 16 bits of r/m8 right once
Rotate 16 bits or r/m8 right CL
times
Rotate 16 bits or r/m8 right imm8
times
Show AH in low byte of the Status
Flags reg
Multiply r/m8 by 2, once
Multiply r/m8 by 2, CL times
Multiply r/m8 by 2, imm8 times
Opcode - Hex
byte byte byte
1
2
3-6
IA188
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
D0
/0
ib
/1
data
8
-
D2
/1
-
D1
/1
ib
/1
data
8
-
D3
/1
-
C1
/1
ib
data
8
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
9E
-
-
3
3
D0
/4
-
D2
/4
data
8
-
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
2/15
5+n/
17+n
5+n/
17+n
C1
C0
D1
Multiply r/m16 by 2, CL times
D3
/4
data
8
-
C0
Multiply r/m8 by 2, once
D0
/4
ib
/4
Multiply r/m8 by 2, CL times
D2
/4
data
8
-
C1
Multiply r/m16 by 2, once
D1
/4
ib
/4
Multiply r/m16 by 2, CL times
D3
/4
-
C1
/4
ib
data
8
Multiply r/m16 by 2, imm8 times
IA186
-
Multiply r/m16 by 2, once
Multiply r/m8 by 2, imm8 times
Clock Cycles
/0
D3
/4
ib
/4
Multiply r/m16 by 2, imm8 times
SAL/SHL
As of Production Version -03
C0
Flags Affected
O D I
T S Z A P C
U -
-
-
-
-
-
-
R
U -
-
-
-
-
-
-
R
-
-
-
-
R R R R R
U -
-
-
-
R R R R
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
SAR
SBB
SCAS
SCASB
SCASW
Description
Perform a signed division of r/m8
by 2, once
Perform a signed division of r/m8
by 2, CL times
Perform a signed division of r/m8
by 2, imm8 times
Perform a signed division of
r/m16 by 2, once
Perform a signed division of
r/m16 by 2, Cl times
Perform a signed division of
r/m16 by 2, imm8 times
Subtract imm8 from Al with
borrow
Subtract imm16 from AX with
borrow
Subtract imm8 from r/m8 with
borrow
Subtract imm16 from r/m16 with
borrow
Subtract sign-extended imm8 from
r/m16 with borrow
Subtract byte reg from r/m8 with
borrow
Subtract word reg from r/m16
with borrow
Subtract r/m8 from r/m8 with
borrow
Subtract r/m8 reg from byte with
borrow
Compare byte AL to ES:[DI];
update DI
Compare word AL to ES:[DI];
update DI
Compare byte AL to ES:[DI];
update DI
Compare word AL to ES:[DI];
update DI
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
Clock Cycles
IA186
IA188
2/15
2/15
5+n/
17+n
5+n/
17+n
D0
/7
-
D2
/7
-
C0
/7
ib
data
8
5+n/
17+n
5+n/
17+n
D1
/7
-
2/15
2/15
D3
/7
-
C1
/7
ib
data
8
5+n/
17+n
5+n/
17+n
5+n/
17+n
5+n/
17+n
1C
ib
-
3
3
1D
iw
data
8
4
4
-
4/16
4/16
-
4/16
4/20
-
4/16
4/20
80
81
83
/3
ib
/3
iw
/3
ib
18
/r
data
8
3/10
3/10
19
/r
-
3/10
3/14
1A
/r
-
3/10
3/10
1B
/r
data
8
3/10
3/14
AE
-
-
15
19
AF
-
-
15
19
AE
-
-
15
19
AF
-
-
15
19
Flags Affected
O D I
T S Z A P C
U -
-
-
R R U R R
R -
-
-
R R R R R
R -
-
-
R R R R R
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
SHR
SS
STC
STD
STI
STOS
STOSB
STOSW
SUB
Description
Divide unsigned of r/m8 by 2,
once
Divide unsigned of r/m8 by 2, CL
times
Divide unsigned of r/m8 by 2,
imm8 times
Divide unsigned of r/m16 by 2,
once
Divide unsigned of r/m16 by 2, CL
times
Divide unsigned of r/m16 by 2,
imm8 times
SS segment reg override prefix
Set the Carry Flag to 1
Set the Direction Flag so the
source Index (SI) and/or the
Destination Index (DI) regs will
decrement during string
instructions
Enable maskable interrupts after
the next instruction
Store AL in byte ES:[DI]; update DI
Store AX in word ES:[DI]; update
DI
Store AL in byte ES:[DI]; update DI
Store AX in word ES:[DI]; update
DI
Subtract imm8 from AL
Subtract imm16 from AX
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
IA186
IA188
2/15
2/15
5+n/
17+n
5+n/
17+n
Flags Affected
O D I
T S Z A P C
U -
-
-
R R U R
0
D0
/7
-
D2
/7
-
C0
/7
ib
data
8
5+n/
17+n
5+n/
17+n
D1
/7
-
2/15
2/15
D3
/7
-
36
F9
/7
ib
-
data
8
-
5+n/
17+n
5+n/
17+n
2
5+n/
17+n
5+n/
17+n
2
-
-
-
-
-
-
-
-
1
FD
-
-
2
2
-
1 -
-
-
-
-
-
-
FB
-
-
2
2
-
-
1 -
-
-
-
-
-
AA
-
-
10
10
AB
-
-
10
14
AA
-
-
10
10
-
-
-
-
-
-
-
-
-
AB
-
-
10
14
2C
2D
ib
iw
/5
ib
/5
iw
/5
ib
/r
/r
/r
/r
-
3
4
3
4
-
4/16
4/16
-
4/16
4/20
R -
-
-
R R R R R
-
4/16
4/20
-
3/10
3/10
3/10
3/10
3/10
3/14
3/10
3/14
C1
Subtract imm8 from r/m8
80
Subtract imm16 from r/m16
81
Subtract sign-extended imm8 from
r/m16
Subtract byte reg from r/m8
Subtract word reg from r/m16
Subtract r/m8 from byte reg
Subtract r/m16 from word reg
Clock Cycles
83
28
29
2A
2B
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Instruction
Mnemonic
Description
AND imm8 with AL
AND imm16 with AX
AND imm8 with r/m8
TEST
AND imm16 with r/m16
AND byte reg with r/m8
AND word reg with r/m16
WAIT
XCHG
XLAT
XLATB
XOR
Performs a NOP
Exchange word reg with AX
Exchange AX with word reg
Exchange byte reg with r/byte
Exchange r/m8 with byte reg
Exchange word reg with r/m16
Exchange r/m16 with word reg
Set AL to memory byte segment
:[BX+unsigned AL]
Set AL to memory byte DS
:[BX+unsigned AL]
XOR imm8 with AL
XOR imm16 with AX
As of Production Version -03
Opcode - Hex
byte byte byte
1
2
3-6
A8
ib
A9
iw
/0 data
F6
8
ib
/0
F7
iw
84
/r
data
85
/r
8
9B
90
+rw
86
/r
87
/r
-
IA186
IA188
3
4
3
4
4/10
4/10
4/10
4/14
3/10
3/10
3/10
3/14
3
3
4/17
4/17
4/17
4/17
3
3
4/17
4/17
4/21
4/21
D7
-
-
11
15
D7
-
-
11
15
34
35
ib
iw
/6
ib
/6
iw
/6
ib
/r
/r
/r
/r
-
3
4
3
4
-
4/16
4/16
-
4/16
4/20
-
4/16
4/20
-
3/10
3/10
3/10
3/10
3/10
3/14
3/10
3/14
XOR imm8 with r/m8
80
XOR imm16 with r/m16
81
XOR sign-extended imm8 with
r/m16
XOR byte reg with r/m8
XOR word reg with r/m16
XOR r/m8 with byte reg
XOR r/m16 with word reg
Clock Cycles
83
30
31
32
33
Flags Affected
O D I
T S Z A P C
0 -
-
-
R R U R
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0 -
-
-
R R U R
0
Key to Abbreviations Used Instruction Summary Table
The Operand Address byte is configured as follows.
7
6
5
4
mod field
aux field
3
2
1
r/m field
0
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
mod field (Modifier Field)
mod
11
00
01
10
Description
r/m is treated as a register field
DISP = 0, disp-low and disp-high are absent - address displacement is 0.
DISP = disp-low sign-extended to 16-bits, disp-high is absent.
DISP = disp-high: disp-low.
aux field (Auxiliary Field)
aux
000
001
010
011
100
101
110
111
If mod = 11 and word = 0
AL
CL
DL
BL
AH
CH
DH
BH
If mod = 11 and word = 1
AX
CX
DX
BX
SP
BP
SI
DI
When mod $ 11, depends on instruction
r/m field
r/m
000
001
010
011
100
101
110
111
Description
EA = (BX) + (SI) + DISP [where EA is the Effective Address]
EA = (BX) + (DI) + DISP
EA = (BP) + (SI) + DISP
EA = (BX) + (DI) + DISP
EA = (SI) + DISP
EA = (DI) + DISP
EA = (BP) + DISP [except if mod = 00, then EA = disp-high: disp-low]
EA = (BX) + DISP
Displacement
The displacement is an 8 or 16 bit value added to the offset portion of the address.
Immediate
The immediate bytes consist of up to 16 bits of immediate data.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Segment Override Prefix
The Operand Address byte is configured as follows.
7
6
5
4
0
0
1
SR
SR
00
01
10
11
3
SR
2
1
1
1
0
0
Segment Register
ES
CS
SS
DS
Notation
Parameter
:
::
Indication
The component of the left is the segment for a component located in
memory. The component on the right is the offset.
The component of the left is concatenated with the component on the right.
Operand
imm8
imm16
m
m8
m16
r/m8
r/m16
Translation
Immediate byte: signed number between –128 and 127
Immediate word: signed number between –32768 and 32767
Operand in memory
Byte string in memory pointed to by DS:SI or ES:DI
Word string in memory pointed to by DS:SI or ES:DI
General byte register or a byte in memory
General word register or a word in memory
Opcode
Parameter
/0 - /7
/r
The Auxiliary Field in the Operand Address byte specifies an extension (from 000 to 111,
i.e. 0 to 7) to the opcode instead of a register. Thus the opcode for adding (AND) an
immediate byte to a general byte register or a byte in memory is ‘80 /4 ib’. This indicates
that the second byte of the opcode is ‘mod 100 r/m’.
The Auxiliary Field in the Operand Address byte specifies a register rather that an opcode
extension. The opcode byte specifies which register, either byte size or word size, is
assigned as in the aux code above.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
/sr
This byte is placed before the instruction as shown above under Segment Override Prefix.
cb
The byte following the Opcode byte specifies the offset.
cd
The double-word following the Opcode byte specifies the offset and is some cases a
segment.
ib
Immediate byte – signed or unsigned determined by the Opcode byte.
iw
Immediate word – signed or unsigned determined by the Opcode byte.
rw
Word register operand as determined by the Opcode byte, aux field.
Flags Affected After Instruction
U
R
Undefined
Unchanged
Result dependent
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Absolute Maximum Ratings
Storage Temperature
Voltage on any pin with respect to ground
Operating Range
Industrial (TA)
TA = ambient temperature
-65%C to +125%C
-0.5 V to VCC +0.5 V
-40%C to +85%C
DC Characteristics Over Commercial Operating Ranges
Symbol
Parameter Description
VIL
VIL1
VIH
VIH1
VIH1
VOL
Input Low Voltage (Except X1)
Clock Input Low Voltage (X1)
Input High Voltage (Except res_n and X1)
Input High Voltage (res_n)
Clock Input High Voltage (X1)
Output Low Voltages(1)
VOH
ICC
ILI
ILO
VCLO
VCHO
Test Conditions
IOL = 2.5 mA (s2_n -s0_n)
IOL = 2.0 mA (other)
Preliminary
Min
Max
-0.5
0.8
-0.5
0.8
2.0
VCC + 0.5
2.4
VCC + 0.5
VCC - 0.8
VCC + 0.5
0.45
0.45
Output High Voltages
IOH = -2.4 mA @ 2.4 V
IOH = -200 &A @ VCC 0.5
2.4
VCC - 0.5
Power Supply Current @ 0%C
Input Leakage Current @ 0.5 MHz
Output Leakage Current @ 0.5 MHz
Clock Output Low
Clock Output High
VCC = 5.5 V(2)
0.45 V ' VIN ' VCC
0.45 V ' VOUT ' VCC(3)
ICLO = 4.0 mA
ICHO = -500 &A
VCC - 0.5
Unit
V
V
V
V
V
V
V
VCC + 0.5
VCC
V
V
5.9
(10
(10
0.45
mA/MHz
&A
&A
V
V
NOTES
1. The lcs_n/once0_n, mcs3_n – mcs0_n, ucs_n/once1_n, and rd_n pins have weak internal pull-up
resistors. Loading the lcs_n/once0_n and ucs_n/once1_n pins in excess of IOH = -200 &A during
reset can cause the device to go into ONCE mode.
2. Current is measured with the device in reset with the x1 and x2 driven and all other non-power
pins open but held High or Low.
3. Testing is performed with the pins floating, either during hold or by invoking the ONCE mode.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
AC Characteristics Over Commercial Operating Ranges (40 MHz)
No. Name
Description
MIN
MAX
General Timing Requirements
1 tDVCL
Data in Setup
10
2 tCLDX
Data in Hold
0
General Timing Responses
3 tCHSV
Status Active Delay
0
6
4 tCLSH
Status Inactive Delay
0
6
5 tCLAV
ad Address Valid Delay
0
12
6 tCLAX
Address Hold
0
12
8 tCHDX
Status Hold Time
0
9 tCHLH
ale Active Delay
0
8
10 tLHLL
ale Width
tCLCH-5
11 tCHLL
ale Inactive Delay
0
8
12 tAVLL
ad Address Valid to ale Low
tCLCH
13 tLLAX
ad Address Hold from ale Inactive
tCHCL
14 tAVCH
ad Address Valid to Clock High
0
15 tCLAZ
ad Address Float Delay
0
12
16 tCLCSV
mcs_n/pcs_n Inactive Delay
0
12
17 tCXCSX
mcs_n/pcs_n Hold from Command Inactive tCLCH
18 tCHCSX
mcs_n/pcs_n Inactive Delay
0
12
19 tDXDL
den_n Inactive to dt_r_n Low
0
20 tCVCTV
Control Active Delay 1
0
10
21 tCVDEX
den_n Inactive Delay
0
0
22 tCHCTV
Control Active Delay 2
0
10
23 tLHAV
ale High to Address Valid
7.5
80 tCLCLX
lcs_n Inactive Delay
0
9
81 tCLCSL
lcs_n Active Delay
0
9
82 tCLRF
clkoutA High to rfsh_n Invalid
0
12
tCLCL +
84 tLRLL
lcs_n Precharge Pulse Width
tCLCH
Read Cycle Timing Responses
24 tAZRL
ad Address Float to rd_n Active
0
25 tCLRL
rd_n Active Delay
0
10
26 tRLRH
rd_n Pulse Width
tCLCL
27 tCLRH
rd_n Inactive Delay
0
10
28 tRHLH
rd_n Inactive to ale High
tCLCH
29 tRHAV
rd_n Inactive to ad Address Active
tCLCL
30 tCLDOX
Data Hold Time
0
Write Cycle Timing Responses
31 tCVCTX
Control Inactive Delay
0
10
32 tWLWH
wr_n Pulse Width
2tCLCL
33 tWHLH
wr_n Inactive to ale High
tCLCH
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
No.
34
35
41
59
65
66
67
68
87
Name
tWHDX
tWHDEX
tDSHLH
tRHDX
tAVWL
tAVRL
tCHCSV
tCHAV
tAVBL
As of Production Version -03
Description
Data Hold after wr_n
wr_n Inactive to den_n Inactive
ds_n Inactive to ale Inactive
rd_n High to Data Hold on ad Bus
a Address Valid to wr_n Low
a Address Valid to rd_n Low
clkoutA High to lcs_n/usc_n Valid
clkoutA High to a Address Valid
a Address Valid to whb_n/wlb_n Low
Refresh Timing Cycle Parameters
79 tCHRFD
clkoutA High to rfsh_n Valid
82 tCLRF
clkoutA High to rfsh_n Invalid
85 tRFCY
rfsh_n Cycle Time
86 tLCRF
lcs_n Inactive to rfsh_n Active Delay
clkin Timing
36 tCKIN
X1 Period
37 tCLCK
X1 Low Time
38 tCHCK
X1 High Time
39 tCKHL
X1 Fall Time
40 tCKLH
X1 Rise time
clkout Timing
42 tCLCL
clkoutA Period
43 tCLCH
clkoutA Low Time
44 tCHCL
clkoutA High Time
45 tCH1CH2
clkoutA Rise Time
46 tCL2CL1
clkoutA Fall Time
61 tLOCK
Maximum PLL Lock Time
69 tCICOA
X1 to clkoutA Skew
70 tCICOB
X1 to clkoutB Skew
Ready & Peripheral Timing Requirements
47 tSRYCL
srdy Transition Setup Time
48 tCLSRY
srdy Transistion Hold Time
49 tARYCH
ardy Resolution Transition Setup Time
50 tCLARX
ardy Active Hold Time
51 tARYCHL
ardy Inactive Holding Time
52 tARYLCL
ardy Setup Time
53 tINVCH
Peripheral Setup Time
54 tINVCL
drq Setup Time
MIN
MAX
tCLCL
tCLCH
tCLCH
0
tCLCL +
tCHCL
tCLCL +
tCHCL
0
9
0
8
tCHCL tCHCL
1.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
6tCLCL
2tCLCL
12
12
ns
ns
ns
ns
25
7.5
7.5
66
5
5
ns
ns
ns
ns
ns
3
3
0.5
25
35
ns
ns
ns
ns
ns
ms
ns
ns
25
TCLCL/2
TCLCL/2
10
3
9
4
6
9
10
10
ns
ns
ns
ns
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
No. Name
Description
Peripheral Timing Responses
55 tCLTMV
Timer Output Delay
Reset & Hold Timing Requirements
57 tRESIN
res_n Setup Time
58 tHVCL
hld Setup Time
Reset & Hold Timing Responses
62 tCLHAV
hlda Valid Delay
63 tCHCZ
Command Lines Float Delay
64 tCHCV
Command Lines Valid Delay (after Float)
Synchronous Serial Port Timing Requirements
75 tDVSH
Data Valid to sclk High
77 tSHDX
sclk High to SPI Data Hold
Synchronous Serial Port Timing Responses
71 tCLEV
clkouta Low to sden Valid
72 tCLSL
clkouta Low to sclk High
78 tSLDV
sclk Low to Data Valid
MIN
MAX
Units
0
12
ns
10
ns
10
ns
0
0
0
7
12
12
10
3
0
0
0
ns
ns
ns
ns
ns
12
12
12
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Waveforms
Alphabetic Key to Waveform Parameters
No. Name
49
51
52
87
14
12
66
65
24
45
68
38
44
67
18
22
64
63
8
9
11
79
3
69
70
39
36
40
46
50
5
6
15
43
37
42
80
81
16
30
7
tARYCH
tARYCHL
tARYLCL
tAVBL
tAVCH
tAVLL
tAVRL
tAVWL
tAZRL
tCH1CH2
tCHAV
tCHCK
tCHCL
tCHCSV
tCHCSX
tCHCTV
tCHCV
tCHCZ
tCHDX
tCHLH
tCHLL
tCHRFD
tCHSV
tCICOA
tCICOB
tCKHL
tCKIN
tCKLH
tCL2CL1
tCLARX
tCLAV
tCLAX
tCLAZ
tCLCH
tCLCK
tCLCL
tCLCLX
tCLCSL
tCLCSV
tCLDOX
tCLDV
Description
ardy Resolution Transition Setup Time
ardy Inactive Holding Time
ardy Setup Time
a Address Valid to whb_n/wlb_n Low
ad Address Valid to Clock High
ad Address Valid to ale Low
a Address Valid to rd_n Low
a Address Valid to wr_n Low
ad Address Float to rd_n Active
clkoutA Rise Time
clkoutA High to A Address Valid
X1 High Time
clkoutA High Time
clkoutA High to lcs_n/usc_n Valid
mcs_n/pcs_n Inactive Delay
Control Active Delay 2
Command Lines Valid Delay (after Float)
Command Lines Float Delay
Status Hold Time
ale Active Delay
ale Inactive Delay
clkoutA High to rfsh_n Valid
Status Active Delay
X1 to clkoutA Skew
X1 to clkoutB Skew
X1 Fall Time
X1 Period
X1 Rise time
clkoutA Fall Time
ardy Active Hold Time
ad Address Valid Delay
Address Hold
ad Address Float Delay
clkoutA Low Time
X1 Low Time
clkoutA Period
lcs_n Inactive Delay
lcs_n Active Delay
mcs_n/pcs_n Inactive Delay
Data Hold Time
Data Valid Delay
No. Name Description
2
71
62
82
27
25
4
72
48
55
83
20
31
21
17
1
75
19
58
53
54
86
23
10
13
61
84
57
85
29
59
28
26
77
78
47
35
34
33
32
tCLDX
tCLEV
tCLHAV
tCLRF
tCLRH
tCLRL
tCLSH
tCLSL
tCLSRY
tCLTMV
tCOAOB
tCVCTV
tCVCTX
tCVDEX
tCXCSX
tDVCL
tDVSH
tDXDL
tHVCL
tINVCH
tINVCL
tLCRF
tLHAV
tLHLL
tLLAX
tLOCK
tLRLL
tRESIN
tRFCY
tRHAV
tRHDX
tRHLH
tRLRH
tSHDX
tSLDV
tSRYCL
tWHDEX
tWHDX
tWHLH
tWLWH
Data in Hold
clkoutA Low to sden Valid
hlda Valid Delay
clkoutA High to rfsh_n Invalid
rd_n Inactive Delay
rd_n Active Delay
Status Inactive Delay
clkoutA Low to sclk Low
srdy Transistion Hold Time
Timer Output Delay
clkoutA to clkoutB Skew
Control Active Delay 1
Control Inactive Delay
den_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
Data in Setup
Data Valid to SCLK High
den_n Inactive to dt_r_n Low
hld Setup Time
Peripheral Setup Time
drq Setup Time
lcs_n Inactive to rfsh_n Active Delay
ale High to Address Valid
ale Width
ad Address Hold from ALE Inactive
Maximum PLL Lock Time
lcs_n Precharge Pulse Width
res_n Setup Time
rfsh_n Cycle Time
rd_n Inactive to ad Address Active
rd_n High to Data Hold on ad Bus
rd_n Inactive to ale High
rd_n Pulse Width
sclk High to SPI Data Hold
sclk Low SPI Data Hold
srdy Transition Setup Time
wr_n Inactive to den_n Inactive
Data Hold after wr_n
wr_n Inactive to ale High
wr_n Pulse Width
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Numeric Key to Waveform Parameters
No. Name
1 tDVCL
2 tCLDX
3 tCHSV
4 tCLSH
5 tCLAV
6 tCLAX
7 tCLDV
8 tCHDX
9 tCHLH
10 tLHLL
11 tCHLL
12 tAVLL
13 tLLAX
14 tAVCH
15 tCLAZ
16 tCLCSV
17 tCXCSX
18 tCHCSX
19 tDXDL
20 tCVCTV
21 tCVDEX
22 tCHCTV
23 tLHAV
24 tAZRL
25 tCLRL
26 tRLRH
27 tCLRH
28 tRHLH
29 tRHAV
30 tCLDOX
31 tCVCTX
32 tWLWH
33 tWHLH
34 tWHDX
35 tWHDEX
36 tCKIN
37 tCLCK
38 tCHCK
39 tCKHL
40 tCKLH
42 tCLCL
Description
No. Name
Data in Setup
43 tCLCH
Data in Hold
44 tCHCL
Status Active Delay
45 tCH1CH2
Status Inactive Delay
46 tCL2CL1
ad Address Valid Delay
47 tSRYCL
Address Hold
48 tCLSRY
Data Valid Delay
49 tARYCH
Status Hold Time
50 tCLARX
ale Active Delay
51 tARYCHL
ale Width
52 tARYLCL
ale Inactive Delay
53 tINVCH
ad Address Valid to ALE Low
54 tINVCL
ad Address Hold from ALE Inactive
55 tCLTMV
ad Address Valid to Clock High
57 tRESIN
ad Address Float Delay
58 tHVCL
mcs_n/pcs_n Inactive Delay
59 tRHDX
mcs_n/pcs_n Hold from Command Inactive 61 tLOCK
mcs_n/pcs_n Inactive Delay
62 tCLHAV
den_n Inactive to dt_r_n Low
63 tCHCZ
Control Active Delay 1
64 tCHCV
den_n Inactive Delay
65 tAVWL
Control Active Delay 2
66 tAVRL
ale High to Address Valid
67 tCHCSV
ad Address Float to rd_n Active
68 tCHAV
rd_n Active Delay
69 tCICOA
rd_n Pulse Width
70 tCICOB
rd_n Inactive Delay
71 tCLEV
rd_n Inactive to ale High
72 tCLSL
rd_n Inactive to ad Address Active
75 tDVSH
Data Hold Time
77 tSHDX
Control Inactive Delay
78 tSLDV
wr_n Pulse Width
79 tCHRFD
wr_n Inactive to ale High
80 tCLCLX
Data Hold after wr_n
81 tCLCSL
wr_n Inactive to den_n Inactive
82 tCLRF
X1 Period
83 tCOAOB
X1 Low Time
84 tLRLL
85 tRFCY
X1 High Time
86 tLCRF
X1 Fall Time
X1 Rise time
87 tAVBL
clkoutA Period
Description
clkoutA Low Time
clkoutA High Time
clkoutA Rise Time
clkoutA Fall Time
srdy Transition Setup Time
srdy Transistion Hold Time
ardy Resolution Transition Setup Time
ardy Active Hold Time
ardy Inactive Holding Time
ardy Setup Time
Peripheral Setup Time
drq Setup Time
Timer Output Delay
res_n Setup Time
hld Setup Time
rd_n High to Data Hold on ad Bus
Maximum PLL Lock Time
hlda Valid Delay
Command Lines Float Delay
Command Lines Valid Delay (after Float)
a Address Valid to wr_n Low
a Address Valid to rd_n Low
clkoutA High to lcs_n/usc_n Valid
clkoutA High to A Address Valid
X1 to clkoutA Skew
X1 to clkoutB Skew
clkouta Low to sden Valid
clkouta Low to sclk High
Data Valid to sclk High
sclk High to SPI Data Hold
sclk Low to Data Valid
clkoutA High to rfsh_n Valid
lcs_n Inactive Delay
lcs_n Active Delay
clkoutA High to rfsh_n Invalid
clkoutA to clkoutB Skew
lcs_n Precharge Pulse Width
rfsh_n Cycle Time
lcs_n Inactive to rfsh_n Active Delay
a Address Valid to whb_n/wlb_n Low
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Read Cycle
0ns
20ns
40ns
60ns
t1
80ns
100ns
t2
120ns
t3
140ns
160ns
t4
clkoutA
66
a19-0
address
68
s6_lock_n
8
s6
lock_n
s6
5
14
ad15-ad0/ad7-ad0
6
1
address
Data
23
15
2
ao15-ao8
Address
12
9
59
11
29
ale
10
26
24
28
rd_n
25
27
bhe_n
bhe_n
67
13
18
lcs_n/ucs_n
16
99
17
mcs_n/pcs_n
20
21
den_n
19
41
22
22
dt_r_n
3
4
s2_n-s0_n
uzi_n
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Read Cycle Timing
No. Name
Description
General Timing Requirements
1 tDVCL
Data in Setup
2 tCLDX
Data in Hold
General Timing Responses
3 tCHSV
Status Active Delay
4 tCLSH
Status Inactive Delay
5 tCLAV
ad Address Valid Delay
6 tCLAX
Address Hold
8 tCHDX
Status Hold Time
9 tCHLH
ale Active Delay
MIN
MAX
10
0
0
0
0
0
0
0
tCLCH10 tLHLL
ale Width
5
11 tCHLL
ale Inactive Delay
0
12 tAVLL
ad Address Valid to ale Low
tCLCH
13 tLLAX
ad Address Hold from ale Inactive
tCHCL
14 tAVCH
ad Address Valid to Clock High
0
15 tCLAZ
ad Address Float Delay
0
16 tCLCSV
mcs_n/pcs_n Inactive Delay
0
17 tCXCSX
mcs_n/pcs_n Hold from Command Inactive tCLCH
18 tCHCSX
mcs_n/pcs_n Inactive Delay
0
19 tDXDL
den_n Inactive to dt_r_n Low
0
20 tCVCTV
Control Active Delay 1
0
21 tCVDEX
den_n Inactive Delay
0
22 tCHCTV
Control Active Delay 2
0
23 tLHAV
ale High to Address Valid
7.5
Read Cycle Timing Responses
24 tAZRL
ad Address Float to rd_n Active
0
25 tCLRL
rd_n Active Delay
0
26 tRLRH
rd_n Pulse Width
tCLCL
27 tCLRH
rd_n Inactive Delay
0
28 tRHLH
rd_n Inactive to ale High
tCLCH
29 tRHAV
rd_n Inactive to ad Address Active
tCLCL
tCLCL
+
66 tAVRL
a Address Valid to rd_n Low
tCHCL
67 tCHCSV
clkoutA High to lcs_n/usc_n Valid
0
68 tCHAV
clkoutA High to a Address Valid
0
Units
ns
ns
6
6
12
12
8
8
12
12
12
10
9
10
10
10
9
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Write Cycle
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
clkoutA
65
a19-0
address
68
s6_lock_n
8
s6
lock_n
s6
14
7
ad15-ad0/ad7-ad0
30
address
12
data
6
ao15-ao8
9
11
23
13
34
ale
31
10
33
wr_n
20
32
87
20
31
whb_n/wlb_n/wb_n
5
bhe_n
18
bhe_n
67
lcs_n/ucs_n
16
17
mcs_n/pcs_n
35
21
31
den_n
22
19
dt_r_n
3
4
s2-s0
uzi_n
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Write Cycle Timing
No. Name
Description
General Timing Requirements
1
tDVCL
Data in Setup
2
tCLDX
Data in Hold
General Timing Responses
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
5
tCLAV
ad Address Valid Delay
6
tCLAX
Address Hold
7
tCLDV
Data Valid Delay
8
tCHDX
Status Hold Time
9
tCHLH
ale Active Delay
MIN
MAX
10
0
0
0
0
0
0
0
0
tCLCH10 tLHLL
ale Width
5
11 tCHLL
ale Inactive Delay
0
12 tAVLL
ad Address Valid to ale Low
tCLCH
13 tLLAX
ad Address Hold from ale Inactive
tCHCL
14 tAVCH
ad Address Valid to Clock High
0
16 tCLCSV
mcs_n/pcs_n Inactive Delay
0
17 tCXCSX
mcs_n/pcs_n Hold from Command Inactive tCLCH
18 tCHCSX
mcs_n/pcs_n Inactive Delay
0
19 tDXDL
den_n Inactive to dt_r_n Low
0
20 tCVCTV
Control Active Delay 1
0
22 tCHCTV
Control Active Delay 2
0
23 tLHAV
ale High to Address Valid
7.5
Write Cycle Timing Responses
30 tCLDOX
Data Hold Time
0
31 tCVCTX
Control Inactive Delay
0
32 tWLWH
wr_n Pulse Width
2tCLCL
33 tWHLH
wr_n Inactive to ale High
tCLCH
34 tWHDX
Data Hold after wr_n
tCLCL
35 tWHDEX
wr_n Inactive to den_n Inactive
tCLCH
tCLCL
+
65 tAVWL
a Address Valid to wr_n Low
tCHCL
67 tCHCSV
clkoutA High to lcs_n/usc_n Valid
0
68 tCHAV
clkoutA High to a Address Valid
0
tCHCL
87 tAVBL
a Address Valid to whb_n/wlb_n Low
-1.5
Units
ns
ns
6
6
12
12
12
8
8
12
12
10
9
10
9
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
PSRAM Read Cycle
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
clkoutA
66
a19-a0
Address
68
s6/lock_n
8
s6
lock_n
5
ad15-ad0/ad7-ad0
s6
7
1
Address
Data
23
Address
2
ao15-ao8
Address
9
11
59
ale
24
10
28
25
27
rd_n
84
26
81
80
lcs_n
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
PSRAM Read Cycle Timing
No.
Name
Comment
General Timing Requirements
1 tDVCL
Data in Setup
2 tCLDX
Data in Hold
General Timing Responses
5 tCLAV
ad Address Valid Delay
7 tCLDV
Data Valid Delay
8 tCHDX
Status Hold Time
9 tCHLH
ale Active Delay
10
11
23
80
81
tLHLL
tCHLL
tLHAV
tCLCLX
tCLCSL
ale Width
ale Inactive Delay
ale High to Address Valid
lcs_n Inactive Delay
lcs_n Active Delay
84 tLRLL
lcs_n Precharge Pulse Width
Read Cycle Timing Responses
24 tAZRL
ad Address Float to rd_n Active
25 tCLRL
rd_n Active Delay
26 tRLRH
rd_n Pulse Width
27 tCLRH
rd_n Inactive Delay
28 tRHLH
rd_n Inactive to ale High
59 tRHDX
rd_n High to Data Hold on ad Bus
66 tAVRL
68 tCHAV
a Address Valid to rd_n Low
clkoutA High to a Address Valid
MIN
MAX
Units
10
0
NLL
ns
ns
0
0
0
0
12
12
ns
ns
ns
ns
8
tCHCL5
0
7.5
0
0
tCLCL
+
tCLCH
0
0
tCLCL
0
tCLCH
0
tCLCL
+
tCHCL
0
8
9
9
ns
ns
ns
ns
ns
ns
10
10
8
ns
ns
ns
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
PSRAM Write Cycle
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
clkoutA
65
a19-a0
Address
68
s6
8
s6
lock_n
5
ad15-ad0/ad7-ad0
s6
7
30
Address
Data
ao15-ao8
Address
23
33
9
11
34
ale
31
10
20
31
wr_n
87
20
32
whb_n/wlb_n/wb_n
80
81
84
80
lcs_n
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
PSRAM Write Cycle Timing
No. Name
Comment
General Timing Requirements
1 tDVCL
Data in Setup
2 tCLDX
Data in Hold
General Timing Responses
5 tCLAV
ad Address Valid Delay
7 tCLDV
Data Valid Delay
8 tCHDX
Status Hold Time
9 tCHLH
ale Active Delay
10 tLHLL
ale Width
11 tCHLL
ale Inactive Delay
20 tCVCTV
Control Active Delay 1
23 tLHAV
ale High to Address Valid
80 tCLCLX
lcs_n Inactive Delay
81 tCLCSL
lcs_n Active Delay
84 tLRLL
lcs_n Precharge Pulse Width
Write Cycle Timing Responses
30 tCLDOX
Data Hold Time
31 tCVCTX
Control Inactive Delay
32 tWLWH
wr_n Pulse Width
33 tWHLH
wr_n Inactive to ale High
34 tWHDX
Data Hold after wr_n
65 tAVWL
68 tCHAV
a Address Valid to wr_n Low
clkoutA High to a Address Valid
87 tAVBL
a Address Valid to whb_n/wlb_n Low
MIN
MAX Units
10
0
ns
ns
0
12
0
12
0
0
8
tCLCH-5
NULL NULL
0
10
7.5
0
9
0
9
tCLCL+
tCLCH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
2tCLCL
tCLCH
tCLCL
tCLCL+
tCHCL
0
tCHCL 1.5
ns
ns
ns
ns
ns
10
8
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
PSRAM Refresh Cycle
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
CLKOUTA
a19-a0
Address
9
11
28
ale
27
10
26
rd_n
80
25
27
81
lcs_n
79
82
rfsh_n
86
85
PSRAM Refresh Cycle
No. Name
Comment
General Timing Requirements
1 tDVCL
Data in Setup
2 tCLDX
Data in Hold
General Timing Responses
9 tCHLH
ale Active Delay
10 tLHLL
ale Width
11 tCHLL
ale Inactive Delay
Read/Write Cycle Timing Responses
25 tCLRL
rd_n Active Delay
26 tRLRH
rd_n Pulse Width
27 tCLRH
rd_n Inactive Delay
28 tRHLH
rd_n Inactive to ale High
80 tCLCLX
lcs_n Inactive Delay
81 tCLCSL
lcs_n Active Delay
Refresh Cycle Timing Responses
79 tCHRFD
clkoutA High to rfsh_n Valid
82 tCLRF
clkoutA High to rfsh_n Invalid
85 tRFCY
rfsh_n Cycle Time
86 tLCRF
lcs_n Inactive to rfsh_n Active Delay
MIN
MAX
10
0
0
tCLCH5
0
0
tCLCL
0
tCLCH
0
0
Units
ns
ns
8
ns
8
ns
ns
10
10
9
9
0
12
0
12
6tCLCL
2tCLCL NULL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Interrupt Acknowledge Cycle
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
clkoutA
68
a19-a0
Address
7
s6
s6
8
lock_n
s6
15
1
ad15-ad0/ad7-ad0
Ptr
12
23
2
ao15-ao8
Address
9
11
ale
10
bhe_n
4
bhe_n
20
31
inta1_n/inta0_n
22
22
21
den_n
19
22
dt_r_n
3
4
s2_n-s0_n
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Interrupt Acknowledge Cycle Timing
No. Name
Description
General Timing Requirements
1
tDVCL
Data in Setup
2
tCLDX
Data in Hold
General Timing Responses
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
7
tCLDV
Data Valid Delay
8
tCHDX
Status Hold Time
9
tCHLH
ale Active Delay
10
11
12
15
19
20
21
22
23
31
68
tLHLL
tCHLL
tAVLL
tCLAZ
tDXDL
tCVCTV
tCVDEX
tCHCTV
tLHAV
tCVCTX
tCHAV
ale Width
ale Inactive Delay
ad Address Valid to ale Low
ad Address Float Delay
den_n Inactive to dt_r_n Low
Control Active Delay 1
den_n Inactive Delay
Control Active Delay 2
ale High to Address Valid
Control Inactive Delay
clkoutA High to a Address Valid
MIN
MAX
10
0
0
0
0
0
0
tCLCH5
0
tCLCH
0
0
0
0
0
7.5
0
0
Units
ns
ns
6
6
12
8
8
12
10
9
10
10
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Software Halt Cycle
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
clkoutA
68
a19-a0
Invalid Address
5
s6/ad[15:0/ad[8:0]/ao[15:8]
Invalid Address
9
11
ale
10
den_n
19
dt_r_n
22
s2_n-s0_n
4
Status
3
Software Halt Cycle Timing
No. Name
Description
General Timing Responses
3
tCHSV
Status Active Delay
4
tCLSH
Status Inactive Delay
5
tCLAV
ad Address Valid Delay
9
tCHLH
ale Active Delay
10
11
19
22
68
tLHLL
tCHLL
tDXDL
tCHCTV
tCHAV
ale Width
ale Inactive Delay
den_n Inactive to dt_r_n Low
Control Active Delay 2
clkoutA High to a Address Valid
MIN
MAX
Units
0
0
0
0
tCLCH5
0
0
0
0
6
6
12
8
ns
ns
ns
ns
8
10
8
ns
ns
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Clock – Active Mode
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
180ns
160ns
180ns
x2
36
37
38
x1
69
42
43
44
clkoutA
70
clkoutB
Clock – Power-Save Mode
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
x2
x1
clkoutA
clkoutB(CBF=1)
clkoutB(CBF=0)
Clock Timing
No. Name
CLKIN Requirements
36 tCKIN
37 tCLCK
38 tCHCK
39 tCKHL
40 tCKLH
CLKOUT Timing
42 tCLCL
43 tCLCH
44 tCHCL
45 tCH1CH2
46 tCL2CL1
61 tLOCK
69 tCICOA
70 tCICOB
Description
MIN
MAX
Units
X1 Period
X1 Low Time
X1 High Time
X1 Fall Time
X1 Rise time
25
7.5
7.5
66
5
5
ns
ns
ns
ns
ns
3
3
0.5
25
35
ns
ns
ns
ns
ns
ms
ns
ns
clkoutA Period
clkoutA Low Time
clkoutA High Time
clkoutA Rise Time
clkoutA Fall Time
Maximum PLL Lock Time
X1 to clkoutA Skew
X1 to clkoutB Skew
25
tCLCL/2
tCLCL/2
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
srdy – Synchronous Ready
0ns
20ns
40ns
60ns
80ns
100ns
120ns
clkoutA
47
srdy
48
ardy - Asynchronous Ready
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140
clkoutA
51
49
ardy
50
Sytem Normally not Ready
49
ardy
Sytem Normally Ready
50
ardy
System Normally Ready
52
Peripherals
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
clkoutA
53
int4-0/NMI/tmrin1-0
54
drq1-drq0
55
tmrout1-tmrout0
Ready and Peripheral Timing
No. Name
Description
MIN
MAX
Units
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Ready and Peripheral Timing Requirements
47 tSRYCL
srdy Transition Setup Time
48 tCLSRY
srdy Transistion Hold Time
49 tARYCH
ardy Resolution Transition Setup Time
50 tCLARX
ardy Active Hold Time
51 tARYCHL
ardy Inactive Holding Time
52 tARYLCL
ardy Setup Time
53 tINVCH
Peripheral Setup Time
54 tINVCL
drq Setup Time
Peripheral Timing Responses
55 tCLTMV
Timer Output Delay
10
3
9
4
6
9
10
10
ns
ns
ns
ns
ns
ns
ns
ns
0
12
ns
Reset 1
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
x1
57
res_n
57
Low for N x1 Cycles
clkoutA
Reset 2
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
160ns
1
res_n
clkoutA
bhe_n/aden_n,rfsh2_n/
aden_n/s6/clkdiv2,uzi_n
ad[15:0],a0[15:8],ad[7:0]
tri-state
tri-state
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Bus Hold Entering
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
100ns
120ns
140ns
clkoutA
58
hold
62
hlda
15
ad[15:0],den_n
63
a[19:0], s6,rd_n,wr_n,bhe_n, dr/r_n
s2_n-s1_n,whb_n,wlb_n
Bus Hold Leaving
0ns
20ns
40ns
60ns
80ns
clkoutA
58
hold
62
hlda
5
ad[15:0],den_n
64
a[19:0], s6,rd_n,wr_n,bhe_n, dr/r_n
s2_n-s1_n,whb_n,wlb_n
Reset and Bus Hold Timing
No. Name
Description
Reset and Bus Hold Timing Requirements
5
tCLAV
ad Address Valid Delay
15 tCLAZ
ad Address Float Delay
57 tRESIN
res_n Setup Time
58 tHVCL
hld Setup Time
Reset and Bus Hold Timing Responses
62 tCLHAV
hlda Valid Delay
63 tCHCZ
Command Lines Float Delay
64 tCHCV
Command Lines Valid Delay (after Float)
MIN
MAX
Units
0
tCLCH
10
10
12
ns
ns
ns
ns
0
0
0
7
12
12
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Synchronous Serial Interface
0ns
20ns
40ns
60ns
80ns
100ns
120ns
140ns
clkoutA
71
sden
72
sclk
75
77
sdata(RX)
DATA
78
sdata(TX)
DATA
Synchronous Serial Interface Timing
No. Name
Description
Synchronous Serial Port Timing Requirements
75 tDVSH
Data Valid to sclk high
77 tSHDX
sclk High to SPI Data Hold
Synchronous Serial Port Timing Responses
71 tCLEV
clkoutA Low to sden Valid
72 tCLSL
clkoutA Low to sclk Low
78 tSLDV
sclk Low to Data Valid
MIN
MAX
10
3
0
0
0
Units
ns
ns
12
12
12
ns
ns
ns
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
ad4
ad11
ad3
ad10
ad2
ad9
sdata
rxd
txd
uzi_n
s6 /clkdiv2_n
ad15
ad7
ad14
vCC
ad6
ad13
gnd
ad5
ad12
IA186EM 100-Pin PQFP
sden1
sden0
sclk
bhe_n/aden
wr_n
rd_n
ale
ardy
s2_n
s1_n
s0_n
gnd
x1
x2
vCC
clkouta
clkoutb
gnd
a19
a18
vCC
a17
a16
a15
a14
a13
a12
a11
a10
a9
hlda
hold
srdy
nmi
dt/r_n
den_n
mcs0
a7
a6
a5
a4
a3
a2
vCC
a1
a0
gnd
whb_n
wlb_n
a8
ad1
ad8
ad0
drq0_n
drq1_n
tmrin0
tmrout0
tmrout1
tmrin1
res_n
gnd
mcs3_n/rfsh_n
mcs2_n
vCC
pcs0_n
pcs1_n
gnd
pcs2_n
pcs3_n
vCC
pcs5_n/a1
pcs6_n/a2
lcs_n/once0_n
ucs_n/once1_n
int0
int1/select_n
int2/inta0_n/pwd
int3/inta1_n/irq
int4
mcs1_n
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
A186EM 100-Pin PQFP Assignments (Sorted by Pin Number)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
sden1/pio23
sden0/pio22
sclk/pio20
bhe_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n
s0_n
gnd
x1
x2
vCC
clkouta
clkoutb
gnd
a19/pio29
a18/pio8
vCC
a17/pio7
a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
vCC
a1
a0
gnd
whb_n
wlb_n
hlda
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
Pin #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
mcs1_n/pio15
int4/pio30
int3/inta1_n/irq
int2/inta0_n/pio31
int1/select_n
int0
ucs_n/once1_n
lcs_n/once0_n
pcs6_n/a2/pio2
pcs5_n/a1/pio3
vCC
pcs3_n/pio19
pcs2_n/pio18
gnd
pcs1_n/pio17
pcs0_n/pio16
vCC
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
gnd
res_n
tmrin1/pio25
tmrout1/pio1
tmrout0/pio10
tmrin0/pio11
drq1/pio13
drq0/pio12
ad0
ad8
ad1
ad9
ad2
ad10
ad3
ad11
ad4
ad12
ad5
gnd
ad13
ad6
vCC
ad14
ad7
ad15
s6/clkdiv2_n/pio29
uzi_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Pin Name
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17/pio7
a18/pio8
a19/pio9
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
ad9
ad10
ad11
ad12
ad13
ad14
ad15
ale
ardy
bhe_n/aden_n
clkouta
clkoutb
den_n/pio5
drq0/pio12
drq1/pio13
dt/r_n/pio4
gnd
gnd
gnd
gnd
gnd
As of Production Version -03
Number
40
39
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
20
19
78
80
82
84
86
88
91
94
79
81
83
85
87
90
93
95
7
8
4
16
17
49
77
76
48
12
18
41
64
70
Pin Name
gnd
hlda
hold
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
lcs_n/once0_n
mcs0_n/pio14
mcs1_n/pio15
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
nmi
pcs0_n/pio16
pcs1_n/pio17
pcs2_n/pio18
pcs3_n/pio19
pcs5_n/a1/pio3
pcs6_n/a2/pio2
rd_n
res_n
rxd/pio28
s0_n
s1_n
s2_n
s6/clkdiv2/pio29
sclk/pio20
sdata/pio21
sden0/pio22
sden1/pio23
srdy/pio6
tmrin0/pio11
tmrin1/pio0
tmrout0/pio10
tmrout1/pio1
txd/pio27
ucs_n/once1_n
uzi_n/pio26
vCC
vCC
vCC
vCC
vCC
vCC
whb_n
wlb_n
wr_n
x1
x2
Number
89
44
45
56
55
54
53
52
58
50
51
68
69
47
66
65
63
62
60
59
6
71
99
11
10
9
96
3
100
2
1
46
75
72
74
73
98
57
97
15
21
38
61
67
92
42
43
5
13
14
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
drq0
drq1
tmrin0
tmrout0
tmrout1
tmrin1
res_n
gnd
mcs3_n/rfsh_n
mcs2_n
vCC
pcs0_n
pcs1_n
gnd
pcs2_n
pcs3_n
vCC
pcs5_n/a1
pcs6_n/a2
lcs_n/once0_n
ucs_n/once1_n
int0
int1/select_n
int2/inta0_n
int3_n/inta1_n/irq
IA186EM TQFP 100-Pin
int4
mcs1_n
mcs0_n
den_n
dt/r_n
nmi
srdy
hold
hlda
wlb_n
whb_n
gnd
a0
a1
vCC
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
sclk
bhe_n/aden_n
wr_n
rd_n
ale
ardy
s2 n
s1_n
s0 n
gnd
x1
x2
vCC
clkouta
clkoutb
gnd
a19
a18
vCC
a17
a16
a15
a14
a13
a12
ad0
ad8
ad1
ad9
ad2
ad10
ad3
ad11
ad4
ad12
ad5
gnd
ad13
ad6
ad7
ad14
vCC
ad15
s6//clkdiv2
uzi_n
txd
rxd
sdata
sden1
sden0
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
IA186EM 100-Pin TQFP Pin Assignments (sorted by Pin number)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
ad0
ad8
ad1
ad9
ad2
ad10
ad3
ad11
ad4
ad12
ad5
gnd
ad13
ad6
vCC
ad14
ad7
ad15
s6/clkdiv2/pio29
uzi_n/pio26
txd
rxd
sdata/pio21
sden1/pio23
sden0/pio22
sclk/pio20
bhe_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n
s0_n
gnd
x1
x2
vCC
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vCC
a17/pio7
a16
a15
a14
a13
a12
Pin #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
vCC
a1
a0
gnd
whb_n
wlb_n
hlda
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
mcs1_n/pio15
int4/pio30
int3/inta1_n/irq
int2/inta0_n/pio31
int1/select_n
int0
ucs_n/once1_n
lcs_n/once0_n
pcs6_n/a2/pio2
pcs5_n/a1/pio3
vCC
pcs3_n/pio19
pcs2_n/pio18
gnd
pcs1_n/pio17
pcs0_n/pio16
vCC
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
gnd
res_n
tmrin1/pio0
tmrout1/pio1
tmrout0/pio10
tmrin0/pio11
drq1/pio13
drq0/pio12
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Pin Name
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17/pio7
a18/pio8
a19/pio9
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ad8
ad9
ad10
ad11
ad12
ad13
ad14
ad15
ale
ardy
bhe_n/aden_n
clkouta
clkoutb
den_n/pio5
drq0/pio12
drq1/pio13
dt/r_n/pio4
gnd
gnd
gnd
gnd
gnd
As of Production Version -03
Number
63
62
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
43
42
1
3
5
7
9
11
14
17
2
4
6
8
10
13
16
18
30
30
27
39
40
72
100
99
71
12
36
41
64
87
Pin Name
gnd
hlda
hold
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
lcs_n/once0_n
mcs0_n/pio14
mcs1_n/pio15
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
nmi
pcs0_n/pio16
pcs1_npio
pcs2_n/pio18
pcs3_n/pio19
pcs5_n/a1/pio3
pcs6_n/a2/pio2
rd_n
res_n
rxd/pio23
s0_n
s1_n
s2_n
s6/clkdiv2/pio29
sclk/pio20
sdata/pio21
sden0/pio22
sden1/pio23
srdy/pio6
tmrin0/pio11
tmrin1/pio0
tmrout0/pio10
tmrout1/pio1
txd/pio27
ucs_n/once1_n
uzi_n/pio26
vCC
vCC
vCC
vCC
vCC
vCC
whb_n
wlb_n
wr_n
x1
x2
Number
93
67
68
79
78
77
76
75
81
73
74
91
92
70
89
88
86
85
83
82
29
94
24
34
33
32
19
26
23
25
24
69
98
95
97
96
21
80
20
15
38
44
61
84
90
65
66
28
36
37
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
txd
uzi_n
s6 /clkdiv2_n
ao15
ad7
ao14
vCC
ad6
ao13
gnd
ad5
ao12
ad4
ao11
ad3
ao10
ad2
ao9
sdata
rxd
IA188EM 100-Pin PQFP
ad1
ao8
ad0
drq0
drq1
tmrin0
tmrout0
tmrout1
tmrin1
res_n
gnd
mcs3_n/rfsh_n
mcs2_n
vCC
pcs0_n
pcs1_n
gnd
pcs2_n
pcs3_n
vCC
pcs5_n/a1
pcs6_n/a2
lcs_n/once0
ucs_n/once1
int0
int1/select_n
int2/inta0_n
int3/inta1_n/irq
int4
mcs1_n
a1
a0
gnd
gnd
wb_n
hlda
hold
srdy
nmi
dt/r_n
den_n
mcs0
a8
a7
a6
a5
a4
a3
a2
vCC
sden1
sden0
sclk
rfsh2/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n
s0_n
gnd
x1
x2
vCC
clkouta
clkoutb
gnd
a19
a18
vCC
a17
a16
a15
a14
a13
a12
a11
a10
a9
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
IA188EM 100 Pin PQFP Assignments (sorted by Pin number)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
sden1/pio23
sden0/pio22
sclk/pio20
rfsh2_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n
s0_n
gnd
x1
x2
vCC
clkouta
clkoutb
gnd
a19/pio29
a18/pio8
vCC
a17/pio7
a16
a15
a14
a13
a12
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
vCC
a1
a0
gnd
gnd
wb_n
hlda
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
Pin #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
mcs1_n/pio15
int4/pio30
int3/inta1_n/irq
int2/inta0_n/pwd/pio31
int1/select_n
int0
ucs_n/once1_n
lcs_n/once0_n
pcs6_n/a2/pio2
pcs5_n/a1/pio3
vCC
pcs3_n/pio19
pcs2_n/pio18
gnd
pcs1_n/pio17
pcs0_n/pio16
vCC
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
gnd
res_n
tmrin1/pio25
tmrout1/pio1
tmrout0/pio10
tmrin0/pio11
drq1/pio13
drq0/pio12
ad0
ao8
ad1
ao9
ad2
ao10
ad3
ao11
ad4
ao12
ad5
gnd
ao13
ad6
VCC
ao14
ad7
ao15
s6/clkdiv2_n/pio29
uzi_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Pin Name
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17/pio7
a18/pio8
a19/pio9
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ale
ao8
ao9
ao10
ao11
ao12
ao13
ao14
ao15
ardy
clkouta
clkoutb
den_n/ds_n/pio5
drq0/pio12
drq1/pio13
dt/r_n/pio4
gnd
gnd
gnd
gnd
gnd
gnd
As of Production Version -03
Number
40
39
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
20
19
78
80
82
84
86
88
91
94
7
79
81
83
85
87
90
93
95
8
16
17
49
77
76
48
12
18
41
42
64
70
Pin Name
gnd
hlda
hold
int0
int1/select_n
int2/inta0_n/pwd/pio31
int3/inta1_n/irq
int4/pio30
lcs_n/once0_n
mcs0_n/pio14
mcs1_n/pio15
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
nmi
pcs0_n/pio16
pcs1_n/pio17
pcs2_n/cts1_n/enrx1_n/pio18
pcs3_n/rts1_n/rtr1_n/pio19
pcs5_n/a1/pio3
pcs6_n/a2/pio2
rd_n
res_n
rfsh2_n/aden_n
rxd/pio28
s0_n
s1_n
s2_n
s6/lock_n/clkdiv2/pio29
sclk/pio20
sdata/pio21
sden0/pio22
sden1/pio23
srdy/pio6
tmrin0/pio11
tmrin1/pio0
tmrout0/pio10
tmrout1/pio1
txd/pio27
ucs_n/once1_n
uzi_n/pio26
vCC
vCC
vCC
vCC
vCC
vCC
wb_n
wr_n
x1
x2
Number
89
44
45
56
55
54
53
52
58
50
51
68
69
47
66
65
63
62
60
59
6
71
4
99
11
10
9
96
3
100
2
1
46
75
72
74
73
98
57
97
15
21
38
61
67
92
42
5
13
14
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
drq0
drq1
tmrin0
tmrout0
tmrout1
tmrin1
res_n
gnd
mcs3_n/rfsh_n
mcs2_n
vCC
pcs0_n
pcs1_n
gnd
pcs2_n
pcs3_n
vCC
pcs5_n/a1
pcs6_n/a2
lcs_n/once0_n
ucs_n/once1_n
int0
int1/select_n
int2/inta0_n
int3_n/inta1_n/irq
IA188EM 100-Pin TQFP
int4
mcs1_n
mcs0_n
den_n
dt/r_n
nmi
srdy
hold
hlda
wb_n
gnd
gnd
a0
a1
vCC
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
sclk
rfsh2/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n
s0_n
gnd
x1
x2
vCC
clkouta
clkoutb
gnd
a19
a18
vCC
a17
a16
a15
a14
a13
a12
ad0
ao8
ad1
ao9
ad2
ao10
ad3
ao11
ad4
ao12
ad5
gnd
ao13
ad6
vCC
ao14
ad7
ao15
s6//clockdiv2
uzi_n
txd
rxd
sdata
sden1
sden0
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
IA188EM 100-Pin TQFP Pin Assignments (sorted by Pin number)
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
ad0
ao8
ad1
ao9
ad2
ao10
ad3
ao11
ad4
ao12
ad5
gnd
ao13
ad6
vCC
ao14
ad7
ao15
s6/clkdiv2/pio29
uzi_n/pio26
txd/pio27
rxd/pio28
sdata/pio21
sden1/pio23
sden0/pio22
sclk/pio20
rfsh2_n/aden_n
wr_n
rd_n
ale
ardy
s2_n
s1_n
s0_n
gnd
x1
x2
vCC
clkouta
clkoutb
gnd
a19/pio9
a18/pio8
vCC
a17/pio7
a16
a15
a14
a13
a12
Pin #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
a11
a10
a9
a8
a7
a6
a5
a4
a3
a2
vCC
a1
a0
gnd
gnd
wb_n
hlda
hold
srdy/pio6
nmi
dt/r_n/pio4
den_n/pio5
mcs0_n/pio14
mcs1_n/pio15
int4/pio30
int3/inta1_n/irq
int2/inta0_n/pio31
int1/select_n
int0
ucs_n/once1_n
lcs_n/once0_n
pcs6_n/a2/pio2
pcs5_n/a1/pio3
vCC
pcs3_n/pio19
pcs2_n/pio18
gnd
pcs1_n/pio17
pcs0_n/pio16
vCC
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
gnd
res_n
tmrin1/pio0
tmrout1/pio1
tmrout0/pio10
tmrin0/pio11
drq1/pio13
drq0/pio12
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
Pin Name
a0
a1
a2
a3
a4
a5
a6
a7
a8
a9
a10
a11
a12
a13
a14
a15
a16
a17/pio7
a18/pio8
a19/pio9
ale
ad0
ad1
ad2
ad3
ad4
ad5
ad6
ad7
ao8
ao9
ao10
ao11
ao12
ao13
ao14
ao15
ardy
clkouta
clkoutb
den_/pio5
drq0/pio12
drq1/pio13
dt/r_n/pio4
gnd
gnd
gnd
gnd
gnd
gnd
As of Production Version -03
Number
63
62
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
43
42
30
1
3
5
7
9
11
14
17
2
4
6
8
10
13
16
18
30
39
40
72
100
99
71
12
35
41
64
65
87
Pin Name
gnd
hlda
hold
int0
int1/select_n
int2/inta0_n/pio31
int3/inta1_n/irq
int4/pio30
lcs_n/once0_n
mcs0_n/pio14
mcs1_n/pio15
mcs2_n/pio24
mcs3_n/rfsh_n/pio25
nmi
pcs0_n/pio16
pcs1_n/pio17
pcs2_n/pio18
pcs3_n/pio19
pcs5_n/a1/pio3
pcs6_n/a2/pio2
rd_n
res_n
rfsh2_n/aden_n
rxd/pio28
s0_n
s1_n
s2_n
s6/lock_n/clkdiv2/pio29
sclk/pio20
sdata/pio21
sden0/pio22
sden1/pio23
srdy/pio6
tmrin0/pio11
tmrin1/pio0
tmrout0/pio10
tmrout1/pio1
txd/pio27
ucs_n/once1_n
uzi_n/pio26
vCC
vCC
vCC
vCC
vCC
vCC
wb_n
wr_n
x1
x2
Number
93
67
68
79
78
77
76
75
81
73
74
91
92
70
89
88
86
85
83
82
29
94
27
22
34
33
32
19
26
23
25
24
69
98
95
97
96
21
80
20
15
38
44
61
84
90
66
28
36
37
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Physical Dimensions
PQFP 100
PLATING
Pin 1 Indicator
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Symbol
A
A1
A2
B
B1
C
C1
D
D1
E
E1
e
L
L1
R1
R2
S
Y
)
)1
)2
)3
Dimensions in Inches
Minimum Nominal
Maximum
------0.134
0.010
------0.107
0.112
0.117
0.010
0.012
0.015
0.009
0.012
0.013
0.005
0.006
0.009
0.004
0.006
0.007
0.906
0.913
0.921
0.783
0.787
0.791
0.669
0.677
0.685
0.547
0.551
0.555
0.026 BSC
0.029
0.035
0.041
0.063 BSC
0.005
------0.005
---0.012
0.008
------------0.004
---0%
7%
------0%
9%
10%
11%
9%
10%
11%
Data Sheet
As of Production Version -03
Dimensions in mm
Minimum Nominal
Maximum
------3.40
0.25
------2.73
2.85
2.97
0.25
0.30
0.38
0.22
0.30
0.33
0.13
0.15
0.23
0.11
0.15
0.17
23.00
23.20
23.40
19.90
20.00
20.10
17.00
17.20
17.40
13.90
14.00
14.10
0.65 BSC
0.73
0.88
1.03
1.60 BSC
0.13
------0.13
---0.30
0.20
------------0.10
---0%
7%
------0%
9%
10%
11%
9%
10%
11%
NOTES
1. Dimensions D1 and E1 do not include mold protrusion. But mold mismatch is included.
Allowable Protrusion is 0.25mm/0.010* per side.
2. Dimension B does not include Dambar protrusion. Allowable protrusion is 0.08mm/0.003* total
in excess of the B dimension at maximum material condition. Dambar cannot be located on the
lower radius or the foot.
3. Controlling dimension: millimeter.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
TQFP 100
Pin 1 Indicator
b
e
D2
E2
Dimensions in mm
Minimum Nominal Maximum
0.17
0.20
0.27
0.50 BSC
12.00
12.00
Dimensions in Inches
Minimum Nominal Maximum
0.007
0.008
0.011
0.02 BSC
0.472
0.472
aaa
bbb
ccc
ddd
0.20
0.20
0.08
0.08
0.008
0.008
0.003
0.003
Symbol
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
Data Sheet
8/16-BIT Microcontrollers
As of Production Version -03
Ordering Information
Innovasic#
Part Number
IA186EM-PQF100I
(standard packaging)
IA186EM-PQF100I-R
(RoHS packaging)
IA186EM-PTQ100I
(standard packaging)
IA186EM-PTQ100I-R
(RoHS packaging)
IA188EM-PQF100I
(standard packaging)
IA188EM-PQF100I-R
(RoHS packaging)
IA188EM-PTQ100I
(standard packaging)
IA188EM-PTQ100I-R
(RoHSpackaging)
AMD# Part
Number
Package
Type
Temperature
Grades
AM186EM-20KC\W
AM186EM-20KI\W
AM186EM-25KC\W
AM186EM-25KI\W
AM186EM-33KC\W
AM186EM-40KC\W
AM186EM-20KC\W
AM186EM-20KI\W
AM186EM-25KC\W
AM186EM-25KI\W
AM186EM-33KC\W
AM186EM-40KC\W
100-Pin Plastic Quad
Flat Package (PQFP)
Commercial and
Industrial
AM186EM-20VC\W
AM186EM-25VC\W
AM186EM-33VC\W
AM186EM-40VC\W
AM186EM-20VC\W
AM186EM-25VC\W
AM186EM-33VC\W
AM186EM-40VC\W
AM188EM-20KC\W
AM188EM-20KI\W
AM188EM-25KC\W
AM188EM-25KI\W
AM188EM-33KC\W
AM188EM-40KC\W
AM188EM-20KC\W
AM188EM-20KI\W
AM188EM-25KC\W
AM188EM-25KI\W
AM188EM-33KC\W
AM188EM-40KC\W
AM188EM-20VC\W
AM188EM-25VC\W
AM188EM-33VC\W
AM188EM-40VC\W
AM188EM-20VC\W
AM188EM-25VC\W
AM188EM-33VC\W
AM188EM-40VC\W
100-Pin Thin Quad Flat
Package (TQFP)
Commercial and
Industrial
100-Pin Plastic Quad
Flat Package (PQFP)
Commercial and
Industrial
100-Pin Thin Quad Flat
Package (TQFP)
Commercial and
Industrial
Other packages and temperature grades may be available for an additional cost and lead time.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Errata
Version -01
1) Problem: MCS chip select signals (MCS0-3) are intermittently suppressed. All other signals in bus cycle
appear correct (i.e. address, data, write/read strobes).
Analysis: Anomaly occurs when an access to I/O space is immediately followed by an MCS access. Given the
way instruction prefetches naturally separate such accesses, one known scenario for this anomaly is via a DMA
sequence. Possible combinations are:
(1) DMA write to destination is followed by previously scheduled
MCS read or write,
(2) DMA from I/O space to MCS space.
Customers using the UART DMA feature of the ES products may be particularly sensitive to this,
because when the TX data register of the PCB is in I/O space, eventually an MCS access will be
corrupted.
Another known scenario occurs when auxiliary flash (containing executable code) is selected by an
MCS signal and the PCB or PCS selects are in I/O space.
The PCB register block and the PCS address spaces are the only areas that can be assigned to I/O
space. The PCB register block is configured by bit 12 of the RELREG, and defaults to I/O space.
PCS space is configured by bit 6 of the MPCS, and must be initialized by the user.
Workaround: If possible, assign PCB and PCS address locations to memory space instead of I/O space.
2) Problem: IA186ES devices do not work in a 188ES socket.
Analysis: The WHB pin should be sampled at reset to configure the bus width. This pin is always
grounded in 188 applications, and floats high during reset in 186 applications. The bus width of the
Innovasic devices are configured via in-package bonding.
Workaround: Use IA188ES devices for 188 sockets.
3) Problem: Noise on TMROUT0 (PIO10) and TMROUT1 (PIO1) when in PIO output mode.
Analysis: Only occurs when application is using HOLD/HLDA function, and either TMROUT pin is
in PIO output mode. Improper logic allows the TMROUT pin to tri-state when HLDA is asserted.
Analysis shows that UZI (PIO26), S6CLK2 (PIO29), DEN (PIO5), and DT_R (PIO4) may also be
affected. PIO input modes and normal operation modes are not affected.
Workaround: If possible, use a PIO pin other than those listed above when utilizing HOLD/HLDA feature. An
external pullup/pulldown may also help.
4) Problem: An extra DMA cycle occurs after ending DMA transfers via a DMA control register write. In certain
applications, this extra DMA cycle occurrence will hang the device because of DREQ/SRDY dependency.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Analysis: The string of DMA transfers is ended by writing x0004 to PCB address xCA or xDA while
DMA request line is asserted. By this time, the sequence to initiate the DMA transfer cannot be
suppressed or recalled, so the IA device executes the spurious transfer.
Workaround: None.
5) Problem: In the 186/188ES devices, the TB8 bit of the UART control register (offset x10 or x80) does not
automatically reset after transmitting the initial word when using 9-bit formats (modes 2 or 3).
Analysis: This feature is used to designate the “address” byte when using the UART in a psuedoLAN configuration. The automatic reset of TB8 allows a convenient means to send a block of words
with little software interaction.
Workaround: Manually reset TB8 after detecting the end of the first transmitted word.
6) Problem: In the 186/188ES devices, the Power Save clock speed is not working correctly.
Analysis: A logic error causes the device to incorrectly clear bits [2:0] of the PDCON when the
device leaves power save mode by clearing bit 15 of the PDCON.
Workaround: Every time the programmer desires to go into power save mode by setting bit 15 of the PDCON
register, then bits [2:0] should also be set according to the desired clock divide factor. It should not be assumed
that once written to, bits [2:0] will retain their values when entering and exiting the power save mode.
7) Problem: The device responds incorrectly to false start bits.
Analysis: If a start bit is less than half width, the device should ignore this start bit completely (no
data byte, no errors). Instead the device treats the data that follows as a valid byte, and generates a
framing error.
Workaround: Eliminate false start bits, or revise how the resulting framing error and extra byte are handled.
8) Problem: The UART is disabled when an external system generates a break condition.
Analysis: The device should not be disabled when an external system generates a break condition,
instead once the break condition is deasserted the UART should start receiving data. However, the
UART in the Innovasic device is disabled by the externally generated break condition and can only
receive data once the break flags (Bit 9: BRK0 of registers SP0ST and/or SP1ST) are cleared.
Workaround: Ensure that every time an external break condition is acknowledged, that the break flag bits are
cleared.
9) Problem: The MOV instruction does work when an attempt is made to load the CS register.
Analysis: On the OEM AMD part a MOV CS, AX command loads CS with the contents of AX. The
Innovasic part never loads CS with AX by use of a MOV instruction.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
Workaround: To load the CS register use a far JMP command.
10) Problem: There is a difference in how priority of timer interrupts are asserted between the original AMD part
and the Innovasic part.
Analysis: In the original AMD part, timer interrupts cannot be interrupted by another timer interrupt,
even if the new timer interrupt is of a higher priority. The Innovasic part will interrupt a timer
interrupt with a higher priority timer interrupt. Additionally, if a lower priority timer interrupt is
interrupted with a higher priority timer interrupt and another occurrence of the lower priority interrupt
occurs during the processing of the higher priority interrupt, upon execution of the EOI a new lower
priority interrupt will be initiated, possibly orphaning the original lower priority timer interrupt.
Workaround: When using nested interrupts, at the beginning of the interrupt routine before the global
interrupts are enabled with a CLI, timer interrupts must be specifically masked. At the end of the timer
interrupt routine being serviced, you need to set the Interrupt Enable Bit in the Process Status Word to globally
disable interrupts prior to clearing the timer interrupt being serviced.
11) Problem: UART will not respond to break condition if RXD is low when receiver is enabled.
Analysis: Detection of a break only occurs with a falling edge of RXD while receiver is enabled.
Workaround: None.
12) Problem: UART transmitter will not start if TX interrupt conditions exist prior to enabling transmitter.
Analysis: Priority of logic design inadvertently causes this lock up condition .
Workaround: Need to have transmitter enabled prior to any expected data transfers, or clear any spurious
interrupts before enabling .
13) Problem: Lock up just after reset is released.
Analysis: Usually, the first instruction is a long jump to the start of the user's code. In this case, the
compiler apparently inserted a short jump instruction with zero displacement before the expected long
jump instruction. The OEM device stuttered, but recovered to execute the long jump, while the IA
device instruction pointer was corrupted, causing the lock up. In summary, a short jump with zero
displacement is a corner case that does not work in the IA device.
Workaround: Do not use a short jump instruction with zero displacement.
14) Problem: Intermittent startup.
Analysis: Processor either came out of reset normally, or would go into a series of watchdog
timeouts. The addition of 10K ohm pullups to the WR_n and RD_n outputs seemed to solve the issue.
Further analysis of the OEM device shows the presence of undocumented pullups on these pins,
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
which will pull them high when the reset condition tristates these pins. The Innovasic device does not
include internal pullups on these pins allowing these outputs to float during reset.
Workaround: Add 10K ohm pullups to WR_n and RD_n pins to guarantee proper logic levels at the end of
reset.
Version -03
1) Problem: There is a difference in how priority of timer interrupts are asserted between the original AMD part
and the Innovasic part.
Analysis: In the original AMD part, timer interrupts cannot be interrupted by another timer interrupt, even if the
new timer interrupt is of a higher priority. The Innovasic part will interrupt a timer interrupt with a higher
priority timer interrupt. Additionally, if a lower priority timer interrupt is interrupted with a higher priority timer
interrupt and another occurrence of the lower priority interrupt occurs during the processing of the higher
priority interrupt, upon execution of the EOI a new lower priority interrupt will be initiated, possibly orphaning
the original lower priority timer interrupt.
Workaround: When using nested interrupts, at the beginning of the interrupt routine before the global interrupts
are enabled with a CLI, timer interrupts must be specifically masked. At the end of the timer interrupt routine
being serviced, you need to set the Interrupt Enable Bit in the Process Status Word to globally disable interrupts
prior to clearing the timer interrupt being serviced and unmask the appropriate timer interrupts.
2) Problem: Lock up just after reset is released.
Analysis: Usually, the first instruction is a long jump to the start of the user's code. In this case, the
compiler apparently inserted a short jump instruction with zero displacement before the expected long
jump instruction. The OEM device stuttered, but recovered to execute the long jump, while the IA
device instruction pointer was corrupted, causing the lock up. In summary, a short jump with zero
displacement is a corner case that does not work in the IA device.
Workaround: Do not use a short jump instruction with zero displacement.
3) Problem: Intermittent startup.
Analysis: Processor either came out of reset normally, or would go into a series of watchdog
timeouts. The addition of 10K ohm pullups to the WR_n and RD_n outputs seemed to solve the issue.
Further analysis of the OEM device shows the presence of undocumented pullups on these pins,
which will pull them high when the reset condition tristates these pins. The Innovasic device does not
include internal pullups on these pins allowing these outputs to float during reset.
Workaround: Add 10K ohm pullups to WR_n and RD_n pins to guarantee proper logic levels at the end of
reset.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
4) Problem: Timer Operation in continuous mode.
Analysis The timers (Timer0 and Timer1) do not function per the specification when set in continuous
mode with no external timer input stimulus to initiate/continue count.
Workaround: None.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com