ON MC74LVX244MELG Octal bus buffer Datasheet

MC74LVX244
Octal Bus Buffer
With 5V−Tolerant Inputs
The MC74LVX244 is an advanced high speed CMOS
non−inverting 3−state octal bus buffer and has two active low output
enables. It is also designed to work with 3−state memory address
drivers, etc. The inputs tolerate voltages up to 7.0 V, allowing the
interface of 5.0 V systems to 3.0 V systems.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
High Speed: tPD = 4.7 ns (Typ) at VCC = 3.3 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
These Devices are Pb−Free and are RoHS Compliant
20
SOIC−20
DW SUFFIX
CASE 751D
20
1
LVX244
AWLYYWWG
1
20
TSSOP−20
DT SUFFIX
CASE 948E
20
1
1
20
SOEIAJ−20
M SUFFIX
CASE 967
1
20
1
LVX244
A
WL, L
Y
WW, W
G or G
LVX
244
ALYWG
G
LVX244
AWLYWWG
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 3
1
Publication Order Number:
MC74LVX244/D
MC74LVX244
VCC
2OE
1O0
2D0
1O1
2D1
1O2
2D2
1O3
2D3
20
19
18
17
16
15
14
13
12
11
PIN NAMES
1
2
3
4
5
6
7
8
9
10
1OE
1D0
2O0
1D1
2O1
1D2
2O2
1D3
2O3
GND
Figure 1. 20−Lead Pinout (Top View)
1OE
1D0
1D1
1D2
1D3
1
2OE
2
18
4
16
6
14
8
12
1O0
2D0
1O1
2D1
1O2
2D2
1O3
2D3
Pins
Function
nOE
1Dn, 2Dn
1On, 2On
Output Enable Inputs
Data Inputs
3−State Outputs
19
FUNCTION TABLE
17
3
15
5
13
7
11
9
2O0
2O1
INPUTS
OUTPUTS
1OE, 2OE
1Dn, 2Dn
1On, 2On
L
L
H
L
H
X
L
H
Z
2O2
2O3
Figure 2. Logic Diagram
ORDERING INFORMATION
Package
Shipping†
SOIC−20
(Pb−Free)
1000 Tape & Reel
MC74LVX244DTG
TSSOP−20*
50 Units / Rail
MC74LVX244DTR2G
TSSOP−20*
2500 Tape & Reel
MC74LVX244MG
SOEIAJ−20
50 Units / Rail
MC74LVX244MELG
SOEIAJ−20
2000 Tape & Reel
Device
MC74LVX244DWR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74LVX244
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MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Supply Voltage
Parameter
–0.5 to +7.0
V
Vin
DC Input Voltage
–0.5 to +7.0
V
Vout
DC Output Voltage
–0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation
180
mW
Tstg
Storage Temperature
–65 to +150
_C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
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RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
2.0
3.6
V
DC Input Voltage
0
5.5
V
DC Output Voltage
0
VCC
V
−40
+85
_C
0
100
ns/V
VCC
DC Supply Voltage
Vin
Vout
TA
Dt/DV
Operating Temperature, All Package Types
Input Rise and Fall Time
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
TA = 25°C
VCC
V
Min
1.5
2.0
2.4
VIH
High−Level Input Voltage
2.0
3.0
3.6
VIL
Low−Level Input Voltage
2.0
3.0
3.6
VOH
High−Level Output Voltage
(Vin = VIH or VIL)
IOH = −50mA
IOH = −50mA
IOH = −4mA
2.0
3.0
3.0
VOL
Low−Level Output Voltage
(Vin = VIH or VIL)
IOL = 50mA
IOL = 50mA
IOL = 4mA
2.0
3.0
3.0
Iin
Input Leakage Current
Vin = 5.5V or GND
IOZ
Maximum 3−State Leakage Current
ICC
Quiescent Supply Current
Typ
TA = − 40 to 85°C
Max
Min
1.5
2.0
2.4
0.5
0.8
0.8
1.9
2.9
2.58
Max
2.0
3.0
V
0.5
0.8
0.8
1.9
2.9
2.48
V
V
0.1
0.1
0.36
0.1
0.1
0.44
V
3.6
±0.1
±1.0
mA
Vin = VIL or VIH
Vout = VCC or GND
3.6
±0.2
5
±2.5
mA
Vin = VCC or GND
3.6
4.0
40.0
mA
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3
0.0
0.0
Unit
MC74LVX244
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
Symbol
tPLH,
tPHL
tPZL,
tPZH
tPLZ,
tPHZ
tOSHL
tOSLH
Parameter
Propagation Delay
Input to Output
Output Enable Time to
High and Low Level
Output Disable Time From
High and Low Level
Output−to−Output Skew
(Note 1)
Test Conditions
Min
TA = − 40 to 85°C
Typ
Max
Min
Max
Unit
ns
VCC = 2.7V
CL = 15pF
CL = 50pF
6.1
8.6
11.4
14.9
1.0
1.0
13.5
17.0
VCC = 3.3 ± 0.3V
CL = 15pF
CL = 50pF
4.7
7.2
7.1
10.6
1.0
1.0
8.5
12.0
VCC = 2.7V
RL = 1kW
CL = 15pF
CL = 50pF
7.1
9.6
13.8
17.3
1.0
1.0
16.5
20.0
VCC = 3.3 ± 0.3V
RL = 1kW
CL = 15pF
CL = 50pF
5.5
8.0
8.8
12.3
1.0
1.0
10.5
14.0
VCC = 2.7V
RL = 1kW
CL = 50pF
11.6
16.0
1.0
19.0
VCC = 3.3 ± 0.3V
RL = 1kW
CL = 50pF
9.7
11.4
1.0
13.0
VCC = 2.7V
VCC = 3.3 ±0.3V
CL = 50pF
CL = 50pF
1.5
1.5
1.5
1.5
ns
ns
ns
1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter
guaranteed by design.
CAPACITIVE CHARACTERISTICS
TA = 25°C
Symbol
Min
Parameter
TA = − 40 to 85°C
Typ
Max
10
Min
Max
Unit
10
pF
Cin
Input Capacitance
4
Cout
Maximum Three−State Output Capacitance
6
pF
CPD
Power Dissipation Capacitance (Note 2)
19
pF
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 8 (per bit). CPD is used to determine the no−load
dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package)
TA = 25°C
Symbol
Typ
Characteristic
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.5
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.5
−0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
2.0
V
VILD
Maximum Low Level Dynamic Input Voltage
0.8
V
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4
MC74LVX244
SWITCHING WAVEFORMS
VCC
VCC
1Dn, 2Dn
1OE, 2OE
50%
50%
GND
GND
tPLH
1On, 2On
tPZL
tPHL
1On, 2On
50% VCC
HIGH
IMPEDANCE
50% VCC
tPZH
1On, 2On
tPLZ
tPHZ
VOL +0.3V
VOH -0.3V
50% VCC
Figure 3.
HIGH
IMPEDANCE
Figure 4.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 5. Propagation Delay Test Circuit
Figure 6. Three−State Test Circuit
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5
MC74LVX244
PACKAGE DIMENSIONS
SOIC−20
CASE 751D−05
ISSUE G
D
A
11
X 45 _
E
h
H
M
10X
0.25
B
M
20
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
1
10
20X
B
B
0.25
DIM
A
A1
B
C
D
E
e
H
h
L
q
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
C
T
SOEIAJ−20
CASE 967−01
ISSUE A
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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6
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.15
0.25
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.81
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.006
0.010
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.032
MC74LVX244
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
L
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
SECTION N−N
−U−
PIN 1
IDENT
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K
K1
0.25 (0.010)
N
10
M
0.15 (0.006) T U
S
N
A
−V−
F
DETAIL E
−W−
C
G
D
H
0.100 (0.004)
−T− SEATING
DETAIL E
SOLDERING FOOTPRINT
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
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MC74LVX244/D