Renesas M30623MGP-XXXGP Single-chip 16-bit cmos microcomputer Datasheet

M16C/62P Group (M16C/62P, M16C/62PT)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
1.
REJ03B0001-0241
Rev.2.41
Jan 10, 2006
Overview
The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin
plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level
of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing
capability, makes it suitable for control of various OA, communication, and industrial equipment which requires highspeed arithmetic/logic operations.
1.1
Applications
Audio, cameras, television, home appliance, office/communications/portable/industrial equipment, automobile,
etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 1 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1.2
1. Overview
Performance Outline
Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version).
Table 1.1
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version)
Item
CPU
Peripheral
Function
Number of Basic Instructions
Minimum Instruction Execution
Time
Operating Mode
Address Space
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion and microprocessor mode
Memory Capacity
See Table 1.4 to 1.5 Product List
Port
Multifunction Timer
Input/Output : 113 pins, Input : 1 pin
Timer A : 16 bits x 5 channels,
Timer B : 16 bits x 6 channels,
Three phase motor control circuit
3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CCITT-CRC
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Stop detection of main clock oscillation, re-oscillation detection
function
Available (option(4))
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7µA (VCC1=VCC2=3V, stop mode)
3.3±0.3 V or 5.0±0.5 V
100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
-20 to 85°C,
-40 to 85°C (3)
128-pin plastic mold LQFP
Serial Interface
A/D Converter
D/A Converter
DMAC
CRC Calculation Circuit
Watchdog Timer
Interrupt
Clock Generation Circuit
Electric
Characteristics
Oscillation Stop Detection
Function
Voltage Detection Circuit
Supply Voltage
Power Consumption
Flash memory
version
Performance
M16C/62P
Program/Erase Supply Voltage
Program and Erase Endurance
Operating Ambient Temperature
Package
1 Mbyte (Available to 4 Mbytes by memory space expansion
function)
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 2 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.2
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version)
Item
CPU
1. Overview
Number of Basic Instructions
Minimum Instruction
Execution Time
Operating Mode
Performance
M16C/62P
M16C/62PT(4)
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip, memory expansion
Single-chip
and microprocessor mode
Address Space
1 Mbyte (Available to 4 Mbytes by 1 Mbyte
memory space expansion function)
Memory Capacity
See Table 1.4 to 1.7 Product List
Peripheral
Port
Input/Output : 87 pins, Input : 1 pin
Function
Multifunction Timer
Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface
3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels
Interrupt
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Stop detection of main clock oscillation, re-oscillation detection function
Detection Function
Absent
Voltage Detection Circuit Available (option (5))
Electric
Supply Voltage
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1=VCC2=4.0 to 5.5V
Characteristics
VCC1 (f(BCLK=24MHz)
(f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=10MHz)
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
Power Consumption
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0µA (VCC1=VCC2=5V, f(XCIN)=32kHz,
wait mode)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz,
wait mode)
0.8µA (VCC1=VCC2=5V, stop mode)
0.7µA (VCC1=VCC2=3V, stop mode)
Flash memory Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V
5.0±0.5 V
version
Program and Erase
100 times (all area)
Endurance
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
T version : -40 to 85°C
V version : -40 to 125°C
-40 to 85°C (3)
Package
100-pin plastic mold QFP, LQFP
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. Use the M16C/62PT on VCC1=VCC2
5. All options are on request basis.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 3 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.3
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version)
Item
CPU
1. Overview
Number of Basic Instructions
Minimum Instruction
Execution Time
Operating Mode
Address Space
Performance
M16C/62P
M16C/62PT(4)
91 instructions
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Single-chip mode
1 Mbyte
See Table 1.4 to 1.7 Product List
Peripheral
Port
Input/Output : 70 pins, Input : 1 pin
Function
Multifunction Timer
Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer),
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial Interface
2 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
1 channel
Clock synchronous, I2C bus(1), IEBus(2)
2 channels
Clock synchronous (1 channel is only transmission)
A/D Converter
10-bit A/D converter: 1 circuit, 26 channels
D/A Converter
8 bits x 2 channels
DMAC
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels
Interrupt
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Stop detection of main clock oscillation, re-oscillation detection function
Detection Function
Absent
Voltage Detection Circuit Available (option (4))
Electric
Supply Voltage
VCC1=3.0 to 5.5 V, (f(BCLK=24MHz)
VCC1=4.0 to 5.5V, (f(BCLK=24MHz)
Characteristics
VCC1=2.7 to 5.5 V, (f(BCLK=10MHz)
Power Consumption
14 mA (VCC1=5V, f(BCLK)=24MHz)
14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz)
2.0µA (VCC1=5V, f(XCIN)=32kHz,
wait mode)
1.8µA (VCC1=3V, f(XCIN)=32kHz,
0.8µA (VCC1=5V, stop mode)
wait mode)
0.7µA (VCC1=3V, stop mode)
5.0 ± 0.5V
Flash memory Program/Erase Supply Voltage 3.3 ± 0.3V or 5.0 ± 0.5V
version
Program and Erase
100 times (all area)
Endurance
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
T version : -40 to 85°C
V version : -40 to 125°C
-40 to 85°C (3)
Memory Capacity
Package
80-pin plastic mold QFP
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 4 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1.3
1. Overview
Block Diagram
Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram,
Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram.
8
8
Port P0
8
Port P1
8
Port P2
8
Port P3
8
Port P5
Port P4
A/D converter
System clock
generation circuit
(10 bits X 8 channels
Output (timer A): 5
Input (timer B): 6
UART or
clock synchronous serial I/O
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Clock synchronous serial I/O
(8 bits X 2 channels)
M16C/60 series16-bit CPU core
SB
R0L
R1L
R2
R3
DMAC
ISP
INTB
D/A converter
PC
FLG
Multiplier
<VCC1 ports>(4)
8
<VCC2 ports>(4)
Port P14
(3)
Port P12
(3)
2
8
(8 bits X 2 channels)
Port P11
RAM (2)
Port P10
A0
A1
FB
(2 channels)
ROM (1)
USP
8
(15 bits)
Port P9
R0H
R1H
Watchdog timer
Memory
Port P8_5
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
<VCC1 ports> (4)
(8 bits X 3 channels)
Three-phase motor
control circuit
7
Expandable up to 26 channels)
Port P8
Timer (16-bit)
8
Internal peripheral functions
Port P6
<VCC1 ports>(4)
Port P7
<VCC2 ports>(4)
8
Port P13
(3)
8
(3)
8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1
M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 5 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
8
8
Port P0
8
Port P2
Port P3
4
8
Port P4
Port P5
8
Port P6
Internal peripheral functions
Timer (16-bit)
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
UART or
clock synchronous serial I/O (2 channels)
UART
(1 channel)
(3)
Watchdog timer
M16C/60 series16-bit CPU core
R0H
R1H
R0L
R1L
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
ISP
INTB
ROM (1)
RAM (2)
PC
FLG
8
Multiplier
Port P10
A0
A1
FB
USP
Memory
7
R2
R3
SB
Port P9
(15 bits)
(4)
(8 bits X 2 channels)
Port P8_5
Clock synchronous serial I/O
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
7
Port P8
Output (timer A): 5
Input (timer B): 6
System clock
generation circuit
A/D converter
(10 bits X 8 channels
4
Port P7
(4)
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).
4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Figure 1.2
M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 6 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1.4
1. Overview
Product List
Table 1.4 to 1.7 list the product list, Figure 1.3 shows the Type No., Memory Size, and Package, Table 1.8 lists the
Product Code of Flash Memory version and ROMless version for M16C/62P, and Table 1.9 lists the Product Code
of Flash Memory version for M16C/62PT. Figure 1.4 shows the Marking Diagram of Flash Memory version and
ROM-less version for M16C/62P (Top View), and Figure 1.5 shows the Marking Diagram of Flash Memory
version for M16C/62PT (Top View) at the time of ROM order.
Table 1.4
Product List (1) (M16C/62P)
Type No.
M30622M6P-XXXFP
M30622M6P-XXXGP
M30622M8P-XXXFP
M30622M8P-XXXGP
M30623M8P-XXXGP
M30622MAP-XXXFP
M30622MAP-XXXGP
M30623MAP-XXXGP
M30620MCP-XXXFP
M30620MCP-XXXGP
M30621MCP-XXXGP
M30622MEP-XXXFP
M30622MEP-XXXGP
M30623MEP-XXXGP
M30622MGP-XXXFP
M30622MGP-XXXGP
M30623MGP-XXXGP
M30624MGP-XXXFP
M30624MGP-XXXGP
M30625MGP-XXXGP
M30622MWP-XXXFP
M30622MWP-XXXGP
M30623MWP-XXXGP
M30624MWP-XXXFP
M30624MWP-XXXGP
M30625MWP-XXXGP
M30626MWP-XXXFP
M30626MWP-XXXGP
M30627MWP-XXXGP
ROM Capacity RAM Capacity Package Type
48 Kbytes
4 Kbytes
PRQP0100JB-A
PLQP0100KB-A
64 Kbytes
4 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
96 Kbytes
5 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
128 Kbytes
10 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
192 Kbytes
12 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
256 Kbytes
12 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
20 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
320 Kbytes
16 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
24 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
31 Kbytes
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
As of Dec. 2005
(1)
Page 7 of 96
Remarks
Mask ROM version
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.5
1. Overview
Product List (2) (M16C/62P)
Type No.
M30622MHP-XXXFP
M30622MHP-XXXGP
M30623MHP-XXXGP
M30624MHP-XXXFP
M30624MHP-XXXGP
M30625MHP-XXXGP
M30626MHP-XXXFP
M30626MHP-XXXGP
M30627MHP-XXXGP
M30626MJP-XXXFP
M30626MJP-XXXGP
M30627MJP-XXXGP
M30622F8PFP
M30622F8PGP
M30623F8PGP
M30620FCPFP
M30620FCPGP
M30621FCPGP
M3062LFGPFP(3)
M3062LFGPGP(3)
M30625FGPGP
M30626FHPFP
M30626FHPGP
M30627FHPGP
M30626FJPFP
M30626FJPGP
M30627FJPGP
M30622SPFP
M30622SPGP
M30620SPFP
M30620SPGP
M30624SPFP
M30624SPGP
M30626SPFP
M30626SPGP
ROM Capacity
384 Kbytes
As of Dec. 2005
RAM
Capacity
16 Kbytes
24 Kbytes
31 Kbytes
(D) 512 Kbytes
(D)
(D)
64K+4 Kbytes
31 Kbytes
4 Kbytes
128K+4 Kbytes 10 Kbytes
(D) 256K+4 Kbytes 20 Kbytes
(D)
384K+4 Kbytes 31 Kbytes
512K+4 Kbytes 31 Kbytes
−
4 Kbytes
10 Kbytes
(D) −
(D)
(D)
(D)
20 Kbytes
31 Kbytes
Package Type (1)
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
Remarks
Mask ROM version
Flash memory
version (2)
ROM-less version
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
3. Please use M3062LFGPFP and M3062LFGPGP for your new system instead of M30624FGPFP
and M30624FGPGP. The M16C/62P Group (M16C/62P, M16C/62PT) hardware manual is still good
for M30624FGPFP and M30624FGPGP.
M30624FGPFP
M30624FGPGP
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
256K+4 Kbytes 20 Kbytes
Page 8 of 96
PRQP0100JB-A Flash memory version
PLQP0100KB-A
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.6
1. Overview
Product List (3) (T version (M16C/62PT))
Type No.
M3062CM6T-XXXFP
M3062CM6T-XXXGP
M3062EM6T-XXXGP
M3062CM8T-XXXFP
M3062CM8T-XXXGP
M3062EM8T-XXXGP
M3062CMAT-XXXFP
M3062CMAT-XXXGP
M3062EMAT-XXXGP
M3062AMCT-XXXFP
M3062AMCT-XXXGP
M3062BMCT-XXXGP
M3062CF8TFP
M3062CF8TGP
M3062AFCTFP
M3062AFCTGP
M3062BFCTGP
M3062JFHTFP
M3062JFHTGP
RAM
Package Type (1)
Capacity
(D) 48 Kbytes
4 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 64 Kbytes
4 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 96 Kbytes
5 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 128 Kbytes
10 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 64 K+4 Kbytes 4 Kbytes PRQP0100JB-A
PLQP0100KB-A
(D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
ROM Capacity
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 9 of 96
As of Dec. 2005
Remarks
Mask ROM T Version
version
(High reliability
85°C version)
Flash
memory
version (2)
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.7
1. Overview
Product List (4) (V version (M16C/62PT))
Type No.
M3062CM6V-XXXFP
M3062CM6V-XXXGP
M3062EM6V-XXXGP
M3062CM8V-XXXFP
M3062CM8V-XXXGP
M3062EM8V-XXXGP
M3062CMAV-XXXFP
M3062CMAV-XXXGP
M3062EMAV-XXXGP
M3062AMCV-XXXFP
M3062AMCV-XXXGP
M3062BMCV-XXXGP
M3062AFCVFP
M3062AFCVGP
M3062BFCVGP
M3062JFHVFP
M3062JFHVGP
RAM
Package Type(1)
Capacity
(P) 48 Kbytes
4 Kbytes PRQP0100JB-A
(P)
PLQP0100KB-A
(P)
PRQP0080JA-A
(P) 64 Kbytes
4 Kbytes PRQP0100JB-A
(P)
PLQP0100KB-A
(P)
PRQP0080JA-A
(P) 96 Kbytes
5 Kbytes PRQP0100JB-A
(P)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 128 Kbytes
10 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A
(D)
PLQP0100KB-A
(P)
PRQP0080JA-A
(P) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
(P)
PLQP0100KB-A
ROM Capacity
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 10 of 96
As of Dec. 2005
Remarks
Mask ROM V Version
version
(High reliability
125°C version)
Flash
memory
version (2)
M16C/62P Group (M16C/62P, M16C/62PT)
Type No.
1. Overview
M3062 6 MH P - XXX FP
Package type:
FP : Package
GP : Package
PRQP0100JB-A (100P6S-A)
PRQP0080JA-A (80P6S-A),
PLQP0100KB-A (100P6Q-A),
PLQP0128KB-A (128P6Q-A),
ROM No.
Omitted for flash memory version and
ROMless version
Classification
P : M16C/62P
T : T version (M16C/62PT)
V : V version (M16C/62PT)
ROM capacity:
6: 48 Kbytes
8: 64 Kbytes
A: 96 Kbytes
C: 128 Kbytes
E: 192 Kbytes
G: 256 Kbytes
W: 320 Kbytes
H: 384 Kbytes
J: 512 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
S: ROM-less version
Shows RAM capacity, pin count, etc
Numeric, Alphabet (L) : M16C/62P
Alphabet (L is excluded.) : M16C/62PT
M16C/62(P) Group
M16C Family
Figure 1.3
Type No., Memory Size, and Package
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 11 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.8
Product Code of Flash Memory version and ROMless version for M16C/62P
Product
Code
Flash memory
Version
1. Overview
D3
D5
Package
Internal ROM
(User ROM Area Without Block A,
Block 1)
Program
and Erase
Endurance
Leadincluded
Temperature
Range
100
Internal ROM
(Block A, Block 1)
Program
and Erase
Endurance
0°C to 60°C
100
0°C to 60°C
1,000
10,000
D9
Lead-free
100
100
-40°C to 85°C
-40°C to 85°C
-20°C to 85°C
-20°C to 85°C
0°C to 60°C
-40°C to 85°C
U5
-20°C to 85°C
U7
1,000
10,000
U9
ROM-less
version
D3
D5
U3
-40°C to 85°C
-20°C to 85°C
D7
U3
Temperature
Range
Operating
Ambient
Temperature
Leadincluded
−
Lead-free
−
−
−
-40°C to 85°C
-40°C to 85°C
-20°C to 85°C
-20°C to 85°C
−
-40°C to 85°C
-20°C to 85°C
−
−
−
U5
-40°C to 85°C
-20°C to 85°C
M1 6 C
M3 0 6 2 6 F H P F P
B D5
XXXXXXX
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Chip version and product code
B : Shows chip version.
Henceforth, whenever it changes a version, it continues with B, C, and D.
D5 : Shows Product code. (See table 1.8 Product Code)
Date code seven digits
The product without marking of chip version of the flash memory version and the ROMless version
corresponds to the chip version “A”.
Figure 1.4
Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 12 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.9
Product Code of Flash Memory version for M16C/62PT
Product
Code
T Version
Flash
memory
Version
1. Overview
B
V Version
T Version
Package
Leadincluded
B7
Internal ROM
(User ROM Area
Without Block A, Block 1)
Program
and Erase
Endurance
100
Temperature
Range
0°C to 60°C
Internal ROM
(Block A, Block 1)
Program
and Erase
Endurance
100
0°C to 60°C
1,000
10,000
-40°C to 85°C
U
Lead-free
100
100
0°C to 60°C
U7
1,000
10,000
-40°C to 85°C
-40°C to 85°C
-40°C to 125°C -40°C to 125°C
M1 6 C
M3 0 6 2 J F H T F P
Y YY X X X X X X X
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Date code seven digits
Product code. (See table 1.9 Product Code)
“
” : Product code “B”
“ P B F ” : Product code “U”
“ B 7
” : Product code “B”
“ U 7
” : Product code “U7”
NOTES:
1.
: Blank
Marking Diagram of Flash Memory version for M16C/62PT (Top View)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
-40°C to 85°C
-40°C to 125°C
V Version
Figure 1.5
-40°C to 85°C
-40°C to 125°C -40°C to 125°C
V Version
T Version
-40°C to 85°C
-40°C to 125°C
V Version
T Version
Temperature
Range
Operating
Ambient
Temperature
Page 13 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1.5
1. Overview
Pin Configuration
Figures 1.6 to 1.9 show the Pin Configuration (Top View).
102 101 100
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
VSS
P3_0/A8(/-/D7)
VCC2
P12_0
P12_1
P12_2
P12_3
P12_4
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P1_1/D9
P1_2/D10
PIN CONFIGURATION (top view)
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
103
104
63
<VCC2> (2)
105
106
62
61
60
59
107
108
109
110
58
57
56
55
54
53
111
112
113
114
M16C/62P Group (M16C/62P)
115
116
52
51
50
49
48
47
117
118
119
120
121
46
45
44
122
123
43
42
41
124
125
126
127
<VCC1> (2)
40
39
128
P12_5
P12_6
P12_7
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P13_0
P13_1
P13_2
P13_3
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P13_4
P13_5
P13_6
P13_7
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
VSS
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/TA0OUT (1)
P6_7/TXD1/SDA1
VCC1
P6_6/RXD1/SCL1
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN
P7_6/TA3OUT
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
P14_1
P14_0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Package : PLQP0128KB-A (128P6Q-A)
Figure 1.6
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 14 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.10
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
1. Overview
Pin Characteristics for 128-Pin Package (1)
Control Pin
Port
Interrupt Pin
Timer Pin
P9_7
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
P14_1
P14_0
BYTE
CNVSS
XCIN
XCOUT
SIN4
SOUT4
CLK4
TB4IN
TB3IN
TB2IN
TB1IN
TB0IN
P8_5
NMI
P8_4
INT2
24
P8_3
INT1
25
P8_2
INT0
26
P8_1
P8_0
P7_7
P7_6
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
P7_5
P7_4
TA2IN/W
TA2OUT/W
P7_3
P7_2
P7_1
P7_0
P6_7
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
27
28
29
30
31
32
ZP
CTS2/RTS2
CLK2
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
VCC1
P6_6
RXD1/SCL1
VSS
P6_5
CLK1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
P6_0
P13_7
P13_6
P13_5
P13_4
CTS0/RTS0
46
47
48
49
50
P5_7
45
ADTRG
ANEX1
ANEX0
DA1
DA0
SOUT3
SIN3
CLK3
P6_4
P6_3
P6_2
P6_1
42
43
44
Bus Control Pin
RESET
XOUT
VSS
XIN
VCC1
23
41
Analog Pin
P8_7
P8_6
22
33
34
35
36
37
38
39
40
UART Pin
VREF
AVCC
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 15 of 96
RDY/CLKOUT
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.11
Pin No.
1. Overview
Pin Characteristics for 128-Pin Package (2)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
51
P5_6
ALE
52
P5_5
HOLD
53
HLDA
54
55
56
57
58
P5_4
P13_3
P13_2
P13_1
P13_0
P5_3
59
P5_2
RD
60
P5_1
WRH/BHE
61
WRL/WR
62
63
64
P5_0
P12_7
P12_6
P12_5
65
P4_7
CS3
66
P4_6
CS2
67
P4_5
CS1
68
P4_4
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
CS0
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
P3_0
A8(/-/D7)
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
BCLK
VCC2
VSS
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
96
P1_7
INT5
D15
97
P1_6
INT4
D14
98
99
100
P1_5
P1_4
P1_3
INT3
D13
D12
D11
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 16 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.12
Pin No.
1. Overview
Pin Characteristics for 128-Pin Package (3)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
120
P10_7
KI3
AN7
121
P10_6
KI2
AN6
122
P10_5
KI1
AN5
123
124
125
126
127
128
P10_4
P10_3
P10_2
P10_1
KI0
AN4
AN3
AN2
AN1
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
AVSS
P10_0
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 17 of 96
AN0
Bus Control Pin
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
P1_0/D8
P1_1/D9
P1_2/D10
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
VSS
P3_0/A8(/-/D7)
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
PIN CONFIGURATION (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
50
49
48
47
46
45
44
43
<VCC2> (2)
M16C/62P Group
(M16C/62P, M16C/62PT)
<VCC1> (2)
100
42
41
40
39
38
37
36
35
34
33
32
31
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN
P7_6/TA3OUT
P7_5/TA2IN/W
P7_4/TA2OUT/W
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/TA0OUT (1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
Package : PRQP0100JB-A (100P6S-A)
Figure 1.7
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 18 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
P1_3/D11
P1_4/D12
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
VSS
P3_0/A8(/-/D7)
VCC2
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
PIN CONFIGURATION (top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P1_2/D10
P1_1/D9
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
76
77
78
50
49
48
47
<VCC2> (2)
79
80
81
46
45
44
82
83
84
85
43
42
41
40
86
87
88
89
M16C/62P Group
(M16C/62P, M16C/62PT)
39
38
92
93
37
36
35
34
33
94
95
96
32
31
30
90
91
29
97
98
99
28
27
<VCC1> (2)
26
100
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT (1)
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_2/CLK2/TA1OUT/V
P7_3/CTS2/RTS2/TA1IN/V
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
P8_5/NMI
P8_4/INT2/ZP
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U
P8_0/TA4OUT/U
P7_7/TA3IN
P7_6/TA3OUT
P7_5/TA2IN/W
P7_4/TA2OUT/W
P9_4/DA1/TB4IN
P9_3/DA0/TB3IN
P9_2/TB2IN/SOUT3
P9_1/TB1IN/SIN3
P9_0/TB0IN/CLK3
BYTE
CNVSS
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
VSS
XIN
VCC1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Package : PLQP0100KB-A (100P6Q-A)
Figure 1.8
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 19 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.13
1. Overview
Pin Characteristics for 100-Pin Package (1)
Pin No.
Control Pin
FP GP
Port
Interrupt Pin
Timer Pin
1
2
99
100
P9_6
P9_5
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
P9_4
TB4IN
P9_3
P9_2
P9_1
P9_0
TB3IN
TB2IN
TB1IN
TB0IN
12
13
14
15
16
10 RESET
11 XOUT
12 VSS
13 XIN
14 VCC1
17
15
P8_5
NMI
18
16
P8_4
INT2
19
17
P8_3
INT1
20
18
P8_2
INT0
21
19
22
23
24
20
21
22
P8_1
P8_0
P7_7
P7_6
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
25
23
26
24
P7_5
P7_4
TA2IN/W
TA2OUT/W
27
25
28
29
30
31
32
33
26
27
28
29
30
31
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
TA1IN/V
TA1OUT/V
TA0IN/TB5IN
TA0OUT
BYTE
CNVSS
XCIN
XCOUT
UART Pin
SOUT4
CLK4
Analog Pin
Bus Control Pin
ANEX1
ANEX0
DA1
DA0
SOUT3
SIN3
CLK3
P8_7
P8_6
ZP
CTS2/RTS2
CLK2
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
34
32
35
33
P6_4
P6_3
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
36
34
P6_2
RXD0/SCL0
37
35
P6_1
CLK0
38
36
P6_0
CTS0/RTS0
39
37
P5_7
RDY/CLKOUT
40
38
P5_6
ALE
41
39
P5_5
HOLD
42
40
43
41
P5_4
P5_3
HLAD
BCLK
44
42
P5_2
RD
45
43
P5_1
WRH/BHE
46
44
P5_0
WRL/WR
47
45
P4_7
CS3
48
46
P4_6
CS2
49
47
P4_5
CS1
50
48
P4_4
CS0
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 20 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.14
1. Overview
Pin Characteristics for 100-Pin Package (2)
Pin No.
Control Pin
FP GP
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
Bus Control Pin
51
52
49
50
P4_3
P4_2
A19
A18
53
54
51
P4_1
A17
52
P4_0
A16
P3_7
A15
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
53
54
55
56
57
58
59
60 VCC2
61
62 VSS
63
64
65
66
67
68
69
70
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A14
A13
A12
A11
A10
A9
P3_0
A8(/-/D7)
73
71
P1_7
INT5
D15
74
72
P1_6
INT4
D14
75
73
INT3
76
77
74
75
P1_5
P1_4
P1_3
D13
D12
D11
78
76
P1_2
D10
79
77
P1_1
D9
80
78
P1_0
81
82
83
84
85
79
80
81
82
83
P0_7
P0_6
P0_5
P0_4
P0_3
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
D7
D6
D5
D4
D3
86
84
P0_2
AN0_2
D2
87
88
85
86
P0_1
P0_0
AN0_1
AN0_0
D1
D0
89
87
P10_7
KI3
AN7
90
88
P10_6
KI2
AN6
91
89
P10_5
KI1
AN5
92
90
91
92
93
94 AVSS
95
P10_4
P10_3
P10_2
P10_1
KI0
93
94
95
96
97
AN4
AN3
AN2
AN1
98
96 VREF
99
97 AVCC
100
98
55
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
AN2_7
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
D8
P10_0
P9_7
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
Page 21 of 96
AN0
SIN4
ADTRG
M16C/62P Group (M16C/62P, M16C/62PT)
1. Overview
P4_1
P4_2
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P2_7/AN2_7
P3_0
P2_6/AN2_6
P2_5/AN2_5
P2_4/AN2_4
P2_3/AN2_3
P2_2/AN2_2
P2_1/AN2_1
P2_0/AN2_0
P0_7/AN0_7
PIN CONFIGURATION (top view)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
61
40
P4_3
62
39
63
38
64
37
65
36
66
35
67
34
68
33
72
29
73
28
74
27
75
26
76
25
77
24
78
23
P9_7/ADTRG/SIN4
79
22
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
P5_6
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT (1)
P7_1/RXD2/SCL2/TA0IN/TB5IN
P9_6/ANEX1/SOUT4
80
21
P7_6/TA3OUT
69
32
M16C/62P Group
(M16C/62P, M16C/62PT)
(1)
P7_7/TA3IN
P8_0/TA4OUT
P8_1/TA4IN
P8_2/INT0
P8_3/INT1
P9_0/TB0IN/CLK3
CNVSS(BYTE)
9 10 11 12 13 14 15 16 17 18 19 20
P8_4/INT2/ZP
P9_2/TB2IN/SOUT3
8
P8_5/NMI
P9_3/DA0/TB3IN
7
VCC1
P9_4/DA1/TB4IN
6
XIN
5
VSS
4
XOUT
3
30
RESET
2
31
P8_6/XCOUT
1
P9_5/ANEX0/CLK4
71
P8_7/XCIN
70
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
Package : PRQP0080JA-A (80P6S-A)
Figure 1.9
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 22 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.15
Pin No.
1. Overview
Pin Characteristics for 80-Pin Package (1)
Control Pin
Port
Interrupt Pin
Timer Pin
1
2
P9_5
P9_4
3
4
5
P9_3
TB3IN
P9_2
P9_0
TB2IN
TB0IN
6
7
8
9
10
11
12
13
CNVSS
(BYTE)
XCIN
XCOUT
TB4IN
Analog Pin
Bus Control Pin
ANEX0
DA1
DA0
SOUT3
CLK3
P8_7
P8_6
RESET
XOUT
VSS
XIN
VCC1
14
P8_5
NMI
15
P8_4
INT2
16
P8_3
INT1
17
P8_2
INT0
18
P8_1
P8_0
19
UART Pin
CLK4
ZP
TA4IN
TA4OUT
20
P7_7
TA3IN
21
22
23
24
25
26
P7_6
P7_1
P7_0
P6_7
P6_6
P6_5
TA3OUT
TA0IN/TB5IN
TA0OUT
27
28
29
30
P6_4
P6_3
P6_2
P6_1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
31
P6_0
CTS0/RTS0
32
P5_7
33
P5_6
34
P5_5
35
36
P5_4
P5_3
37
P5_2
38
P5_1
39
P5_0
40
P4_3
41
P4_2
42
P4_1
43
P4_0
44
P3_7
45
P3_6
46
P3_5
47
P3_4
48
P3_3
49
P3_2
50
P3_1
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 23 of 96
RXD2/SCL2
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
CLKOUT
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.16
Pin No.
1. Overview
Pin Characteristics for 80-Pin Package (2)
Control Pin
Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
51
52
P3_0
P2_7
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
P2_6
AN2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
68
P10_7
KI3
AN7
69
P10_6
KI2
AN6
70
P10_5
KI1
AN5
71
KI0
72
P10_4
P10_3
AN4
AN3
73
P10_2
AN2
P10_1
AN1
P10_0
AN0
74
75
AN2_7
AVSS
76
77
VREF
78
AVCC
79
P9_7
SIN4
ADTRG
80
P9_6
SOUT4
ANEX1
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 24 of 96
Bus Control Pin
M16C/62P Group (M16C/62P, M16C/62PT)
1.6
1. Overview
Pin Description
Table 1.17
Signal Name
Power supply
input
Analog power
supply input
Reset input
Pin Description (100-pin and 128-pin Version) (1)
Pin Name
VCC1,VCC2
VSS
AVCC
AVSS
I/O
Power
Description
Type Supply(3)
I
−
Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 ≥ VCC2. (1, 2)
I
VCC1 Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
RESET
CNVSS
I
I
VCC1
VCC1
External data
bus width
select input
BYTE
I
VCC1
Bus control
pins (4)
D0 to D7
I/O
VCC2
D8 to D15
I/O
VCC2
A0 to A19
A0/D0 to
A7/D7
A1/D0 to
A8/D7
O
I/O
VCC2
VCC2
I/O
VCC2
CS0 to CS3
O
VCC2
Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
WRL/WR
WRH/BHE
RD
O
VCC2
ALE
O
VCC2
Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
BHE and WR can be switched by program.
• WRL, WRH and RD are selected
The WRL signal becomes "L" by writing data to an even address in
an external memory space.
The WRH signal becomes "L" by writing data to an odd address in
an external memory space.
The RD pin signal becomes "L" by reading data in an external
memory space.
• WR, BHE and RD are selected
The WR signal becomes "L" by writing data in an external memory space.
The RD signal becomes "L" by reading data in an external memory space.
The BHE signal becomes "L" by accessing an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
ALE is a signal to latch the address.
HOLD
I
VCC2
While the HOLD pin is held "L", the microcomputer is placed in a
hold state.
HLDA
O
VCC2
In a hold state, HLDA outputs a "L" signal.
RDY
I
VCC2
While applying a "L" signal to the RDY pin, the microcomputer is
placed in a wait state.
CNVSS
The microcomputer is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode.
Switches the data bus in external memory space. The data bus is
16 bits long when the this pin is held "L" and 8 bits long when the
this pin is held "H". Set it to either one. Connect this pin to VSS
when an single-chip mode.
Inputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
Inputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
Output address bits (A0 to A19).
Input and output data (D0 to D7) and output address bits (A0 to A7) by
timesharing when external 8-bit data bus are set as the multiplexed bus.
Input and output data (D0 to D7) and output address bits (A1 to A8)
by timesharing when external 16-bit data bus are set as the
multiplexed bus.
I : Input O : Output I/O : Input and output
Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be
interfaced using the different voltage as VCC1.
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2.
3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
4. Bus control pins in M16C/62PT cannot be used.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 25 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.18
Signal Name
Main clock
input
Main clock
output
Sub clock input
Sub clock
output
BCLK output (2)
Clock output
1. Overview
Pin Description (100-pin and 128-pin Version) (2)
Pin Name
XIN
XOUT
I/O
Power
Description
Type Supply(1)
I
VCC1 I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (3). To use
O
VCC1 the external clock, input the clock from XIN and leave XOUT open.
XCIN
XCOUT
I
O
VCC1
VCC1
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT (3). To use the external clock,
input the clock from XCIN and leave XCOUT open.
BCLK
CLKOUT
VCC2
VCC2
Outputs the BCLK signal.
The clock of the same cycle as fC, f8, or f32 is outputted.
VCC1
Input pins for the INT interrupt.
INT interrupt
input
INT0 to INT2
O
O
I
NT3 to INT5
I
VCC2
NMI interrupt
input
Key input
interrupt input
Timer A
NMI
I
VCC1
KI0 to KI3
I
VCC1
I/O
VCC1
I
VCC1
These are timer A0 to timer A4 I/O pins. (however, output of
TA0OUT for the N-channel open drain output.)
These are timer A0 to timer A4 input pins.
I
I
VCC1
VCC1
Input pin for the Z-phase.
These are timer B0 to timer B5 input pins.
O
VCC1
These are Three-phase motor control output pins.
I
VCC1
These are send control input pins.
O
VCC1
These are receive control output pins.
I/O
VCC1
These are transfer clock I/O pins.
I
VCC1
These are serial data input pins.
I
O
VCC1
VCC1
O
VCC1
These are serial data input pins.
These are serial data output pins. (however, output of TXD2 for the
N-channel open drain output.)
These are serial data output pins.
O
VCC1
I/O
VCC1
I/O
VCC1
Timer B
TA0OUT to
TA4OUT
TA0IN to
TA4IN
ZP
TB0IN to
TB5IN
Three-phase
U, U, V, V,
motor control
W, W
output
Serial interface CTS0 to
CTS2
RTS0 to
RTS2
CLK0 to
CLK4
RXD0 to
RXD2
SIN3, SIN4
TXD0 to
TXD2
SOUT3,
SOUT4
CLKS1
I2C mode
I : Input
SDA0 to
SDA2
SCL0 to
SCL2
O : Output
Input pin for the NMI interrupt. Pin states can be read by the P8_5
bit in the P8 register.
Input pins for the key input interrupt.
This is output pin for transfer clock output from multiple pins
function.
These are serial data I/O pins. (however, output of SDA2 for the Nchannel open drain output.)
These are transfer clock I/O pins. (however, output of SCL2 for the
N-channel open drain output.)
I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. This pin function in M16C/62PT cannot be used.
3. Ask the oscillator maker the oscillation characteristic.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 26 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.19
Signal Name
Reference
voltage input
A/D converter
Pin Description (100-pin and 128-pin Version) (3)
Pin Name
VREF
AN0 to AN7,
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
ADTRG
ANEX0
D/A converter
I/O port
Input port
I : Input
1. Overview
ANEX1
DA0, DA1
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P12_0 to
P12_7 (2),
P13_0 to
P13_7 (2)
P6_0 to P6_7,
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to
P10_7,
P11_0 to
P11_7 (2)
P8_0 to P8_4,
P8_6, P8_7,
P14_0,
P14_1(2)
P8_5
O : Output
I/O
Power
Description
Type Supply(1)
I
VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
I
VCC1 Analog input pins for the A/D converter.
I
VCC1
This is an A/D trigger input pin.
I/O
VCC1
I
O
I/O
VCC1
VCC1
VCC2
This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
This is the output pin for the D/A converter.
8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
I/O
VCC1
8-bit I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
I/O
VCC1
I/O ports having equivalent functions to P0.
I
VCC1
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. Ports P11 to P14 in M16C/62P (100-pin version) and M16C/62PT (100-pin version) cannot be used.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 27 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.20
Signal Name
Power supply
input
Analog power
supply input
Reset input
CNVSS
Main clock
input
Main clock
output
Sub clock input
Sub clock
output
Clock output
1. Overview
Pin Description (80-pin Version) (1) (1)
Pin Name
I/O
Type
I
Power
Supply
−
AVCC
AVSS
I
VCC1
Applies the power supply for the A/D converter. Connect the
AVCC pin to VCC1. Connect the AVSS pin to VSS.
RESET
CNVSS
(BYTE)
I
I
VCC1
VCC1
XIN
I
VCC1
XOUT
O
VCC1
The microcomputer is in a reset state when applying “L” to the this pin.
Switches processor mode. Connect this pin to VSS to when after a
reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode. As for the BYTE pin of the 80-pin
versions, pull-up processing is performed within the microcomputer.
I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (3). To use
the external clock, input the clock from XIN and leave XOUT
open.
XCIN
XCOUT
I
O
VCC1
VCC1
I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT (3). To use the external
clock, input the clock from XCIN and leave XCOUT open.
CLKOUT
VCC2
The clock of the same cycle as fC, f8, or f32 is outputted.
VCC1
Input pins for the INT interrupt.
VCC1, VSS
Description
Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. (1, 2)
INT interrupt
input
INT0 to INT2
O
I
NMI interrupt
input
Key input
interrupt input
Timer A
NMI
I
VCC1
Input pin for the NMI interrupt.
KI0 to KI3
I
VCC1
Input pins for the key input interrupt.
I/O
VCC1
These are Timer A0,Timer A3 and Timer A4 I/O pins. (however,
output of TA0OUT for the N-channel open drain output.)
I
VCC1
These are Timer A0, Timer A3 and Timer A4 input pins.
I
I
VCC1
VCC1
Input pin for the Z-phase.
These are Timer B0, Timer B2 to Timer B5 input pins.
Serial interface CTS0 to CTS1
I
VCC1
These are send control input pins.
RTS0 to RTS1
CLK0, CLK1,
CLK3, CLK4
RXD0 to RXD2
SIN4
TXD0 to TXD2
O
VCC1
These are receive control output pins.
I/O
VCC1
These are transfer clock I/O pins.
I
I
O
VCC1
VCC1
VCC1
These are serial data input pins.
This is serial data input pin.
These are serial data output pins. (however, output of TXD2 for
the N-channel open drain output.)
These are serial data output pins.
Timer B
I2C mode
I : Input
TA0OUT,
TA3OUT,
TA4OUT
TA0IN, TA3IN,
TA4IN
ZP
TB0IN, TB2IN
to TB5IN
SOUT3,
SOUT4
CLKS1
O
VCC1
O
VCC1
SDA0 to SDA2
I/O
VCC1
SCL0 to SCL2
I/O
VCC1
O : Output
This is output pin for transfer clock output from multiple pins
function.
These are serial data I/O pins. (however, output of SDA2 for the
N-channel open drain output.)
These are transfer clock I/O pins. (however, output of SCL2 for
the N-channel open drain output.)
I/O : Input and output
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin.
3. Ask the oscillator maker the oscillation characteristic.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 28 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 1.21
Signal Name
Reference
voltage input
A/D converter
Pin Description (80-pin Version) (2)
Pin Name
VREF
AN0 to AN7,
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
ADTRG
ANEX0
D/A converter
I/O port (1)
Input port
I : Input
1. Overview
ANEX1
DA0, DA1
P0_0 to P0_7,
P2_0 to P2_7,
P3_0 to P3_7,
P5_0 to P5_7,
P6_0 to P6_7,
P10_0 to
P10_7
P8_0 to P8_4,
P8_6, P8_7,
P9_0,
P9_2 to P9_7
P4_0 to P4_3,
P7_0, P7_1,
P7_6, P7_7
P8_5
O : Output
I/O
Power
Description
Type Supply(1)
I
VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
I
VCC1 Analog input pins for the A/D converter.
I
VCC1
This is an A/D trigger input pin.
I/O
VCC1
I
O
I/O
VCC1
VCC1
VCC1
This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
This is the output pin for the D/A converter.
8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
I/O
VCC1
I/O ports having equivalent functions to P0.
I/O
VCC1
I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
I
VCC1
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I/O : Input and output
NOTES:
1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the
direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 29 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
b15
b8 b7
R2
R0H
R3
R1H
b0
R0L
R1L
Data Registers (1)
R2
R3
A0
Address Registers (1)
A1
FB
b19
b15
Frame Base Registers (1)
b0
INTBH
Interrupt Table Register
INTBL
b19
b0
Program Counter
PC
b15
b0
USP
User Stack Pointer
ISP
Interrupt Stack Pointer
SB
Static Base Register
b15
b0
FLG
b15
b8
IPL
b7
U I
Flag Register
b0
O B S Z D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTES:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
2.1
Central Processing Unit Register
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 30 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
2.2
2. Central Processing Unit (CPU)
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative
addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1
Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3
Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4
Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6
Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7
Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 31 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
2.8.8
2. Central Processing Unit (CPU)
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0
to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10
Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 32 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
3.
3. Memory
Memory
Figure 3.1 is a Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for
storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte
internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated.
The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here.
Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users.
Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expansion and microprocessor
modes cannot be used
.
00000h
SFR
00400h
Internal RAM
XXXXXh
Reserved area (1)
FFE00h
0F000h
Internal ROM
(data area) (3)
0FFFFh
Special page
vector table
10000h
Internal RAM
Internal ROM
(3)
Address XXXXXh
Size
Address YYYYYh
4 Kbytes
013FFh
48 Kbytes
F4000h
5 Kbytes
017FFh
64 Kbytes
F0000h
10 Kbytes
02BFFh
96 Kbytes
E8000h
12 Kbytes
033FFh
128 Kbytes
E0000h
16 Kbytes
043FFh
192 Kbytes
D0000h
20 Kbytes
053FFh
256 Kbytes
C0000h
24 Kbytes
063FFh
320 Kbytes
B0000h
31 Kbytes
07FFFh
384 Kbytes
A0000h
512 Kbytes
80000h
Size
External area
27000h
Reserved area
Memory Map
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 33 of 96
Overflow
External area
80000h
Reserved area (2)
YYYYYh
Internal ROM
(program area) (5)
FFFFFh
NOTES:
1. During memory expansion and microprocessor modes, can be used.
2. In memory expansion mode, can be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1”
and the PM13 bit in the PM1 register is “1”.
5. When using the masked ROM version, write nothing to internal ROM area.
Figure 3.1
FFFDCh Undefined instruction
28000h
FFFFFh
BRK instruction
Address match
Single step
Watchdog timer
DBC
NMI
Reset
M16C/62P Group (M16C/62P, M16C/62PT)
4.
4. Special Function Register (SFR)
Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR
information.
Table 4.1
SFR Information (1) (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
NOTES:
1.
2.
3.
4.
5.
6.
Register
Symbol
After Reset
Processor Mode Register 0 (2)
PM0
00000000b(CNVSS pin is “L”)
00000011b(CNVSS pin is “H”)
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register (6)
Address Match Interrupt Enable Register
Protect Register
Data Bank Register (6)
Oscillation Stop Detection Register (3)
PM1
CM0
CM1
CSR
AIER
PRCR
DBR
CM2
00001000b
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
00h
0X000000b
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
WDTS
WDC
RMAD0
XXh
00XXXXXXb (4)
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
Voltage Detection Register 1 (5, 6)
Voltage Detection Register 2 (5, 6)
Chip Select Expansion Control Register (6)
PLL Control Register 0
VCR1
VCR2
CSE
PLC0
00001000b
00h
00h
0001X010b
Processor Mode Register 2
Low Voltage Detection Interrupt Register (6)
DMA0 Source Pointer
PM2
D4INT
SAR0
XXX00000b
00h
XXh
XXh
XXh
DMA0 Destination Pointer
DAR0
XXh
XXh
XXh
DMA0 Transfer Counter
TCR0
XXh
XXh
DMA0 Control Register
DM0CON
00000X00b
DMA1 Source Pointer
SAR1
XXh
XXh
XXh
DMA1 Destination Pointer
DAR1
XXh
XXh
XXh
DMA1 Transfer Counter
TCR1
XXh
XXh
DMA1 Control Register
DM1CON
00000X00b
The blank areas are reserved and cannot be accessed by users.
The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
The WDC5 bit is “0” (cold start) immediately after power-on. I t can only be set to “1” in a program.
This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
This register in M16C/62PT cannot be used.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 34 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.2
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
4. Special Function Register (SFR)
SFR Information (2) (1)
Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register, UART0 BUS Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register, INT5 Interrupt Control Register
SI/O3 Interrupt Control Register, INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
DMA1 Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
INT2 Interrupt Control Register
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 35 of 96
Symbol
INT3IC
TB5IC
TB4IC, U1BCNIC
TB3IC, U0BCNIC
S4IC, INT5IC
S3IC, INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
After Reset
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
to
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01C0h
to
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
to
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
4. Special Function Register (SFR)
SFR Information (3) (1)
Register
Symbol
After Reset
Flash Identification Register (2)
Flash Memory Control Register 1 (2)
FIDR
FMR1
XXXXXX00b
0X00XX0Xb
Flash Memory Control Register 0 (2)
Address Match Interrupt Register 2
FMR0
RMAD2
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 3
AIER2
RMAD3
00000001b
00h
00h
XXh
XXXXXX00b
00h
00h
XXh
Peripheral Clock Select Register
PCLKR
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. This register is included in the flash memory version.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 36 of 96
00000011b
M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.4
Address
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
4. Special Function Register (SFR)
SFR Information (4) (1)
Register
Symbol
After Reset
000XXXXXb
Timer B3, 4, 5 Count Start Flag
TBSR
Timer A1-1 Register
TA11
Timer A2-1 Register
TA21
Timer A4-1 Register
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Occurrence Frequency Set Counter
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
Timer B3 Register
TB3
Timer B4 Register
TB4
Timer B5 Register
TB5
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Factor Select Register 2
Interrupt Factor Select Register
SI/O3 Transmit/Receive Register
TB3MR
TB4MR
TB5MR
IFSR2A
IFSR
S3TRR
00XX0000b
00XX0000b
00XX0000b
00XXXXXXb
00h
XXh
SI/O3 Control Register
SI/O3 Bit Rate Generator
SI/O4 Transmit/Receive Register
S3C
S3BRG
S4TRR
01000000b
XXh
XXh
SI/O4 Control Register
SI/O4 Bit Rate Generator
S4C
S4BRG
01000000b
XXh
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
UART2 Transmit Buffer Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 37 of 96
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.5
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
4. Special Function Register (SFR)
SFR Information (5) (1)
Count Start Flag
Clock Prescaler Reset Fag
One-Shot Start Flag
Trigger Select Register
Up-Down Flag
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After Reset
00h
0XXXXXXXb
00h
00h
00h (2)
Timer A0 Register
TA0
Timer A1 Register
TA1
Timer A2 Register
TA2
Timer A3 Register
TA3
Timer A4 Register
TA4
Timer B0 Register
TB0
Timer B1 Register
TB1
Timer B2 Register
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Generator
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Generator
UART1 Transmit Buffer Register
U1MR
U1BRG
U1TB
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
UART Transmit/Receive Control Register 2
UCON
00h
XXh
XXh
XXh
00001000b
00XX0010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00XX0010b
XXh
XXh
X0000000b
DMA0 Request Factor Select Register
DM0SL
00h
DMA1 Request Factor Select Register
DM1SL
00h
CRC Data Register
CRCD
CRC Input Register
CRCIN
XXh
XXh
XXh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 38 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 4.6
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
4. Special Function Register (SFR)
SFR Information (6) (1)
Register
Symbol
After Reset
A/D Register 0
AD0
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
D/A Register 0
ADCON0
ADCON1
DA0
00000XXXb
00h
00h
D/A Register 1
DA1
00h
D/A Control Register
DACON
00h
Port P14 Control Register (3)
Pull-Up Control Register 3 (3)
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register (3)
Port P10 Direction Register
Port P11 Direction Register (3)
Port P12 Register (3)
Port P13 Register (3)
Port P12 Direction Register (3)
Port P13 Direction Register (3)
Pull-Up Control Register 0
Pull-Up Control Register 1
PC14
PUR3
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
PUR0
PUR1
Pull-Up Control Register 2
Port Control Register
PUR2
PCR
XX00XXXXb
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00X00000b
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
00h
00000000b (2)
00000010b (2)
00h
00h
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. At hardware reset 1 or hardware reset 2, the register is as follows:
• “00000000b” where “L” is inputted to the CNVSS pin
• “00000010b” where “H” is inputted to the CNVSS pin
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode).
• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode).
3. These registers do not exist in M16C/62P (80-pin version), and M16C/62PT (80-pin version).
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 39 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5.
5. Electrical Characteristics
Electrical Characteristics
5.1
Electrical Characteristics (M16C/62P)
Table 5.1
Symbol
VCC1, VCC2
VCC2
AVCC
VI
VO
Pd
Topr
Tstg
Absolute Maximum Ratings
Parameter
Supply Voltage
Supply Voltage
Analog Supply Voltage
Input Voltage
RESET, CNVSS, BYTE,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
VREF, XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1
Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
XOUT
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1
Power Dissipation
Operating
When the Microcomputer is Operating
Ambient
Temperature
Flash Program Erase
Storage Temperature
Condition
VCC1=AVCC
VCC2
VCC1=AVCC
−40°C<Topr≤85°C
Rated Value
−0.3 to 6.5
−0.3 to VCC1+0.1
−0.3 to 6.5
−0.3 to VCC1+0.3 (1)
Unit
V
V
V
V
−0.3 to VCC2+0.3 (1)
V
−0.3 to 6.5
−0.3 to VCC1+0.3 (1)
V
V
−0.3 to VCC2+0.3 (1)
V
−0.3 to 6.5
V
mW
°C
300
−20 to 85 / −40 to 85
0 to 60
−65 to 150
°C
NOTES:
1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in
80-pin version.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 40 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.2
Recommended Operating Conditions (1) (1)
Symbol
VCC1, VCC2
AVCC
VSS
AVSS
VIH
VIL
5. Electrical Characteristics
Parameter
Supply Voltage (VCC1 ≥ VCC2)
Analog Supply Voltage
Supply Voltage
Analog Supply Voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
HIGH Input
P12_0 to P12_7, P13_0 to P13_7
Voltage
LOW Input
Voltage
Min.
2.7
Standard
Typ.
5.0
VCC1
0
0
Max.
5.5
Unit
0.8VCC2
VCC2
V
V
V
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0.8VCC2
VCC2
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
0.5VCC2
VCC2
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
0.8VCC1
VCC1
V
P7_0, P7_1
0.8VCC1
0
6.5
0.2VCC2
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0
0.2VCC2
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
0
0.16VCC2
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
0
0.2VCC
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH(peak)
HIGH Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
−10.0
mA
IOH(avg)
HIGH Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
−5.0
mA
IOL(peak)
LOW Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
10.0
mA
IOL(avg)
LOW Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
5.0
mA
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be 80mA max. The total IOL(peak)
for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2
must be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports
P6, P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P14_0, and P14_1 must be
−40mA max. Set Average Output Current to 1/2 of peak. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and
P14_1 must be −40mA max.
As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS.
4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 41 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Recommended Operating Conditions (2) (1)
Table 5.3
Symbol
Parameter
Main Clock Input Oscillation Frequency (2)
f(XIN)
Min.
0
0
VCC1=3.0V to 5.5V
VCC1=2.7V to 3.0V
f(XCIN)
f(Ring)
f(PLL)
Sub-Clock Oscillation Frequency
On-chip Oscillation Frequency
PLL Clock Oscillation Frequency (2)
0.5
10
10
VCC1=3.0V to 5.5V
VCC1=2.7V to 3.0V
f(BCLK)
tSU(PLL)
CPU Operation Clock
PLL Frequency Synthesizer Stabilization
Wait Time
Standard
Typ.
32.768
1
0
VCC1=5.5V
VCC1=3.0V
Max.
16
20×VCC1
−44
50
2
24
46.67×VCC1
−116
24
20
50
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. Relationship between main clock oscillation frequency, and supply voltage.
PLL clock oscillation frequency
f(PLL) operating maximum frequency [MHz]
f(XIN) operating maximum frequency [MHz]
Main clock input oscillation frequency
20 x VCC1-44MHz
16.0
10.0
0.0
2.7
3.0
VCC1[V] (main clock: no division)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 42 of 96
5.5
46.67 x VCC1-116MHz
24.0
10.0
0.0
2.7
3.0
VCC1[V] (PLL clock oscillation)
5.5
Unit
MHz
MHz
kHz
MHz
MHz
MHz
MHz
ms
ms
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.4
A/D Conversion Characteristics (1)
Symbol
−
INL
−
−
DNL
−
−
RLADDER
tCONV
tCONV
tSAMP
VREF
VIA
5. Electrical Characteristics
Parameter
Resolution
Integral Non-Linearity
Error
Absolute Accuracy
10bit
8bit
10bit
8bit
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
Gain Error
Ladder Resistance
10-bit Conversion Time, Sample & Hold
Available
8-bit Conversion Time, Sample & Hold
Available
Sampling Time
Reference Voltage
Analog Input Voltage
Measuring Condition
Min.
VREF=VCC1
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
5V
ANEX0, ANEX1 input
External operation amp
connection mode
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
3.3V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
VREF=VCC1=5V, 3.3V
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
VREF= AN0 to AN7 input,
VCC1
AN0_0 to AN0_7 input,
=3.3V AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
VREF=VCC1=5V, 3.3V
Standard
Typ.
Max.
10
±3
10
2.75
VREF=VCC1=5V, φAD=12MHz
2.33
0.25
2.0
0
Bits
LSB
±7
LSB
±5
LSB
±7
LSB
±2
±3
LSB
LSB
±7
LSB
±5
LSB
±7
LSB
±2
LSB
kΩ
LSB
LSB
LSB
kΩ
µs
3
VREF=VCC1
VREF=VCC1=5V, φAD=12MHz
Unit
±1
±3
±3
40
µs
µs
VCC1
VREF
V
V
NOTES:
1. Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. If VCC1 > VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into 10 MHz or less.
4. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 3.
When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 3.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 43 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.5
D/A Conversion Characteristics (1)
Symbol
−
−
tSU
RO
IVREF
5. Electrical Characteristics
Parameter
Resolution
Absolute Accuracy
Setup Time
Output Resistance
Reference Power Supply Input Current
Measuring Condition
Min.
4
(NOTE 2)
Standard
Typ.
10
Max.
8
1.0
3
20
1.5
Unit
Bits
%
µs
kΩ
mA
NOTES:
1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor
ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id
disconnected by the A/D control register.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 44 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.6
Flash Memory Version Electrical Characteristics (1) for 100 cycle products (D3, D5, U3,
U5)
Symbol
−
Parameter
Program and Erase Endurance (3)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
Block Erase Time
(VCC1=5.0V)
−
−
−
−
−
−
−
5. Electrical Characteristics
Min.
100
Table 5.7
−
−
tPS
−
200
200
4
4
4
4
4×n
15
10
Parameter
Program and Erase Endurance (3, 8, 9)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
Block Erase Time
(VCC1=5.0V)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
−
Max.
Unit
cycle
µs
µs
s
s
s
s
s
µs
year
Flash Memory Version Electrical Characteristics (6) for 10,000 cycle products (D7, D9,
U7, U9) (Block A and Block 1 (7))
Symbol
−
25
25
0.3
0.3
0.5
0.8
4-Kbyte block
8-Kbyte block
32-Kbyte block
64-Kbyte block
Erase All Unlocked Blocks Time (2)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
tPS
−
Standard
Typ.
Min.
10,000 (4)
Standard
Typ.
Max.
cycle
µs
µs
s
25
25
0.3
4-Kbyte block
15
10
Unit
µs
year
NOTES:
1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (D3, D5, U3, U5) unless otherwise specified.
2. n denotes the number of block erases.
3. Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times.
For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as
one program and erase endurance. Data cannot be written to the same address more than once without erasing the block.
(Rewrite prohibited)
4. Maximum number of E/W cycles for which operation is guaranteed.
5. Topr = -40 to 85 °C (D3, D7, U3, U7) / -20 to 85 °C (D5, D9, U5, U9).
6. Referenced to VCC1 = 4.5 to 5.5V, 3.0 to 3.6V at Topr = -40 to 85 °C (D7, U7) / -20 to 85 °C (D9, U9) unless otherwise specified.
7. Table 5.7 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 5.6.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to
unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For
example, an 8-word program can be written 256 times maximum before erase becomes necessary.
Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the
total number of times erasure is used.
9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command
at least three times until erase error disappears.
10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (D7, D9, U7 and U9).
11. Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Table 5.8
Flash Memory Version Program / Erase Voltage and Read Operation Voltage
Characteristics (at Topr = 0 to 60 °C(D3, D5, U3, U5), Topr = -40 to 85 °C(D7, U7) / Topr =
-20 to 85 °C(D9, U9))
Flash Program, Erase Voltage
VCC1 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 45 of 96
Flash Read Operation Voltage
VCC1=2.7 to 5.5 V
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.9
Low Voltage Detection Circuit Electrical Characteristics
Symbol
Vdet4
Vdet3
Vdet4-Vdet3
Vdet3s
Vdet3r
5. Electrical Characteristics
Parameter
Low Voltage Detection Voltage (1)
Reset Level Detection Voltage (1, 2)
Electric potential difference of Low Voltage
Detection and Reset Level Detection
Low Voltage Reset Retention Voltage
Low Voltage Reset Release Voltage (3)
Measuring Condition
VCC1=0.8V to 5.5V
Min.
3.3
2.2
0.3
2.2
Standard
Typ.
3.8
2.8
Max.
4.4
3.6
2.9
0.8
4.0
Unit
V
V
V
V
V
NOTES:
1. Vdet4 > Vdet3.
2. Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection
voltage, the microcomputer operates with f(BCLK) ≤ 10MHz.
3. Vdet3r > Vdet3 is not guaranteed.
4. The voltage detection circuit is designed to use when VCC1 is set to 5V.
Table 5.10
Power Supply Circuit Timing Characteristics
Symbol
td(P-R)
td(R-S)
td(W-S)
td(S-R)
td(E-A)
Parameter
Time for Internal Power Supply Stabilization
During Powering-On
STOP Release Time
Low Power Dissipation Mode Wait Mode
Release Time
Brown-out Detection Reset (Hardware Reset 2)
Release Wait Time
Low Voltage Detection Circuit Operation Start
Time
NOTES:
1. When VCC1 = 5V.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 46 of 96
Measuring Condition
Min.
Standard
Typ.
VCC1=2.7V to 5.5V
VCC1=Vdet3r to 5.5V
VCC1=2.7V to 5.5V
6 (1)
Max.
2
Unit
ms
150
150
µs
20
ms
20
µs
µs
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Recommended
operation voltage
td(P-R)
Time for Internal Power
Supply Stabilization During
Powering-On
VCC1
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
CPU clock
(a)
td(R-S)
(b)
td(W-S)
td(S-R)
Low Voltage Detection
Reset (Hardware Reset 2)
Release Wait Time
Vdet3r
VCC1
td(S-R)
CPU clock
td(E-A)
VC26, VC27
Low Voltage Detection Circuit
Operation Start Time
Low Voltage
Detection Circuit
Stop
Operate
td(E-A)
Figure 5.1
Power Supply Circuit Timing Diagram
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 47 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Table 5.11
Electrical Characteristics (1)
Symbol
VOH
VOH
(1)
Parameter
HIGH
Output
Voltage (3)
HIGH
Output
Voltage (3)
Measuring Condition
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOH=−5mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−5mA (2)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
VOH
HIGH Output Voltage
XOUT
HIGH Output Voltage
VOL
VOL
VOL
LOW
Output
Voltage (3)
LOW
Output
Voltage (3)
XCOUT
HIGHPOWER
IOH=−1mA
LOWPOWER
IOH=−0.5mA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
IOL=5mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=5mA (2)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOL=200µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=200µA (2)
LOW Output Voltage
Hysteresis
IOH=−200µA (2)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
XOUT
LOW Output Voltage
VT+-VT-
OH=−200µA
XCOUT
Min.
Standard
Typ.
Max.
VCC1−2.0
VCC1
VCC2−2.0
VCC2
VCC1−0.3
VCC1
Unit
V
V
VCC2−0.3
VCC2
VCC1−2.0
VCC1−2.0
VCC1
VCC1
2.5
1.6
V
V
2.0
V
2.0
0.45
V
0.45
HIGHPOWER
IOL=1mA
LOWPOWER
IOL=0.5mA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
2.0
2.0
0
0
V
V
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
0.2
1.0
V
0.2
2.5
V
5.0
µA
−5.0
µA
170
kΩ
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
VT+-VT-
Hysteresis
RESET
IIH
HIGH Input
Current (3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
VI=5V
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
IIL
LOW Input
Current (3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
VI=0V
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
RPULLUP Pull-Up
Resistance
(3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
VI=0V
30
50
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
RfXIN
RfXCIN
VRAM
1.5
15
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
At stop mode
2.0
MΩ
MΩ
V
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise
specified.
2. Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on VCC2 port
side.
3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 48 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.12
Electrical Characteristics (2) (1)
Symbol
ICC
5. Electrical Characteristics
Parameter
Measuring Condition
Power Supply Current
In single-chip
(VCC1=VCC2=4.0V to 5.5V) mode, the output
pins are open and
other pins are VSS
Mask ROM
f(BCLK)=24MHz
No division, PLL operation
No division,
On-chip oscillation
Flash
Memory
Flash Memory
Program
Flash Memory
Erase
Mask ROM
Flash Memory
Idet4
Idet3
(4)
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current (4)
Standard
Typ. Max.
14
20
1
Page 49 of 96
mA
mA
18
No division,
On-chip oscillation
1.8
mA
f(BCLK)=10MHz,
VCC1=5.0V
15
mA
f(BCLK)=10MHz,
VCC1=5.0V
25
mA
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
25
µA
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
25
µA
420
µA
On-chip oscillation,
Wait mode
50
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability High
7.5
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability Low
2.0
µA
Stop mode
Topr =25°C
0.8
3.0
µA
0.7
1.2
4
8
µA
27
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Unit
f(BCLK)=24MHz,
No division, PLL operation
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory (3)
Mask ROM
Flash Memory
Min.
mA
µA
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.13
External Clock Input (XIN input) (1)
Symbol
Parameter
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
External Clock Fall Time
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
62.5
25
25
Max.
15
15
Unit
ns
ns
ns
ns
ns
NOTES:
1. The condition is VCC1=VCC2=3.0 to 5.0V.
Table 5.14
Memory Expansion Mode and Microprocessor Mode
Symbol
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
Parameter
Data Input Access Time (for setting with no wait)
Data Input Access Time (for setting with wait)
Data Input Access Time (when accessing multiplex bus area)
Data Input Setup Time
RDY Input Setup Time
HOLD Input Setup Time
Data Input Hold Time
RDY Input Hold Time
HOLD Input Hold Time
Standard
Min.
Max.
(NOTE 1)
(NOTE 2)
(NOTE 3)
40
30
40
0
0
0
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 45 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 45 [ ns ]
f ( BCLK )
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x 10
------------------------------------- – 45 [ ns ]
f ( BCLK )
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
n is “2” for 2-wait setting, “3” for 3-wait setting.
Page 50 of 96
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.15
Timer A Input (Counter Input in Event Counter Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 5.16
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.17
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.18
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.19
Parameter
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Standard
Min.
400
200
200
Unit
ns
ns
ns
Standard
Min.
200
100
100
Max.
Unit
ns
ns
ns
Standard
Min.
100
100
Parameter
Max.
Unit
ns
ns
Standard
tc(UP)
TAiOUT Input Cycle Time
Min.
2000
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
1000
1000
400
400
Max.
Unit
ns
ns
ns
ns
ns
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Max.
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Table 5.20
ns
ns
ns
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
tw(TAH)
tw(TAL)
Unit
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Max.
Timer A Input (Gating Input in Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Standard
Min.
100
40
40
Parameter
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 51 of 96
Standard
Min.
800
200
200
Max.
Unit
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.21
Timer B Input (Counter Input in Event Counter Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Table 5.22
Parameter
TBiIN Input Cycle Time (counted on one edge)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
Table 5.23
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.24
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Standard
Min.
400
200
200
Parameter
tw(ADL)
ADTRG input LOW Pulse Width
125
Unit
ns
ns
ns
Max.
Unit
ns
ns
Serial Interface
Symbol
Parameter
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
RXDi Input Setup Time
RXDi Input Hold Time
Standard
Min.
200
100
100
Max.
80
0
70
90
Unit
ns
ns
ns
ns
ns
ns
ns
External Interrupt INTi Input
Symbol
tw(INL)
Max.
Standard
ADTRG Input Cycle Time
tw(INH)
Unit
ns
ns
ns
Standard
tc(AD)
Table 5.26
Max.
Min.
400
200
200
Min.
1000
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
ns
ns
ns
ns
ns
ns
A/D Trigger Input
Symbol
Table 5.25
Unit
Timer B Input (Pulse Width Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Max.
Timer B Input (Pulse Period Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Standard
Min.
100
40
40
200
80
80
Parameter
Standard
INTi Input HIGH Pulse Width
Min.
250
INTi Input LOW Pulse Width
250
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 52 of 96
Max.
Unit
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.27
Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Parameter
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR) (3)
HLDA Output Delay Time
See
Figure 5.2
Standard
Min.
Max.
25
4
0
(NOTE 2)
25
4
15
−4
25
0
25
0
40
4
(NOTE 1)
(NOTE 2)
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
f(BCLK) is 12.5MHz or less.
------------------------ – 40 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2)
= 6.7ns.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 5.2
Ports P0 to P14 Measurement Circuit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 53 of 96
R
DBi
C
30pF
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.28
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol
Standard
Min.
Max.
25
4
0
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)(3)
HLDA Output Delay Time
Unit
ns
ns
ns
(NOTE 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
4
15
See
Figure 5.2
-4
25
0
25
0
40
4
(NOTE 1)
(NOTE 2)
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 54 of 96
R
DBi
C
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.29
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
Standard
Min.
Max.
25
4
(NOTE 1)
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(AD-ALE)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
Chip Select Output Hold Time (in relation to RD)
Chip Select Output Hold Time (in relation to WR)
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
ALE Signal Output Delay Time (in relation to BCLK)
ALE Signal Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time (in relation to Address)
ALE Signal Output Hold Time (in relation to Address)
RD Signal Output Delay From the End of Address
WR Signal Output Delay From the End of Address
Address Output Floating Start Time
(NOTE 1)
25
4
(NOTE 1)
(NOTE 1)
25
0
25
See
Figure 5.2
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 25 [ ns ]
f ( BCLK )
4. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 15 [ ns ]
f ( BCLK )
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 55 of 96
0
40
4
(NOTE 2)
(NOTE 1)
40
15
−4
(NOTE 3)
(NOTE 4)
0
0
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
th(TIN-UP) tsu(UP-TIN)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.3
Timing Diagram (1)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 56 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 5.4
Timing Diagram (2)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 57 of 96
th(C-D)
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA input
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2
td(BCLK−HLDA)
Hi−Z
(1)
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
· Measuring conditions :
· VCC1=VCC2=5V
· Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
· Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 5.5
Timing Diagram (3)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 58 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
25ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 × tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
40ns.min
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
tcyc=
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.6
Timing Diagram (4)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 59 of 96
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
0ns.min
th(BCLK-ALE)
25ns.max
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
25ns.max
0ns.min
RD
tac2(RD-DB)
(1.5 × tcyc-45)ns.max
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD)
0ns.min
40ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
25ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
4ns.min
40ns.max
Hi-Z
DBi
td(DB-WR)
tcyc=
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.7
Timing Diagram (5)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 60 of 96
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
CSi
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(RD-AD)
th(BCLK-ALE)
0ns.min
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
25ns.max
RD
tac2(RD-DB)
(2.5×tcyc-45)ns.max
DBi
Hi-Z
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
25ns.max
th(BCLK-CS)
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
4ns.min
CSi
ADi
BHE
td(BCLK-ALE)
25ns.max
th(WR-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
40ns.max
Hi-Z
DBi
td(DB-WR)
(1.5×tcyc-40)ns.min
Tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 5.8
th(BCLK-DB)
4ns.min
Timing Diagram (6)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 61 of 96
th(WR-DB)
(0.5×tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
25ns.max
4ns.min
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
25ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
25ns.max
0ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
25ns.max
0ns.min
RD
tac2(RD-DB)
(3.5×tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
40ns.min
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
25ns.max
th(BCLK-CS)
td(BCLK-AD)
th(BCLK-AD)
4ns.min
CSi
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
25ns.max
th(WR-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
th(BCLK-DB)
4ns.min
40ns.max
Hi-Z
DBi
td(DB-WR)
(2.5×tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 5.9
Timing Diagram (7)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 62 of 96
th(WR-DB)
(0.5×tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection )
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
(0.5×tcyc-10)ns.min
tcyc
25ns.max
4ns.min
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-25)ns.min
(0.5×tcyc-15)ns.min
ADi
/DBi
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5×tcyc-45)ns.max
tsu(DB-RD)
th(RD-DB)
0ns.min
40ns.min
td(AD-RD)
0ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
(0.5×tcyc-10)ns.min
th(BCLK-ALE)
−4ns.min
25ns.max
ALE
td(BCLK-RD)
th(BCLK-RD)
25ns.max
0ns.min
RD
Write timing
BCLK
th(BCLK-CS)
th(WR-CS)
tcyc
td(BCLK-CS)
4ns.min
(0.5×tcyc-10)ns.min
25ns.max
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
40ns.max
ADi
/DBi
Address
Address
Data output
td(DB-WR)
(1.5×tcyc-40)ns.min
td(AD-ALE)
(0.5×tcyc-25)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
25ns.max
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
td(AD-WR)
−4ns.min
0ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
ALE
td(BCLK-WR)
25ns.max
WR,WRL,
WRH
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 5.10
Timing Diagram (8)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 63 of 96
th(BCLK-WR)
0ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection )
Read timing
tcyc
BCLK
th(RD-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
4ns.min
25ns.max
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-25)ns.min
ADi
/DBi
(0.5×tcyc-15)ns.min
Address
Data input
th(RD-DB)
tdZ(RD-AD)
td(BCLK-AD)
8ns.max
td(AD-RD)
25ns.max
(2.5×tcyc-45)ns.max
0ns.min
ADi
BHE
tac3(RD-DB)
tsu(DB-RD)
0ns.min
th(BCLK-AD)
4ns.min
40ns.min
(no multiplex)
td(BCLK-ALE)
25ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
25ns.max
RD
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
4ns.min
25ns.max
CSi
ADi
/DBi
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Address
Data output
td(AD-ALE)
(0.5×tcyc-25)ns.min
td(DB-WR)
(2.5×tcyc-40)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
th(WR-AD)
-4ns.min
td(AD-WR)
(0.5×tcyc-10)ns.min
0ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
25ns.max
WR, WRL
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : V IL=0.8V, VIH=2.0V
· Output timing voltage : V OL=0.4V, VOH=2.4V
Figure 5.11
Timing Diagram (9)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 64 of 96
0ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Table 5.30
Electrical Characteristics (1)
Symbol
VOH
VOH
Parameter
HIGH Output
Voltage (3)
IOH=−1mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−1mA (2)
HIGH Output Voltage
VOL
LOW Output
Voltage (3)
XOUT
XCOUT
IOH=−0.1mA
LOWPOWER
IOH=−50µA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
IOL=1mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=1mA (2)
LOW Output Voltage
Hysteresis
HIGHPOWER
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
XOUT
LOW Output Voltage
VT+-VT-
Measuring Condition
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
HIGH Output Voltage
VOL
(1)
XCOUT
HIGHPOWER
IOL=0.1mA
LOWPOWER
IOL=50µA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, NMI,
ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
RESET
HIGH Input
Current (3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
VI=3V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
VI=0V
Resistance
(3)
RfXIN
RfXCIN
VRAM
VCC1−0.5
VCC1
VCC2−0.5
VCC2
VCC1−0.5
VCC1−0.5
VCC1
VCC1
2.5
1.6
V
0.5
0.5
0
0
50
(0.7)
100
Feedback Resistance XCIN
At stop mode
0.8
V
1.8
V
4.0
µA
−4.0
µA
500
kΩ
2.0
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless
otherwise specified.
2. VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13
3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Page 65 of 96
V
V
3.0
25
Feedback Resistance XIN
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
V
V
0.2
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 VI=0V
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to
P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
RAM Retention Voltage
Unit
V
0.2
IIH
RPULLUP Pull-Up
Max.
0.5
Hysteresis
LOW Input
Current (3)
Standard
Typ.
0.5
VT+-VT-
IIL
Min.
MΩ
MΩ
V
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.31
Electrical Characteristics (2) (1)
Symbol
ICC
5. Electrical Characteristics
Parameter
Measuring Condition
Power Supply Current
In single-chip
(VCC1=VCC2=2.7V to 3.6V) mode, the output
pins are open and
other pins are VSS
Mask ROM
Flash
Memory
Flash Memory
Program
Flash Memory
Erase
Mask ROM
Flash Memory
Idet4
Idet3
(4)
Low Voltage Detection Dissipation Current
Reset Area Detection Dissipation Current (4)
Standard
Typ. Max.
8
No division,
On-chip oscillation
1
f(BCLK)=10MHz,
No division
8
No division,
On-chip oscillation
1.8
mA
f(BCLK)=10MHz,
VCC1=3.0V
12
mA
f(BCLK)=10MHz,
VCC1=3.0V
22
mA
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
25
µA
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
25
µA
420
µA
On-chip oscillation,
Wait mode
45
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability High
6.0
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability Low
1.8
µA
Stop mode
Topr =25°C
0.7
3.0
µA
0.6
0.4
4
2
µA
11
Page 66 of 96
mA
mA
13
NOTES:
1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=10MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Unit
f(BCLK)=10MHz
No division
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory (3)
Mask ROM
Flash Memory
Min.
mA
µA
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.32
External Clock Input (XIN input)(1)
Symbol
Parameter
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
External Clock Fall Time
tc
tw(H)
tw(L)
tr
tf
Standard
Min.
Max.
(NOTE 2)
(NOTE 3)
(NOTE 3)
(NOTE 4)
(NOTE 4)
Unit
ns
ns
ns
ns
ns
NOTES:
1. The condition is VCC1=VCC2=2.7 to 3.0V.
2. Calculated according to the VCC1 voltage as follows:
10 –6
---------------------------------------- [ns]
20 × V C C2 – 44
3. Calculated according to the VCC1 voltage as follows:
–6
10
---------------------------------------- × 0.4 [ns]
20 × V C C1 – 44
4. Calculated according to the VCC1 voltage as follows:
– 10 × V C C1 + 45 [ns]
Table 5.33
Memory Expansion Mode and Microprocessor Mode
Symbol
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
tsu(RDY-BCLK)
tsu(HOLD-BCLK)
th(RD-DB)
th(BCLK-RDY)
th(BCLK-HOLD)
Parameter
Data Input Access Time (for setting with no wait)
Data Input Access Time (for setting with wait)
Data Input Access Time (when accessing multiplex bus area)
Data Input Setup Time
RDY Input Setup Time
HOLD Input Setup Time
Data Input Hold Time
RDY Input Hold Time
HOLD Input Hold Time
Standard
Min.
Max.
(NOTE 1)
(NOTE 2)
(NOTE 3)
50
40
50
0
0
0
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 60 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 60 [ ns ]
f ( BCLK )
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 60 [ ns ]
f ( BCLK )
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
n is “2” for 2-wait setting, “3” for 3-wait setting.
Page 67 of 96
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.34
Timer A Input (Counter Input in Event Counter Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 5.35
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.36
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.37
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.38
Parameter
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Standard
Min.
600
300
300
Unit
ns
ns
ns
Standard
Min.
300
150
150
Max.
Unit
ns
ns
ns
Standard
Min.
150
150
Parameter
Max.
Unit
ns
ns
Standard
tc(UP)
TAiOUT Input Cycle Time
Min.
3000
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
1500
1500
600
600
Max.
Unit
ns
ns
ns
ns
ns
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Max.
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
Table 5.39
ns
ns
ns
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
tw(TAH)
tw(TAL)
Unit
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Max.
Timer A Input (Gating Input in Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Standard
Min.
150
60
60
Parameter
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 68 of 96
Standard
Min.
2
500
500
Max.
Unit
µs
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.40
Timer B Input (Counter Input in Event Counter Mode)
Symbol
Parameter
Standard
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
Min.
150
60
60
300
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
120
120
Table 5.41
Table 5.42
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.43
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
tc(AD)
Table 5.44
Parameter
Table 5.45
tw(INL)
Max.
Unit
ns
ns
ns
Standard
Min.
600
300
300
Max.
Unit
ns
ns
ns
Standard
ADTRG Input Cycle Time
ADTRG Input LOW Pulse Width
200
Max.
Unit
ns
ns
Serial Interface
Parameter
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
RXDi Input Setup Time
RXDi Input Hold Time
Standard
Min.
300
150
150
Max.
160
0
100
90
Unit
ns
ns
ns
ns
ns
ns
ns
External Interrupt INTi Input
Symbol
tw(INH)
Standard
Min.
600
300
300
Min.
1500
Symbol
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
ns
ns
A/D Trigger Input
Symbol
tw(ADL)
ns
ns
ns
ns
Timer B Input (Pulse Width Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Unit
Timer B Input (Pulse Period Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Max.
Parameter
Standard
INTi Input HIGH Pulse Width
Min.
380
INTi Input LOW Pulse Width
380
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 69 of 96
Max.
Unit
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.46
Memory Expansion and Microprocessor Modes (for setting with no wait)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Parameter
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR) (3)
HLDA Output Delay Time
See
Figure 5.12
Standard
Min.
Max.
30
4
0
(NOTE 2)
30
4
25
−4
30
0
30
0
40
4
(NOTE 1)
(NOTE 2)
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
f(BCLK) is 12.5MHz or less.
------------------------ – 40 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2)
= 6.7ns.
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 5.12
Ports P0 to P14 Measurement Circuit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 70 of 96
R
DBi
C
30pF
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.47
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Symbol
Standard
Min.
Max.
30
4
0
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
ALE Signal Output Hold Time
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)(3)
HLDA Output Delay Time
Unit
ns
ns
ns
(NOTE 2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
4
25
See
Figure 5.12
-4
30
0
30
0
40
4
(NOTE 1)
(NOTE 2)
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
( n – 0.5 ) x10
------------------------------------ – 40 [ ns ]
f ( BCLK )
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 71 of 96
R
DBi
C
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.48
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Symbol
Standard
Min.
Max.
50
4
(NOTE 1)
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(AD-ALE)
td(AD-RD)
td(AD-WR)
tdz(RD-AD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
Chip Select Output Hold Time (in relation to BCLK)
Chip Select Output Hold Time (in relation to RD)
Chip Select Output Hold Time (in relation to WR)
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
ALE Signal Output Delay Time (in relation to BCLK)
ALE Signal Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time (in relation to Address)
ALE Signal Output Hold Time (in relation to Address)
RD Signal Output Delay From the End of Address
WR Signal Output Delay From the End of Address
Address Output Floating Start Time
(NOTE 1)
50
4
(NOTE 1)
(NOTE 1)
40
0
40
See
Figure 5.12
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 10 [ ns ]
f ( BCLK )
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 50 [ ns ]
f ( BCLK )
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 40 [ ns ]
f ( BCLK )
4. Calculated according to the BCLK frequency as follows:
9
0.5x10
------------------------ – 15 [ ns ]
f ( BCLK )
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 72 of 96
0
50
4
(NOTE 2)
(NOTE 1)
40
25
−4
(NOTE 3)
(NOTE 4)
0
0
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During Event Counter Mode
TAiIN input
(When count on falling
edge is selected)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(When count on rising
edge is selected)
Two-Phase Pulse Input in
Event Counter Mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.13
Timing Diagram (1)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 73 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 5.14
Timing Diagram (2)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 74 of 96
th(C-D)
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
VCC1=VCC2=3V
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA output
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
P5_0 to P5_2 (1)
td(BCLK−HLDA)
Hi−Z
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions :
· VCC1=VCC2=3V
· Input timing voltage : Determined with V IL=0.6V, VIH=2.4V
· Output timing voltage : Determined with V OL=1.5V, VOH=1.5V
Figure 5.15
Timing Diagram (3)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 75 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
30ns.max
th(RD-AD)
0ns.min
ALE
td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
RD
tac1(RD-DB)
(0.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
th(BCLK-AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
th(WR-AD)
(0.5 × tcyc-10)ns.min
-4ns.min
30ns.max
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
tcyc=
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 5.16
Timing Diagram (4)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 76 of 96
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK−AD)
th(BCLK−AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK−ALE)
th(RD−AD)
th(BCLK−ALE)
0ns.min
−4ns.min
30ns.max
ALE
td(BCLK−RD)
th(BCLK−RD)
30ns.max
0ns.min
RD
tac2(RD−DB)
(1.5 × tcyc−60)ns.max
Hi−Z
DBi
th(RD−DB)
tsu(DB−RD)
0ns.min
50ns.min
Write timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK−AD)
th(BCLK−AD)
30ns.max
4ns.min
ADi
BHE
td(BCLK−ALE)
th(BCLK−ALE)
th(WR−AD)
(0.5 × tcyc−10)ns.min
−4ns.min
30ns.max
ALE
td(BCLK−WR)
30ns.max
th(BCLK−WR)
0ns.min
WR,WRL,
WRH
td(BCLK−DB)
th(BCLK−DB)
40ns.max
4ns.min
Hi−Z
DBi
td(DB−WR)
tcyc=
(0.5 × tcyc−40)ns.min
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 5.17
Timing Diagram (5)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 77 of 96
th(WR−DB)
(0.5 × tcyc−10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
30ns.max
th(RD-AD)
0ns.min
th(BCLK-ALE)
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
30ns.max
RD
tac2(RD-DB)
(2.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
td(BCLK-CS)
30ns.max
th(BCLK-CS)
4ns.min
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
CSi
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
(0.5 × tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
ALE
td(BCLK-WR)
30ns.max
th(BCLK-WR)
0ns.min
WR, WRL
WRH
td(BCLK-DB)
40ns.max
Hi-Z
DBi
td(DB-WR)
(1.5 × tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 5.18
th(BCLK-DB)
4ns.min
Timing Diagram (6)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 78 of 96
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1 = VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
4ns.min
30ns.max
CSi
th(BCLK-AD)
td(BCLK-AD)
4ns.min
30ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
30ns.max
0ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
30ns.max
RD
tac2(RD-DB)
(3.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
th(RD-DB)
50ns.min
0ns.min
Write timing
tcyc
BCLK
th(BCLK-CS)
td(BCLK-CS)
4ns.min
30ns.max
CSi
th(BCLK-AD)
td(BCLK-AD)
4ns.min
30ns.max
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
th(BCLK-ALE)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
0ns.min
30ns.max
WR, WRL
WRH
td(BCLK-DB)
th(BCLK-DB)
40ns.max
4ns.min
Hi-Z
DBi
td(DB-WR)
(2.5 × tcyc-40)ns.min
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 5.19
Timing Diagram (7)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 79 of 96
th(WR-DB)
(0.5 × tcyc-10)ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Memory Expansion Mode, Microprocessor Mode
VCC1=VCC2=3V
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
(0.5×tcyc-10)ns.min
tcyc
40ns.max
4ns.min
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
ADi
/DBi
th(ALE-AD)
(0.5×tcyc-15)ns.min
Address
8ns.max
Address
Data input
tdZ(RD-AD)
tac3(RD-DB)
(1.5×tcyc-60)ns.max
tsu(DB-RD)
th(RD-DB)
0ns.min
50ns.min
td(AD-RD)
0ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
th(RD-AD)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
td(BCLK-RD)
th(BCLK-RD)
40ns.max
0ns.min
RD
Write timing
BCLK
tcyc
td(BCLK-CS)
th(BCLK-CS)
th(WR-CS)
(0.5×tcyc-10)ns.min
40ns.max
4ns.min
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
50ns.max
ADi
/DBi
Address
Address
Data output
td(DB-WR)
(1.5×tcyc-50)ns.min
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
40ns.max
ADi
BHE
td(BCLK-ALE)
40ns.max
td(AD-WR)
th(BCLK-ALE)
-4ns.min
0ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
WR,WRL,
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 5.20
Timing Diagram (8)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 80 of 96
th(BCLK-WR)
0ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
6ns.min
40ns.max
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(ALE-AD)
(0.5×tcyc-15)ns.min
ADi
/DBi
Data input
Address
td(BCLK-AD)
40ns.max
tac3(RD-DB)
8ns.max
td(AD-RD)
(2.5×tcyc-60)ns.max
0ns.min
ADi
BHE
th(RD-DB)
tdZ(RD-AD)
tsu(DB-RD)
0ns.min
th(BCLK-AD)
50ns.min
4ns.min
(No multiplex)
td(BCLK-ALE)
40ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-RD)
td(BCLK-RD)
0ns.min
40ns.max
RD
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
th(BCLK-CS)
4ns.min
40ns.max
CSi
th(BCLK-DB)
td(BCLK-DB)
4ns.min
50ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
(0.5×tcyc-40)ns.min
td(DB-WR)
(2.5×tcyc-50)ns.min
th(WR-DB)
(0.5×tcyc-10)ns.min
td(BCLK-AD)
th(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
(No multiplex)
td(BCLK-ALE)
th(BCLK-ALE)
40ns.max
-4ns.min
th(WR-AD)
td(AD-WR)
(0.5×tcyc-10)ns.min
0ns.min
ALE
th(BCLK-WR)
td(BCLK-WR)
40ns.max
WR, WRL
WRH
tcyc=
1
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : V IL=0.6V, VIH=2.4V
· Output timing voltage : V OL=1.5V, VOH=1.5V
Figure 5.21
Timing Diagram (9)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 81 of 96
0ns.min
M16C/62P Group (M16C/62P, M16C/62PT)
5.2
5. Electrical Characteristics
Electrical Characteristics (M16C/62PT)
Table 5.49
Symbol
VCC1, VCC2
AVCC
VI
VO
Pd
Absolute Maximum Ratings
Parameter
Supply Voltage
Analog Supply Voltage
Input Voltage
RESET, CNVSS, BYTE,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
VREF, XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1
Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
XOUT
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
P7_0, P7_1
Power Dissipation
Condition
VCC1=VCC2=AVCC
VCC1=VCC2=AVCC
−40°C<Topr≤85°C
85°C<Topr≤125°C
Topr
Tstg
Operating
Ambient
Temperature
When the Microcomputer is Operating
Rated Value
−0.3 to 6.5
−0.3 to 6.5
Unit
V
V
−0.3 to VCC1+0.3 (1)
V
−0.3 to VCC2+0.3 (1)
V
−0.3 to 6.5
V
−0.3 to VCC1+0.3 (1)
V
−0.3 to VCC2+0.3 (1)
V
−0.3 to 6.5
V
300
200
−40 to 85 / −40 to 125
(2)
Flash Program Erase
Storage Temperature
0 to 60
−65 to 150
mW
°C
°C
NOTES:
1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in
80-pin version.
2. T version = −40 to 85 °C, V version= −40 to 125 °C.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 82 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Recommended Operating Conditions (1) (1)
Table 5.50
Symbol
VCC1, VCC2
AVCC
VSS
AVSS
VIH
VIL
IOH(peak)
Parameter
Supply Voltage (VCC1 = VCC2)
Analog Supply Voltage
Supply Voltage
Analog Supply Voltage
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
HIGH Input
P12_0 to P12_7, P13_0 to P13_7
Voltage (4)
LOW Input
Voltage (4)
HIGH Peak
Output Current
(4)
IOH(avg)
HIGH Average
Output Current
(4)
IOL(peak)
LOW Peak
Output Current
(4)
IOL(avg)
LOW Average
Output Current
(4)
f(XIN)
f(XCIN)
f(Ring)
f(PLL)
f(BCLK)
tSU(PLL)
5. Electrical Characteristics
Min.
4.0
Standard
Typ.
5.0
VCC1
0
0
Max.
5.5
Unit
0.8VCC2
VCC2
V
V
V
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0.8VCC2
VCC2
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
0.8VCC1
VCC1
V
P7_0, P7_1
0.8VCC1
0
6.5
0.2VCC2
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0
0.2VCC2
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
0
0.2VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
−10.0
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
−5.0
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
10.0
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
5.0
mA
16
50
2
24
24
20
MHz
kHz
MHz
MHz
MHz
ms
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
Main Clock Input Oscillation Frequency
Sub-Clock Oscillation Frequency
On-chip Oscillation Frequency
PLL Clock Oscillation Frequency
CPU Operation Clock
PLL Frequency Synthesizer Stabilization
Wait Time
VCC1=4.0V to 5.5V
VCC1=4.0V to 5.5V
VCC1=5.5V
0
0.5
10
0
32.768
1
NOTES:
1. Referenced to VCC1 = VCC2 = 4.7 to 5.5V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified.
T version = −40 to 85 °C, V version= −40 to 125 °C.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10 P1, P14_0 and P14_1 must be 80mA max. The total IOL(peak) for
ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must
be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports P6,
P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and P14_1 must
be −40mA max.
As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS.
4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 83 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.51
A/D Conversion Characteristics (1)
Symbol
−
INL
−
Parameter
Resolution
Integral Non-Linearity
Error
Absolute Accuracy
−
DNL
−
−
RLADDER
tCONV
tCONV
tSAMP
VREF
VIA
5. Electrical Characteristics
10bit
8bit
10bit
8bit
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
Gain Error
Ladder Resistance
10-bit Conversion Time, Sample & Hold
Function Available
8-bit Conversion Time, Sample & Hold
Function Available
Sampling Time
Reference Voltage
Analog Input Voltage
Measuring Condition
Min.
VREF=VCC1
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
5V
ANEX0, ANEX1 input
External operation amp
connection mode
VREF=VCC1=5V
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
VREF=VCC1=5V
Standard
Typ.
Max.
10
±3
10
2.75
VREF=VCC1=5V, φAD=12MHz
2.33
Bits
LSB
±7
LSB
±2
±3
LSB
LSB
±7
LSB
±2
LSB
kΩ
LSB
LSB
LSB
kΩ
µs
3
VREF=VCC1
VREF=VCC1=5V, φAD=12MHz
Unit
±1
±3
±3
40
µs
µs
0.25
2.0
0
VCC1
VREF
V
V
NOTES:
1. Referenced to VCC1=AVCC=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified.
T version = −40 to 85°C, V version =−40 to 125°C
2. φAD frequency must be 12 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.
When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2.
Table 5.52
D/A Conversion Characteristics (1)
Symbol
−
−
tSU
RO
IVREF
Parameter
Resolution
Absolute Accuracy
Setup Time
Output Resistance
Reference Power Supply Input Current
Measuring Condition
Min.
4
(NOTE 2)
Standard
Typ.
10
Max.
8
1.0
3
20
1.5
Unit
Bits
%
µs
kΩ
mA
NOTES:
1. Referenced to VCC1=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified. T
version = −40 to 85°C, V version =−40 to 125°C
2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor
ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id
disconnected by the A/D control register.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 84 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.53
5. Electrical Characteristics
Flash Memory Version Electrical Characteristics (1) for 100 cycle products (B, U)
Symbol
Parameter
−
Program and Erase Endurance (3)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
Block Erase Time
(VCC1=5.0V)
−
−
−
−
−
−
−
tPS
−
Min.
100
4-Kbyte block
8-Kbyte block
32-Kbyte block
64-Kbyte block
Erase All Unlocked Blocks Time (2)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
Table 5.54
Program and Erase Endurance (3, 8, 9)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
Block Erase Time
(VCC1=5.0V)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
−
−
tPS
−
4
200
200
4
4
4
4
4×n
15
20
Parameter
−
25
25
0.3
0.3
0.5
0.8
Max.
Unit
cycle
µs
µs
s
s
s
s
s
µs
year
Flash Memory Version Electrical Characteristics (6) for 10,000 cycle products (B7, U7)
(Block A and Block 1 (7))
Symbol
−
Standard
Typ.
Min.
10,000 (4)
4-Kbyte block
Standard
Typ.
4
Max.
cycle
µs
µs
s
25
25
0.3
15
20
Unit
µs
year
NOTES:
1. Referenced to VCC1=4.5 to 5.5V at Topr = 0 to 60 °C unless otherwise specified.
2. n denotes the number of block erases.
3. Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times.
For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as
one program and erase endurance. Data cannot be written to the same address more than once without erasing the block.
(Rewrite prohibited)
4. Maximum number of E/W cycles for which operation is guaranteed.
5. Ta (ambient temperature)=55 °C. As to the data hold time except Ta=55 °C, please contact Renesas Technology Corp. or an
authorized Renesas Technology Corp. product distributor.
6. Referenced to VCC1 = 4.5 to 5.5V at Topr = −40 to 85 °C (B7, U7 (T version)) / −40 to 125 °C (B7, U7 (V version)) unless
otherwise specified.
7. Table 5.54 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 5.53.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to
unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For
example, an 8-word program can be written 256 times maximum before erase becomes necessary.
Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the
total number of times erasure is used.
9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command
at least three times until erase error disappears.
10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (B7 and U7).
11. Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Table 5.55
Flash Memory Version Program/Erase Voltage and Read Operation Voltage
Characteristics (at Topr = 0 to 60 °C(B, U), Topr = −40 to 85 °C (B7, U7 (T version)) / −40
to 125 °C (B7, U7 (V version))
Flash Program, Erase Voltage
VCC1 = 5.0 V ± 0.5 V
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 85 of 96
Flash Read Operation Voltage
VCC1=4.0 to 5.5 V
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.56
Power Supply Circuit Timing Characteristics
Symbol
td(P-R)
td(R-S)
td(W-S)
5. Electrical Characteristics
Parameter
Measuring Condition
Time for Internal Power Supply Stabilization
During Powering-On
STOP Release Time
Low Power Dissipation Mode Wait Mode
Release Time
Standard
Typ.
VCC1=4.0V to 5.5V
Time for Internal Power
Supply Stabilization During
Powering-On
VCC1
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
(b)Wait mode release
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation
Mode Wait Mode Release
Time
CPU clock
(a)
(b)
Power Supply Circuit Timing Diagram
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 86 of 96
Max.
2
150
150
Recommended
operation voltage
td(P-R)
Figure 5.22
Min.
td(R-S)
td(W-S)
Unit
ms
µs
µs
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Table 5.57
Electrical Characteristics (1)
Symbol
VOH
VOH
VOH
Parameter
HIGH
Output
Voltage (2)
HIGH
Output
Voltage (2)
IOH=−5mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−5mA
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
OH=−200µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−200µA
HIGH Output Voltage
VOL
VOL
LOW
Output
Voltage (2)
LOW
Output
Voltage (2)
XOUT
XCOUT
IOH=−1mA
IOH=−0.5mA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
IOL=5mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=5mA
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOL=200µA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=200µA
LOW Output Voltage
Hysteresis
HIGHPOWER
LOWPOWER
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
XOUT
LOW Output Voltage
VT+-VT-
Measuring Condition
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
HIGH Output Voltage
VOL
(1)
XCOUT
HIGHPOWER
IOL=1mA
LOWPOWER
IOL=0.5mA
HIGHPOWER
With no load applied
LOWPOWER
With no load applied
HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
RESET
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
VI=5V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
VI=0V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
VI=0V
(2)
RfXIN
RfXCIN
VRAM
VCC1
VCC2−2.0
VCC2
VCC1−0.3
VCC1
V
V
VCC2−0.3
VCC2
VCC1−2.0
VCC1−2.0
VCC1
VCC1
2.5
1.6
V
V
V
2.0
2.0
V
0.2
1.0
V
0.2
2.5
V
5.0
µA
−5.0
µA
170
kΩ
30
50
1.5
15
Feedback Resistance XCIN
At stop mode
V
0
0
Feedback Resistance XIN
RAM Retention Voltage
V
0.45
HIGH Input
Current (2)
Resistance
VCC1−2.0
Unit
0.45
IIH
RPULLUP Pull-Up
Max.
2.0
Hysteresis
LOW Input
Current (2)
Standard
Typ.
2.0
VT+-VT-
IIL
Min.
2.0
MΩ
MΩ
V
NOTES:
1. Referenced to VCC1=VCC2=4.0 to 5.5V, VSS = 0V at Topr = −40 to 85°C / −40 to 125°C, f(BCLK)=24MHz unless otherwise
specified. T version = −40 to 85°C, V version =−40 to 125°C.
2. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 87 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
Table 5.58
Electrical Characteristics (2) (1)
Symbol
ICC
5. Electrical Characteristics
Parameter
Power Supply Current
In single-chip
(VCC1=VCC2=4.0V to 5.5V) mode, the output
pins are open and
other pins are VSS
Measuring Condition
Mask ROM
f(BCLK)=24MHz
No division, PLL operation
No division,
On-chip oscillation
Flash
Memory
Flash Memory
Program
Flash Memory
Erase
Mask ROM
Flash Memory
Standard
Typ. Max.
14
20
1
Unit
mA
mA
f(BCLK)=24MHz,
No division, PLL operation
18
No division,
On-chip oscillation
1.8
mA
f(BCLK)=10MHz,
VCC1=5.0V
15
mA
f(BCLK)=10MHz,
VCC1=5.0V
25
mA
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
25
µA
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
25
µA
420
µA
On-chip oscillation,
Wait mode
50
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability High
7.5
µA
f(BCLK)=32kHz
Wait mode (2),
Oscillation capability Low
2.0
µA
Stop mode
Topr =25°C
2.0
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory (3)
Mask ROM
Flash Memory
Min.
27
mA
6.0
µA
Stop mode
Topr =85°C
20
µA
Stop mode
Topr =125°C
TBD
µA
NOTES:
1. Referenced to VCC1=VCC2=4.0 to 5.5V, VSS = 0V at Topr = −40 to 85°C / −40 to 125°C, f(BCLK)=24MHz unless otherwise
specified. T version = −40 to 85°C, V version =−40 to 125°C.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 88 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 5.59
External Clock Input (XIN input)
Symbol
tc
tw(H)
tw(L)
tr
tf
Parameter
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
External Clock Fall Time
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 89 of 96
Standard
Min.
62.5
25
25
Max.
15
15
Unit
ns
ns
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 5.60
Timer A Input (Counter Input in Event Counter Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 5.61
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.62
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.63
Parameter
TAiIN Input Cycle Time
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.64
Parameter
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.65
Parameter
TAiOUT Input Cycle Time
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
Max.
Unit
ns
ns
ns
Standard
Min.
200
100
100
Max.
Unit
ns
ns
ns
Standard
Min.
100
100
Max.
Unit
ns
ns
Standard
Min.
Max.
2000
1000
1000
400
400
Unit
ns
ns
ns
ns
ns
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Symbol
tc(TA)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
Standard
Min.
400
200
200
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Symbol
tc(UP)
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
ns
ns
ns
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Symbol
tw(TAH)
tw(TAL)
Unit
Timer A Input (External Trigger Input in One-shot Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Max.
Timer A Input (Gating Input in Timer Mode)
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Standard
Min.
100
40
40
Parameter
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 90 of 96
Standard
Min.
800
200
200
Max.
Unit
ns
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 5.66
Timer B Input (Counter Input in Event Counter Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Table 5.67
Parameter
TBiIN Input Cycle Time (counted on one edge)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
Table 5.68
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.69
Parameter
TBiIN Input Cycle Time
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Standard
Min.
400
200
200
Parameter
tw(ADL)
ADTRG input LOW Pulse Width
125
Unit
ns
ns
ns
Max.
Unit
ns
ns
Serial Interface
Symbol
Parameter
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
RXDi Input Setup Time
RXDi Input Hold Time
Standard
Min.
200
100
100
Max.
80
0
70
90
Unit
ns
ns
ns
ns
ns
ns
ns
External Interrupt INTi Input
Symbol
tw(INL)
Max.
Standard
ADTRG Input Cycle Time
tw(INH)
Unit
ns
ns
ns
Standard
tc(AD)
Table 5.71
Max.
Min.
400
200
200
Min.
1000
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
ns
ns
ns
ns
ns
ns
A/D Trigger Input
Symbol
Table 5.70
Unit
Timer B Input (Pulse Width Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Max.
Timer B Input (Pulse Period Measurement Mode)
Symbol
tc(TB)
tw(TBH)
tw(TBL)
Standard
Min.
100
40
40
200
80
80
Parameter
Standard
INTi Input HIGH Pulse Width
Min.
250
INTi Input LOW Pulse Width
250
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 91 of 96
Max.
Unit
ns
ns
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
Figure 5.23
Ports P0 to P10 Measurement Circuit
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 92 of 96
30pF
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tw(H)
tr
tf
tw(L)
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
th(TIN-UP) tsu(UP-TIN)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.24
Timing Diagram (1)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 93 of 96
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
tsu(D-C)
td(C-Q)
RXDi
tw(INL)
INTi input
tw(INH)
Figure 5.25
Timing Diagram (2)
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 94 of 96
th(C-D)
M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-LQFP128-14x20-0.50
PLQP0128KB-A
128P6Q-A
0.9g
HD
*1
D
102
65
103
64
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
c
*2
E
HE
c1
b1
Reference
Symbol
ZE
Terminal cross section
Dimension in Millimeters
Min
Nom
Max
D
19.9
20.0
20.1
E
13.9
14.0
14.1
A2
128
39
38
ZD
HD
21.8
22.0
22.2
HE
15.8
16.0
16.2
A1
0.05
0.125
0.2
bp
0.17
0.22
0.27
A
A
A2
Index mark
c
1
1.4
F
1.7
0.20
b1
A1
c
*3
y
e
DetailF
8°
0.5
0.10
x
y
0.10
ZD
0.75
ZE
0.75
L
0.35
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
PRQP0100JB-A
100P6S-A
1.6g
0.5
0.65
1.0
L1
P-QFP100-14x20-0.65
0.20
0.125
e
x
0.145
0°
L1
bp
0.09
c1
L
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
Dimension in Millimeters
Min
Nom
Max
D
19.8
20.0
20.2
E
13.8
14.0
HD
22.5
22.8
23.1
30
Index mark
ZD
c
F
A2
1
HE
16.5
16.8
17.1
A1
0
0.1
0.2
bp
0.25
0.3
0.4
c
0.13
0.15
A1
A
A
L
*3
e
y
3.05
0°
bp
Detail F
e
0.5
0.65
0.575
ZD
Page 95 of 96
0.8
0.10
ZE
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
0.2
10°
y
L
14.2
2.8
A2
0.825
0.4
0.6
0.8
M16C/62P Group (M16C/62P, M16C/62PT)
JEITA Package Code
RENESAS Code
P-LQFP100-14x14-0.50
PLQP0100KB-A
Appendix 1. Package Dimensions
Previous Code
MASS[Typ.]
100P6Q-A / FP-100U / FP-100UV
0.6g
HD
*1
D
51
75
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
50
76
bp
c1
Reference
Symbol
c
E
*2
HE
b1
Terminal cross section
26
Nom
13.9
14.0
14.1
E
13.9
14.0
14.1
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A1
0.05
0.1
0.15
bp
0.15
0.20
0.25
A2
ZE
100
Dimension in Millimeters
Min
D
1.4
A
1
25
Index mark
ZD
F
1.7
0.18
b1
0.09
c
0°
*3
e
bp
A1
e
y
0.08
0.08
1.0
ZD
Detail F
1.0
ZE
L
0.35
RENESAS Code
Previous Code
MASS[Typ.]
PRQP0080JA-A
80P6S-A
1.1g
0.5
0.65
1.0
L1
P-QFP80-14x14-0.65
8°
y
L1
0.20
0.5
x
L
x
JEITA Package Code
0.145
0.125
c1
A2
A
c
Max
HD
*1 D
60
41
61
40
HE
ZE
*2 E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Reference
Symbol
80
1
20
ZD
c
Nom
Max
D
13.8
14.0
14.2
E
13.8
14.0
14.2
A2
A2
Index mark
Dimension in Millimeters
Min
21
F
2.8
HD
16.5
16.8
17.1
HE
16.5
16.8
17.1
A1
0
0.1
0.2
bp
0.25
0.3
0.4
c
0.13
0.15
A
A1
A
L
Detail F
*3
e
y
3.05
0°
bp
e
0.5
0.65
y
0.825
ZD
Rev.2.41 Jan 10, 2006
REJ03B0001-0241
Page 96 of 96
0.8
0.10
ZE
L
0.2
10°
0.825
0.4
0.6
0.8
REVISION HISTORY
Rev.
Date
1.10
May 28, 2003
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
1
Applications are partly revised.
2
Table 1.1.1 is partly revised.
4-5
Table 1.1.2 and 1.1.3 is partly revised.
“Note 1” is partly revised.
22
23
Table 1.5.3 is partly revised.
Table 1.5.5 is partly revised.
Table 1.5.6 is added.
24
30
31
Table 1.5.9 is partly revised.
Notes 1 and 2 in Table 1.5.26 is partly revised.
Notes 1 in Table 1.5.27 is partly revised.
30-31
32
Note 3 is added to “Data output hold time (refers to BCLK)” in Table 1.5.26
and 1.5.27.
Note 4 is added to “th(ALE-AD)” in Table 1.5.28.
30-32 Switching Characteristics is partly revised.
36-39 th(WR-AD) and th(WR-DB) in Figure 1.5.5 to 1.5.8 is partly revised.
40-41 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.9 to
42
1.5.10 is partly revised.
Note 2 is added to Table 1.5.29.
Notes 1 and 2 in Table 1.5.45 is partly revised.
47
Notes 1 in Table 1.5.46 is partly revised.
48
47-48 Note 3 is added to “Data output hold time (refers to BCLK)” in Table
1.5.45 and 1.5.46.
Note 4 is added to “th(ALE-AD)” in Table 1.5.47.
49
47-48 Switching Characteristics is partly revised.
53-56 th(WR-AD) and th(WR-DB) in Figure 1.5.15 to 1.5.18 is partly revised.
57-58 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.19 to
1.5.20 is partly revised.
2.00
Oct 29, 2003
2-4
Since high reliability version is added, a group name is revised.
M16C/62 Group (M16C/62P) → M16C/62 Group (M16C/62P, M16C/62PT)
Table 1.1 to 1.3 are revised.
Note 3 is partly revised.
Table 1.1 to 1.3 are revised.
Note 3 is partly revised.
Figure 1.2 Note5 is deleted.
6
7-9 Table 1.4 to 1.7 Product List is partly revised.
Table 1.8 and Figure 1.4 are added.
11
12-15 Figure 1.5 to 1.9 ZP is added.
17,19 Table 1.10 and 1.12 ZP is added to timer A.
18,20 Table 1.11 and 1.13 VCC1 is added to VREF.
30
Table 5.1 is revised.
31-32 Table 5.2 and 5.3 are revised.
2-4
C-1
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
Table 5.4 A-D Conversion Characteristics is revised.
Table 5.5 D-A Conversion Characteristics revised.
34,74 Table 5.6 to 5.7 and table 5.54 to 5.55 are revised.
Table 5.11 is revised.
36
38,55 Table 5.14 and 5.33 HLDA output deley time is deleted.
Figure 5.1 is partly revised.
41
41-43, Table 5.27 to 5.29 and table 5.46 to 48 HLDA output deley time is added.
58-60
Figure 5.2 Timing Diagram (1) XIN input is added.
44
33
47-48
49-50
52
53
58
61
64-65
66-67
69
70-85
2.10
2.11
Nov 07, 2003
Jan 06, 2004
8-9
23
Table 1.5 to 1.7 Product List is partly revised. Note 1 is deleted.
Table 3.1 is revised.
71
72
Table 5.50 is revised.
Table 5.51 is deleted.
16
Table 1.9 NOTE 3 VCC1 VCC2 → VCC1 > VCC2
17-18 Table 1.10 to 1.11 NOTE 1 VCC1 VCC2 → VCC1 > VCC2
31
2.30
Sep 01, 2004
Figure 5.5 to 5.6 Read timing DB → DBi
Figure 5.7 to 5.8 Write timing DB → DBi
Figure 5.10 DB → DBi
Table 5.30 is revised.
Figure 5.11 is partly revised.
Figure 5.12 Timing Diagram (1) XIN input is added.
Figure 5.15 to 5.16 Read timing DB → DBi
Figure 5.17 to 5.18 Write timing DB → DBi
Figure 5.20 DB → DBi
Electrical Characteristics (M16C/62PT) is added.
12
18, 20
19,21
24
25
33
34
35
37
Table 5.2 Power Supply Ripple Allowable Frequency Unit MHz → kHz
Table 1.9 and Figure 1.5 are added.
Table 1.11 to 1.13 are revised.
Table 1.12 to 1.14 are revised.
Figure 3.1 is partly revised.
Note 3 is added.
Note 6 is added.
Table 5.3 is revised.
Note 2 in Table 5.4 is added.
Table 5.5 to 5.6 is partly revised.
Table 5.8 is revised.
Table 5.9 is revised.
Table 5.11 is revised.
C-2
REVISION HISTORY
Rev.
Date
Description
Page
40
57
70
72
73
74
76
79
2.41
Jan 01, 2006
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
2-4
Summary
Table 5.24 is partly revised.
Table 5.43 is partly revised.
Table 5.48 is partly revised.
Table 5.50 is partly revised.
Table 5.53 is partly revised.
Table 5.55 is revised.
Table 5.57 is partly revised.
Table 5.69 is partly revised.
voltage down detection reset -> brown-out detection Reset
Tables 1.1 to 1.3 Performance outline of M16C/62P group are partly
revised.
7
Table 1.4 Product List (1) is partly revised.
Note 1 is added.
8
Table 1.5 Product List (2) is partly revised.
Note 1, 2 and 3 are added.
9
Table 1.6 Product List (3) is partly revised.
Note 1 and 2 are added.
10
Table 1.7 Product List (4) is partly revised.
Note 1 and 2 are added.
11
Figure 1.3 Type No., Memory Size, Shows RAM capacity, and Package is
partly revised
12
Table 1.8 Product Code of Flash Memory version and ROMless version for
M16C/62P is partly revised.
13
Table 1.9 Product Code of Flash Memory version for M16C/62P is partly
revised.
14
Figure 1.6 Pin Configuration (Top View) is partly revised.
15-17 Tables 1.10 to 1.12 Pin Characteristics for 128-Pin Package are added.
18-19 Figure 1.7 and 1.8 Pin Configuration (Top View) are partly revised.
20-21 Tables 1.13 to 1.14 Pin Characteristics for 100-Pin Package are added.
22
Figure 1.9 Pin Configuration (Top View) is partly revised.
23-24 Tables 1.15 to 1.16 Pin Characteristics for 80-Pin Package are added.
25-29 Tables 1.17 to 1.21 are partly revised.
34
Note 4 of Table 4.1 SFR Information is partly revised.
43
Table 5.4 A/D Conversion Characteristics is partly revised.
45
Table 5.6 Flash Memory Version Electrical Characteristics for 100 cycle
products is partly revised.
Table 5.7 Flash Memory Version Electrical Characteristics for 10,000 cycle
products is partly revised.
Table 5.8 Flash Memory Version Program / Erase Voltage and Read
Operation Voltage Characteristics is partly revised.
46
Table 5.9 Low Voltage Detection Circuit Electrical Characteristics is partly
revised.
C-3
REVISION HISTORY
Rev.
Date
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Page
Summary
47
Figure 5.1 Power Supply Circuit Timing Diagram is partly revised.
48
Table 5.11 Electrical Characteristics (1) is partly deleted.
49
Table 5.12 Electrical Characteristics (2) is partly revised.
50
Note 1 of Table 5.13 External Clock Input (XIN input) is added.
67
Notes 1 to 4 of Table 5.32 External Clock Input (XIN input) are added.
85
Table 5.53 Flash Memory Version Electrical Characteristics for 100 cycle
products is partly revised. Standard (Min.) is partly revised.
Table 5.54 Flash Memory Version Electrical Characteristics for 10,000
cycle products is partly revised. Standard (Min.) is partly revised.
Note 5 is revised.
Table 23.55 Flash Memory Version Program / Erase Voltage and Read
Operation Voltage Characteristics is partly revised.
87
Table 5.57 Electrical Characteristics (1) is partly deleted.
88
Table 5.58 Electrical Characteristics is partly revised.
C-4
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> 2-796-3115, Fax: <82> 2-796-2145
Renesas Technology Malaysia Sdn. Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .3.0