STMicroelectronics M48T35AVPC 256 kbit 32kb x8 timekeeper sram Datasheet

M48T35AY
M48T35AV
256 Kbit (32Kb x8) TIMEKEEPER® SRAM
■
INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT and BATTERY
■
BYTEWIDE™ RAM-LIKE CLOCK ACCESS
■
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES and SECONDS
■
BATTERY LOW FLAG (BOK)
■
FREQUENCY TEST OUTPUT for REAL TIME
CLOCK
■
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
SNAPHAT (SH)
Battery/Crystal
28
1
28
PCDIP28 (PC)
Battery/Crystal
CAPHAT
1
SOH28 (MH)
– M48T35AY: 4.2V ≤ V PFD ≤ 4.5V
– M48T35AV: 2.7V ≤ VPFD ≤ 3.0V
■
SELF-CONTAINED BATTERY and CRYSTAL
in the CAPHAT DIP PACKAGE
■
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT HOUSING
CONTAINING the BATTERY and CRYSTAL
■
SNAPHAT® HOUSING (BATTERY and
CRYSTAL) is REPLACEABLE
■
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32Kb x8 SRAMs
DESCRIPTION
The M48T35AY/35AV TIMEKEEPER ® RAM is a
32Kb x8 non-volatile static RAM and real time
clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock
solution.
The M48T35AY/35AV is a non-volatile pin and
function equivalent to any JEDEC standard 32Kb
x8 SRAM. It also easily fits into many ROM,
EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement
for special write timing or limitations on the number
of writes that can be performed.
May 2000
Figure 1. Logic Diagram
VCC
15
8
A0-A14
W
DQ0-DQ7
M48T35AY
M48T35AV
E
G
VSS
AI02797B
1/19
M48T35AY, M48T35AV
Figure 2A. DIP Connections
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
27
2
26
3
25
4
24
5
23
6
7 M48T35AY 22
8 M48T35AV 21
20
9
19
10
18
11
17
12
13
16
14
15
Figure 2B. SOIC Connections
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02798B
Table 1. Signal Names
A0-A14
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
The 28 pin 600mil DIP CAPHAT™ houses the
M48T35AY/35AV silicon with a quartz crystal and
a long life lithium button cell in a single package.
The 28 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design
allows the SNAPHAT battery package to be
mounted on top of the SOIC package after the
2/19
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7 M48T35AY
8 M48T35AV
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02799
completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to
the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form.
For the 28 lead SOIC, the battery/crystal package
(i.e. SNAPHAT) part number is "M4T28BR12SH1".
As Figure 3 shows, the static memory array and
the quartz controlled clock oscillator of the
M48T35AY/35AV are integrated on one silicon
chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes
with addresses 7FF8h-7FFFh.
The clock locations contain the year, month, date,
day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31
day months are made automatically. Byte 7FF8h
is the clock control register. This byte controls user
access to the clock information and also stores the
clock calibration setting.
M48T35AY, M48T35AV
Table 2. Absolute Maximum Ratings (1)
Symbol
TA
TSTG
TSLD (2)
VIO
Parameter
Value
Unit
Grade 1
0 to 70
°C
Grade 6
–40 to 85
°C
–40 to 85
°C
260
°C
M48T35AY
–0.3 to 7
V
M48T35AV
–0.3 to 4.6
V
M48T35AY
–0.3 to 7
V
M48T35AV
–0.3 to 4.6
V
Ambient Operating Temperature
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
VCC
Supply Voltage
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes (1)
Mode
VCC
Deselect
Write
Read
4.5V to 5.5V
or
3.0V to 3.6V
Read
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min) (2)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO
X
X
X
High Z
Battery Back-up Mode
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT™ read/write memory cells.
The M48T35AY/35AV includes a clock control circuit which updates the clock bytes with current information once per second. The information can
be accessed by the user in the same manner as
any other location in the static memory array.
The M48T35AY/35AV also has its own Power-fail
Detect circuit. The control circuitry constantly mon-
itors the single 5V supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation brought on by low V CC. As VCC falls
below approximately 3V, the control circuitry connects the battery which maintains data and clock
operation until valid power returns.
3/19
M48T35AY, M48T35AV
Figure 3. Block Diagram
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A14
POWER
32,760 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
VCC
READ MODE
The M48T35AY/35AV is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable)
is low. The unique address specified by the 15 Address Inputs defines which one of the 32,768 bytes
of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access
time (t AVQV) after the last address input signal is
stable, providing that the E and G access times
are also satisfied.
If the E and G access times are not met, valid data
will be available after the latter of the Chip Enable
Access time (t ELQV) or Output Enable Access time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated before t AVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
4/19
DQ0-DQ7
W
VPFD
G
VSS
AI01623
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
WRITE MODE
The M48T35AY/35AV is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or
E. A write is terminated by the earlier rising edge
of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for
a minimum of tEHAX from Chip Enable or tWHAX
from Write Enable prior to the initiation of another
read or write cycle. Data-in must be valid tDVWH
prior to the end of write and remain valid for tWHDX
afterward. G should be kept high during write cycles to avoid bus contention; although, if the output
bus has been activated by a low on E and G, a low
on W will disable the outputs tWLQZ after W falls.
M48T35AY, M48T35AV
Figure 4. AC Testing Load Circuit
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤ 5ns
0 to 3V
1.5V
Note that Output Hi-Z is defined as the point where data is no longer
driven.
DATA RETENTION MODE
With valid VCC applied, the M48T35AY/35AV operates as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when V CC falls within the VPFD (max), VPFD
(min) window. All outputs become high impedance, and all inputs are treated as "don’t care."
Note: A power failure during a write cycle may corrupt data at the currently addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below V PFD (min), the user can be assured the memory will be in a write protected state,
provided the VCC fall time is not less than tF. The
M48T35AY/35AV may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling V CC. Therefore, decoupling of the power supply lines is recommended.
When V CC drops below VSO, the control circuit
switches power to the internal battery which preserves data and powers the clock. The internal
button cell will maintain data in the M48T35AY/
35AV for an accumulated period of at least 7 years
when VCC is less than V SO. As system power returns and V CC rises above VSO , the battery is disconnected, and the power supply is switched to
external V CC. Write protection continues until VCC
reaches V PFD (min) plus tREC (min). E should be
kept high as V CC rises past VPFD (min) to prevent
inadvertent write cycles prior to processor stabilization. Normal RAM operation can resume tREC
after VCC exceeds VPFD (max).
Also, as VCC rises, the battery voltage is checked.
If the voltage is less than approximately 2.5V, an
internal Battery Not OK (BOK) flag will be set. The
BOK flag can be checked after power up. If the
BOK flag is set, the first write attempted will be
blocked. The flag is automatically cleared after the
first write, and normal RAM operation resumes.
645Ω
DEVICE
UNDER
TEST
CL = 100pF
(or 5pF)
CL includes JIG capacitance
1.75V
AI02586
Figure 9 illustrates how a BOK check routine could
be structured.
For more information on Battery Storage Life refer
to the Application Note AN1012.
CLOCK OPERATIONS
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register 7FF8h. As
long as a ’1’ remains in that position, updating is
halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and the time that were
current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in
progress. Updating is within a second after the bit
is reset to a ’0’.
5/19
M48T35AY, M48T35AV
Table 5. Capacitance (1, 2)
(TA = 25°C)
Symbol
CIN
CIO (3)
Parameter
Test Condition
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
Note: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6A. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V)
Symbol
Parameter
ILI (1)
Input Leakage Current
ILO (1)
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±5
µA
Outputs open
50
mA
E = VIH
3
mA
E = VCC – 0.2V
3
mA
VIL (2)
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
2.4
V
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per Cycle.
Table 6B. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.0V to 3.6V)
Symbol
Parameter
ILI (1)
Input Leakage Current
ILO (1)
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±5
µA
Outputs open
30
mA
E = VIH
2
mA
E = VCC – 0.2V
2
mA
VIL (2)
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
Note: 1. Outputs deselected.
2. Negative spikes of –1V allowed for up to 10ns once per Cycle.
6/19
2.4
V
M48T35AY, M48T35AV
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70 °C or –40 to 85 °C)
Symbol
Parameter
VPFD
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR
Expected Data Retention Time (at 25°C)
Min
Typ
Max
Unit
M48T35AY
4.2
4.35
4.5
V
M48T35AV
2.7
2.9
3.0
V
M48T35AY
3.0
V
M48T35AV
VPFD –100mV
V
Grade 1
10 (2)
YEARS
Grade 6
10 (3)
YEARS
Note: 1. All voltages referenced to VSS.
2. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top tDR = 7 years (typ).
3. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - grade 6 device).
Table 8. Power Down/Up AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C)
Symbol
Parameter
Min
E or W at VIH before Power Down
tPD
tF (1)
VPFD (max) to VPFD (min) VCC Fall Time
tFB (2)
VPFD (min) to VSS VCC Fall Time
Max
Unit
0
µs
300
µs
M48T35AY
10
µs
M48T35AV
150
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
tREC (3)
VPFD (max) to Inputs Recognized
40
200
ms
Note: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes V PFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
3. tREC (min) = 20ms for industrial temperature grade 6 device.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tDR
tPD
INPUTS
tRB
RECOGNIZED
tREC
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
7/19
M48T35AY, M48T35AV
Table 9. Read Mode AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 3.0V to 3.6V)
Symbol
M48T35AY
M48T35AV
-70
-100
Parameter
Min
tAVAV
Read Cycle Time
Max
70
Min
Unit
Max
100
ns
tAVQV (1)
Address Valid to Output Valid
70
100
ns
tELQV (1)
Chip Enable Low to Output Valid
70
100
ns
tGLQV (1)
Output Enable Low to Output Valid
35
50
ns
tELQX (2)
Chip Enable Low to Output Transition
5
10
ns
tGLQX (2)
Output Enable Low to Output Transition
5
5
ns
tEHQZ (2)
Chip Enable High to Output Hi-Z
25
50
ns
tGHQZ (2)
Output Enable High to Output Hi-Z
25
40
ns
tAXQX (1)
Address Transition to Output Transition
10
10
ns
Note: 1. CL = 100pF.
2. CL = 5pF.
Figure 6. Read Mode AC Waveforms.
tAVAV
VALID
A0-A14
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note: Write Enable (W) = High.
8/19
M48T35AY, M48T35AV
Table 10. Write Mode AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 3.0V to 3.6V)
Symbol
M48T35AY
M48T35AV
-70
-100
Parameter
Min
Max
Min
Unit
Max
tAVAV
Write Cycle Time
70
100
ns
tAVWL
Address Valid to Write Enable Low
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
ns
tWLWH
Write Enable Pulse Width
50
80
ns
tELEH
Chip Enable Low to Chip Enable High
55
80
ns
tWHAX
Write Enable High to Address Transition
0
10
ns
tEHAX
Chip Enable High to Address Transition
0
10
ns
tDVWH
Input Valid to Write Enable High
30
50
ns
tDVEH
Input Valid to Chip Enable High
30
50
ns
tWHDX
Write Enable High to Input Transition
5
5
ns
tEHDX
Chip Enable High to Input Transition
5
5
ns
tWLQZ (1, 2)
Write Enable Low to Output Hi-Z
25
50
ns
tAVWH
Address Valid to Write Enable High
60
80
ns
tAVEH
Address Valid to Chip Enable High
60
80
ns
Write Enable High to Output Transition
5
10
ns
tWHQX (1, 2)
Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Setting the Clock
Bit D7 of the Control Register 7FF8h is the WRITE
bit. Setting the WRITE bit to a '1', like the READ
bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 11). Resetting the WRITE bit to a '0' then
transfers the values of all time registers 7FF9h7FFFh to the actual TIMEKEEPER counters and
allows normal operation to resume. The FT bit and
the bits marked as '0' in Table 11 must be written
to '0' to allow for normal TIMEKEEPER and RAM
operation. After the WRITE bit is reset, the next
clock update will occur within one second.
See the Application Note AN923 "TIMEKEEPER
rolling into the 21st century" on the for information
on Century Rollover.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is the MSB of the seconds register. Setting it to
a '1' stops the oscillator. The M48T35AY/35AV is
shipped from STMicroelectronics with the STOP
bit set to a '1'. When reset to a '0', the M48T35AY/
35AV oscillator starts within 1 second.
9/19
M48T35AY, M48T35AV
Figure 7. Write Enable Controlled, Write AC Waveform
tAVAV
VALID
A0-A14
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A14
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
10/19
M48T35AY, M48T35AV
Calibrating the Clock
The M48T35AY/35AV is driven by a quartz controlled oscillator with a nominal frequency of
32,768Hz. The devices are tested not to exceed
35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes
per month. With the calibration bits properly set,
the accuracy of each M48T35AY/35AV improves
to better than ±4 ppm at 25°C.
The oscillation rate of any crystal changes with
temperature (see Figure 11). Most clock chips
compensate for crystal frequency and temperature shift error with cumbersome trim capacitors.
The M48T35AY/35AV design, however, employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Figure 9. The number of times pulses are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, subtracting counts slows the clock down.
The Calibration byte occupies the five lower order
bits (D4-D0) in the Control Register 7FF8h. These
bits can be set to represent any value between 0
and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative
calibration. Calibration occurs within a 64 minute
cycle. The first 62 minutes in the cycle may, once
per minute, have one second either shortened by
128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2
minutes in the 64 minute cycle will be modified; if
a binary 6 is loaded, the first 12 will be affected,
and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that
the oscillator is in fact running at exactly 32,768Hz,
each of the 31 increments in the Calibration byte
would represent +10.7 or –5.35 seconds per
month which corresponds to a total range of +5.5
or –2.75 minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T35AY/35AV may
require. The first involves simply setting the clock,
letting it run for a month and comparing it to a
known accurate reference (like WWV broadcasts).
While that may seem crude, it allows the designer
to give the end user the ability to calibrate his clock
as his environment may require, even after the final product is packaged in a non-user serviceable
enclosure.
All the designer has to do is provide a simple utility
that accesses the Calibration byte.
Figure 9. Checking the BOK Flag Status
POWER-UP
READ DATA
AT ANY ADDRESS
WRITE DATA
COMPLEMENT BACK
TO SAME ADDRESS
READ DATA
AT SAME
ADDRESS AGAIN
IS DATA
COMPLEMENT
OF FIRST
READ?
(BATTERY OK)
YES
NO (BATTERY LOW)
NOTIFY SYSTEM
OF LOW BATTERY
(DATA MAY BE
CORRUPTED)
WRITE ORIGINAL
DATA BACK TO
SAME ADDRESS
CONTINUE
AI00607
The second approach is better suited to a manufacturing environment, and involves the use of
some test equipment. When the Frequency Test
(FT) bit, the seventh-most significant bit in the Day
Register is set to a '1', and D7 of the Seconds Register is a '0' (Oscillator Running), DQ0 will toggle at
512Hz during a read of the Seconds Register. Any
deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024Hz
would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into
the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency.
The FT bit MUST be reset to '0' for normal clock
operations to resume. The FT bit is automatically
Reset on power-up.
For more information on calibration, see the Application Note AN934 "TIMEKEEPER Calibration".
11/19
M48T35AY, M48T35AV
Table 11. Register Map
Data
Address
D7
7FFFh
D6
D5
D4
D3
10 Years
0
10 M.
D2
D1
D0
Function/Range
BCD Format
Year
Year
00-99
Month
Month
01-12
Date
Date
01-31
Century/Day
00-01/01-07
Hours
Hour
00-23
7FFEh
0
0
7FFDh
0
0
7FFCh
0
FT
7FFBh
0
0
7FFAh
0
10 Minutes
Minutes
Minutes
00-59
7FF9h
ST
10 Seconds
Seconds
Seconds
00-59
7FF8h
W
10 Date
CEB
CB
10 Hours
R
S
0
Day
Calibration
Control
Keys:
S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to ‘0’ upon power for normal operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to ‘0’
CEB = Century Enable Bit
CB = Century Bit
Note: When CEB is set to ‘1’, CB will toggle from ‘0’ to ‘1’ or from ‘1’ to ‘0’ at the turn of the century (dependent upon the initial value set).
When CEB is set to ‘0’, CB will not toggle.
The WRITE Bit does not need to be set to write to CEB and CB.
Figure 10. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
12/19
M48T35AY, M48T35AV
Figure 11. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
∆F = -0.038 ppm (T - T )2 ± 10%
0
F
C2
-60
T0 = 25 °C
-80
-100
0
5
10
15
20
25
30
35
40
45
50
55
60
65
°C
70
AI02124
POWER SUPPLY DECOUPLING and
UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy, which stabilizes the V CC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass capacitor value of 0.1µF (as shown in Figure 12) is
recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on V CC that drive it to values
below V SS by as much as one Volt. These negative spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to connect a schottky diode from V CC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 12. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
13/19
M48T35AY, M48T35AV
Table 12. Ordering Information Scheme
Example:
M48T35AY
-70 MH
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
35AY = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V
35AV = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V
Speed
-70 = 70ns (35AY)
-10 = 100ns (35AV)
Package
PC = PCDIP28
MH (1) = SOH28
Temperature Range
1 = 0 to 70 °C
6 (2) = –40 to 85 °C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4TXX-BR00SH1" in plastic tube or "M4TXX-BR00SH1TR" in Tape & Reel form.
2. Available in SOIC package only.
Caution: Do not place the SNAPHAT battery package "M4TXX-BR00SH1" in conductive foam since will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
Table 13. Revision History
Date
Revision Details
November 1999
First Issue
04/21/00
From Preliminary Data to Data Sheet
05/29/00
tFB change (Table 8)
14/19
M48T35AY, M48T35AV
Table 14. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
8.89
A1
Typ
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
29.72
36.32
1.170
1.430
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
28
Figure 13. PCDIP28 - 28 pin Plastic DIP, battery CAPHAT, Package Outline
A2
A1
B1
B
e1
A
L
C
eA
e3
D
N
E
1
PCDIP
Drawing is not to scale.
15/19
M48T35AY, M48T35AV
Table 15. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
1.27
0.050
28
CP
0.10
0.004
Figure 14. SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
1
SOH-A
Drawing is not to scale.
16/19
α
L
M48T35AY, M48T35AV
Table 16. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
Max
9.78
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
Figure 15. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHTK-A
Drawing is not to scale.
17/19
M48T35AY, M48T35AV
Table 17. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
Max
10.54
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
Figure 16. M4T32-BR12SH SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHTK-A
Drawing is not to scale.
18/19
M48T35AY, M48T35AV
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19/19