AD ADA4077-1ARMZ-RL 4 mhz, 7 nv/â hz, low offset and drift, high precision amplifier Datasheet

4 MHz, 7 nV/√Hz, Low Offset and
Drift, High Precision Amplifiers
ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
PIN CONNECTION DIAGRAMS
Offset voltage and offset voltage drift
B grade: 25 µV and 0.25 µV/°C at VSY = ±5 V
A grade maximum offset at 25°C and maximum drift from
−40°C to +125°C
SOIC: 50 µV and 0.55 µV/°C single/dual and 0.75 µV/°C quad
MSOP: 90 µV and 1.2 µV/°C dual and 120 µV and 1.2 µV/°C
single
TSSOP: 120 µV and 1.2 µV/°C quad
MSL1 rated
Low input bias current: 1 nA maximum at TA = 25°C
Low voltage noise density: 6.9 nV/√Hz typical at f = 1000 Hz
CMRR, PSRR, and AV > 120 dB minimum
Low supply current: 400 µA per amplifier typical
Wide gain bandwidth product: 3.9 MHz at ±5 V
Dual-supply operation: ±2.5 V to ±15 V
Unity gain stable
No phase reversal
2
+IN
3
V–
4
ADA4077-1
TOP VIEW
(Not to Scale)
8
NC
7
V+
6
OUT
5
NC
8
V+
–IN A 2
ADA4077-2
7
OUT B
+IN A 3
TOP VIEW
(Not to Scale)
6
–IN B
5
+IN B
OUT A 1
V– 4
10238-001
Figure 1. ADA4077-1, 8-Lead SOIC (and 8-Lead MSOP)
OUT A 1
–IN A
2
14
OUT D
13
–IN D
+IN A 3
ADA4077-4
12
+IN D
V+
4
TOP VIEW
(Not to Scale)
11
V–
+IN B
5
10
+IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
10238-202
Figure 2. ADA4077-2, 8-Lead MSOP (and 8-Lead SOIC)
Figure 3. ADA4077-4, 14-Lead TSSOP (and 14-Lead SOIC)
The ADA4077-1 and ADA4077-2 are available in an 8-lead SOIC
package, including the B grade, and in an 8-lead MSOP (A grade
only). The ADA4077-4 is offered in a 14-lead TSSOP and a 14-lead
SOIC package.
200
GENERAL DESCRIPTION
160
140
120
100
80
60
40
20
0
VOS (µV)
10238-103
Unlike amplifiers by some competitors, the ADA4077-1/
ADA4077-2/ADA4077-4 have an MSL1 rating that is compliant
with the most stringent of assembly processes, and they are
specified over the extended industrial temperature range from
−40°C to +125°C for the most demanding operating environments.
VSY = ±5V
SOIC
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
MORE
Applications for this amplifier include sensor signal conditioning
(such as thermocouples, RTDs, strain gauges), process control
front-end amplifiers, and precision diode power measurement
in optical and wireless transmission systems. The ADA4077-1,
ADA4077-2, and ADA4077-4 are useful in line powered and
portable instrumentation, precision filters, and voltage or
current measurement and level setting.
180
NUMBER OF AMPLIFIERS
The single ADA4077-1, dual ADA4077-2, and quad ADA4077-4
amplifiers feature extremely low offset voltage and drift, and low
input bias current, noise, and power consumption. Outputs are
stable with capacitive loads of more than 1000 pF with no
external compensation.
Rev. D
1
NC = NO CONNECT. NOT INTERNALLY CONNECTED.
APPLICATIONS
Process control front-end amplifiers
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls: thermocouples, RTDs, strain bridges,
and shunt current measurements
Precision filters
NC
–IN
10238-101
FEATURES
Figure 4. Offset Voltage Distribution
Table 1. Evolution of Precision Devices by Generation
Op Amp
Single
Dual
Quad
First
OP07
Second
OP77
Third
OP177
Fourth
OP1177
OP2177
OP4177
Fifth
AD8677
Sixth
ADA4077-1
ADA4077-2
ADA4077-4
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ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................7
Applications ....................................................................................... 1
Pin Configurations and Function Descriptions ............................8
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 11
Pin Connection Diagrams ............................................................... 1
Theory of Operation ...................................................................... 21
Revision History ............................................................................... 2
Applications Information .............................................................. 22
Specifications..................................................................................... 3
Output Phase Reversal ............................................................... 22
Electrical Characteristics, ±5 V .................................................. 3
Low Power Linearized RTD ...................................................... 22
Electrical Characteristics, ±15 V ................................................ 5
Proper Board Layout .................................................................. 22
Absolute Maximum Ratings ....................................................... 7
Outline Dimensions ....................................................................... 23
Thermal Resistance ...................................................................... 7
Ordering Guide .......................................................................... 25
REVISION HISTORY
10/2016—Rev. C to Rev. D
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Figure 19 ...................................................................... 12
Changes to Figure 23 and Figure 26............................................. 13
Changes to Figure 29, Figure 30, Figure 32, and Figure 33 ...... 14
6/2015—Rev. B to Rev. C
Change to Figure 63 ....................................................................... 18
1/2014—Rev. A to Rev. B
Added ADA4077-1 ............................................................. Universal
Changes to Features Section............................................................ 1
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Added Figure 5, Figure 6, and Table 6; Renumbered
Sequentially ....................................................................................... 7
Changes to Figure 17, Figure 20, and Figure 21 ......................... 11
Changes to Figure 65 ...................................................................... 19
Added Figure 67 and Figure 68 .................................................... 19
Changes to Output Phase Reversal Section and Figure 70 ....... 21
Changes to Ordering Guide .......................................................... 24
10/2013—Rev. 0 to Rev. A
Added ADA4077-4............................................................. Universal
Changes to Features, General Description, and Figure 1.............1
Deleted Figure 2; Renumbered Sequentially .................................1
Added Figure 2 ..................................................................................1
Changes to Table 2.............................................................................3
Changes to Table 3.............................................................................4
Changes to Table 4.............................................................................6
Added Figure 6, Figure 7, and Table 7; Renumbered
Sequentially ........................................................................................8
Changes to Typical Performance Characteristics Section ...........9
Changes to Figure 65...................................................................... 20
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 23
10/2012—Revision 0: Initial Version
Rev. D | Page 2 of 25
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, ±5 V
VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
ADA4077-1/ADA4077-2
B Grade, SOIC
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
10
25
65
50
105
90
220
µV
µV
µV
µV
µV
µV
50
105
120
220
µV
µV
µV
µV
0.1
0.25
0.5
0.25
0.55
1.2
µV/°C
µV/°C
µV/°C
0.4
0.5
−0.4
0.75
1.2
+1
+1.5
+0.5
+1
+3
5
70
µV/°C
µV/°C
nA
nA
nA
nA
V
dB
dB
dB
dB
dB
pF
GΩ
±10
22
0.05
V
V
V
V
mA
mA
Ω
VOS
−40°C < TA < +125°C
A Grade, SOIC
15
−40°C < TA < +125°C
A Grade, MSOP
50
−40°C < TA < +125°C
ADA4077-4
A Grade, SOIC
15
−40°C < TA < +125°C
A Grade, TSSOP
Offset Voltage Drift
ADA4077-1/ADA4077-2
B Grade, SOIC
A Grade, SOIC
A Grade, MSOP
ADA4077-4
A Grade, SOIC
A Grade, TSSOP
Input Bias Current
15
∆VOS/∆T
−40°C < TA < +125°C
−40°C < TA < +125°C
IB
−40°C < TA < +125°C
Input Offset Current
IOS
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
Av
Input Capacitance
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
Short-Circuit Current
Closed-Loop Output Impedance
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
CINCM
RIN
VOH
VOL
IOUT
ISC
ZOUT
PSRR
ISY
VCM = −3.8 V to +3 V
VCM = −3.8 V to +3 V, −40°C < TA < +85°C
VCM = −3.8 V to +2.8 V, 85°C < TA < 125°C
RL = 2 kΩ, VO = −3.0 V to +3.0 V
−40°C < TA < +125°C
Common mode
Common mode
−1
−1.5
−0.5
−1
−3.8
122
120
120
121
120
IL = 1 mA
−40°C < TA < +125°C
IL = 1 mA
−40°C < TA < +125°C
VDROPOUT < 1.6 V
TA = 25°C
f = 1 kHz, AV = +1
3.8
3.7
VS = ±2.5 V to ±18 V
−40°C < TA < +125°C
VO = 0 V
−40°C < TA < +125°C
123
120
Rev. D | Page 3 of 25
+0.1
140
130
−3.8
−3.7
128
400
450
650
dB
dB
µA
µA
ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
Parameter
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.1%
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Phase Margin
Total Harmonic Distortion Plus Noise
Symbol
Test Conditions/Comments
SR
tS
GBP
UGC
−3 dB
ΦM
THD + N
RL = 2 kΩ
VIN = 1 V step, RL = 2 kΩ, AV = −1
VIN = 10 mV p-p, RL = 2 kΩ, AV = +100
VIN = 10 mV p-p, RL = 2 kΩ, AV = +1
AV = +1, VIN = 10 mV p-p, RL = 2 kΩ
VIN = 10 mV p-p, RL = 2 kΩ, AV = +1
VIN = 1 V rms, AV = +1, RL = 2 kΩ,
f = 1 kHz
1.2
3
3.9
3.9
5.9
55
0.004
V/µs
µs
MHz
MHz
MHz
Degrees
%
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
Current Noise Density
MULTIPLE AMPLIFIERS CHANNEL SEPARATION
in
CS
0.1 Hz to 10 Hz
f = 1 Hz
f = 100 Hz
f = 1000 Hz
f = 1 kHz
f = 1 kHz, RL = 10 kΩ
0.25
13
7
6.9
0.2
−125
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
dB
Rev. D | Page 4 of 25
Min
Typ
Max
Unit
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
ELECTRICAL CHARACTERISTICS, ±15 V
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
ADA4077-1/ADA4077-2
B Grade, SOIC
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
10
35
65
50
105
90
220
µV
µV
µV
µV
µV
µV
50
105
120
220
µV
µV
µV
µV
VOS
−40°C < TA < +125°C
A Grade, SOIC
15
−40°C < TA < +125°C
A Grade, MSOP
50
−40°C < TA < +125°C
ADA4077-4
A Grade, SOIC
15
−40°C < TA < +125°C
A Grade, TSSOP
15
−40°C < TA < +125°C
Offset Voltage Drift
ADA4077-1/ADA4077-2
B Grade, SOIC
∆VOS/∆T
−40°C < TA < +125°C
0.1
0.25
µV/°C
−40°C < TA < +125°C
0.25
0.55
µV/°C
−40°C < TA < +125°C
0.5
1.2
µV/°C
−40°C < TA < +125°C
−40°C < TA < +125°C
0.4
0.5
−0.4
0.75
1.2
+1
+1.5
+0.5
+1
+13
µV/°C
µV/°C
nA
nA
nA
nA
V
dB
dB
A Grade, SOIC
A Grade, MSOP
ADA4077-4
A Grade, SOIC
A Grade, TSSOP
Input Bias Current
IB
−40°C < TA < +125°C
Input Offset Current
IOS
−40°C < TA < +125°C
Input Voltage Range
Common-Mode Rejection Ratio
Large Signal Voltage Gain
ADA4077-1/ADA4077-2 (SOIC, MSOP)
CMRR
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage High
+0.1
150
Av
ADA4077-4 (SOIC, TSSOP)
Input Capacitance
VCM = −13.8 V to +13 V
−40°C < TA < +125°C
−1
−1.5
−0.5
−1
−13.8
132
130
CINDM
CINCM
RIN
VOH
Output Voltage Low
VOL
Output Current
Short-Circuit Current
Closed-Loop Output Impedance
IOUT
ISC
ZOUT
RL = 2 kΩ, VO = −13.0 V to +13.0 V
−40°C < TA < +125°C
RL = 2 kΩ, VO = −13.0 V to +13.0 V
−40°C < TA < +125°C
Differential mode
Common mode
Common mode
125
120
122
120
IL = 1 mA
−40°C < TA < +125°C
IL = 1 mA
−40°C < TA < +125°C
VDROPOUT < 1.2 V
TA = 25°C
f = 1 kHz, AV = +1
13.8
13.7
Rev. D | Page 5 of 25
130
3
5
70
dB
dB
dB
dB
pF
pF
GΩ
±10
22
0.05
V
V
V
V
mA
mA
Ω
130
−13.8
−13.7
ADA4077-1/ADA4077-2/ADA4077-4
Parameter
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
Data Sheet
Symbol
Test Conditions/Comments
Min
Typ
PSRR
VS = ±2.5 V to ±18 V
−40°C < TA < +125°C
VO = 0 V
−40°C < TA < +125°C
123
120
128
ISY
400
Max
Unit
500
650
dB
dB
µA
µA
DYNAMIC PERFORMANCE
Slew Rate
Settling Time to 0.01%
Settling Time to 0.1%
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Phase Margin
Total Harmonic Distortion Plus Noise
SR
ts
ts
GBP
UGC
−3 dB
ΦM
THD + N
RL = 2 kΩ
VIN = 10 V p-p, RL = 2 kΩ, AV = −1
VIN = 10 V p-p, RL = 2 kΩ, AV = −1
VIN = 10 mV p-p, RL = 2 kΩ, AV = +100
VIN = 10 mV p-p, RL = 2 kΩ, AV = +1
AV = +1, VIN = 10 mV p-p, RL = 2 kΩ
VIN = 10 mV p-p, RL = 2 kΩ, AV = +1
VIN = 1 V rms, AV = +1, RL = 2 kΩ,
f = 1 kHz
1.2
16
10
3.6
3.9
5.5
58
0.004
V/µs
µs
µs
MHz
MHz
MHz
Degrees
%
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
en p-p
en
Current Noise Density
MULTIPLE AMPLIFIERS CHANNEL SEPARATION
in
CS
0.1 Hz to 10 Hz
f = 1 Hz
f = 100 Hz
f = 1000 Hz
f = 1 kHz
f = 1 kHz, RL = 10 kΩ
0.25
13
7
6.9
0.2
−125
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
dB
Rev. D | Page 6 of 25
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
Supply Voltage
Input Voltage
Input Current1
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature, Soldering (10 sec)
ESD Human Body Model (HBM)2
Field Induced Charge Device Model (FICDM)3
Rating
36 V
±VSY
±10 mA
±VSY
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
6 kV
1.25 kV
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
8-Lead MSOP
8-Lead SOIC
14-Lead TSSOP
14-Lead SOIC
ESD CAUTION
1
The input pins have clamp diodes to the power supply pins and to each
other. Limit the input current to 10 mA or less whenever input signals
exceed the power supply rail by 0.3 V.
2
ESDA/JEDEC JS-001-2011 applicable standard.
3
JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 7 of 25
θJA
190
158
240
115
θJC
44
43
43
36
Unit
°C/W
°C/W
°C/W
°C/W
ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
1
2
+IN
3
V–
4
ADA4077-1
TOP VIEW
(Not to Scale)
8
NC
NC
1
7
V+
–IN
2
6
OUT
+IN
3
5
NC
V–
4
NC = NO CONNECT. NOT INTERNALLY CONNECTED.
10238-205
NC
–IN
NC
7
V+
6
OUT
5
NC
Figure 6. ADA4077-1 Pin Configuration, 8-Lead SOIC (R-8)
Table 6. ADA4077-1 Pin Function Descriptions, 8-Lead MSOP and 8-Lead SOIC
Mnemonic
NC
−IN
+IN
V−
OUT
V+
TOP VIEW
(Not to Scale)
8
NC = NO CONNECT. NOT INTERNALLY CONNECTED.
Figure 5. ADA4077-1 Pin Configuration, 8-Lead MSOP (RM-8)
Pin No.
1, 5, 8
2
3
4
6
7
ADA4077-1
10238-105
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Description
No Connect. Not internally connected.
Inverting Input.
Noninverting Input.
Negative Supply Voltage.
Output.
Positive Supply Voltage.
Rev. D | Page 8 of 25
ADA4077-1/ADA4077-2/ADA4077-4
OUT A 1
8
V+
–IN A 2
ADA4077-2
7
OUT B
–IN A 2
ADA4077-2
+IN A 3
TOP VIEW
(Not to Scale)
6
–IN B
+IN A 3
5
+IN B
TOP VIEW
(Not to Scale)
10238-004
V– 4
OUT A 1
V– 4
Table 7. ADA4077-2 Pin Function Descriptions, 8-Lead MSOP and 8-Lead SOIC
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
V+
7
OUT B
6
–IN B
5
+IN B
Figure 8. ADA4077-2 Pin Configuration, 8-Lead SOIC
Figure 7. ADA4077-2 Pin Configuration, 8-Lead MSOP
Pin No.
1
2
3
4
5
6
7
8
8
10238-005
Data Sheet
Description
Output Channel A.
Inverting Input Channel A.
Noninverting Input Channel A.
Negative Supply Voltage.
Noninverting Input Channel B.
Inverting Input Channel B.
Output Channel B.
Positive Supply Voltage.
Rev. D | Page 9 of 25
ADA4077-1/ADA4077-2/ADA4077-4
–IN A
14
2
13
OUT A 1
OUT D
–IN D
+IN A 3
13 –IN D
ADA4077-4
12 +IN D
+IN A 3
ADA4077-4
12
+IN D
V+
4
TOP VIEW
(Not to Scale)
11
V–
+IN B 5
+IN B
5
10
+IN C
–IN B 6
9
–IN C
–IN B
6
9
–IN C
OUT B 7
8
OUT C
OUT B
7
8
OUT C
10238-206
V+ 4
Table 8. ADA4077-4 Pin Function Descriptions, 14-Lead TSSOP and 14-Lead SOIC
Mnemonic
OUT A
−IN A
+IN A
V+
+IN B
−IN B
OUT B
OUT C
−IN C
+IN C
V−
+IN D
−IN D
OUT D
TOP VIEW
(Not to Scale)
11 V–
10 +IN C
Figure 10. ADA4077-4 Pin Configuration, 14-Lead SOIC
Figure 9. ADA4077-4 Pin Configuration, 14-Lead TSSOP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
14 OUT D
–IN A 2
10238-207
OUT A 1
Data Sheet
Description
Output Channel A.
Negative Input Channel A.
Positive Input Channel A.
Positive Supply Voltage.
Positive Input Channel B.
Negative Input Channel B.
Output Channel B.
Output Channel C.
Negative Input Channel C.
Positive Input Channel C.
Negative Supply Voltage.
Positive Input Channel D.
Negative Input Channel D.
Output Channel D.
Rev. D | Page 10 of 25
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
TYPICAL PERFORMANCE CHARACTERISTICS
140
120
VSY = ±5V
MSOP
NUMBER OF AMPLIFIERS
60
40
100
80
60
40
20
20
0
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
MORE
VOS (µV)
Figure 11. ADA4077-2 Offset Voltage (VOS) Distribution, VSY = ±5 V
Figure 14. ADA4077-2 Offset Voltage (VOS) Distribution, VSY = ±15 V
200
200
VSY = ±5V
SOIC
180
VSY = ±15V
SOIC
180
160
NUMBER OF AMPLIFIERS
160
120
100
80
60
140
120
100
80
60
20
0
0
10238-144
VOS (µV)
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
MORE
40
20
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
MORE
40
VOS (µV)
Figure 12. Offset Voltage (VOS) Distribution, VSY = ±5 V
10238-009
140
Figure 15. Offset Voltage (VOS) Distribution, VSY = ±15 V
20
15
VSY = ±5V
VSY = ±15V
10
10
5
VOS (µV)
15
5
0
0
–5
–5
–10
–10
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
10238-210
VOS (µV)
10238-003
VOS (µV)
10238-006
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
MORE
0
Figure 13. Offset Voltage (VOS) vs. Temperature, VSY = ±5 V
–15
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 16. Offset Voltage (VOS) vs. Temperature, VSY = ±15 V
Rev. D | Page 11 of 25
10238-213
NUMBER OF AMPLIFIERS
80
NUMBER OF AMPLIFIERS
VSY = ±15V
MSOP
120
100
ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
70
50
VSY = ±15V, ±5V
SOIC, A GRADE
VSY = ±15V, ±5V
TSSOP AND MSOP, A GRADE
45
60
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
40
35
30
25
20
15
50
40
30
20
10
10
5
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
10238-130
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
TCVOS (µV/°C)
TCVOS (µV/°C)
10238-008
0
0
Figure 20. TCVOS (SOIC, A Grade)
Figure 17. TCVOS (TSSOP and MSOP, A Grade)
10
140
VSY = ±15V, ±5V
SOIC, B GRADE
120
NUMBER OF AMPLIFIERS
VOS (µV)
5
0
–5
100
80
60
40
20
10
15
20
25
30
35
VSY (V)
0
TCVOS (µV/°C)
10238-308
5
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
0
10238-134
–10
Figure 21. TCVOS (SOIC, B Grade)
Figure 18. Offset Voltage (VOS) vs. Voltage Supplies (VSY)
0.6
100
VS = ±15V
–15V ≤ V CM ≤ +15V
80
60
0.4
20
ISY (mA)
VOS (µV)
40
0
–20
0.2
–40°C
+25°C
+85°C
+125°C
–60
AVERAGE
AVERAGE +3σ
AVERAGE –3σ
–100
–15 –13 –11 –9 –7 –5 –3 –1
1
VCM (V)
3
5
7
9
11 13 15
0
10238-419
–80
Figure 19. Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±15 V
VO = 0V
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38
VSY (V)
10238-218
–40
Figure 22. Supply Current per Amplifier (ISY) vs. Power Supply Voltage (VSY)
Rev. D | Page 12 of 25
Data Sheet
VOH = 1mA
VOL = 1mA
14.10
4.05
4.00
3.95
3.90
3.85
14.05
14.00
13.95
13.90
13.85
13.80
3.80
–25
0
25
50
75
100
125
TEMPERATURE (°C)
13.75
–50
10238-423
3.75
–50
0
25
50
75
125
Figure 23. Output Voltage Swing vs. Temperature, VSY = ±5 V
Figure 26. Output Voltage Swing vs. Temperature, VSY = ±15 V
350
400
VSY = ±15V
350
150
MORE
0
–0.1
–0.2
–1
INPUT BIAS CURRENT (nA)
Figure 24. Input Bias Current, VSY = ±5 V
10238-016
INPUT BIAS CURRENT (nA)
10238-013
0
MORE
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
0
–0.8
0
–0.9
50
–1.0
50
–0.3
100
–0.4
100
200
–0.5
150
250
–0.6
200
300
–0.7
250
–0.8
NUMBER OF AMPLIFIERS
300
Figure 27. Input Bias Current, VSY = ±15 V
0
0
VSY = ±5V
VSY = ±15V
–0.1
–0.1
–0.2
–0.2
+IB
–IB
–IB
IB (nA)
–0.3
–0.4
–0.3
–0.4
–0.5
–0.5
–0.6
–0.6
–0.7
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 25. Input Bias Current (IB) vs. Temperature, VSY = ±5 V
–0.7
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 28. Input Bias Current (IB) vs. Temperature, VSY = ±15 V
Rev. D | Page 13 of 25
10238-017
+IB
10238-014
IB (nA)
100
TEMPERATURE (°C)
VSY = ±5V
NUMBER OF AMPLIFIERS
–25
10238-426
VS = ±15V
VS = ±5V
–0.9
OUTPUT VOLTAGE SWING (V)
4.10
14.15
VOH = 1mA
VOL = 1mA
OUTPUT VOLTAGE SWING (V)
4.15
ADA4077-1/ADA4077-2/ADA4077-4
ADA4077-1/ADA4077-2/ADA4077-4
100k
1k
100
OUTPUT DROPOUT VOLTAGE (mV)
0.1
1
10
100
–150
10k
100k
1M
–50
–150
100M
FREQUENCY (Hz)
0.1
1
10
100
150
VSY = ±15V
AV = –1
RL = 2kΩ
100
50
0
0
–50
–100
10M
0.01
50
GAIN (dB)
PHASE WITH CL = 0pF
PHASE WITH CL = 100pF
PHASE WITH CL = 200pF
GAIN WITH CL = 0pF
GAIN WITH CL = 100pF
GAIN WITH CL = 200pF
100
–100
10238-227
GAIN (dB)
0
0
–100
150
PHASE MARGIN (Degrees)
50
VS = ±15V
–40°C ≤ T ≤ +125°C
Figure 33. Output Dropout Voltage vs. ILOAD, Source Current, VSY = ±15 V
100
50
–50
= –40°C
= +25°C
= +85°C
= +125°C
ILOAD (mA)
150
VSY = ±5V
AV = –1
RL = 2kΩ
100
1k
100
0.001
Figure 30. Output Saturation Voltage vs. ILOAD, Source Current, VSY = ±5 V
100
ISOURCE
ISOURCE
ISOURCE
ISOURCE
VS = ±5V
–40°C ≤ T ≤ +125°C
0.01
10
10k
10238-430
OUTPUT DROPOUT VOLTAGE (mV)
100k
= –40°C
= +25°C
= +85°C
= +125°C
ILOAD (mA)
150
1
Figure 32. Output Saturation Voltage vs. ILOAD, Sink Current, VSY = ±15 V
1k
100
0.001
0.1
ILOAD (mA)
Figure 29. Output Saturation Voltage vs. ILOAD, Sink Current, VSY = ±5 V
ISOURCE
ISOURCE
ISOURCE
ISOURCE
0.01
10238-433
10
–150
10k
Figure 31. Open-Loop Gain and Phase vs. Frequency, VSY = ±5 V
PHASE WITH CL = 0pF
PHASE WITH CL = 100pF
PHASE WITH CL = 200pF
GAIN WITH CL = 0pF
GAIN WITH CL = 100pF
GAIN WITH CL = 200pF
100k
1M
–50
–100
10M
–150
100M
FREQUENCY (Hz)
Figure 34. Open-Loop Gain and Phase vs. Frequency, VSY = ±15 V
Rev. D | Page 14 of 25
PHASE MARGIN (Degrees)
1
VS = ±15V
–40°C ≤ T ≤ +125°C
100
0.001
10238-230
0.1
ILOAD (mA)
10k
1k
VS = ±5V
–40°C ≤ T ≤ +125°C
0.01
= –40°C
= +25°C
= +85°C
= +125°C
10k
10238-429
100
0.001
ISINK
ISINK
ISINK
ISINK
10238-432
ISINK = –40°C
ISINK = +25°C
ISINK = +85°C
ISINK = +125°C
OUTPUT DROPOUT VOLTAGE (mV)
OUTPUT DROPOUT VOLTAGE (mV)
10k
Data Sheet
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
140
133
VSY = ±15V
VSY = ±5V
VSY = ±5V TO ±15V
132
120
131
100
CMRR (dB)
PSRR (dB)
130
129
128
127
80
60
40
126
20
–25
0
25
50
75
100
125
TEMPERATURE (°C)
0
100
10238-035
124
–50
10k
1k
1M
100k
Figure 35. PSRR vs. Temperature, VSY = ±5 V to ±15 V
Figure 38. CMRR vs. Frequency, VSY = ±5 V and VSY = ±15 V
120
120
VSY = ±15V
VSY = ±5V
100
100
80
80
PSRR (dB)
PSRR (dB)
10M
FREQUENCY (Hz)
10238-029
125
60
PSRR–
40
60
PSRR–
40
PSRR+
20
20
0
0
10k
1k
100k
1M
10M
FREQUENCY (Hz)
–20
100
10238-034
–20
100
10k
1k
100k
1M
10M
FREQUENCY (Hz)
Figure 36. PSRR vs. Frequency, VSY = ±5 V
10238-037
PSRR+
Figure 39. PSRR vs. Frequency, VSY = ±15 V
152
159
151
VSY = ±15V
VSY = ±5V
158
150
149
157
CMRR (dB)
147
146
145
156
155
144
143
154
141
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
125
153
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
Figure 40. CMRR vs. Temperature, VSY = ±15 V
Figure 37. CMRR vs. Temperature, VSY = ±5 V
Rev. D | Page 15 of 25
125
10238-033
142
10238-030
CMRR (dB)
148
ADA4077-1/ADA4077-2/ADA4077-4
50
50
VSY = ±5V
G = 100
40
Data Sheet
30
10
G=1
0
–10
–20
10
–10
–20
–30
–40
–40
10k
100k
1M
10M
100M
FREQUENCY (Hz)
G=1
0
–30
–50
1k
G = 10
20
–50
1k
10M
100M
1k
VSY = ±15V
VSY = ±5V
100
AV = +1
1
0.1
0.1
0.01
0.01
1k
10k
100k
1M
10M
FREQUENCY (Hz)
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 45. Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V
Figure 42. Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V
10238-040
VOLTAGE (1V/DIV)
VSY = ±5V
VIN = 1V p-p
AV = +1
RL = 2kΩ
CL = 300pF
TIME (100µs/DIV)
AV = +1
0.001
100
10238-036
0.001
100
AV = +10
0V
VSY = ±15V
VIN = 4V p-p
AV = +1
RL = 2kΩ
CL = 300pF
TIME (100µs/DIV)
Figure 43. Large Signal Transient Response, VSY = ±5 V
Figure 46. Large Signal Transient Response, VSY = ±15 V
Rev. D | Page 16 of 25
10238-043
1
AV = +100
10
AV = +10
ZOUT (Ω)
AV = +100
10
10238-039
100
ZOUT (Ω)
1M
Figure 44. Closed-Loop Gain vs. Frequency, VSY = ±15 V
1k
VOLTAGE (0.2V/DIV)
100k
FREQUENCY (Hz)
Figure 41. Closed-Loop Gain vs. Frequency, VSY = ±5 V
0V
10k
10238-031
20
CLOSED-LOOP GAIN (dB)
G = 10
10238-028
CLOSED-LOOP GAIN (dB)
30
VSY = ±15V
G = 100
40
ADA4077-1/ADA4077-2/ADA4077-4
0.20
0.15
0.15
0.10
0.10
0.05
0.05
0
–0.05
VSY = ±5V
VIN = 100mV p-p
AV = +1
LOAD = 2kΩ||1000pF
–0.10
–0.15
–0.20
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0
–0.05
–0.15
0.5
0.6
0.7
0.8
TIME (ms)
–0.20
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
TIME (ms)
Figure 50. Small Signal Transient Response, VSY = ±15 V
Figure 47. Small Signal Transient Response, VSY = ±5 V
0.5
0.5
35
0
30
–0.5
25
INPUT
INPUT (V)
–1.0
5
3
1
OUTPUT
–1
TIME (10µs/DIV)
20
VSY = ±15V
VIN = 200mV p-p
AV = –100
LOAD = 10kΩ
–1.5
–2.0
15
10
–2.5
5
–3.0
0
–3.5
–10
–5
0
10
20
30
40
50
60
70
80
10238-248
VSY = ±5V
AV = –100
VIN = 200mV
RL = 10kΩ
OUTPUT VOLTAGE (V)
90
TIME (µs)
Figure 51. Positive Overload Recovery, VSY = ±15 V
INPUT VOLTAGE (V)
0.5
INPUT
0
–0.5
0.5
INPUT
0
–0.5
OUTPUT
–1
VSY = ±5V
AV = –100
VIN = 200mV
RL = 10kΩ
–3
–5
TIME (10µs/DIV)
OUTPUT VOLTAGE (V)
OUTPUT
–5
VSY = ±15V
AV = –100
VIN = 200mV
RL = 10kΩ
–15
TIME (10µs/DIV)
Figure 52. Negative Overload Recovery, VSY = ±15 V
Figure 49. Negative Overload Recovery, VSY = ±5 V
Rev. D | Page 17 of 25
–10
OUTPUT VOLTAGE (V)
0
1
10238-047
INPUT VOLTAGE (V)
Figure 48. Positive Overload Recovery, VSY = ±5 V
10238-051
–0.5
OUTPUT (V)
0
10238-046
INPUT VOLTAGE (V)
VSY = ±15V
VIN = 100mV p-p
AV = +1
LOAD = 2kΩ||1000pF
–0.10
10238-247
VOLTAGE (V)
0.20
10238-344
VOLTAGE (V)
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
40
35
30
OVERSHOOT (%)
25
20
15
OS+
OS–
10
15
OS+
OS–
10n
0
1p
100p
1n
Figure 56. Small Signal Overshoot vs. Load Capacitance, VSY = ±15 V
0.25
0.04
0.20
0.03
0.15
0.02
0.10
0
INPUT (V)
OUTPUT (V)
0.05
0.01
0.05
0
–0.01
VSY = ±15V
VIN = 10V p-p
RL = 2kΩ
10238-251
–0.02
–0.03
TIME (1µs/DIV)
Figure 57. Positive 0.1% Settling Time, VSY = ±15 V
0.25
0.04
0.20
VSY = ±15V
VIN = 10V p-p
RL = 2kΩ
0.03
0
INPUT (V)
0.01
0.15
0.10
OUTPUT (V)
0.02
0.05
0
–0.01
–0.05
–0.02
–0.10
–0.03
10238-252
INPUT (V)
–0.10
–0.15
0.05
TIME (1µs/DIV)
–0.05
TIME (1µs/DIV)
Figure 54. Positive 0.1% Settling Time, VSY = ±5 V
VSY = ±5V
VIN = 1V p-p
RL = 2kΩ
10n
LOAD CAPACITANCE (F)
Figure 53. Small Signal Overshoot vs. Load Capacitance, VSY = ±5 V
VSY = ±5V
VIN = 1V p-p
RL = 2kΩ
10p
OUTPUT (V)
1n
10238-254
100p
10238-250
10p
10238-253
5
LOAD CAPACITANCE (F)
INPUT (V)
20
10
5
0
1p
25
Figure 55. Negative 0.1% Settling Time, VSY = ±5 V
–0.15
TIME (1µs/DIV)
Figure 58. Negative 0.1% Settling Time, VSY = ±15 V
Rev. D | Page 18 of 25
OUTPUT (V)
OVERSHOOT (%)
30
VSY = ±15V
RL = 2kΩ
10238-255
35
40
VSY = ±5V
RL = 2kΩ
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
100
VSY = ±15V
VSY = ±5V
AV = +1
VSY = ±5V
VSY = ±15V
90
VOLTAGE NOISE CORNER (nV/√Hz)
VOLTAGE NOISE DENSITY (nV/√Hz)
1k
100
10
80
70
60
50
40
30
20
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
10238-053
100
Figure 59. Voltage Noise Density vs. Frequency, VSY = ±5 V and VSY = ±15 V
0
0.5
1.0
1.5
2.0
3.0
2.5
FREQUENCY (Hz)
10238-153
10
1
10
Figure 62. Voltage Noise Corner vs. Frequency, VSY = ±15 V and VSY = ±5 V
1
100
VSY = ±15V
VSY = ±5V
10
THD + NOISE (%)
0.01
BANDWIDTH = 80kHz
BANDWIDTH = 500kHz
BANDWIDTH = 80kHz
BANDWIDTH = 500kHz
1
0.1
0.01
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
0.0001
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 63. THD + N vs. Frequency, VSY = ±15 V
Figure 60. THD + N vs. Frequency, VSY = ±5 V
VSY = ±15V
VSY = ±5V
TIME (1s/DIV)
Figure 64. 0.1 Hz to 10 Hz Noise, VSY = ±15 V
Figure 61. 0.1 Hz to 10 Hz Noise, VSY = ±5 V
Rev. D | Page 19 of 25
10238-058
INPUT VOLTAGE (50nV/DIV)
10238-054
TIME (1s/DIV)
10238-158
0.0001
10238-155
0.001
INPUT VOLTAGE (50nV/DIV)
THD + NOISE (%)
0.1
ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
100
200
VSY = ±15V
IB (pA)
–200
–300
–400
–500
–600
–700
–900
–1000
–20
–15
–10
0
–5
5
10
15
20
VCM (V)
1
0.1
10238-219
MEAN +3σ
MEAN
MEAN –3σ
–800
10
1
–
+
VEE
CH A
2kΩ
2kΩ
CURRENT NOISE DENSITY (pA/√Hz)
VIN
–60
–
+
VEE
CH B,
CH C,
CH D
–80
–100
–120
VSY = ±15V
VIN = 10V p-p
AV = +1
RL = 10kΩ
–140
–160
100
1k
10k
100k
VSY = ±5V
1kΩ
100k
FREQUENCY (Hz)
1M
10238-244
CHANNEL SEPARATION (dB)
–40
10k
100
10kΩ
VCC
1k
Figure 67. Current Noise Density, VSY = ±15 V
0
VCC
100
FREQUENCY (Hz)
Figure 65. Input Bias Current (IB) vs. Common-Mode Voltage (VCM)
–20
10
10238-267
–100
Figure 66. Channel Separation, VSY = ±15 V
10
1
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 68. Current Noise Density, VSY = ±5 V
Rev. D | Page 20 of 25
100k
10238-268
0
CURRENT NOISE DENSITY (pA/√Hz)
VSY = ±15V
–15V ≤ VCM ≤ +15V
TA = 25°C
100
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
THEORY OF OPERATION
The ADA4077-1, ADA4077-2, and ADA4077-4 are the sixth
generation of the Analog Devices, Inc., industry-standard OP07
amplifier family. The ADA4077-1, ADA4077-2, and ADA4077-4
are high precision, low noise operational amplifiers with a
combination of extremely low offset voltage and very low input
bias currents. Unlike JFET amplifiers, the low bias and offset
currents are relatively insensitive to ambient temperatures, even
up to 125°C.
The Analog Devices proprietary process technology and linear
design expertise have produced a high voltage amplifier with
superior performance to the OP07, OP77, OP177, and OP1177
in tiny, 8-lead SOIC and 8-lead MSOP packages (ADA4077-1
and ADA4077-2) and 14-lead TSSOP and 14-lead SOIC packages
(ADA4077-4). Despite their small size, the ADA4077-1,
ADA4077-2, and ADA4077-4 offer numerous improvements,
including low wideband noise, wide bandwidth, lower offset and
offset drift, lower input bias current, and complete freedom from
phase inversion.
The ADA4077-1, ADA4077-2, and ADA4077-4 have a specified
operating temperature range of −40°C to +125°C with an MSL1
rating, which is as wide as any similar device in a plastic surfacemount package. This MSL1 rating is increasingly important as
printed circuit board (PCB) and overall system sizes continue to
shrink, causing internal system temperatures to rise.
In the ADA4077-1, ADA4077-2, and the ADA4077-4, the power
consumption is reduced by a factor of four compared to the OP177,
and the bandwidth and slew rate are both increased by a factor
of six. The low power dissipation and very stable performance
vs. temperature also reduce warmup drift errors to insignificant
levels.
Inputs are protected internally from overvoltage conditions
referenced to either supply rail. Like any high performance
amplifier, maximum performance is achieved by following
appropriate circuit and PCB guidelines.
Rev. D | Page 21 of 25
ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
APPLICATIONS INFORMATION
OUTPUT PHASE REVERSAL
+15V
Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase
reversal when the voltage applied to the input is greater than the
maximum common-mode voltage. In some instances, this phase
reversal can cause permanent damage to the amplifier. In feedback
loops, it can result in system lockups or equipment damage. The
ADA4077-1, ADA4077-2, and the ADA4077-4 are immune to
phase reversal problems even at input voltages beyond the
power supply settings.
0.1µF
500Ω
FULL-SCALE ADJ
ADR4525
0.1µF
4.37kΩ
4.12kΩ
200Ω
6
4.12kΩ
1/2
ADA4077-2
100Ω
7
VOUT
5
100Ω
20Ω
RP,
ZERO ADJ
49.9kΩ
100Ω
RTD
5kΩ
LINEARITY
ADJ
V+
2
8
3
4
V–
2
1
10238-064
1/2
1
ADA4077-2
Figure 70. Low Power Linearized RTD Circuit
PROPER BOARD LAYOUT
The ADA4077-1, ADA4077-2, and ADA4077-4 are high precision
devices. To ensure optimum performance at the PCB level, care
must be taken in the design of the board layout.
CH2 5.00V
M10.0ms
T 0.000%
A CH1
300mV
To avoid leakage currents, maintain a clean and moisture free
board surface. Coating the surface creates a barrier to moisture
accumulation, and reduces parasitic resistance on the board.
10238-063
CH1 5.00V
Figure 69. No Phase Reversal
LOW POWER LINEARIZED RTD
A common application for a single element varying bridge is a
resistance temperature detector (RTD) thermometer amplifier, as
shown in Figure 70. The excitation is delivered to the bridge by a
2.5 V reference applied at the top of the bridge.
RTDs can have a thermal resistance as high as 0.5°C to 0.8°C per
mW. To minimize errors due to resistor drift, keep the current
low through each leg of the bridge. In this circuit, the amplifier
supply current flows through the bridge. However, at a maximum
supply current of 500 µA for the ADA4077-2, the RTD dissipates
less than 0.1 mW of power, even at the highest resistance.
Therefore, errors due to power dissipation in the bridge
are kept under 0.1°C.
Calibration of the bridge is made at the minimum value of the
temperature to be measured by adjusting RP until the output is
zero.
To calibrate the output span, set the full-scale and linearity
potentiometers to midpoint, and apply a 500°C temperature to
the sensor, or substitute the equivalent 500°C RTD resistance.
Adjust the full-scale potentiometer for a 5 V output. Finally,
apply 250°C or the equivalent RTD resistance, and adjust the
linearity potentiometer for 2.5 V output. The circuit achieves
higher than ±0.5°C accuracy after adjustment.
Keeping supply traces short and properly bypassing the power
supplies minimizes the power supply disturbances caused by
the output current variation, such as when driving an ac signal
into a heavy load. Connect bypass capacitors as closely as possible
to the device supply pins. Stray capacitances are a concern at the
outputs and the inputs of the amplifier. It is recommended that
the signal traces be kept at least 5 mm from supply lines to
minimize coupling.
A variation in temperature across the PCB can cause a mismatch
in the Seebeck voltages at solder joints and other points where
dissimilar metals are in contact, resulting in thermal voltage errors.
To minimize these thermocouple effects, orient resistors so that
heat sources warm both ends equally. Ensure, where possible, that
input signal paths contain matching numbers and types of
components, to match the number and type of thermocouple
junctions. For example, dummy components such as zero value
resistors can be used to match real resistors in the opposite input
path. Place matching components in close proximity to each other,
and orient them in the same manner. Ensure that leads are of equal
length so that thermal conduction is in equilibrium. Keep heat
sources on the PCB as far away from amplifier input circuitry as
is practical.
The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and maintains a constant temperature
across the circuit board.
Rev. D | Page 22 of 25
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 71. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 72. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. D | Page 23 of 25
012407-A
4.00 (0.1574)
3.80 (0.1497)
ADA4077-1/ADA4077-2/ADA4077-4
Data Sheet
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.20
0.09
0.30
0.19
0.75
0.60
0.45
8°
0°
SEATING
PLANE
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 73. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 74. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. D | Page 24 of 25
060606-A
4.00 (0.1575)
3.80 (0.1496)
Data Sheet
ADA4077-1/ADA4077-2/ADA4077-4
ORDERING GUIDE
Model1
ADA4077-1ARMZ
ADA4077-1ARMZ-R7
ADA4077-1ARMZ-RL
ADA4077-1ARZ
ADA4077-1ARZ-R7
ADA4077-1ARZ-RL
ADA4077-1BRZ
ADA4077-1BRZ-R7
ADA4077-1BRZ-RL
ADA4077-2ARMZ
ADA4077-2ARMZ-R7
ADA4077-2ARMZ-RL
ADA4077-2ARZ
ADA4077-2ARZ-R7
ADA4077-2ARZ-RL
ADA4077-2BRZ
ADA4077-2BRZ-R7
ADA4077-2BRZ-RL
ADA4077-4ARUZ
ADA4077-4ARUZ-R7
ADA4077-4ARUZ-RL
ADA4077-4ARZ
ADA4077-4ARZ-R7
ADA4077-4ARZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
Package Option
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
RU-14
RU-14
RU-14
R-14
R-14
R-14
Branding
A35
A35
A35
A2X
A2X
A2X
Z = RoHS Compliant Part.
©2012–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10238-0-10/16(D)
www.analog.com/ADA4077-1/ADA4077-2/ADA4077-4
Rev. D | Page 25 of 25