Sanyo LA6544M Four-channel bridge (btl) driver for cd-rom Datasheet

Ordering number : ENN6295
Monolithic Linear IC
LA6544M
Four-Channel Bridge (BTL) Driver for CD-ROM
Overview
The LA6544M is a 4-channel bridge (BTL) driver
developed for use in CD-ROM systems.
Functions
• Bridge connected (BTL) four-channel power amplifier
• VCE (residual voltage) minimized (channels 1 to 3) by
using two power supplies.
• IOmax: 1.0 A
• Muting circuit provided (output on/off control)
(MUTE pin: low for output off, high for output on.
MUTE1: controls channel 1, MUTE2: controls channels
2, 3, and 4.)
• Thermal protection (shutdown) circuit
• Separated output stage power supply (VS1: channels 1,
2, and 3, VS2: channel 4)
Package Dimensions
unit: mm
3129-MFP36SLF
Mounted on a PCB
2.1
[LA6544M]
PCB: 76.1 × 114.3 × 1.6
glass epoxy
19
36
mm3,
7.9
9.2
10.5
2.0
1.6
1.26
1.2
Independent IC
1
18
0.25
15.3
2.25
2.5max
0.54
0.4
0.4
0
–20
0
20
40
60
75 80
0.65
0.9
0.8
0.8
100
0.85
0.1
Allowable power dissipation, Pdmax — W
Pd max — Ta
2.4
SANYO: MFP36SLF
Ambient temperature, Ta — °C
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Ratings
V
VS max
VS1, 2, VCC ≥ VS1, 2
14
V
VIN max
Each of the input pins VIN1 to VIN4
Maximum supply voltage 2
13
V
13
V
Independent IC
0.9
W
Mounted on the specified PCB (76.1 × 114.3 × 1.6 mm3, glass epoxy)
2.1
W
VMUTE max
MUTE pin voltage
Allowable power dissipation
Unit
14
VCC max
Input voltage
Conditions
VCC ≥ VS1, 2
Maximum supply voltage 1
Pd max
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
42800RM (OT) No. 6295-1/7
LA6544M
Recommended Operating Conditions at Ta = 25°C
Parameter
Symbol
VCC
Operating supply voltage
VS1, 2
Conditions
Ratings
Unit
VCC ≥ VS1, 2
4 to 13
V
VS1 and VS2 are the output stage power supply.
VCC ≥ VS1 and VS2
4 to 13
V
Electrical Characteristics at Ta = 25°C, VCC = VS2 = 12 V, VS1 = 5 V, VREF = 2.5 V
Parameter
Symbol
Ratings
Conditions
VCC no load current drain 1
ICC-ON
Output on (MUTE1 and MUTE2: high), VCC
VCC no load current drain 2
ICC-OFF
Output off (MUTE1 and MUTE2: low), VCC
VS1 no load current drain 1
IS1-ON
Output on (MUTE1 and MUTE2: high), VS1
VS1 no load current drain 2
IS2-OFF
Output off (MUTE1 and MUTE2: low), VS1
VS2 no load current drain 1
IS2-ON
Output on (MUTE1 and MUTE2: high), VS2
VS2 no load current drain 2
IS2-OFF
Output off (MUTE1 and MUTE2: low), VS2
Output offset voltage
Potential difference between the + and – outputs for each
VOF1 to 4
channel
min
typ
Unit
max
10
25
mA
4
mA
20
35
mA
4
mA
5
10
mA
4
mA
+50
mV
–50
Input voltage range 1
VIN1
Input voltage range for channels 1, 2, and 3
0
VS1
V
Input voltage range 2
VIN2
Input voltage range for channel 4
0
VS2
V
Output voltage 1
VO1
IO = 700 mA, the difference between the outputs for
channels 1, 2, and 3
4
4.5
V
Output voltage 2
VO2
IO = 700 mA, the difference between the outputs for
channel 4
10.5
11
V
VG1
The BTL amplifier voltage gain for channels 1, 2, and 3
7
dB
VG2
The BTL amplifier voltage gain for channel 4
14
dB
*1
0.5
V/µs
MUTE1 and MUTE2. The voltage at which the output
turns on. *2
1.5
Closed circuit voltage gain
Slew rate
Muting on voltage
SR
VMUTE
2
V
Notes: 1. Design guarantee value.
2. The MUTE1, and MUTE2 pins turn the output on when high and off when low. When the output is off, the outputs will be in the high-impedance
state.
The figure below shows the relationship between the channels and the MUTE pins and between the channels and the power supplies.
System Figure
MUTE1
CH1 (7 dB)
CH2 (7 dB)
MUTE2
VS1
CH3 (7 dB)
CH4 (14 dB)
VS2
A12681
No. 6295-2/7
LA6544M
Block Diagram and Pin Assignment
RF
1
36 RF
RF
2
MUTE1
Channel 1 output on/off
(NC)
3
MUTE2
Channels 2, 3, and 4 output on/off
VSS2
4
VSS2-OUT
5
MUTE1
6
Thermal shutdown circuit
35 RF
–
+
34 VSS1
–
+
33 VSS1-OUT
32 VO1+
31 VO1–
MUTE1
12.5 kΩ
11 kΩ
VIN1
7
VG1
8
–
+
VS1 power supply
(channels 1, 2, and 3)
30 VS1
29 VO2+
12.5 kΩ
11 kΩ
VIN2
9
28 VO2–
–
+
27 VO3+
VG2 10
12.5 kΩ
11 kΩ
VIN3 11
26 VO3–
–
+
VG3 12
VS1 power supply (channel 4)
25 VS2
27.5 kΩ
11 kΩ
VIN4 13
24 VO4+
–
+
23 VO4–
VG4 14
MUTE2 15
VCC 16
22 VREF OUT
MUTE2
Input stage power supply
(all channels)
–
+
21 VREF IN
RF 17
20 RF
RF 18
19 RF
A12682
No. 6295-3/7
LA6544M
Pin Functions
Pin No.
Pin
1
RF
Substrate (lowest potential)
2
RF
Substrate (lowest potential)
3
(NC)
Unused.
4
VSS2
Connect to VS2.
5
VSS2-OUT
6
MUTE1
Function
Output stage reference voltage output ((VS2-VBE)/2, typical)
Channel 1 output on/off control
7
VIN1
Channel 1 input
8
VG1
Channel 1 input (gain adjustment)
9
VIN2
Channel 2 input
10
VG2
Channel 2 input (gain adjustment)
11
VIN3
Channel 3 input
12
VG3
Channel 3 input (gain adjustment)
13
VIN4
Channel 4 input
14
VG4
Channel 4 input (adjustment)
15
MUTE2
16
VCC
Power supply
17
RF
Substrate (lowest potential)
18
RF
Substrate (lowest potential)
19
RF
Substrate (lowest potential)
20
RF
21
VREF IN
Channels 2, 3, and 4 on/off control
Substrate (lowest potential)
Reference voltage input (VREF1 buffer amplifier input)
22
VREF OUT
23
VO4–
Reference voltage output (VREF1 buffer amplifier output)
24
VO4+
Channel 4 noninverted output
25
VS 2
Channel 4 output stage power supply
26
VO3–
Channel 3 inverted output
27
VO3+
Channel 3 noninverted output
28
VO2–
Channel 2 inverted output
29
VO2+
Channel 2 noninverted output
30
VS 1
Channels 1, 2, and 3 output stage power supply
31
VO1–
Channel 1 inverted output
32
VO1+
Channel 1 noninverted output
33
VSS1-OUT
34
VSS1
35
RF
Substrate (lowest potential)
36
RF
Substrate (lowest potential)
Channel 4 inverted output
Output stage reference voltage (Outputs VSS/2: typical) (VREF2 buffer amplifier output)
Connect to VS1. (VSS1 - OUT is generated by a resistor divider.)
No. 6295-4/7
LA6544M
Sample Application Circuit
VS(5V)
1
RF
RF 36
2
RF
RF 35
3
(NC)
4
VSS2
5
VSS2-OUT
VO1+ 32
VO1– 31
VSS1 34
VSS1-OUT 33
M
MUTE1
6
MUTE1
Loading input
7
VIN1
VS1 30
8
VG1
VO2+ 29
9
VIN2
VO2– 28
10
VG2
VO3+ 27
11
VIN3
VO3– 26
12
VG3
VS2 25
13
VIN4
VO4+ 24
14
VG4
VO4– 23
MUTE2
15
MUTE2
VCC (12 V)
16
VCC
17
RF
RF 20
18
RF
RF 19
Loading motor
Gain setting
Focus input
Focus coil
LA6544M
Gain setting
Tracking input
Tracking coil
Gain setting
Sled input
M
Gain setting
Sled motor
VREF OUT 22
VREF IN 21
VREF
A12683
No. 6295-5/7
LA6544M
Pin Description
Pin No.
Pin
Symbol
Function
Equivalent circuit
VCC
7
VIN1
8
VG1
9
VIN2
10
11
12
VIN*
VG*
(Input)
VG2
VIN3
11 9
Inputs for each channel
11 kΩ
VG3
13
VIN4
14
VG4
VIN
13 7
VG
12 8
14 10
RF
VREF OUT
A12684
VS
VO1+
32
31
VO1–
29
VO2+
28
VO *
VO2–
27
(Output)
VO3+
26
VO3–
24
VO4+
23
VO4–
VCC
Outputs for each channel
VO
23 24 26 27
28 29 31 32
RF
A12685
VCC
MUTE1
MUTE2
Output on/off control
6
MUTE1, 2
15
100 kΩ
MUTE
100 kΩ
6
15
RF
A12686
No. 6295-6/7
LA6544M
Gain Setting (Functions of the Input and Gain Adjustment Pins)
The figures present overviews of the VIN and VG pin circuits. (These are the same as the block diagrams.)
1. Consider resistors (11 kΩ, typical) to be inserted between the VIN and VG pins. This should be seen as being the
same as the operational amplifier noninverting input (VIN+).
2. If the VG pins are not used, and only the VIN pins are used, the BTL gain (across the VO+ and VO- outputs) will be 7
dB for channels 1, 2, and 3 (amplifier units: 1 dB + BTL: 6 dB) and 14 dB for channel 4 (amplifier units: 8 dB +
BTL: 6 dB).
If the VIN pins are not used and 11 kΩ external resistors are attached to the VG pins, input to the opposite ends of
those resistors will result in equivalent circuit operation. However, the VIN pins should be used and the gain set to
minimize the I/O gain temperature characteristics.
12.5 kΩ
11 kΩ
VIN1 to VIN3
–
+
VG1 to VG3
27.5 kΩ
11 kΩ
VIN4
–
+
VG4
A12687
Offset Voltage
This IC includes built-in level shifting circuits. For input to which VREF is applied as a reference, the output is referenced
to the voltage VSS1/2 (V) for channels 1, 2, and 3, and the output is referenced to the voltage (VSS2 – VBE(0.7))/2 (V) for
channel 4.
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of April, 2000. Specifications and information herein are subject to
change without notice.
PS No. 6295-7/7
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