LINER LTC2418CGN 8-/16-channel 24-bit no latency tm adc Datasheet

LTC2414/LTC2418
8-/16-Channel
24-Bit No Latency ∆ΣTM ADCs
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FEATURES
DESCRIPTIO
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The LTC®2414/LTC2418 are 8-/16-channel (4-/8-differential) micropower 24-bit ∆Σ analog-to-digital converters. They operate from 2.7V to 5.5V and include an
integrated oscillator, 2ppm INL and 0.2ppm RMS noise.
They use delta-sigma technology and provide single cycle
settling time for multiplexed applications. Through a
single pin, the LTC2414/LTC2418 can be configured for
better than 110dB differential mode rejection at 50Hz or
60Hz ±2%, or they can be driven by an external oscillator
for a user-defined rejection frequency. The internal oscillator requires no external frequency setting components.
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8-/16-Channel Single-Ended or 4-/8-Channel
Differential Inputs (LTC2414/LTC2418)
Low Supply Current (200µA, 4µA in Autosleep)
Differential Input and Differential Reference
with GND to VCC Common Mode Range
2ppm INL, No Missing Codes
2.5ppm Full-Scale Error and 0.5ppm Offset
0.2ppm Noise
No Latency: Digital Filter Settles in a Single Cycle
Each Conversion Is Accurate, Even After a New
Channel is Selected
Single Supply 2.7V to 5.5V Operation
Internal Oscillator—No External Components
Required
110dB Min, 50Hz/60Hz Notch Filter
The LTC2414/LTC2418 accept any external differential
reference voltage from 0.1V to VCC for flexible ratiometric
and remote sensing measurement applications. They can
be configured to take 4/8 differential channels or
8/16 single-ended channels. The full-scale bipolar input
range is from – 0.5VREF to 0.5VREF. The reference common
mode voltage, VREFCM, and the input common mode voltage, VINCM, may be independently set within GND to VCC.
The DC common mode input rejection is better than 140dB.
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APPLICATIO S
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Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain Gauge Transducers
Instrumentation
Data Acquisition
Industrial Process Control
The LTC2414/LTC2418 communicate through a flexible
4-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
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TYPICAL APPLICATIO
Total Unadjusted Error
vs Input Voltage
2.7V TO 5.5V
THERMOCOUPLE
21 CH0
22 CH1
•
•
•
28 CH7
1 CH8
•
•
•
8 CH15
REF
VCC
VCC
FO
16-CHANNEL
MUX
+
–
DIFFERENTIAL
24-BIT ∆Σ ADC
3
1µF
9
SDI
SCK
SDO
CS
19
20
18
17
16
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
4-WIRE
SPI INTERFACE
2
TUE (ppm OF VREF)
11
+
1
VCC = 5V
VREF = 5V
VINCM = VREFCM = 2.5V
FO = GND
TA = 25°C
0
TA = –45°C
–1
TA = 85°C
10 COM
–2
12
15
REF –
GND
LTC2418
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
241418 TA01a
2414/18 TA01b
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LTC2414/LTC2418
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ABSOLUTE
RATI GS (Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2414/LTC2418C ................................ 0°C to 70°C
LTC2414/LTC2418I ............................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
NC
1
28 CH7
CH8
1
28 CH7
NC
2
27 CH6
CH9
2
27 CH6
NC
3
26 CH5
CH10
3
26 CH5
NC
4
25 CH4
CH11
4
25 CH4
NC
5
24 CH3
CH12
5
24 CH3
NC
6
23 CH2
CH13
6
23 CH2
NC
7
22 CH1
CH14
7
22 CH1
NC
8
21 CH0
CH15
8
21 CH0
VCC
9
20 SDI
VCC
9
20 SDI
COM 10
19 FO
COM 10
19 FO
11
18 SCK
REF+
11
18 SCK
REF– 12
17 SDO
REF– 12
17 SDO
REF+
NC 13
16 CS
NC 13
16 CS
NC 14
15 GND
NC 14
15 GND
GN PACKAGE
28-LEAD PLASTIC SSOP
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 110°C/W
TJMAX = 125°C, θJA = 110°C/W
ORDER PART NUMBER
PART MARKING
LTC2414CGN
LTC2414IGN
ORDER PART NUMBER
PART MARKING
LTC2418CGN
LTC2418IGN
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
*The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges.
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LTC2414/LTC2418
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, – 0.5 • VREF ≤ VIN ≤ 0.5 • VREF (Note 5)
Integral Nonlinearity
4.5V ≤ VCC ≤ 5.5V, REF + = 2.5V, REF– = GND, VINCM = 1.25V (Note 6)
5V ≤ VCC ≤ 5.5V, REF + = 5V, REF – = GND, VINCM = 2.5V (Note 6)
REF + = 2.5V, REF – = GND, VINCM = 1.25V (Note 6)
●
TYP
MAX
UNITS
24
Bits
●
1
2
5
14
ppm of VREF
ppm of VREF
ppm of VREF
●
2.5
10
µV
Offset Error
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN + = IN – ≤ VCC (Note 14)
Offset Error Drift
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN + = IN – ≤ VCC
Positive Full-Scale Error
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.75 • REF+, IN – = 0.25 • REF +
Positive Full-Scale Error Drift
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.75 • REF+, IN – = 0.25 • REF +
Negative Full-Scale Error
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.25 • REF+, IN – = 0.75 • REF +
Negative Full-Scale Error Drift
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.25 • REF+, IN – = 0.75 • REF +
Total Unadjusted Error
4.5V ≤ VCC ≤ 5.5V, REF + = 2.5V, REF – = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF + = 5V, REF – = GND, VINCM = 2.5V
REF + = 2.5V, REF – = GND, VINCM = 1.25V
3
3
6
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
5V ≤ VCC ≤ 5.5V, REF + = 5V, VREF – = GND,
GND ≤ IN – = IN + ≤ 5V (Note 13)
1
µVRMS
20
●
2.5
nV/°C
12
0.03
●
2.5
ppm of VREF
ppm of VREF/°C
12
0.03
ppm of VREF
ppm of VREF/°C
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN – = IN + ≤ 5V (Note 5)
MIN
TYP
Input Common Mode Rejection
60Hz ±2%
MAX
UNITS
●
130
140
2.5V ≤ REF+ ≤ VCC, REF – = GND,
GND ≤ IN – = IN + ≤ 5V (Notes 5, 7)
●
140
dB
Input Common Mode Rejection
50Hz ±2%
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN – = IN + ≤ 5V (Notes 5, 8)
●
140
dB
Input Normal Mode Rejection
60Hz ±2%
(Notes 5, 7)
●
110
140
dB
Input Normal Mode Rejection
50Hz ±2%
(Notes 5, 8)
●
110
140
dB
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF – ≤ 2.5V,
VREF = 2.5V, IN – = IN + = GND (Note 5)
●
130
140
dB
Power Supply Rejection, DC
REF + = 2.5V, REF – = GND, IN – = IN + = GND
110
dB
Power Supply Rejection, 60Hz ±2%
REF + = 2.5V, REF – = GND, IN –
= IN + = GND (Note 7)
120
dB
Power Supply Rejection, 50Hz ±2%
REF + = 2.5V, REF – = GND, IN –
= IN + = GND (Note 8)
120
dB
dB
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LTC2414/LTC2418
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN +
Absolute/Common Mode IN + Voltage
CONDITIONS
●
GND – 0.3
MIN
TYP
VCC + 0.3
MAX
UNITS
V
IN –
Absolute/Common Mode IN – Voltage
●
GND – 0.3
VCC + 0.3
V
VIN
Input Differential Voltage Range
(IN + – IN –)
●
– VREF/2
VREF/2
V
REF +
Absolute/Common Mode REF + Voltage
●
0.1
VCC
V
REF –
Absolute/Common Mode REF – Voltage
●
GND
VCC – 0.1
V
VREF
Reference Differential Voltage Range
(REF + – REF –)
●
0.1
VCC
V
CS (IN +)
IN + Sampling Capacitance
18
pF
CS (IN –)
IN – Sampling Capacitance
18
pF
CS
(REF +)
REF + Sampling Capacitance
18
pF
CS
(REF –)
REF – Sampling Capacitance
18
pF
IDC_LEAK (IN +)
IN + DC Leakage Current
CS = VCC = 5.5V, IN+ = GND
●
–10
1
10
nA
IDC_LEAK (IN –)
IN – DC Leakage Current
CS = VCC = 5.5V, IN– = 5V
●
–10
1
10
nA
●
–10
1
10
nA
●
–10
1
10
nA
(REF +)
REF + DC Leakage Current
CS = VCC
IDC_LEAK (REF –)
REF – DC Leakage Current
CS = VCC = 5.5V, REF– = GND
Off Channel to In Channel Isolation
(RIN = 100Ω)
DC
1Hz
fS = 15,3600Hz
tOPEN
MUX Break-Before-Make Interval
2.7V ≤ VCC ≤ 5.5V
IS(OFF)
Channel Off Leakage Current
Channel at VCC and GND
140
140
140
●
dB
dB
dB
70
100
300
ns
–10
1
10
nA
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IDC_LEAK
= 5.5V, REF+ = 5V
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
CS, FO, SDI
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
●
MIN
VIL
Low Level Input Voltage
CS, FO, SDI
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
●
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
●
IIN
Digital Input Current
CS, FO, SDI
0V ≤ VIN ≤ VCC
●
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
●
CIN
Digital Input Capacitance
CS, FO, SDI
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = – 800µA
●
TYP
MAX
2.5
2.0
UNITS
V
V
0.8
0.6
2.5
2.0
V
V
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
VCC – 0.5
10
pF
10
pF
V
241418fa
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LTC2414/LTC2418
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
MIN
VOH
High Level Output Voltage
SCK
IO = – 800µA (Note 10)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
●
IOZ
Hi-Z Output Leakage
SDO
●
TYP
MAX
UNITS
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
CONDITIONS
MIN
●
CS = 0V (Note 12)
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V (Note 12)
TYP
2.7
●
●
200
4
2
MAX
UNITS
5.5
V
300
10
µA
µA
µA
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
●
tHEO
External Oscillator High Period
●
tLEO
External Oscillator Low Period
●
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
●
fESCK
External SCK Frequency Range
(Note 9)
●
tLESCK
External SCK Low Period
(Note 9)
●
250
ns
tHESCK
External SCK High Period
(Note 9)
●
250
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.64
tDOUT_ESCK
External SCK 32-Bit Data Output Time (Note 9)
●
●
●
TYP
MAX
UNITS
2.56
2000
kHz
0.25
390
µs
0.25
390
µs
130.86
133.53
136.20
157.03
160.23
163.44
20510/fEOSC (in kHz)
19.2
fEOSC/8
●
45
ms
ms
ms
kHz
kHz
55
%
2000
kHz
1.67
1.70
256/fEOSC (in kHz)
ms
ms
32/fESCK (in kHz)
ms
241418fa
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LTC2414/LTC2418
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t1
CS ↓ to SDO Low
●
0
200
ns
t2
CS ↑ to SDO High Z
●
0
200
ns
t3
CS ↓ to SCK ↓
(Note 10)
●
0
200
ns
t4
CS ↓ to SCK ↑
(Note 9)
●
50
tKQMAX
SCK ↓ to SDO Valid
220
ns
tKQMIN
SDO Hold After SCK ↓
t5
t6
t7
SDI Setup Before SCK↑
(Note 5)
●
100
ns
t8
SDI Hold After SCK↑
(Note 5)
●
100
ns
●
●
15
SCK Set-Up Before CS ↓
●
50
SCK Hold After CS ↓
●
(Note 5)
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF + – REF –, VREFCM = (REF + + REF –)/2; VIN = IN+ – IN –,
VINCM = (IN + + IN –)/2, IN+ and IN– are defined as the selected positive
and negative input respectively.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
ns
ns
ns
50
ns
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
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LTC2414/LTC2418
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TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
FO = GND
TA = –45°C
6 VCC = 2.7V
VREF = 2.5V
= VREFCM = 1.25V
V
4 INCM
0
TA = –45°C
–1
TA = 85°C
TUE (ppm OF VREF)
TA = 25°C
1
TA = 25°C
0
TA = 85°C
–1
TA = –45°C
–2
–2
–3
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
–3
–1.25
–0.75
–8
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
8
FO = GND
6 VCC = 2.7V
VREF = 2.5V
= VREFCM = 1.25V
V
4 INCM
–1
0
TA = 25°C
–1
TA = –45°C
TA = 85°C
–2
–2
–3
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
–3
–1.25
14
NUMBER OF READINGS (%)
10
5
0.6
241418 G07
0
–2
TA = 85°C
–4
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
–8
–1.25
1.25
–0.75
Long Term ADC Readings
10,000 CONSECUTIVE READINGS
FO = GND
12 T = 25°C
A
VCC = 2.7V
GAUSSIAN
10 VREF = 2.5V
DISTRIBUTION
VIN = 0V
m = –0.48ppm
σ = 0.375ppm
8 VINCM = 2.5V
6
1.0
RMS NOISE = 0.19ppm
FO = GND
VREF = 5V
TA = 25°C VIN = 0V
0.5 VCC = 5V
VINCM = 2.5V
0
–0.5
4
0
–2.4
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
241418 G06
Noise Histogram
(VCC = 2.7V, VREF = 2.5V)
–1.0
2
–0.6
0
OUTPUT CODE (ppm OF VREF)
TA = 25°C
2
241418 G05
30
15
TA = –45°C
–6
241418 G04
Noise Histogram
(VCC = 5V, VREF = 5V)
10,000 CONSECUTIVE READINGS
FO = GND
25 TA = 25°C
VCC = 5V
GAUSSIAN
VREF = 5V
DISTRIBUTION
20 VIN = 0V
m = –0.24ppm
VINCM = 2.5V
σ = 0.183ppm
INL (ppm OF VREF)
0
TA = –45°C
1
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
ADC READING (ppm OF VREF)
TA = 25°C
–0.75
241418 G03
FO = GND
VCC = 5V
2 VREF = 2.5V
VINCM = VREFCM = 1.25V
INL (ppm OF VREF)
INL (ppm OF VREF)
TA = 25°C
–4
3
FO = GND
VCC = 5V
2 VREF = 5V
VINCM = VREFCM = 2.5V
TA = 85°C
TA = 85°C
–2
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
3
NUMBER OF READINGS (%)
0
241418 G02
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
1
2
–6
241418 G01
0
–1.2
TUE (ppm OF VREF)
FO = GND
VCC = 5V
2 VREF = 2.5V
VINCM = VREFCM = 1.25V
FO = GND
VCC = 5V
2 VREF = 5V
VINCM = VREFCM = 2.5V
TUE (ppm OF VREF)
8
3
3
1
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
–1.5
0
0.6
–1.8 –1.2 –0.6
OUTPUT CODE (ppm OF VREF)
1.2
241418 G08
0
10
20
30
40
TIME (HOURS)
50
60
LTXXXX • TPCXX
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LTC2414/LTC2418
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TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Input Differential
Voltage
1.0
FO = GND
TA = 25°C
VCC = 5V
0.4 V
REF = 5V
VINCM = 2.5V
RMS Noise vs Temperature (TA)
RMS Noise vs VINCM
1.2
1.1
0.9
0.3
0.2
0.8
FO = GND
TA = 25°C
VCC = 5V
REF+ = 5V
REF – = GND
VIN = 0V
VINCM = GND
0.7
0.6
0.1
0.5
0
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
INPUT DIFFERENTIAL VOLTAGE (V)
–1
1
0
3
2
VINCM (V)
4
5
0.9
0.8
FO = GND
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
0.7
0.6
0.5
–50
6
–25
0
25
50
TEMPERATURE (°C)
75
RMS Noise vs VCC
100
241418 G12
241418 G11
241418 G10
1.0
RMS NOISE (µV)
1.0
RMS NOISE (µV)
RMS NOISE (ppm OF VREF)
0.5
Offset Error vs VINCM
RMS Noise vs VREF
0
1.0
0.9
0.8
0.7
FO = GND
TA = 25°C
VIN = 0V
VINCM = GND
REF+ = 2.5V
REF – = GND
0.6
0.5
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
RMS NOISE (µV)
RMS NOISE (µV)
0.9
0.8
0.7
FO = GND
TA = 25°C
VCC = 5V
VIN = 0V
VINCM = GND
REF – = GND
0.6
0.5
5.5
1
0
3
2
VREF (V)
4
241418 G13
Offset Error vs Temperature
1.0
–0.4
FO = GND
0.8 TA = 25°C
V = 0V
0.6 VIN = GND
INCM
+
0.4 REF – = 2.5V
REF = GND
0.2
90
241418 G16
–0.8
–1.0
–1
1
0
3
2
VINCM (V)
4
5
6
241418 G15
FO = GND
TA = 25°C
VCC = 5V
VIN = 0V
VINCM = GND
REF – = GND
0.8
0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
75
FO = GND
TA = 25°C
VCC = 5V
REF+ = 5V
REF – = GND
VIN = 0V
–0.7
Offset Error vs VREF
–0.8
0 15 30 45 60
TEMPERATURE (°C)
–0.6
1.0
–0.6
–0.7
–45 –30 –15
–0.5
Offset Error vs VCC
–0.4
–0.6
–0.4
5
–0.2
–0.5
–0.3
–0.9
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
–0.3
–0.2
241418 G14
0
FO = GND
–0.1 VCC = 5V
VREF = 5V
VIN = 0V
–0.2 VINCM = GND
OFFSET ERROR (ppm OF VREF)
–0.1
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
241418 G17
–1.0
0
1
3
2
VREF (V)
4
5
241418 G18
241418fa
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Full-Scale Error vs Temperature
+FS ERROR
1
0
–1
–2
–FS ERROR
–3
–4
–5
–60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80
Full-Scale Error vs VREF
Full-Scale Error vs VCC
5
5
4
3
FULL-SCALE ERROR (ppm OF VREF)
FO = GND
4 VCC = 5V
= 5V
V
3 REF
VINCM = 2.5V
2
FULL-SCALE ERROR (ppm OF VREF)
FULL-SCALE ERROR (ppm OF VREF)
5
+FS ERROR
2
FO = GND
1 T = 25°C
A
0 VREF = 2.5V
VINCM = 0.5VREF
–1 REF – = GND
–FS ERROR
–2
–3
–4
–5
100
2.7
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
241418 G19
PSRR vs Frequency at VCC
–80
–1
FO = GND
T = 25°C
–20 VA = 4.1V ±1.4V
CC
DC
REF+ = 2.5V
–
–40 REF = GND
IN+ = GND
–
–60 IN = GND
SDI = GND
FO = GND
TA = 25°C
VCC = 4.1VDC ±0.7VP-P
REF+ = 2.5V
–40 REF – = GND
IN+ = GND
–
–60 IN = GND
SDI = GND
–20
–80
–80
–100
–100
–120
–120
–120
–140
10
100 1000 10000 100000 1000000
FREQUENCY AT VCC (Hz)
0
30
90
241418 G22
170
160
–45 –30 –15
6
CS = GND
FO = EXT OSC
IN+ = GND
IN– = GND
SCK = NC
SDO = NC
SDI = GND
TA = 25°C
VREF = VCC
VCC = 5V
VCC = 3V
SUPPLY CURRENT (µA)
900
210
CS = GND
200 FO = GND
SCK = NC
190 SDO = NC
SDI = GND
180
Sleep Mode Current
vs Temperature
1000
VCC = 5.5V
800
700
600
500
VCC = 5V
400
VCC = 3V
300
VCC = 5.5V
4
3
2
1
100
0 15 30 45 60
TEMPERATURE (°C)
75 90
241418 G25
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
241418 G26
CS = VCC
FO = GND
SCK = NC
SDO = NC
SDI = GND
5
200
VCC = 2.7V
15450
241418 G24
Supply Current at Elevated
Output Rates (FO Over Driven)
240
220
15300
15350
15400
FREQUENCY AT VCC (Hz)
241418 G23
Conversion Current
vs Temperature
230
–140
15250
120 150 180 210 240
FREQUENCY AT VCC (Hz)
60
SLEEP-MODE CURRENT (µA)
1
–FS ERROR
–2 FO = GND
T = 25°C
–3 A
VCC = 5V
–4 VINCM = 0.5VREF
REF – = GND
–5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VREF (V)
–100
–140
CONVERSION CURRENT (µA)
0
0
REJECTION (dB)
–60
+FS ERROR
1
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
REJECTION (dB)
REJECTION (dB)
–40
2
241418 G21
0
FO = GND
TA = 25°C
VCC = 4.1VDC
REF+ = 2.5V
REF – = GND
IN+ = GND
IN – = GND
SDI = GND
3
241418 G20
0
–20
5.5
4
0
–45 –30 –15
VCC = 5V
VCC = 3V
VCC = 2.7V
0 15 30 45 60
TEMPERATURE (°C)
75 90
241418 G27
241418fa
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LTC2414/LTC2418
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PI FU CTIO S
CH0 to CH15 (Pin 21 to Pin 28 and Pin 1 to Pin 8): Analog
Inputs. May be programmed for single-ended or differential mode. CH8 to CH15 (Pin 1 to Pin 8) not connected on
the LTC2414.
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
VCC (Pin 9): Positive Supply Voltage. Bypass to GND
(Pin 15) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
SCK (Pin 18): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial
interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
COM (Pin 10): The common negative input (IN–) for all
single-ended multiplexer configurations. The voltage on
Channel 0 to 15 and COM input pins can have any value
between GND – 0.3V and VCC + 0.3V. Within these limits,
the two selected inputs (IN+ and IN–) provide a bipolar
input range (VIN = IN+ – IN–) from – 0.5 • VREF to 0.5 • VREF.
Outside this input range, the converter produces unique
overrange and underrange output codes.
REF + (Pin 11), REF – (Pin 12): Differential Reference
Input. The voltage on these pins can have any value
between GND and VCC as long as the positive reference
input, REF +, is maintained more positive than the negative
reference input, REF –, by at least 0.1V.
GND (Pin 15): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 16): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 17): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
FO (Pin 19): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the FO pin is connected
to GND (FO = 0V), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converters use this signal as their system clock and the
digital filter first null is located at a frequency fEOSC/2560.
SDI (Pin 20): Serial Digital Data Input. During the Data
Output period, this pin is used to shift in the multiplexer
address started from the first rising SCK edge. During the
Conversion and Sleep periods, this pin is in the DON’T
CARE state. However, a HIGH or LOW logic level should be
maintained on SDI in the DON’T CARE mode to avoid an
excessive current in the SDI input buffers.
NC Pins: Do Not Connect.
241418fa
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LTC2414/LTC2418
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FU CTIO AL BLOCK DIAGRA
U
INTERNAL
OSCILLATOR
U
VCC
GND
REF
REF –
CH0
CH1
CH15
COM
FO
(INT/EXT)
AUTOCALIBRATION
AND CONTROL
+
–
IN +
•
•
•
MUX
IN –
+
DIFFERENTIAL
3RD ORDER
∆Σ MODULATOR
SDI
SCK
SDO
CS
SERIAL
INTERFACE
DECIMATING FIR
ADDRESS
241418 F01
Figure 1
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k
CLOAD = 20pF
CLOAD = 20pF
241418 TA03
241418 TA02
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
Converter Operation Cycle
The LTC2414/LTC2418 are multichannel, low power, deltasigma analog-to-digital converters with an easy-to-use
4-wire serial interface (see Figure 1). Their operation is made
up of three states. The converter operating cycle begins with
the conversion, followed by the low power sleep state and
ends with the data input/output (see Figure 2). The 4-wire
interface consists of serial data input (SDI), serial data output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2414 or LTC2418 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as
CS is HIGH. While in the sleep state, power consumption
is reduced by nearly two orders of magnitude. The conversion result is held indefinitely in a static shift register while
the converter is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins outputting the conversion result and inputting channel selection
bits. Taking CS high at this point will terminate the data
output state and start a new conversion. The channel
selection control bits are shifted in through SDI from the
241418fa
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APPLICATIO S I FOR ATIO
POWER UP
IN + = CH0, IN – = CH1
CONVERT
SLEEP
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
ADDRESS INPUT
241418 F02
Figure 2. LTC2414/LTC2418 State Transition Diagram
first rising edge of SCK and depending on the control bits,
the converter updates its channel selection immediately
and is valid for the next conversion. The details of channel
selection control bits are described in the Input Data Mode
section. The output data is shifted out the SDO pin under
the control of the serial clock (SCK). The output data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats.
Through timing control of the CS and SCK pins, the
LTC2414/LTC2418 offer several flexible modes of operation (internal or external SCK and free-running conversion
modes). These various modes do not require programming configuration registers; moreover, they do not disturb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or
60Hz plus their harmonics. The filter rejection performance is directly related to the accuracy of the converter
system clock. The LTC2414/LTC2418 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2414/
LTC2418 achieve a minimum of 110dB rejection at the line
frequency (50Hz or 60Hz ±2%).
Ease of Use
The LTC2414/LTC2418 data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.
The LTC2414/LTC2418 perform offset and full-scale calibrations in every conversion cycle. This calibration is transparent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.
Power-Up Sequence
The LTC2414/LTC2418 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 3-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a typical duration of 1ms. The POR signal
clears all internal registers. Following the POR signal, the
LTC2414/LTC2418 start a normal conversion cycle and
follow the succession of states described above. The first
conversion result following POR is accurate within the
specifications of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
Reference Voltage Range
The LTC2414/LTC2418 accept a truly differential external
reference voltage. The absolute/common mode voltage
241418fa
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LTC2414/LTC2418
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APPLICATIO S I FOR ATIO
specification for the REF + and REF – pins covers the entire
range from GND to VCC. For correct converter operation,
the REF + pin must always be more positive than the REF –
pin.
The LTC2414/LTC2418 can accept a differential reference
voltage from 0.1V to VCC. The converter output noise is
determined by the thermal noise of the front-end circuits,
and, as such, its value in nanovolts is nearly constant with
reference voltage. A decrease in reference voltage will not
significantly improve the converter’s effective resolution.
On the other hand, a reduced reference voltage will improve the converter’s overall INL performance. A reduced
reference voltage will also improve the converter performance when operated with an external conversion clock
(external FO signal) at substantially higher output data rates.
Input Voltage Range
The two selected pins are labeled IN+ and IN– (see Tables
1 and 2). Once selected (either differential or single-ended
multiplexing mode), the analog input is differential with a
common mode range for the IN+ and IN– input pins extending from GND – 0.3V to V CC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase rapidly. Within these limits, the LTC2414/LTC2418 convert
the bipolar differential input signal, VIN = IN + – IN –, from
– FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF =
REF+ – REF –. Outside this range the converters indicate
the overrange or the underrange condition using distinct
output codes.
Input signals applied to IN+ and IN– pins may extend
300mV below ground or above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ or IN– pins without affecting the performance
of the device. In the physical layout, it is important to
maintain the parasitic capacitance of the connection between these series resistors and the corresponding pins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. In addition, series
resistors will introduce a temperature dependent offset
error due to the input leakage current. A 1nA input leakage
current will develop a 1ppm offset error on a 5k resistor if
VREF = 5V. This error has a very strong temperature
dependency.
Input Data Format
When the LTC2414/LTC2418 are powered up, the default
selection used for the first conversion is IN+ = CH0 and IN–
= CH1 (Address = 00000). In the data input/output mode
following the first conversion, a channel selection can be
updated using an 8-bit word. The LTC2414/LTC2418
serial input data is clocked into the SDI pin on the rising
edge of SCK (see Figure 3). The input is composed of an
8-bit word with the first 3 bits acting as control bits and the
remaining 5 bits as the channel address bits.
The first 2 bits are always 10 for proper updating operation. The third bit is EN. For EN = 1, the following 5 bits are
used to update the input channel selection. For EN = 0,
previous channel selection is kept and the following bits
are ignored. Therefore, the address is updated when the 3
control bits are 101 and kept for 100. Alternatively, the 3
control bits can be all zero to keep the previous address.
This alternation is intended to simplify the SDI interface
allowing the user to simply connect SDI to ground if no
update is needed. Combinations other than 101, 100 and
000 of the 3 control bits should be avoided.
When update operation is set (101), the following 5 bits
are the channel address. The first bit, SGL, decides if the
differential selection mode (SGL = 0) or the single-ended
selection mode is used (SGL = 1). For SGL = 0, two
adjacent channels can be selected to form a differential
input; for SGL = 1, one of the 8 channels (CH0-CH7) for the
LTC2414 or one of the 16 channels (CH0-CH15) for the
LTC2418 is selected as the positive input and the COM pin
is used as the negative input. For the LTC2414, the lower
half channels (CH0-CH7) are used and the channel address bit A2 should be always 0, see Table 1. While for the
LTC2418, all the 16 channels are used and the size of the
corresponding selection table (Table 2) is doubled from
that of the LTC2414 (Table 1). For a given channel selection, the converter will measure the voltage between the
two channels indicated by IN+ and IN– in the selected row
of Tables 1 or 2.
241418fa
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LTC2414/LTC2418
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CS
SDO
Hi-Z
BIT31
BIT30
BIT29
BIT28
BIT27
EOC
DMY
SIG
MSB
B22
BIT26
BIT25
BIT24
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
LSB
SGL
ODD/
SIGN
A2
A1
A0
PARITY
ADDRESS CORRESPONDING TO RESULT
CONVERSON RESULT
SCK
SDI
1
0
EN
SGL
ODD/
SIGN
A2
A1
A0
SLEEP
DON’T CARE
CONVERSION
DATA INPUT/OUTPUT
241418 F03a
Figure 3a. Input/Output Data Timing
CONVERSION RESULT
N–1
CONVERSION RESULT
N
CONVERSION RESULT
N+1
SDO
Hi-Z
Hi-Z
ADDRESS
N–1
Hi-Z
ADDRESS
N
ADDRESS
N+1
SCK
SDI
DON’T CARE
DON’T CARE
ADDRESS
N
OPERATION
OUTPUT
N–1
ADDRESS
N+1
CONVERSION N
ADDRESS
N+2
OUTPUT
N
OUTPUT
N+1
CONVERSION N + 1
241418 F03b
Figure 3b. Typical Operation Sequence
Table 1. Channel Selection for the LTC2414 (Bit A2 Should Always Be 0)
MUX ADDRESS
ODD/
SGL
SIGN A2 A1
* 0
0
0 0
0
0
0 0
0
0
0 1
0
0
0 1
0
1
0 0
0
1
0 0
0
1
0 1
0
1
0 1
1
0
0 0
1
0
0 0
1
0
0 1
1
0
0 1
1
1
0 0
1
1
0 0
1
1
0 1
1
1
0 1
CHANNEL SELECTION
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
IN+
IN–
1
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN+
IN–
IN–
IN–
IN–
IN–
IN–
IN–
IN–
*Default at power up
241418fa
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LTC2414/LTC2418
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Table 2. Channel Selection for the LTC2418
MUX ADDRESS
SGL
ODD/
SIGN
CHANNEL SELECTION
A2 A1 A0
* 0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
IN+
IN–
IN–
2
3
IN+
IN–
4
5
IN+
IN–
6
7
IN+
IN–
8
9
IN+
IN–
10
11
IN+
IN–
12
13
IN+
IN–
14
15
IN+
IN–
IN–
IN+
COM
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
IN+
IN–
*Default at power up
Output Data Format
The LTC2414/LTC2418 serial output data stream is 32 bits
long. The first 3 bits represent status information indicating the sign and conversion state. The next 23 bits are the
conversion result, MSB first. The next 5 bits (Bit 5 to Bit 1)
indicate which channel the conversion just performed was
selected. The address bits programmed during this data
output phase select the input channel for the next conversion cycle. These address bits are output during the subsequent data read, as shown in Figure 3b. The last bit is a
241418fa
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parity bit representing the parity of the previous 31 bits. The
parity bit is useful to check the output data integrity especially when the output data is transmitted over a distance.
The third and fourth bits together are also used to indicate
an underrange condition (the differential input voltage is below – FS) or an overrange condition (the differential input
voltage is above + FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 3.
Table 3. LTC2414/LTC2418 Status Bits
Input Range
Bit 31 Bit 30 Bit 29 Bit 28
EOC DMY SIG MSB
VIN ≥ 0.5 • VREF
0
0
1
1
0V ≤ VIN < 0.5 • VREF
0
0
1
0
–0.5 • VREF ≤ VIN < 0V
0
0
0
1
VIN < – 0.5 • VREF
0
0
0
0
Bits 28-6 are the 23-bit conversion result MSB first.
Bit 6 is the least significant bit (LSB).
Bits 5-1 are the corresponding channel selection bits for
the present conversion result with bit SGL output first as
shown in Figure 3.
Bit 0 is the parity bit representing the parity of the previous
31 bits. Including the parity bit, the total numbers of 1’s
and 0’s in the output data are always even.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 4 summarizes
the output data format.
As long as the voltage applied to any channel (CH0-CH15,
COM) is maintained within the – 0.3V to (VCC + 0.3V)
absolute maximum operating range, a conversion result is
generated for any differential input voltage VIN from
–FS = – 0.5 • VREF to +FS = 0.5 • VREF. For differential input
voltages greater than +FS, the conversion result is clamped
to the value corresponding to the +FS + 1LSB. For differential input voltages below –FS, the conversion result is
clamped to the value corresponding to –FS – 1LSB.
Frequency Rejection Selection (FO)
The LTC2414/LTC2418 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For
60Hz rejection, FO should be connected to GND while for
50Hz rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
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Table 4. LTC2414/LTC2418 Output Data Format
Differential Input Voltage
VIN *
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 6
LSB
VIN* ≥ 0.5 • VREF**
0
0
1
1
0
0
0
…
0
0.5 • VREF** – 1LSB
0
0
1
0
1
1
1
…
1
0.25 • VREF**
0
0
1
0
1
0
0
…
0
0.25 • VREF** – 1LSB
0
0
1
0
0
1
1
…
1
0
0
0
1
0
0
0
0
…
0
–1LSB
0
0
0
1
1
1
1
…
1
– 0.25 • VREF**
0
0
0
1
1
0
0
…
0
– 0.25 • VREF** – 1LSB
0
0
0
1
0
1
1
…
1
– 0.5 • VREF**
0
0
0
1
0
0
0
…
0
VIN* < –0.5 • VREF**
0
0
0
0
1
1
1
…
1
= IN+
– IN–.
*The differential input voltage VIN
**The differential reference voltage VREF = REF+ – REF–.
While operating with an external conversion clock of a
frequency fEOSC, the converter provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
enters the Internal Conversion Clock mode. The converter
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
–80
–85
NORMAL MODE REJECTION (dB)
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2414/
LTC2418 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the FO pin and turns off the internal
oscillator. The frequency fEOSC of the external signal must
be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods tHEO and tLEO are observed.
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
241418 F04
Figure 4. LTC2414/LTC2418 Normal Mode Rejection
When Using an External Oscillator of Frequency fEOSC
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 5 summarizes the duration of each state and the
achievable output data rate as a function of FO.
SERIAL INTERFACE PINS
The LTC2414/LTC2418 transmit the conversion results
and receive the start of conversion command through a
synchronous 4-wire interface. During the conversion and
sleep states, this interface can be used to assess the converter status and during the data I/O state it is used to read
the conversion result and write in channel selection bits.
241418fa
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Table 5. LTC2414/LTC2418 State Duration
State
Operating Mode
CONVERT
Internal Oscillator
External Oscillator
Duration
FO = LOW
(60Hz Rejection)
133ms, Output Data Rate ≤ 7.5 Readings/s
FO = HIGH
(50Hz Rejection)
160ms, Output Data Rate ≤ 6.2 Readings/s
FO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
SLEEP
DATA OUTPUT
As Long As CS = HIGH Until CS = LOW and SCK
Internal Serial Clock
FO = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
FO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 256/fEOSCms
(32 SCK cycles)
External Serial Clock with
Frequency fSCK kHz
As Long As CS = LOW But Not Longer Than 32/fSCKms
(32 SCK cycles)
Serial Clock Input/Output (SCK)
Serial Data Output (SDO)
The serial clock signal present on SCK (Pin 18) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock and each
input bit is shifted in the SDI pin on the rising edge of the
serial clock.
The serial data output pin, SDO (Pin 17), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2414/LTC2418 create their own serial
clock by dividing the internal conversion clock by 8. In the
External SCK mode of operation, the SCK pin is used as
input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or floating at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
When CS (Pin 16) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Serial Data Input (SDI)
The serial data input pin, SDI (Pin 20), is used to shift in the
channel control bits during the data output state to prepare
the channel selection for the following conversion.
When CS (Pin 16) is HIGH or the converter is in the conversion state, the SDI input is ignored and may be driven
HIGH or LOW. When CS goes LOW and the conversion is
complete, SDO goes low and then SDI starts to shift in bits
on the rising edge of SCK.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 16), is used to test the
conversion status and to enable the data input/output
transfer as described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2414/LTC2418 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data input/
output state (i.e., after the first rising edge of SCK occurs
with CS = LOW). If the device has not finished loading the
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last input bit A0 of SDI by the time CS pulled HIGH, the
address information is discarded and the previous
address is kept.
nal serial clock, 3- or 4-wire I/O, single cycle conversion.
The following sections describe each of these serial interface timing modes in detail. In all these cases, the converter can use the internal oscillator (FO = LOW or FO =
HIGH) or an external oscillator connected to the FO pin.
Refer to Table 6 for a summary.
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
SERIAL INTERFACE TIMING MODES
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The LTC2414/LTC2418’s 4-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exterTable 6. LTC2414/LTC2418 Interface Timing Modes
Configuration
SCK
Source
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 5, 6
External SCK, 3-Wire I/O
External
SCK
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS ↓
CS ↓
Figures 8, 9
Internal SCK, 3-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
2.7V TO 5.5V
VCC
1µF
9
VCC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
19
FO
LTC2414/
LTC2418
REFERENCE
VOLTAGE
0.1V TO VCC
11
REF +
12
REF –
21
•
•
•
ANALOG
INPUTS
TEST EOC
(OPTIONAL)
28
1
•
•
•
8
10
18
SCK
CH0
•
•
•
20
SDI
CH7
SDO
CH8
•
CS
4-WIRE
SPI INTERFACE
17
16
•
•
CH15
COM
GND
15
CS
TEST EOC
BIT 31
SDO
BIT 30
EOC
Hi-Z
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 25
BIT 24
BIT 6
BIT 0
LSB
PARITY
Hi-Z
TEST EOC
Hi-Z
SCK
(EXTERNAL)
SDI
DON’T CARE
(1)
(0)
EN
SGL
ODD/
SIGN
A2
A1
A0
DATA OUTPUT
CONVERSION
DON’T CARE
CONVERSION
241418 F05
SLEEP
SLEEP
Figure 5. External Serial Clock, Single Cycle Operation
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and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 32nd
falling edge of SCK, see Figure 6. On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion. If the device has not finished
loading the last input bit A0 of SDI by the time CS is pulled
HIGH, the address information is discarded and the previous address is kept. This is useful for systems not requiring all 32 bits of output data, aborting an invalid conversion
cycle or synchronizing the start of a conversion.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK
is seen while CS is LOW. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the
first rising edge) and the output data is shifted out of the
SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
2.7V TO 5.5V
VCC
1µF
9
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
19
LTC2414/
LTC2418
11
REFERENCE
VOLTAGE
0.1V TO VCC
12
21
•
•
•
ANALOG
INPUTS
28
1
•
•
•
TEST EOC
(OPTIONAL)
8
10
REF +
REF –
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
20
18
4-WIRE
SPI INTERFACE
17
16
•
•
CH15
COM
GND
15
CS
BIT 0
SDO
TEST EOC
BIT 31
EOC
BIT 30
EOC
Hi-Z
Hi-Z
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 25
BIT 24
Hi-Z
BIT 9
TEST EOC
BIT 8
Hi-Z
SCK
(EXTERNAL)
SDI
SLEEP
DON’T CARE
DATA
OUTPUT
(1)
CONVERSION
(0)
EN
SGL
ODD/
SIGN
A2
A1
DATA OUTPUT
A0
DON’T CARE
CONVERSION
241418 F06
SLEEP
SLEEP
Figure 6. External Serial Clock, Reduced Data Output Length
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External Serial Clock, 3-Wire I/O
each falling edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 32nd falling edge of SCK, SDO
goes HIGH (EOC = 1) indicating a new conversion has
begun.
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 1ms after VCC exceeds approximately 2V. The
level applied to SCK at this time determines if SCK is
internal or external. SCK must be driven LOW prior to the
end of POR in order to enter the external serial clock timing
mode.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The input data is then shifted in via the SDI
pin on the rising edge of SCK (including the first rising
edge) and the output data is shifted out of the SDO pin on
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
2.7V TO 5.5V
VCC
1µF
9
VCC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
19
FO
LTC2414/
LTC2418
REFERENCE
VOLTAGE
0.1V TO VCC
11
REF +
SDI
12
REF –
SCK
21
•
•
•
ANALOG
INPUTS
28
1
•
•
•
8
10
CH0
•
•
•
CH7
SDO
CH8
•
CS
20
18
3-WIRE
SPI INTERFACE
17
16
•
•
CH15
COM
GND
15
CS
BIT 31
SDO
BIT 30
EOC
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 25
BIT 24
BIT 6
BIT 0
LSB
PARITY
SCK
(EXTERNAL)
SDI
DON’T CARE
CONVERSION
(1)
(0)
EN
SGL
ODD/
SIGN
A2
A1
A0
DATA OUTPUT
DON’T CARE
CONVERSION
241418 F07
Figure 7. External Serial Clock, CS = 0 Operation
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2.7V TO 5.5V
VCC
1µF
9
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
19
LTC2414/
LTC2418
REFERENCE
VOLTAGE
0.1V TO VCC
11
REF +
SDI
12
REF –
SCK
21
•
•
•
ANALOG
INPUTS
CH0
•
•
•
28
1
•
•
•
SDO
CH8
•
CS
10k
18
4-WIRE
SPI INTERFACE
17
16
•
•
8
CH15
10
TEST EOC
CH7
VCC
20
COM
GND
15
<tEOCtest
CS
BIT 31
SDO
BIT 30
EOC
Hi-Z
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 25
BIT 24
BIT 6
BIT 0
LSB
PARITY
Hi-Z
TEST EOC
Hi-Z
Hi-Z
SCK
(INTERNAL)
SDI
DON’T CARE
(1)
CONVERSION
(0)
EN
SGL
ODD/
SIGN
A2
A1
A0
DATA OUTPUT
SLEEP
DON’T CARE
CONVERSION
241418 F08
SLEEP
Figure 8. Internal Serial Clock, Single Cycle Operation
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time tEOCtest
after the falling edge of CS (if EOC = 0) or tEOCtest after EOC
goes LOW (if CS is LOW during the falling edge of EOC).
The value of tEOCtest is 23µs if the device is using its internal
oscillator (FO = logic LOW or HIGH). If FO is driven by an
external oscillator of frequency fEOSC, then tEOCtest is
3.6/fEOSC. If CS is pulled HIGH before time tEOCtest, the
device returns to the sleep state and the conversion result
is held in the internal static shift register.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 32nd rising edge. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 32nd rising edge of
SCK. After the 32nd rising edge, SDO goes HIGH (EOC =
1), SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. If the device has not finished loading the
last input bit A0 of SDI by the time CS is pulled HIGH, the
address information is discarded and the previous address is still kept. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
241418fa
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2.7V TO 5.5V
VCC
1µF
9
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
19
LTC2414/
LTC2418
REFERENCE
VOLTAGE
0.1V TO VCC
11
REF +
SDI
12
REF –
SCK
21
•
•
•
ANALOG
INPUTS
TEST EOC
(OPTIONAL)
> tEOCtest
28
1
•
•
•
8
10
CH0
•
•
•
CH7
SDO
CH8
•
CS
VCC
20
10k
18
4-WIRE
SPI INTERFACE
17
16
•
•
CH15
COM
GND
15
<tEOCtest
CS
TEST EOC
BIT 0
SDO
BIT 31
EOC
Hi-Z
BIT 30
EOC
Hi-Z
Hi-Z
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 25
BIT 24
Hi-Z
BIT 8
TEST EOC
Hi-Z
SCK
(INTERNAL)
SDI
SLEEP
DON’T CARE
DATA
OUTPUT
(1)
(0)
EN
CONVERSION
SGL
ODD/
SIGN
A2
A1
A0
DATA OUTPUT
SLEEP
DON’T CARE
CONVERSION
2411 F09
SLEEP
Figure 9. Internal Serial Clock, Reduced Data Output Length
Whenever SCK is LOW, the LTC2414/LTC2418’s internal
pull-up at pin SCK is disabled. Normally, SCK is not externally driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2414/LTC2418’s internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK timing
mode. By adding an external 10k pull-up resistor to SCK,
this pin goes HIGH once the external driver goes Hi-Z. On
the next CS falling edge, the device will remain in the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal, see Figure 10. CS may be permanently tied to ground, simplifying the user interface or
isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
241418fa
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2.7V TO 5.5V
VCC
1µF
9
VCC
FO
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
19
LTC2414/
LTC2418
REFERENCE
VOLTAGE
0.1V TO VCC
11
REF +
12
–
21
•
•
•
ANALOG
INPUTS
28
1
•
•
•
8
10
REF
SDI
SCK
CH0
•
•
•
CH7
SDO
CH8
•
CS
20
18
3-WIRE
SPI INTERFACE
17
16
•
•
CH15
COM
GND
15
CS
BIT 31
SDO
BIT 30
EOC
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 25
BIT 24
BIT 6
BIT 0
LSB
PARITY
SCK
(INTERNAL)
SDI
DON’T CARE
(1)
(0)
EN
SGL
ODD/
SIGN
CONVERSION
A2
A1
A0
DON’T CARE
DATA OUTPUT
CONVERSION
241418 F10
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the 32nd rising edge. The input data is then
shifted in via the SDI pin on the rising edge of SCK
(including the first rising edge) and the output data is
shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2414/LTC2418 are designed to reduce as much as
possible the conversion result sensitivity to device
decoupling, PCB layout, antialiasing circuits, line fre-
quency perturbations and so on. Nevertheless, in order to
preserve the extreme accuracy capability of this part,
some simple precautions are desirable.
Digital Signal Levels
The LTC2414/LTC2418’s digital interface is easy to use.
Its digital inputs (SDI, FO, CS and SCK in External SCK mode
of operation) accept standard TTL/CMOS logic levels and
the internal hysteresis receivers can tolerate edge rates as
slow as 100µs. However, some considerations are required
to take advantage of the exceptional accuracy and low
supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, FO, CS and
SCK in External SCK mode of operation) is within this
range, the power supply current may increase even if the
signal in question is at a valid logic level. For micropower
241418fa
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operation, it is recommended to drive all digital input
signals to full CMOS levels [V IL < 0.4V and
VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins
may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2414/
LTC2418. For reference, on a regular FR-4 board, signal
propagation velocity is approximately 183ps/inch for
internal traces and 170ps/inch for surface traces. Thus, a
driver generating a control signal with a minimum transition time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
Parallel termination near the LTC2414/LTC2418 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27Ω and 56Ω
placed near the driver or near the LTC2414/LTC2418 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input and reference architecture reduce substantially the converter’s
sensitivity to ground currents.
Particular attention must be given to the connection of the
FO signal when the LTC2414/LTC2418 are used with an
external conversion clock. This clock is active during the
conversion time and the normal mode rejection provided
by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the
converter reference terminals may result into DC gain and
INL errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capacitive coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the FO connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or reference. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2414/LTC2418
converters are directly connected to a network of sampling
capacitors. Depending upon the relation between the
differential input voltage and the differential reference
voltage, these capacitors are switching between these
four pins transferring small amounts of charge in the
process. A simplified equivalent circuit is shown in
Figure 11.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure 11), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worstcase circumstances, the errors may add.
When using the internal oscillator (FO = LOW or HIGH), the
LTC2414/LTC2418’s front-end switched-capacitor network is clocked at 76800Hz corresponding to a 13µs
sampling period. Thus, for settling errors of less than
1ppm, the driving source impedance should be chosen
such that τ ≤ 13µs/14 = 920ns. When an external oscillator
of frequency fEOSC is used, the sampling period is 2/fEOSC
and, for a settling error of less than 1ppm, τ ≤ 0.14/fEOSC.
241418fa
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Input Current
If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN + and IN – pins as a result of the
sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2414/LTC2418 pin capacitance (5pF typical) plus the capacitance of the test fixture used to obtain
the results shown in Figures 13 and 14. A careful implementation can bring the total input capacitance (CIN +
CPAR) closer to 5pF thus achieving better performance
than the one predicted by Figures 13 and 14. For simplicity, two distinct situations can be considered.
For relatively small values of input capacitance (CIN <
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
IREF+
VCC
ILEAK
−
VCC
VIN + VINCM − VREFCM
0.5 • REQ
−VIN + VINCM − VREFCM
=
AVG
0.5 • REQ
=
+
ILEAK
RSW (TYP)
20k
AVG
VIN+
CEQ
18pF
(TYP)
ILEAK
VCC
RSW (TYP)
20k
ILEAK
ILEAK
VCC
ILEAK
RSW (TYP)
20k
2414/18 F11
VREF –
−
AVG
=
2
VIN
1.5 • VREF − VINCM + VREFCM
−
0.5 • REQ
VREF • REQ
=
2
VIN
−1.5 • VREF − VINCM + VREFCM
+
0.5 • REQ
VREF • REQ
where:
VREF = REF + − REF −
⎛ REF + + REF − ⎞
VREFCM = ⎜
⎟
2
⎝
⎠
VIN –
IREF –
( )
I(IN )
I(REF )
I(REF )
AVG
ILEAK
IIN –
Larger values of input capacitors (CIN > 0.01µF) may be
required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
I IN+
RSW (TYP)
20k
VREF+
IIN+
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2414/LTC2418 can maintain its exceptional accuracy
while operating with relative large values of source resistance as shown in Figures 13 and 14. These measured
results may be slightly different from the first order
approximation suggested earlier because they include the
effect of the actual second order input network together
with the nonlinear settling process of the input amplifiers.
For small CIN values, the settling on IN+ and IN – occurs
almost independently and there is little benefit in trying to
match the source impedance for the two pins.
ILEAK
VIN = IN+ − IN−
⎛ IN+ − IN− ⎞
VINCM = ⎜
⎟
2
⎝
⎠
(
(
)
)
REQ = 3.61MΩ INTERNAL OSCILLATOR 60Hz Notch FO = LOW
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)
fSW = 0.5 • fEOSC EXTERNAL OSCILLATOR
REQ = 4.32MΩ INTERNAL OSCILLATOR 50Hz Notch FO = HIGH
(
)
REQ = 0.555 • 1012 / fEOSC EXTERNAL OSCILLATOR
Figure 11. LTC2414/LTC2418 Equivalent Analog Input Circuit
241418fa
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RSOURCE
VINCM + 0.5VIN
IN +
CIN
CPAR
≅ 20pF
RSOURCE
VINCM – 0.5VIN
LTC2414/
LTC2418
IN –
CIN
CPAR
≅ 20pF
2414/18 F12
Figure 12. An RC Network at IN+ and IN–
50
0
CIN = 0.01µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
40
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
CIN = 0.001µF
CIN = 100pF
CIN = 0pF
30
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
20
10
0
–10
–20
–30
CIN = 0.01µF
CIN = 0.001µF
–40
CIN = 100pF
CIN = 0pF
–50
1
10
100
1k
RSOURCE (Ω)
10k
100k
1
10
100
1k
RSOURCE (Ω)
2414/18 F13
Figure 13. +FS Error vs RSOURCE
at IN+
or IN–
(Small CIN)
typical differential input resistance is 1.8MΩ which will
generate a gain error of approximately 0.28ppm for each
ohm of source resistance driving IN+ or IN –. When FO =
HIGH (internal oscillator and 50Hz notch), the typical
differential input resistance is 2.16MΩ which will generate
a gain error of approximately 0.23ppm for each ohm of
source resistance driving IN+ or IN –. When FO is driven by
an external oscillator with a frequency fEOSC (external
conversion clock operation), the typical differential input
resistance is 0.28 • 1012/fEOSCΩ and each ohm of
source resistance driving IN+ or IN – will result in
1.78 • 10–6 • fEOSCppm gain error. The effect of the source
resistance on the two input pins is additive with respect to
this gain error. The typical +FS and –FS errors as a function
of the sum of the source resistance seen by IN+ and IN– for
large values of CIN are shown in Figures 15 and 16.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
10k
100k
2414/18 F14
Figure 14. –FS Error vs RSOURCE
at IN+
or IN– (Small CIN)
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modulation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. When FO = LOW (internal
oscillator and 60Hz notch), every 1Ω mismatch in source
impedance transforms a full-scale common mode input
signal into a differential mode input signal of 0.28ppm.
When FO = HIGH (internal oscillator and 50Hz notch), every
1Ω mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 0.23ppm. When FO is driven by an external
oscillator with a frequency fEOSC, every 1Ω mismatch in
source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
241418fa
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1.78 • 10–6 • fEOSCppm. Figure 17 shows the typical offset
error due to input common mode voltage for various
values of source resistance imbalance between the IN+
and IN– pins when large CIN values are used.
+FS ERROR (ppm OF VREF)
300
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
240
180
CIN = 1µF, 10µF
CIN = 0.1µF
120
CIN = 0.01µF
60
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2414/18 F15
Figure 15. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
0
–FS ERROR (ppm OF VREF)
CIN = 0.01µF
–60
–120
CIN = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
–180
–240
CIN = 1µF, 10µF
–300
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2414/18 F16
Figure 16. –FS Error vs RSOURCE
120
OFFSET ERROR (ppm OF VREF)
100
80
B
40
D
0
E
–20
F
–40
–60
FO = GND
TA = 25°C
RSOURCEIN – = 500Ω
CIN = 10µF
G
–80
–100
0
0.5
1
1.5
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
2 2.5 3
VINCM (V)
3.5
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
Reference Current
C
20
–120
or IN– (Large CIN)
VCC = 5V
REF + = 5V
REF – = GND
IN + = IN – = VINCM
A
60
at IN+
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
4
4.5
5
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
2414/18 F17
Figure 17. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance Imbalance
(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
In a similar fashion, the LTC2414/LTC2418 samples the
differential reference pins REF+ and REF– transferring
small amount of charge to and from the external driving
circuits thus producing a dynamic reference current. This
current does not change the converter offset, but it may
degrade the gain and INL performance. The effect of this
current can be analyzed in the same two distinct situations.
For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
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values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi constant reference differential impedance. When FO = LOW
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3MΩ which will generate a gain
error of approximately 0.38ppm for each ohm of source
resistance driving REF+ or REF–. When FO = HIGH (internal
oscillator and 50Hz notch), the typical differential reference resistance is 1.56MΩ which will generate a gain error
of approximately 0.32ppm for each ohm of source resistance driving REF+ or REF–. When FO is driven by an
external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference
resistance is 0.20 • 1012/fEOSCΩ and each ohm of source
resistance driving REF + or REF – will result in
2.47 • 10–6 • fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
REF+ and REF– pins and external capacitance CREF connected to these pins are shown in Figures 18, 19, 20
and 21.
50
CREF = 0.01µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
–10
–20
CREF = 0.001µF
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
–30
CREF = 0.01µF
CREF = 0.001µF
–40
CREF = 100pF
CREF = 0pF
–50
1
10
40
CREF = 100pF
CREF = 0pF
30
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
20
10
0
100
1k
RSOURCE (Ω)
10k
1
100k
10
100
1k
RSOURCE (Ω)
10k
2414/18 F19
2414/18 F18
Figure 18. +FS Error vs RSOURCE
at REF+
or REF–
(Small CIN)
Figure 19. –FS Error vs RSOURCE at REF+ or REF– (Small CIN)
450
0
–90
–180
–360
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
CREF = 0.01µF
–270
100k
CREF = 0.1µF
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
360
270
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
180
CREF = 0.01µF
90
CREF = 1µF, 10µF
0
–450
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2414/18 F21
2414/18 F20
Figure 20. +FS Error vs RSOURCE
at REF+
and REF– (Large C
REF)
Figure 21. –FS Error vs RSOURCE
at REF+
and REF– (Large CREF)
241418fa
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In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100Ω of source resistance driving REF+ or REF– translates
into about 1.34ppm additional INL error. When FO = HIGH
(internal oscillator and 50Hz notch), every 100Ω of source
resistance driving REF+ or REF– translates into about
1.1ppm additional INL error. When FO is driven by an
external oscillator with a frequency fEOSC, every 100Ω of
source resistance driving REF+ or REF– translates into
about 8.73 • 10–6 • fEOSCppm additional INL error.
Figure 22 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF+
and REF– pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF+ and REF– pins rather than to
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
15
12
RSOURCE = 1000Ω
INL (ppm OF VREF)
9
RSOURCE = 500Ω
6
3
0
–3
RSOURCE = 100Ω
–6
–9
–12
–15
–0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
VCC = 5V
FO = GND
REF+ = 5V
CREF = 10µF
TA = 25°C
REF– = GND
2414/18 F22
VINCM = 0.5 • (IN + + IN –) = 2.5V
Figure 22. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF– for
Large CREF Values (CREF ≥ 1µF)
an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a onetime calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2414/LTC2418
can produce up to 7.5 readings per second with a notch
frequency of 60Hz (FO = LOW) and 6.25 readings per
second with a notch frequency of 50Hz (FO = HIGH). The
actual output data rate will depend upon the length of the
sleep and data output phases which are controlled by the
user and which can be made insignificantly short. When
operated with an external conversion clock (FO connected
to an external oscillator), the LTC2414/LTC2418 output
data rate can be increased as desired up to that determined
by the maximum fEOSC frequency of 2000kHz. The duration of the conversion phase is 20510/fEOSC. If fEOSC =
153600Hz, the converter behaves as if the internal oscillator is used and the notch is set at 60Hz. There is no
significant difference in the LTC2414/LTC2418 performance between these two operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2414/LTC2418’s exceptional common
241418fa
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Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the
output data rate) will start to decrease the effectiveness of
the internal autocalibration circuits. This will result in a
progressive degradation in the converter accuracy and
linearity. Typical measured performance curves for output
data rates up to 100 readings per second are shown in
Figures 23, 24, 25, 26, 27, 28, 29 and 30. In order to obtain
the highest possible level of accuracy from this converter
at output data rates above 20 readings per second, the
user is advised to maximize the power supply voltage used
and to limit the maximum ambient operating temperature.
In certain circumstances, a reduction of the differential
reference voltage may be beneficial.
Input Bandwidth
The combined effect of the internal Sinc4 digital filter and
of the analog and digital autocalibration circuits determines the LTC2414/LTC2418 input bandwidth. When the
internal oscillator is used with the notch set at 60Hz
(FO = LOW), the 3dB input bandwidth is 3.63Hz. When the
internal oscillator is used with the notch set at 50Hz
(FO = HIGH), the 3dB input bandwidth is 3.02Hz. If an
external conversion clock generator of frequency fEOSC is
connected to the FO pin, the 3dB input bandwidth is 0.236
• 10–6 • fEOSC.
OFFSET ERROR (ppm of VERROR)
160
120
TA = 25°C
80
40
0
–40
VCC = 5V
–80 V
REF = 5V
TA = 85°C
–120 VIN = 2.5V
VINCM = 2.5V
–160 SDI = GND
FO = EXTERNAL OSCILLATOR
–200
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2414/18 F23
Figure 23. Offset Error vs Output Data Rate and Temperature
2000
0
+FS ERROR (ppm of VREF)
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2414/LTC2418
typical performance can be inferred from Figures 12, 13,
18 and 19 in which the horizontal axis is scaled by 153600/
fEOSC.
200
TA = 25°C
–2000
–4000
–6000
VCC = 5V
TA = 85°C
–8000 VREF = 5V
VIN = 2.5V
–10000 VINCM = 2.5V
SDI = GND
FO = EXTERNAL OSCILLATOR
–12000
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2414/18 F24
Figure 24. +FS Error vs Output Data Rate and Temperature
12000
–FS ERROR (ppm of VREF)
mode rejection and by carefully eliminating common
mode to differential mode conversion sources in the input
circuit. The user should avoid single-ended input filters
and should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
VCC = 5V
VREF = 5V
10000 VIN = 2.5V
TA = 85°C
VINCM = 2.5V
8000 SDI = GND
FO = EXTERNAL OSCILLATOR
6000
4000
2000
TA = 25°C
0
–2000
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2414/18 F25
Figure 25. –FS Error vs Output Data Rate and Temperature
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22
24
23
20
RESOLUTION (BITS)
TA = 85°C
19
18
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
SDI = GND
FO = EXTERNAL OSCILLATOR
RESOLUTION = LOG2(VREF/NOISERMS)
17
16
15
14
13
0
18
TA = 85°C
TA = 25°C
16
14
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
–2.5V < VIN < 2.5V
SDI = GND
FO = EXTERNAL OSCILLATOR
12
10
8
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0
VREF = 5V
VREF = 2.5V
20
19
18
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
SDI = GND
FO = EXTERNAL OSCILLATOR
TA = 25°C
RESOLUTION = LOG2(VREF/NOISERMS)
17
16
15
14
13
18
16
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
VREF = 2.5V
14
10
0
2414/18 F28
Figure 28. Offset Error vs Output
Data Rate and Reference Voltage
2414/18 F30
Figure 30. Resolution (INLMAX ≤ 1LSB) vs
Output Data Rate and Reference Voltage
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled very
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2414/LTC2418 input bandwidth is shown
in Figure 31 for FO = LOW and FO = HIGH. When an external
oscillator of frequency fEOSC is used, the shape of the
LTC2414/LTC2418 input bandwidth can be derived from
Figure 31, FO = LOW curve in which the horizontal axis is
scaled by fEOSC/153600.
The conversion noise (1µVRMS typical for VREF = 5V) can
be modeled by a white noise source connected to a noise
–0.5
–1.0
–1.5
–2.0
FO = HIGH
FO = LOW
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2414/18 F29
Figure 29. Resolution (NoiseRMS ≤ 1LSB) vs
Output Data Rate and Reference Voltage
VREF = 5V
TA = 25°C
VCC = 5V
REF – = GND
VINCM = 0.5 • REF +
–0.5V • VREF < VIN < 0.5 • VREF
SDI = GND
FO = EXTERNAL OSCILLATOR
12
8
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0.0
RESOLUTION =
LOG2(VREF/INLMAX)
20
RESOLUTION (BITS)
RESOLUTION (BITS)
21
VREF = 2.5V
0
0
22
22
50
Figure 27. Resolution (INLRMS ≤ 1LSB)
vs Output Data Rate and Temperature
24
23
VREF = 5V
2414/18 F27
2414/18 F26
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
FO = EXTERNAL OSCILLATOR
VCC = 5V
REF – = GND
150 V = 0V
IN
VINCM = 2.5V
SDI = GND
100 TA = 25°C
–50
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
INPUT SIGNAL ATTENUATION (dB)
RESOLUTION (BITS)
TA = 25°C
21
12
OFFSET ERROR (ppm of VREF)
20
22
12
200
RESOLUTION = LOG2(VREF/INLMAX)
–6.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2414/18 F31
Figure 31. Input Signal Bandwidth
Using the Internal Oscillator
free converter. The noise spectral density is 78nV/√Hz for
an infinite bandwidth source and 107nV/√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplification circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is a
high gain, low bandwidth amplifier stage followed by a
high bandwidth unity-gain buffer.
241418fa
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INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
100
FO = LOW
10
FO = HIGH
1
0.1
0.1
1
10 100 1k 10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz) 2414/18 F32
Figure 32. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
0
INPUT NORMAL MODE REJECTION (dB)
When external amplifiers are driving the LTC2414/
LTC2418, the ADC input referred system noise calculation
can be simplified by Figure 32. The noise of an amplifier
driving the LTC2414/LTC2418 input pin can be modeled
as a band limited white noise source. Its bandwidth can be
approximated by the bandwidth of a single pole lowpass
filter with a corner frequency fi. The amplifier noise spectral density is ni. From Figure 32, using fi as the x-axis
selector, we can find on the y-axis the noise equivalent
bandwidth freqi of the input driving amplifier. This bandwidth includes the band limiting effects of the ADC internal
calibration and filtering. The noise of the driving amplifier
referred to the converter input and including all these
effects can be calculated as N = ni • √freqi. The total system
noise (referred to the LTC2414/LTC2418 input) can now
be obtained by summing as square root of sum of squares
the three ADC input referred noise sources: the LTC2414/
LTC2418 internal noise (1µV), the noise of the IN + driving
amplifier and the noise of the IN – driving amplifier.
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 32 can still be used for noise calculation if the
x-axis is scaled by fEOSC/153600. For large values of the
ratio fEOSC/153600, the Figure 32 plot accuracy begins to
decrease, but in the same time the LTC2414/LTC2418
noise floor rises and the noise contribution of the driving
amplifiers lose significance.
–10
FO = HIGH
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2414/18 F33
Normal Mode Rejection and Antialiasing
The Sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2414/LTC2418’s autocalibration circuits further simplify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN in the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz and with a
60Hz notch setting fS = 15360Hz. In the external oscillator
mode, fS = fEOSC/10.
0
INPUT NORMAL MODE REJECTION (dB)
One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2414/LTC2418 significantly simplify antialiasing filter requirements.
Figure 33. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
FO = LOW OR
FO = EXTERNAL
OSCILLATOR,
fEOSC = 10 • fS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2414/18 F34
Figure 34. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
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The combined normal mode rejection performance is
shown in Figure 33 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure 34 for the internal
oscillator with 60Hz notch setting (FO = LOW) and for the
external oscillator mode. The regions of low rejection
occurring at integer multiples of fS have a very narrow
bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure 35 (rejection near DC) and
Figure 36 (rejection at fS = 256fN) where fN represents the
notch frequency. These curves have been derived for the
external oscillator mode but they can be used in all
operating modes by appropriately selecting the fN value.
As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front
of the LTC2414/LTC2418. If passive RC components are
placed in front of the LTC2414/LTC2418, the input dynamic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of dynamic input current.
0
0
–10
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demonstrated by Figures 37 and 38. Typical measured values of
the normal mode rejection of the LTC2414/LTC2418
operating with an internal oscillator and a 60Hz notch
setting are shown in Figure 37 superimposed over the
theoretical calculated curve. Similarly, typical measured
values of the normal mode rejection of the LTC2414/
LTC2418 operating with an internal oscillator and a 50Hz
notch setting are shown in Figure 38 superimposed over
the theoretical calculated curve.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
–40
–50
–60
–70
–80
–90
–100
–110
2414/18 F36
Figure 35. Input Normal Mode Rejection
Figure 36. Input Normal Mode Rejection
0
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
SDI = GND
FO = GND
TA = 25°C
–80
–100
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2414/18 F37
Figure 37. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (60Hz Notch)
NORMAL MODE REJECTION (dB)
0
NORMAL MODE REJECTION (dB)
–30
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
2414/18 F35
–120
–20
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
SDI = GND
FO = 5V
TA = 25°C
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2414/18 F38
Figure 38. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full Scale (50Hz Notch)
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Traditional high order delta-sigma modulators, while
providing very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The proprietary architecture used for the LTC2414/LTC2418 third
order modulator resolves this problem and guarantees a
predictable stable behavior at input signal levels of up to
150% of full scale. In many industrial applications, it is not
uncommon to have to measure microvolt level signals
superimposed over volt level perturbations and LTC2414/
LTC2418 is eminently suited for such tasks. When the
perturbation is differential, the specification of interest is
the normal mode rejection for large input signal levels.
With a reference voltage VREF = 5V, the LTC2414/LTC2418
has a full-scale differential input range of 5V peak-to-peak.
Figures 39 and 40 show measurement results for the
LTC2414/LTC2418 normal mode rejection ratio with a 7.5V
peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full scale)
input signal. In Figure 39, the LTC2414/LTC2418 uses the
internal oscillator with the notch set at 60Hz (FO = LOW)
and in Figure 40 it uses the internal oscillator with the
notch set at 50Hz (FO = HIGH). It is clear that the LTC2414/
LTC2418 rejection performance is maintained with no compromises in this extreme situation. When operating with
large input signal levels, the user must observe that such
signals do not violate the device absolute maximum
ratings.
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
SDI = GND
FO = GND
TA = 25°C
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2414/18 F39
Figure 39. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
– 60
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
SDI = GND
FO = 5V
TA = 25°C
–80
–100
–120
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2414/18 F40
Figure 40. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)
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BRIDGE APPLICATIONS
Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2414/LTC2418 is 5V, remote sensing of applied excitation without additional circuitry requires that excitation
be limited to 5V. This gives only 10mV full scale input
signal, which can be resolved to 1 part in 10000 without
averaging. For many solid state sensors, this is still better
than the sensor. Averaging 64 samples however reduces
the noise level by a factor of eight, bringing the resolving
power to 1 part in 80000, comparable to better weighing
systems. Hysteresis and creep effects in the load cells are
typically much greater than this. Most applications that
require strain measurements to this level of accuracy are
measuring slowly changing phenomena, hence the time
required to average a large number of readings is usually
not an issue. For those systems that require accurate
measurement of a small incremental change on a significant tare weight, the lack of history effects in the LTC2400
family is of great benefit.
For those applications that cannot be fulfilled by the
LTC2414/LTC2418 alone, compensating for error in external amplification can be done effectively due to the “no
latency” feature of the LTC2414/LTC2418. No latency
operation allows samples of the amplifier offset and gain
to be interleaved with weighing measurements. The use of
correlated double sampling allows suppression of 1/f
noise, offset and thermocouple effects within the bridge.
Correlated double sampling involves alternating the polarity of excitation and dealing with the reversal of input
polarity mathematically. Alternatively, bridge excitation
can be increased to as much as ±10V, if one of several
precision attenuation techniques is used to produce a
precision divide operation on the reference signal. Another option is the use of a reference within the 5V input
range of the LTC2414/LTC2418 and developing excitation
via fixed gain, or LTC1043 based voltage multiplication,
along with remote feedback in the excitation amplifiers, as
shown in Figures 46 and 47.
Figure 41 shows an example of a simple bridge connection. Note that it is suitable for any bridge application
where measurement speed is not of the utmost importance. For many applications where large vessels are
weighed, the average weight over an extended period of
time is of concern and short term weight is not readily
determined due to movement of contents, or mechanical
resonance. Often, large weighing applications involve load
cells located at each load bearing point, the output of
which can be summed passively prior to the signal processing circuitry, actively with amplification prior to the
ADC, or can be digitized via multiple ADC channels and
summed mathematically. The mathematical summation
of the output of multiple LTC2414/LTC2418’s provides the
benefit of a root square reduction in noise. The low power
consumption of the LTC2414/LTC2418 makes it attractive
for multidrop communication schemes where the ADC is
located within the load-cell housing.
+
R1
350Ω
BRIDGE
0.1µF
LT1019
10µF
0.1µF
9
11
REF +
12
REF –
21
VCC
SDI
SCK
SDO
CH0
CS
20
18
17
16
LTC2414/
LTC2418
22
CH1
GND
R2
FO
19
15
2414/18 F41
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
Figure 41. Simple Bridge Connection
A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to
the sensor largely eliminates the need for protection
devices, RFI suppression and wiring. The LTC2414/
LTC2418 exhibits extremely low temperature dependent
drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates thermal stability, as input offset voltages and currents, temperature coefficient of gain settling resistors all
become factors.
241418fa
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changes the rationale. Achieving high gain accuracy and
linearity at higher gains may prove difficult, while providing little benefit in terms of noise reduction.
The circuit in Figure 42 shows an example of a simple
amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as
determined by the bridge. The use of a true three amplifier
instrumentation amplifier is not necessary, as the LTC2414/
LTC2418 has common mode rejection far beyond that of
most amplifiers. The LTC1051 is a dual autozero amplifier
that can be used to produce a gain of 15 before its input
referred noise dominates the LTC2414/LTC2418 noise.
This example shows a gain of 34, that is determined by a
feedback network built using a resistor array containing 8
individual resistors. The resistors are organized to optimize temperature tracking in the presence of thermal
gradients. The second LTC1051 buffers the low noise
input stage from the transient load steps produced during
conversion.
At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is –1ppm, however,
worst-case is at the minimum gain of 116dB, giving a gain
error of –158ppm. Worst-case gain error at a gain of 34,
is –54ppm. The use of the LTC1051A reduces the worstcase gain error to –33ppm. The advantage of gain higher
than 34, then becomes dubious, as the input referred
noise sees little improvement and gain accuracy is potentially compromised.
Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in
the output stage that usually dominates when and instrumentation amplifier is used at low gain. If this amplifier is
used at a gain of 10, the gain error is only 10ppm and input
referred noise is reduced to 0.1µVRMS. The buffer stages
can also be configured to provide gain of up to 50 with high
gain stability and linearity.
The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor matching. A gain of 34 may seem low, when compared to
common practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2414/LTC2418
5VREF
0.1µF
5V
3
8
+
2
5V
–
2
4
350Ω
BRIDGE
–
14
4
5
12
3
1
RN1
16
6
11
7
2
6
8
3
RN1 = 5k × 8 RESISTOR ARRAY
U1A, U1B, U2A, U2B = 1/2 LTC1051
11
REF +
12
REF –
4
21
VCC
SDI
SCK
SD0
CH0
CS
13
U2B
5
20
18
17
16
LTC2414/
LTC2418
–
7
+
1
9
6
–
U1B
5
10
+
2
8
U2A
15
0.1µF
0.1µF
1
U1A
7
22
CH1
GND
+
FO
19
15
2414/18 F42
Figure 42. Using Autozero Amplifiers to Reduce Input Referred Noise
241418fa
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LTC2414/LTC2418
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APPLICATIO S I FOR ATIO
Remote Half Bridge Interface
Figure 43 shows an example of a single amplifier used to
produce single-ended gain. This topology is best used in
applications where the gain setting resistor can be made
to match the temperature coefficient of the strain gauges.
If the bridge is composed of precision resistors, with only
one or two variable elements, the reference arm of the
bridge can be made to act in conjunction with the feedback
resistor to determine the gain. If the feedback resistor is
incorporated into the design of the load cell, using resistors which match the temperature coefficient of the loadcell elements, good results can be achieved without the
need for resistors with a high degree of absolute accuracy.
The common mode voltage in this case, is again a function
of the bridge output. Differential gain as used with a 350Ω
bridge is AV = (R1+ R2)/(R1+175Ω). Common mode gain
is half the differential gain. The maximum differential
signal that can be used is 1/4 VREF, as opposed to 1/2 VREF
in the 2-amplifier topology above.
As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output, as signal swing is often much greater. Applications
include RTD’s, thermistors and other resistive elements
that undergo significant changes over their span. For
single variable element bridges, the nonlinearity of the half
bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC,
as shown in Figure 44. The LTC2414/LTC2418 can accept
inputs up to 1/2 VREF. Hence, the reference resistor R1
must be at least 2x the highest value of the variable
resistor.
In the case of 100Ω platinum RTD’s, this would suggest a
value of 800Ω for R1. Such a low value for R1 is not
advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.
5V
+
VS
2.7V TO 5.5V
10µF
0.1µF
5V
9
350Ω
BRIDGE
3
+
0.1µV
7
LTC1050S8
2
+
–
9
6
175Ω
REF +
12
REF –
+
1µF
4
11
20k
21
1µF
R1
4.99k
R2
46.4k
VCC
R1
25.5k
0.1%
VCC
21
CH0
PLATINUM
100Ω
RTD
LTC2414/
LTC2418
20k
22
11 REF +
LTC2414/
LTC2418
12
REF –
22
CH0
CH1
GND
15
CH1
GND
15
2410 F50
AV = 9.95 =
(
R1 + R2
R1 + 175Ω
)
Figure 43. Bridge Amplification Using a Single Amplifier
2410 F49
Figure 44. Remote Half Bridge Interface
241418fa
38
LTC2414/LTC2418
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APPLICATIO S I FOR ATIO
The basic circuit shown in Figure 44 shows connections
for a full 4-wire connection to the sensor, which may be
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however, the
reference inputs do not have the same rejection. If 60Hz or
other noise is present on the reference input, a low pass
filter is recommended as shown in Figure 45. Note that you
cannot place a large capacitor directly at the junction of R1
and R2, as it will store charge from the sampling process.
A better approach is to produce a low pass filter decoupled
from the input lines with a high value resistor (R3).
The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set the
excitation current with a 100Ω RTD, the negative reference input is sampling the same external node as the
positive input and may result in errors if used with a long
cable. For short cable applications, the errors may be
acceptably low. If instead the single 25k resistor is replaced with a 10k 5% and a 10k 0.1% reference resistor,
the noise level introduced at the reference, at least at
higher frequencies, will be reduced. A filter can be introduced into the network, in the form of one or more
capacitors, or ferrite beads, as long as the sampling pulses
are not translated into an error. The reference voltage is
also reduced, but this is not undesirable, as it will decrease
the value of the LSB, although, not the input referred noise
level.
The circuit shown in Figure 45 shows a more rigorous
example of Figure 44, with increased noise suppression
and more protection for remote applications.
Figure 46 shows an example of gain in the excitation circuit
and remote feedback from the bridge. The LTC1043’s
provide voltage multiplication, providing ±10V from a 5V
reference with only 1ppm error. The amplifiers are used at
unity gain and introduce very little error due to gain error
or due to offset voltages. A 1µV/°C offset voltage drift
translates into 0.05ppm/°C gain error. Simpler alternatives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar to
bridge sensing schemes via attenuators. Note that the
amplifiers must have high open-loop gain or gain error will
be a source of error. The fact that input offset voltage has
relatively little effect on overall error may lead one to use
low performance amplifiers for this application. Note that
the gain of a device such as an LF156, (25V/mV over
temperature) will produce a worst-case error of –180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce –10V from a 5V reference.
5V
R2
10k
0.1%
R1
10k, 5%
PLATINUM
100Ω
RTD
5V
R3
10k
5%
+
1µF
LTC1050
9
11
560Ω 12
–
REF +
VCC
REF –
LTC2414/
LTC2418
10k
21
10k
22
CH0
CH1
GND
15
2410 F51
Figure 45. Remote Half Bridge Sensing with Noise Suppression on Reference
241418fa
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APPLICATIO S I FOR ATIO
The error associated with the 10V excitation would be
–80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.
is configured to provide 10V and –5V excitation to the
bridge, producing a common mode voltage at the input to
the LTC2414/LTC2418 of 2.5V, maximizing the AC input
range for applications where induced 60Hz could reach
amplitudes up to 2VRMS.
Figure 47 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit
15V
7
20Ω
Q1
2N3904
6
+
–
10V
3
200Ω
2
10V
LT1236-5
47µF
11
0.1µF
*
12
13
14
+
10µF
0.1µF
1k
5V
7
1µF
–15V
33Ω
8
+
LTC1150
4
350Ω
BRIDGE
15V
U1
4
LTC1043
15V
17
10V
5V
0.1µF
9
VCC
LTC2414/
LTC2418
11
REF +
12
REF –
–10V
33Ω
21
22
U2
LTC1043
15V
7
Q2
2N3906
6
+
3
4
–15V
–
15
6
2
2
*
3
–15V
1k
CH1
GND
5
LTC1150
20Ω
CH0
15
18
0.1µF
*FLYING CAPACITORS ARE
1µF FILM (MKP OR EQUIVALENT)
5V
U2
4
LTC1043
8
7
SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1
11
1µF
FILM
*
12
200Ω
14
13
–10V
17
–10V
2410 F52
Figure 46. LTC1043 Provides Precise 4X Reference for Excitation Voltages
241418fa
40
LTC2414/LTC2418
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APPLICATIO S I FOR ATIO
15V
+
20Ω
Q1
2N3904
1/2
LT1112
1
–
C1
0.1µF
22Ω
5V
3
LT1236-5
+
C3
47µF
2
C1
0.1µF
RN1
10k
10V
1
5V
2
3
4
350Ω BRIDGE
TWO ELEMENTS
VARYING
9
RN1
10k
VCC
LTC2414/
LTC2418
11
REF +
12
REF –
21
–5V
22
8
RN1
10k
5
7
CH1
GND
15
6
15V
C2
0.1µF
33Ω
×2
Q2, Q3
2N3906
×2
RN1
10k
CH0
20Ω
7
RN1 IS CADDOCK T914 10K-010-02
8
–
1/2
LT1112
4
–15V
–15V
+
6
5
2410 F53
Figure 47. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
MULTIPLE CHANNEL USAGE
The LTC2414/LTC2418 have up to sixteen input channels
and this feature provides a very flexible and efficient
solution in applications where more than one variable
need to be measured.
Measurements of a Ladder of Sensors
In industrial process, it is likely that a large group of real
world phenomena need to be monitored where the speed
is not critical. One example is the cracking towers in
petroleum refineries where a group of temperature measurements need to be taken and related. This is done by
passing an excitation current through a ladder of RTDs.
The configuration using a single LTC2418 to monitor up to
eight RTDs in differential mode is shown in Figure 48. A
high accuracy R1 is used to set the excitation current and
the reference voltage. A larger value of 25k is selected to
reduce the self-heating effects. R1 can also be broken into
two resistors, one 25k to set the excitation current and the
other a high accuracy 1k resistor to set the reference
voltage, assuming 100Ω platinum RTDs. This results in a
reduced reference voltage and a reduced common mode
difference between the reference and the input signal,
which improves the conversion linearity and reduces total
error.
Each input should be taken close to the related RTD to
minimize the error caused by parasitic wire resistance.
The interference on a signal transmission line from RTD to
the LTC2418 is rejected due to the excellent common
mode rejection and the digital LPF included in the LTC2418.
It should be noted that the input source resistance of CHO
can have a maximum value of 800Ω • 8 = 6.4k, so the
parasitic capacitance and resistance of the connection
wires need to be minimized in order not to degrade the
converter performance.
241418fa
41
LTC2414/LTC2418
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Figure 49 shows the 4-wire SPI connection between the
LTC2414/LTC2418 and a PIC16F84 microcontroller. The
sample program for CC5X compiler in Figure 50 can be
used to program the PIC16F84 to control the LTC2414/
LTC2418. It uses PORT B to interface with the device.
5V
0.1µF
+
10µF
R1
25k
0.1%
9
11
REF +
12
REF –
VCC
LTC2418
21
PT1
100Ω
RTD
22
23
PT2
100Ω
RTD
CH1
SDI
CH2
SCK
24
•
•
•
PT8
100Ω
RTD
CH0
CH3
•
•
•
7
CH14
8
SDO
CS
CH15
GND
FO
20
18
4-WIRE
SPI
17
16
19
15
2418 F48
Figure 48. Measurement of a Ladder of Sensors Using
Differential Mode
The program begins by declaring variables and allocating
four memory locations to store the 32-bit conversion
result. In execution, it first initiates the PORT B to the
proper SPI configuration and prepares channel address.
The LTC2414/LTC2418 is activated by setting the CS low.
Then the microcontroller waits until a logic LOW is detected on the data line, signifying end-of-conversion. After
a LOW is detected, a subroutine is called to exchange data
between the LTC2414/LTC2418 and the microcontroller.
The main loop ends by setting CS high, ending the data
output state.
The performance of the LTC2414/LTC2418 can be verified
using the demonstration board DC434A, see Figure 51 for
the schematic. This circuit uses the computer’s serial port
to generate power and the SPI digital signals necessary for
starting a conversion and reading the result. It includes a
Multichannel Bridge Digitizer and Digital Cold
Junction Compensation
The bridge application as shown in Figures 41, 42, and 43
can be expanded to multiple bridge transducers. Figure 54
shows the expansion for simple bridge measurement.
Also included is the temperature measurement.
In Figure 54, CH0 to CH13 are configured as differential to
measure up to seven bridge transducers using the LTC2418.
CH14 and CH15 are configured as single-ended. CH14
measures the thermocouple while CH15 measures the
output of the cold junction sensor (diode, thermistor,
etc.). The measured cold junction sensor output is then
used to compensate the thermocouple output to find the
absolute temperature. The final temperature value may
then be used to compensate the temperature effects of the
bridge transducers.
Sample Driver for LTC2414/LTC2418 SPI Interface
PIC16F84
LTC2414/
LTC2418
SCK
SDI
SDO
CS
18
20
17
16
8
9
10
11
RB2
RB3
RB4
RB5
2414/18 F49
Figure 49. Connecting the LTC2414/LTC2418 to
a PIC16F84 MCU Using the SPI Serial Interface
LabVIEWTM application software program (see Figure 52)
which graphically captures the conversion results. It can
be used to determine noise performance, stability and with
an external source linearity. As exemplified in the schematic, the LTC2414/LTC2418 is extremely easy to use.
This demonstration board and associated software is
available by contacting Linear Technology.
The LTC2414/LTC2418 have a simple 4-wire serial interface and it is easy to program microprocessors and
microcontrollers to control the device.
241418fa
42
LTC2414/LTC2418
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APPLICATIO S I FOR ATIO
// LTC2418 PIC16F84 Interface Example
// Written for CC5X Compiler
// Processor is PIC16F84 running at 10 MHz
#include <16f84.h>
#include <int16cxx.h>
#pragma origin = 0x4
#pragma config |= 0x3fff, WDTE=off,FOSC=HS
// global pin definitions:
#pragma bit rx_pin
#pragma bit tx_pin
#pragma bit sck
#pragma bit sdi
#pragma bit sdo
#pragma bit cs_bar
@
@
@
@
@
@
PORTB.0
PORTB.1
PORTB.2
PORTB.3
PORTB.4
PORTB.5
//input
//output
//output
//output
//input
//output
// Global Variables
uns8 result_3;
uns8 result_2;
uns8 result_1;
uns8 result_0;
//
//
//
//
void shiftbidir(char nextch);
// function prototype
Conversion result MS byte
..
..
Conversion result LS byte
void main( void)
{
INTCON=0b00000000;
TRISA=0b00000000;
TRISB=0b00010001;
// no interrupts
// all PORTA pins outputs
// according to definitions above
char channel;
// next channel to send
while(1)
{
/* channel bit fields are 7:6, 10 always; 5, EN; 4, SGL; 3, ODD/SIGN; 2:0, ADDR */
channel = 0b10101000;
cs_bar=0;
// CH0,1 DIFF.
// activate ADC
while(sdo==1)
{
// test for end of conversion
// wait if conversion is not complete
}
shiftbidir(channel);
// read ADC, send next channel
cs_bar = 1;
// deactivate ADC
/* At this point global variables result 3,2,1 contain the 24 bit conversion result. Variable result3
contains the corresponding channel information in the following fields:
bits 7:6, 00 always, 5, EN; 4, SGL; 3, ODD/SIGN; 2:0, ADDR */
}
}
// end of loop
// end of main
Figure 50. Sample Program in CC5X for PIC16F84
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////////// Bidirectional Shift Routine for ADC //////////
void shiftbidir(char nextch)
{
int i;
for(i=0;i<2;i++)
// send config bits 7:6,
// ignore EOC/ and DMY bits
{
sdi=nextch.7;
nextch = rl(nextch);
sck=1;
sck=0;
//
//
//
//
put data on pin
get next config bit ready
clock high
clock low
}
for(i=0;i<8;i++)
// send config, read byte 3
{
sdi=nextch.7;
// put data on pin
nextch = rl(nextch);
// get next config bit ready
result_3 = rl(result_3);// get ready to load lsb
result_3.0 = sdo;
// load lsb
sck=1;
// clock high
sck=0;
// clock low
}
for(i=0;i<8;i++)
// read byte 2
{
result_2 = rl(result_2);// get ready to load lsb
result_2.0 = sdo;
// load lsb
sck=1;
// clock high
sck=0;
// clock low
}
for(i=0;i<8;i++)
// read byte 1
{
result_1 = rl(result_1);// get ready to load lsb
result_1.0 = sdo;
// load lsb
sck=1;
// clock high
sck=0;
// clock low
}
result_0=0;
for(i=0;i<6;i++)
// ensure bits 7:6 are zero
// read byte 0
{
result_0 = rl(result_0);// get ready to load lsb
result_0.0 = sdo;
// load lsb
sck=1;
// clock high
sck=0;
// clock low
}
}
Figure 50. Sample Program in CC5X for PIC16F84 (cont)
241418fa
44
LTC2414/LTC2418
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APPLICATIO S I FOR ATIO
VCC
1
JP1
JMPR
VCC 2.5V
3
C1 +
10µF
35V
2
BANANA
JACK
J1
VEX
J2
REF +
J3
REF –
J4
1
GND
2.5V
JP3
JMPR
VIN
VOUT
GND
2
C3
10µF
35V
3
+
VOUT
VIN
GND
E1
R1
10Ω
+
VEXT
E2
C4
100µF
16V
GND
JP2
JMPR
P1
DB9
1
6
2
7
3
8
4
9
5
3
2
NC
VCC
NC
D1
BAV74LT1
U2
LT1236ACN8-5
1
5V
1
JP5
JMPR
VCC
C2
22µF
25V
R2
3Ω
VCC
E3
1
C6
0.1µF
3
+
GND
VCC
2
REMOVE TO
DISCONNECT
VCC AND
5V REF
U1
LT1460ACN8-2.5
+
C5
10µF
35V
50Hz/60Hz
JP4
JMPR
3
U3F
74HC14
R3
51k
U3B
74HC14
U3A
74HC14
R4
51k
2
9
E4
GND
U3E
74HC14
VCC
U5
LTC2418CGN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
P2
CON40A
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
12
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
REF+
REF–
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
CH11
CH12
CH13
CH14
CH15
FO
SCK
SDO
CS
SDI
19
18
17
16
20
U3C
74HC14
VCC
13
NC
14
NC
15
GND
VCC
10
11
12
13
14
3
4
5
6
2
15
1
16
VCC
SER
A
B
U4
C
74HC165
D
E
F
G
H
9
QH
CLK
7
QH
INH
8
SH/LD GND
COM
10
1
2
GND
3
U3D
74HC14
JP6
JMPR
R6
3k
R5
49.9Ω
R7
22k
Q1
MMBT3904LT1
R8
51k
VCC
VCC
C7
0.1µF
C8
0.1µF
BYPASS
CAPACITOR
FOR U3 AND U4
2414/18 F51
NC
Figure 51. Demo Board Schematic
241418fa
45
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Figure 52. LTC2418 Demo Program Display
Top Silkscreen
Top Layer
Bottom Layer
Figure 53. PCB Layout and Film
241418fa
46
LTC2414/LTC2418
U
PACKAGE DESCRIPTIO
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.0075 – 0.0098
(0.191 – 0.249)
0.033
(0.838)
REF
2 3
4
5 6
7
8
9 10 11 12 13 14
0.053 – 0.069
(1.351 – 1.748)
0.004 – 0.009
(0.102 – 0.249)
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
GN28 (SSOP) 1098
241418fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
47
LTC2414/LTC2418
U
TYPICAL APPLICATIO
5V
0.1µF
+
10µF
9
11
REF +
VCC
12
REF –
LTC2418
LTC2418
•
•
•
THERMISTOR
21
CH0
THERMOCOUPLE
22
23
CH1
SDI
CH2
SCK
24
CH3
•••
•
7
CH14
8
10
SDO
CS
CH15
FO
20
18
17
16
19
COM
GND
15
2418 F54
Figure 54. Multichannel Bridge Digitizer and Digital Cold Junction Compensation
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max Initial Accuracy
LT1025
Micropower Thermocouple Cold Junction Compensator
80µA Supply Current, 0.5°C Initial Accuracy
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
24-Bit, Fully Differential, No Latency ∆Σ ADC
0.16ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2411
24-Bit, Fully Differential, No Latency∆Σ ADC in MSOP
0.3ppm Noise, 2ppm INL, 3ppm Total Unadjusted Error, 200µA
LTC2411-1
24-Bit, Simultaneous 50Hz/60Hz Rejection ∆Σ ADC
0.3ppm Noise, 2ppm INL, Pin Compatible with LTC2411
LTC2413
24-Bit, Fully Differential, No Latency ∆Σ ADC
Simultaneous 50Hz and 60Hz Rejection, 800nVRMS Noise
LTC2415/LTC2415-1
24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate
Pin Compatible with the LTC2410/LTC2413
LTC2420
20-Bit, No Latency ∆Σ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428
4-/8-Channel, 20-Bit, No Latency ∆Σ ADC
1.2ppm Noise, Pin Compatible with LTC2404/LTC2408
241418fa
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Linear Technology Corporation
LT 1105 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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