CY7C10612DV33 16-Mbit (1M x 16) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns The CY7C10612DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 175 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 25 mA ■ Operating voltages of 3.3 ± 0.3V To write to the device, take Chip Enables (CE) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19). ■ 2.0V data retention ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 54-Pin TSOP II package To read from the device, take Chip Enables (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 9 for a complete description of Read and Write modes. The input or output pins (IO0 through IO15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). The CY7C10612DV33 is available in a 54-Pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram 1M x 16 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER IO0 – IO7 IO8 – IO15 A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 COLUMN DECODER Cypress Semiconductor Corporation Document Number: 001-49315 Rev. *A • 198 Champion Court BHE WE CE OE BLE • San Jose, CA 95134-1709 • 408-943-2600 Revised June 15, 2009 [+] Feedback CY7C10612DV33 Selection Guide Description –10 Unit Maximum Access Time 10 ns Maximum Operating Current 175 mA Maximum CMOS Standby Current 25 mA Pin Configuration Figure 1. 54-Pin TSOP II (Top View) [1] IO12 VCC IO13 IO14 VSS IO15 A4 A3 A2 A1 A0 BHE CE VCC WE NC A19 A18 A17 A16 A15 IO0 VCC IO1 IO2 VSS IO3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 IO11 VSS IO10 IO9 VCC IO8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC OE VSS NC BLE A10 A11 A12 A13 A14 IO7 VSS IO6 IO5 VCC IO4 54 53 52 51 50 49 48 47 46 Note 1. NC pins are not connected on the die. Document Number: 001-49315 Rev. *A Page 2 of 10 [+] Feedback CY7C10612DV33 DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage.................................................>2001V Storage Temperature ................................. –65°C to +150°C (MIL-STD-883, Method 3015) Ambient Temperature with Power Applied ............................................ –55°C to +125°C Latch Up Current ..................................................... >200 mA Operating Range Supply Voltage on VCC Relative to GND [2] ....–0.5V to +4.6V DC Voltage Applied to Outputs in High Z State [2] ................................... –0.5V to VCC + 0.5V Range Ambient Temperature VCC Industrial –40°C to +85°C 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage [2] –10 Min Unit Max 2.4 V 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC –1 +1 μA IOZ Output Leakage Current GND < VOUT < VCC, Output disabled –1 +1 μA ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels 175 mA ISB1 Automatic CE Power Down Max VCC, CE > VIH, Current — TTL Inputs VIN > VIH or VIN < VIL, f = fMAX 30 mA ISB2 Automatic CE Power Down Max VCC, CE > VCC – 0.3V, Current —CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 25 mA Note 2. VIL (min) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. Document Number: 001-49315 Rev. *A Page 3 of 10 [+] Feedback CY7C10612DV33 Capacitance Tested initially and after any design or process changes that may affect these parameters. Description Test Conditions CIN Parameter Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V COUT IO Capacitance TSOP II Unit 6 pF 8 pF TSOP II Unit 24.18 °C/W 5.40 °C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board The AC Test Loads and Waveforms diagram follows. [3] Figure 2. AC Test Loads and Waveforms HIGH-Z CHARACTERISTICS: R1 317Ω 3.3V 50Ω VTH = 1.5V OUTPUT Z0 = 50Ω OUTPUT 30 pF* 5 pF* INCLUDING JIG AND SCOPE (b) (a) * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT R2 351Ω ALL INPUT PULSES 3.0V GND 90% 90% 10% RISE TIME: > 1 V/ns 10% (c) FALL TIME: > 1 V/ns Note 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 μs (tpower) after reaching the minimum operating VDD, normal SRAM operation begins including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document Number: 001-49315 Rev. *A Page 4 of 10 [+] Feedback CY7C10612DV33 AC Switching Characteristics Over the Operating Range [4] Parameter Description –10 Min Max Unit Read Cycle tpower VCC(Typical) to the First Access [5] 100 μs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns tLZOE OE LOW to Low Z [6] [6] tLZCE CE LOW to Low Z tHZCE CE HIGH to High Z [6] tPU CE LOW to Power Up [7] tPD CE HIGH to Power Down tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low Z ns 5 ns 5 ns ns 0 [7] ns ns 3 ns 10 ns 5 ns 1 Byte Disable to High Z tHZBE Write Cycle 3 1 OE HIGH to High Z tHZOE 10 ns 5 ns [8, 9] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 7 ns tAW Address Setup to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Setup to Write End 5.5 ns tHD Data Hold from Write End 0 ns [6] tLZWE WE HIGH to Low Z tHZWE WE LOW to High Z [6] tBW Byte Enable to End of Write 3 ns 5 7 ns ns Notes 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading shown in part a) of AC Test Loads and Waveforms, unless specified otherwise. 5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 6. tHZOE, tHZCE, tHZWE, tHZBE , tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV from steady state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal write time of the memory is defined by the overlap of WE, CE = VIL. Chip enable must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 001-49315 Rev. *A Page 5 of 10 [+] Feedback CY7C10612DV33 Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [10] Chip Deselect to Data Retention Time tR [ 11] Min Typ Max 2 VCC = 2V , CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V V 25 Operation Recovery Time Unit mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V VDR > 2V tCDR 3.0V tR CE Switching Waveforms Figure 3. Read Cycle No. 1 [12, 13] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Notes 10. Tested initially and after any design or process changes that may affect these parameters. 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs. 12. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 13. WE is HIGH for read cycle. Document Number: 001-49315 Rev. *A Page 6 of 10 [+] Feedback CY7C10612DV33 Switching Waveforms (continued) Figure 4. Read Cycle No. 2 (OE Controlled) [13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% 50% IICC CC IISB SB Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE t BW BHE, BLE tSD tHD DATA IO Notes 14. Address valid before or similar to CE transition LOW. 15. Data IO is high impedance if OE, BHE, and/or BLE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document Number: 001-49315 Rev. *A Page 7 of 10 [+] Feedback CY7C10612DV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA IO tLZWE Figure 7. Write Cycle No. 3 (BLE or BHE Controlled) [15] tWC ADDRESS tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD DATA IO Document Number: 001-49315 Rev. *A Page 8 of 10 [+] Feedback CY7C10612DV33 Truth Table CE H OE X WE X BLE X BHE X L L H L L L H L L L X L IO0–IO7 IO8–IO15 Mode Power High-Z High-Z Power Down Standby (ISB) L Data Out Data Out Read All Bits Active (ICC) L H Data Out High-Z Read Lower Bits Only Active (ICC) H H L High-Z Data Out Read Upper Bits Only Active (ICC) L L L Data In Data In Write All Bits Active (ICC) X L L H Data In High-Z Write Lower Bits Only Active (ICC) L X L H L High-Z Data In Write Upper Bits Only Active (ICC) L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C10612DV33-10ZSXI Package Diagram 51-85160 Package Type 54-Pin TSOP II (Pb-Free) Operating Range Industrial Package Diagrams Figure 8. 54-Pin TSOP Type II 51-85160-** Document Number: 001-49315 Rev. *A Page 9 of 10 [+] Feedback CY7C10612DV33 Document History Page Document Title: CY7C10612DV33, 16-Mbit (1M x 16) Static RAM Document Number: 001-49315 Rev. ECN No. Orig. of Change Submission Date ** 2589743 VKN/PYRS 10/15/08 *A 2718906 VKN 06/15/2009 Description of Change New datasheet Post to external web Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors image.cypress.com psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. 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Document Number: 001-49315 Rev. *A Revised June 15, 2009 Page 10 of 10 All product and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback