CD40192BMS CD40193BMS CMOS Presettable Up/Down Counters (Dual Clock With Reset) December 1992 Features Description • CD40192BMS - BCD Type CD40192BMS Presettable BCD Up/Down Counter and the CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET ENABLE control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY and BORROW outputs for multiple-stage counting schemes are provided. • CD40193BMS - Binary Type • High Voltage Type (20V Rating) • Individual Clock Lines for Counting Up or Counting Down • Synchronous High-Speed Carry and Borrow Propagation Delays for Cascading The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET ENABLE control is low. • Asynchronous Reset and Preset Capability • Medium Speed Operation - fCL = 8MHz (typ.) at 10V • 5V, 10V and 15V Parametric Ratings • Standardize Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications • Up/Down Difference Counting The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down one count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high. The CARRY and BORROW signals are high when the counter is counting up or down. The CARRY signal goes low one-half clock cycle after the counter reaches its maximum count in the count-up mode. The BORROW signal goes low one-half clock cycle after the counter reaches its minimum count in the countdown mode. Cascading of multiple packages is easily accomplished without the need for additional external circuitry by tying the BORROW and CARRY outputs to the CLOCK DOWN and CLOCK UP inputs, respectively, of the succeeding counter package. The CD40192BMS and CD40193BMS are supplied in these 16-lead outline packages: • Multistage Ripple Counting • Synchronous Frequency Dividers • A/D and D/A Conversion • Programmable Binary or BCD Counting Braze Seal DIP Frit Seal DIP Ceramic Flatpack *H4W, H1F *H6P, †H4X * CD40192B Only †CD40193B Only †H6W Functional Diagram Pinout CD40192BMS, CD40193BMS TOP VIEW J2 Q2 Q1 1 2 3 CLOCK DOWN 4 CLOCK UP 5 PRESET ENABLE 16 VDD J1 15 J1 J2 14 RESET J3 J4 13 BORROW CLOCK UP 12 CARRY Q3 6 11 PRESET ENABLE Q4 7 10 J3 VSS 8 9 J4 CLOCK DOWN 11 15 3 1 2 10 6 9 7 5 13 4 12 Q2 Q3 Q4 BORROW CARRY 14 RESET Q1 VDD = 16 VSS = 8 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1419 File Number 3363 Specifications CD40192BMS, CD40193BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20V VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20V VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH15 VNTH VPTH F VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1420 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD40192BMS, CD40193BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) Propagation Delay Clock Up or Clock Down to Q TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND Propagation Delay Reset to Q TPHL2 VDD = 5V, VIN = VDD or GND Propagation Delay PE to Q TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND Propagation Delay PE to Borrow or Carry TPHL5 TPLH5 VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency 9 10, 11 TPHL4 TPLH4 Transition Time 9 10, 11 Propagation Delay Clock Up to Carry, Clock Down to Borrow Propagation Delay Reset to Borrow or Carry GROUP A SUBGROUPS TEMPERATURE TPHL6 TPLH6 TTHL TTLH 9 +125oC, -55oC +25oC o o - 500 ns - 675 ns - 500 ns - 675 ns - 400 ns - 540 ns 9 - 320 ns - 432 ns - 600 ns - 810 ns - 600 ns - 810 ns - 200 ns - 270 ns 2 - MHz 1.48 - MHz MIN MAX UNITS µA 9 9 10, 11 VDD = 5V, VIN = VDD or GND +25oC UNITS +25oC 9 10, 11 FCL -55oC MAX +125 C, -55 C 10, 11 VDD = 5V, VIN = VDD or GND +125oC, MIN 10, 11 10, 11 VDD = 5V, VIN = VDD or GND +25oC LIMITS 9 10, 11 +125oC, -55oC +25oC +125oC, -55oC o +25 C +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA µA -55oC, +25oC - 10 +125oC - 600 µA Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA Output Current (Sink) Output Current (Sink) IOL10 IOL15 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V 7-1421 1, 2 1, 2 Specifications CD40192BMS, CD40193BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Output Current (Source) IOH5A Output Current (Source) Output Current (Source) Output Current (Source) IOH5B IOH10 IOH15 CONDITIONS VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC 1, 2 VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V 1, 2 1, 2 - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V 1, 2, 3 +25oC - 240 ns Propagation Delay Clock Up or Down to Q TPHL1 TPLH1 VDD = 10V VDD = 15V 1, 2, 3 +25oC - 180 ns Propagation Delay Reset to Q TPHL2 VDD = 10V 1, 2, 3 +25oC - 240 ns 1, 2, 3 +25oC - 180 ns 1, 2, 3 +25oC - 200 ns VDD = 15V Propagation Delay PE to Q TPHL3 TPLH3 VDD = 15V 1, 2, 3 +25oC - 140 ns Propagation Delay Clock Up to Carry, Clock Down to Borrow TPHL4 TPLH4 VDD = 10V 1, 2, 3 +25oC - 160 ns VDD = 15V 1, 2, 3 +25oC - 120 ns Propagation Delay PE to Borrow or Carry TPHL5 TPLH5 VDD = 10V 1, 2, 3 +25oC - 300 ns 1, 2, 3 +25oC - 220 ns VDD = 10V 1, 2, 3 +25oC - 300 ns VDD = 15V 1, 2, 3 +25oC - 220 ns 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns VDD = 5V 1, 2, 3, 4 +25oC - 15 µs VDD = 10V 1, 2, 3, 4 +25oC - 15 µs 1, 2, 3, 4 +25oC - 5 µs 1, 2, 3, 5 +25oC - 80 ns VDD = 10V 1, 2, 3, 5 +25oC - 40 ns VDD = 15V 1, 2, 3, 5 +25oC - 30 ns 1, 2, 3 +25oC - 480 ns 1, 2, 3 +25oC - 300 ns VDD = 15V 1, 2, 3 +25oC - 260 ns VDD = 5V 1, 2, 3 +25oC - 240 ns 1, 2, 3 +25oC - 170 ns 1, 2, 3 +25oC - 140 ns Propagation Delay Reset to Borrow or Carry Transition Time Maximum Clock Rise and Fall Time TPHL6 TPLH6 TTHL1 TTLH1 TRCL TFCL VDD = 10V VDD = 15V VDD = 10V VDD = 15V VDD = 15V Minimum Removal Time Reset or PE Minimum Pulse Width Reset Minimum Pulse Width PE TREM TW VDD = 5V VDD = 5V VDD = 10V TW VDD = 10V VDD = 15V 7-1422 Specifications CD40192BMS, CD40193BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Minimum Clock Pulse Width SYMBOL TW CONDITIONS VDD = 5V VDD = 10V VDD = 15V NOTES TEMPERATURE MIN MAX UNITS 1, 2, 3 +25oC - 180 ns 1, 2, 3 +25oC - 90 ns 1, 2, 3 +25oC - 60 ns - 15 pF - 7.5 pF Input Capacitance CIN Reset 1, 2 +25oC Input Capacitance CIN All Other Inputs 1, 2 +25oC NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. 5. The time required for RESET or PRESET ENABLE control to be removed before clocking. See timing diagram defining TREM. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 20V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 25 µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 7-1423 Specifications CD40192BMS, CD40193BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz 2, 3, 6, 7, 12, 13 4 - PART NUMBER CD40192BMS, CD40193BMS Static Burn-In 1 (Note 1) 2, 3, 6, 7, 12, 13 1, 4, 5, 8 - 11, 14, 15 16 Static Burn-In 2 (Note 1) 2, 3, 6, 7, 12, 13 8 1, 4, 5, 9 - 11, 14 - 16 Dynamic BurnIn (Note 1) - 8, 14 1, 5, 9 - 11, 15, 16 2, 3, 6, 7, 12, 13 8 1, 4, 5, 9 - 11, 14 - 16 Irradiation (Note 2) NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1424 CD40192BMS, CD40193BMS Logic Diagrams *RESET 14 *PE 11 S1 *J1 R1 15 ** CONTROL LOGIC 1 S2 R2 ** S3 R3 1 10 9 *J2 *J3 *J4 ** S4 R4 **SAME AS CONTROL LOGIC 1 CARRY 12 S1 *CLOCK UP S 5 S2 S Q1 CL *CLOCK DOWN S Q2 CL S4 S Q3 CL Q1 4 S3 Q4 CL Q2 Q3 Q4 R R R R R1 R2 R3 R4 13 BORROW VDD 3 2 6 7 Q1 Q2 Q3 Q4 *ALL INPUTS PROTECTED BY VSS COS/MOS PROTECTION NETWORK FIGURE 1. CD40192BMS LOGIC DIAGRAM (BCD) 7-1425 CD40192BMS, CD40193BMS Logic Diagrams (Continued) *RESET 14 *PE 11 S1 *J1 R1 15 ** CONTROL LOGIC 1 S2 R2 ** S3 R3 1 10 9 *J2 *J3 *J4 ** S4 R4 **SAME AS CONTROL LOGIC 1 VSS CARRY VDD 12 S1 *CLOCK UP S 5 S2 S Q1 CL *CLOCK DOWN S Q2 CL S4 S Q3 CL Q1 4 S3 Q4 CL Q2 Q3 Q4 R R R R R1 R2 R3 R4 13 VDD BORROW VDD VDD 3 2 6 7 Q1 Q2 Q3 Q4 *ALL INPUTS PROTECTED BY VSS COS/MOS PROTECTION NETWORK FIGURE 2. CD40193BMS LOGIC DIAGRAM (BINARY) 7-1426 CD40192BMS, CD40193BMS CL CL CL CL CL S R S p p Q CL n = R n CL Q Q R S CL CL CL p p n n CL CL Q FIGURE 3. INTERNAL LOGIC OF FLIP-FLOP TRUTH TABLE CLOCK UP CLOCK DOWN PRESET ENABLE RESET ACTION 1 1 0 Count Up 1 1 0 No Count 1 1 0 Count Down 1 1 0 No Count X X 0 0 Preset X X X 1 Reset 1 = High Level 0 = Low Level X = Don’t Care AMBIENT TEMPERATURE (TA) = +25oC 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 5. MIMIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-1427 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V -5 12.5 10.0 -10V 10V 7.5 -10 5.0 -15V 2.5 -15 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) 0 200 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 20 400 AMBIENT TEMPERATURE (TA) = +25oC 350 300 SUPPLY VOLTAGE (VDD) = 5V 250 200 150 POWER DISSIPATION PER GATE (PD) (µW) 15V 50 10 0 FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 30 50 70 20 40 60 80 LOAD CAPACITANCE (CL) (pF) CL = 15pF 8 6 4 2 104 8 6 4 2 103 8 6 4 2 102 2 4 68 1 2 4 6 8 10 90 FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC CL = 50pF 8 6 4 2 105 10V 100 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 106 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) CD40192BMS, CD40193BMS 2 4 68 2 4 68 2 103 104 102 INPUT FREQUENCY (fIN) (kHz) FIGURE 10. DYNAMIC POWER DISSIPATION 7-1428 4 68 105 100 CD40192BMS, CD40193BMS RESET 1 0 PE 1 0 1 0 J1 1 0 1 0 1 0 1 0 J2 1 0 J3 1 0 J3 1 0 J4 1 0 J4 1 0 CLK UP 1 0 CLK DN 1 0 J1 J2 CLK UP CLK DN RESET PE 1 0 1 0 Q1 1 0 Q1 1 0 Q2 1 0 Q2 1 0 Q3 1 0 Q3 1 0 Q4 1 0 Q4 1 0 CARRY 1 0 CARRY 1 0 1 BORROW 0 COUNT 0 7 8 9 0 1 2 1 0 9 8 1 BORROW 0 COUNT 7 FIGURE 11. CD40192BMS TIMING DIAGRAM 0 13 14 15 0 1 2 FIGURE 12. CD40193BMS TIMING DIAGRAM tWH tWL CLOCK RESET PRESET ENABLE trem* *RESET OR PRESET ENABLE REMOVAL TIME FIGURE 13. TIMING DIAGRAM DEFINING trem J1 J2 J3 J4 CLOCK UP CLOCK DOWN J1 J2 J3 J4 CARRY CD40192BMS OR CD40193BMS 1 0 15 14 13 BORROW CLOCK UP CLOCK DOWN Q1 Q2 Q3 Q4 CD40192BMS OR CD40193BMS Q1 Q2 Q3 Q4 RESET PRESET ENABLE FIGURE 14. CASCADED COUNTER PACKAGES 7-1429 CARRY BORROW CD40192BMS, CD40193BMS Chip Dimensions and Pad Layout Dimensions and pad layout for the CD40192BMSH (dimensions and pad layout for the CD40193BMSH are identical). Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch) METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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