bq20z95
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SLUS757C – JULY 2007 – REVISED OCTOBER 2013
SBS 1.1-COMPLIANT GAS GAUGE and PROTECTION ENABLED WITH IMPEDANCE
TRACK™
Check for Samples: bq20z95
FEATURES
1
•
2
•
•
•
•
•
•
•
Next Generation Patented Impedance Track™
Technology Accurately Measures Available
Charge in Li-Ion and Li-Polymer Batteries
– Better Than 1% Error Over Lifetime of the
Battery
Supports the Smart Battery Specification
SBS V1.1
Flexible Configuration for 2-Series to 4-Series
Li-Ion and Li-Polymer Cells
Powerful 8-Bit RISC CPU With Ultra-Low
Power Modes
Full Array of Programmable Protection
Features
– Voltage, Current, and Temperature
Supports SHA-1 Authentication
Complete Battery Protection and Gas Gauge
Solution in One Package
Small 44-Pin TSSOP (DBT) Package
APPLICATIONS
•
•
•
Notebook PCs
Medical and Test Equipment
Portable Instrumentation
DESCRIPTION
The bq20z95 SBS-compliant gas gauge and
protection IC is a single IC solution designed for
battery-pack or in-system installation. The bq20z95
measures and maintains an accurate record of
available charge in Li-Ion or Li-Polymer batteries
using its integrated high-performance analog
peripherals, monitors capacity change, battery
impedance, open-circuit voltage, and other critical
parameters of the battery pack as well and reports
the information to the system host controller over a
serial-communication bus. Together with the
integrated analog front-end (AFE) short-circuit and
overload protection, the bq20z95 maximizes
functionality and safety while minimizing external
component count, cost, and size in smart battery
circuits.
The implemented Impedance Track™ gas gauging
technology continuously analyzes the battery
impedance, resulting in superior gas-gauging
accuracy. This enables remaining capacity to be
calculated with discharge rate, temperature, and cell
aging all accounted for during each stage of every
cycle with high accuracy.
Table 1. AVAILABLE OPTIONS
TA
–40°C to 85°C
(1)
(2)
(3)
PACKAGE (1)
44-PIN TSSOP (DBT) Tube
44-PIN TSSOP (DBT) Tape and Reel
bq20z95DBT (2)
bq20z95DBTR (3)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
A single tube quantity is 50 units.
A single reel quantity is 2000 units.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
bq20z95
SLUS757C – JULY 2007 – REVISED OCTOBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SYSTEM PARTITIONING DIAGRAM
VSS
BAT
VCC
PACK
CHG
DSG
ZVCHG
GPOD
PMS
SAFE
PFIN
¯¯¯¯
LED5
LED4
LED3
LED2
LED1
Pack +
RBI
¯¯¯¯
DISP
SMBD
SMBC
LED Display
Fuse Blow
Detection and
Logic
SMB 1.1
System Control
Oscillator
Pre Charge FET
& PGOD Drive
N-Channel FET
Drive
Power Mode
Control
MSRT
¯¯¯¯¯
RESET
¯¯¯¯¯¯
SMBD
SMBC
AFE HW Control
ALERT
¯¯¯¯¯¯
Watchdog
VCELL+
Data Flash
Memory
Charging
Algorithm
Voltage
Measurement
Over
Temperature
Protection
Over- & UnderVoltage
Protection
Cell Voltage
Multiplexer
Impedance
Track ™
Gas Gauging
VC1
VC1
VDD
VC2
VC2
OUT
VC3
VC3
CD
VC4
VC4
GND
Cell Balancing
VC5
bq294xx
ASRN
GSRN
ASRP
HW Over
Current &
Short Circuit
Protection
Coloumb
Counter
GSRP
Over Current
Protection
TS2
TS1
Temperature
Measurement
TOUT
SHA-1
Authentication
REG33
REG25
Regulators
bq20z95
Pack RSNS
5mΩ – 20mΩ typ.
bq20z95
DBT Package
(TOP VIEW)
DSG
PACK
VCC
ZVCHG
GPOD
PMS
VSS
REG33
TOUT
VCELL+
¯¯¯¯¯¯
ALERT
NC
TS1
TS2
¯¯¯¯¯
PRES
¯¯¯¯
PFIN
SAFE
SMBD
NC
SMBC
¯¯¯¯
DISP
VSS
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
CHG
BAT
VC1
VC2
VC3
VC4
VC5
ASRP
ASRN
¯¯¯¯¯¯
RESET
VSS
RBI
REG25
VSS
MRST
¯¯¯¯¯
GSRN
GSRP
LED5
LED4
LED3
LED2
LED1
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SLUS757C – JULY 2007 – REVISED OCTOBER 2013
TERMINAL FUNCTIONS
TERMINAL
(1)
I/O (1)
DESCRIPTION
NO.
NAME
1
DSG
O
2
PACK
IA, P
3
VCC
P
Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to
ensure device supply either from battery stack or battery pack input.
4
ZVCHG
O
P-chan pre-charge FET gate drive
5
GPOD
OD
6
PMS
I
PRE-CHARGE mode setting input. Connect to PACK to enable 0-V pre-charge using charge FET
connected at CHG pin. Connect to VSS to disable 0-V pre-charge using charge FET connected at
CHG pin.
7
VSS
P
Negative device power supply input. Connect all VSS pins together for operation of device.
8
REG33
P
3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS.
9
TOUT
P
Thermistor bias supply output
10
VCELL+
—
Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and
VSS.
11
ALERT
I/OD
12
NC
—
Not connected
13
TS1
IA
Temperature sensor 1 input
High-side N-chan discharge FET gate drive
Battery pack input voltage sense input. It also serves as device wake up when device is in
SHUTDOWN mode.
High voltage general purpose open drain output. Can be configured to be used in pre-charge
condition.
Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will
be triggered.
14
TS2
IA
Temperature sensor 2 input
15
PRES
I/OD
System/Host present input
16
PFIN
I/OD
Fuse blow detection input
17
SAFE
I/OD
Blow fuse signal output
18
SMBD
I/OD
SMBus data line
19
NC
—
20
SMBC
I/OD
SMBus clock line
21
DISP
I/OD
Display enable input
22
VSS
P
Negative device power supply input. Connect all VSS pins together for operation of device.
23
LED1
I
LED 1 current sink input
24
LED2
I
LED 2 current sink input
25
LED3
I
LED 3 current sink input
26
LED4
I
LED 4 current sink input
27
LED5
I
LED 5 current sink input
28
GSRP
IA
Coulomb counter differential input. Connect to one side of the sense resistor.
29
GSRN
IA
Coulomb counter differential input. Connect to one side of the sense resistor.
30
MRST
I
Reset input for internal CPU core. Connect to RESET for correct operation of device.
31
VSS
P
Negative device power supply input. Connect all VSS pins together for operation of device.
32
REG25
P
2.5-V regulator output. Connect at least a 1-μF capacitor to REG25 and VSS.
33
RBI
P
RAM backup input. Connect a capacitor to this pin and VSS to protect loss of RAM data in case of
short circuit condition.
Not connected
34
VSS
P
Negative device power supply input. Connect all VSS pins together for operation of device.
35
RESET
O
Reset output. Connect to MSRT.
36
ASRN
IA
Short circuit and overload detection differential input. Connect to sense resistor.
37
ASRP
IA
Short circuit and overload detection differential input. Connect to sense resistor.
38
VC5
IA, P
Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell
stack.
39
VC4
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the
negative voltage of the second lowest cell in cell stack.
I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O (1)
DESCRIPTION
VC3
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in
cell stack and the negative voltage of the second highest cell in 4-series cell applications.
41
VC2
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell
and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2-cell stack
applications.
42
VC1
IA, P
Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell
stack in 4-cell applications. Connect to VC2 in 3- or 2-series cell applications.
43
BAT
I, P
44
CHG
O
NO.
NAME
40
Battery stack voltage sense input
High side N-chan charge FET gate drive
ABSOLUTE MAXIMUM RATINGS
Over Operating Free-Air Temperature (unless otherwise noted)
(1)
DESCRIPTION
PIN
UNIT
VBAT, VCC
VSS
Supply voltage range
VIN
Input voltage range
–0.3 V to 34 V
PACK, PMS
–0.3 V to 34 V
VC(n)-VC(n+1); n = 1, 2, 3, 4
–0.3 V to 8.5 V
VC1, VC2, VC3, VC4
–0.3 V to 34 V
VC5
–0.3 V to 1 V
PFIN, SMBD, SMBC, LED1, LED2,
LED3, LED4, LED5, DISP
–0.3 V to 6 V
TS1, TS2, SAFE, VCELL+, PRES;
ALERT
–0.3 V to V(REG25) + 0.3 V
MRST, GSRN, GSRP, RBI
–0.3 V to V(REG25) + 0.3 V
ASRN, ASRP
–1 V to 1 V
DSG, CHG, GPOD
–0.3 V to 34 V
ZVCHG
VOUT
Output voltage range
–0.3 V to V (BAT)
TOUT, ALERT, REG33
–0.3 V to 6 V
RESET
–0.3 V to 7 V
REG25
–0.3 V to 2.75 V
PRES, PFIN, SMBD, SMBC, LED5,
LED4, LED3, LED2, LED1
ISS
Maximum combined sink current for input pins
TA
Operating free-air temperature range
–40°C to 85°C
TF
Functional temperature
–40°C to 100°C
Tstg
Storage temperature range
–65°C to 150°C
(1)
4
50 mA
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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SLUS757C – JULY 2007 – REVISED OCTOBER 2013
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
PIN
MIN
VSS
Supply voltage
VCC, VBAT
4.5
V(STARTUP)
Minimum startup voltage
VCC, BAT, PACK
5.5
VIN
Input Voltage Range
NOM
MAX
UNIT
25
V
V
VC(n) – VC(n+1); n = 1,2,3,4
0
5
V
VC1, VC2, VC3, VC4
0
VSUP
V
VC5
0
0.5
V
–0.5
0.5
V
PACK, PMS
0
25
V
0
25
V
1
mA
ASRN, ASRP
V(GPOD)
Output Voltage Range
GPOD
A(GPOD)
Drain Current (1)
GPOD
C(REG25)
2.5-V LDO Capacitor
REG25
1
µF
C(REG33)
3.3-V LDO Capacitor
REG33
2.2
µF
C(VCELL+)
Cell Voltage Output Capacitor
VCELL+
0.1
µF
C(PACK)
PACK input block resistor (2)
PACK
1
kΩ
(1)
(2)
Use an external resistor to limit the current to GPOD to 1mA in high voltage application.
Use an external resistor to limit the inrush current PACK pin required.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
I(NORMAL)
Firmware running
SLEEP Mode
I(SLEEP)
I(SHUTDOWN)
550
µA
CHG FET on; DSG FET on
124
µA
CHG FET off; DSG FET on
90
µA
CHG FET off; DSG FET off
52
SHUTDOWN Mode
0.1
µA
1
µA
1
µA
1.25
10
mV
V(WAKE) = 1 mV;
I(WAKE)= 0, RSNS1 = 0, RSNS0 = 1
-0.7
0.7
V(WAKE) = 2.25 mV;
I(WAKE) = 1, RSNS1 = 0, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0
-0.8
0.8
V(WAKE) = 4.5 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0
–1.0
1.0
V(WAKE) = 9 mV;
I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1
–1.4
1.4
SHUTDOWN WAKE; TA = 25°C (unless otherwise noted)
I(PACK)
Shutdown exit at VSTARTUP threshold
SRx WAKE FROM SLEEP; TA = 25°C (unless otherwise noted)
V(WAKE)
V(WAKE_ACR)
Positive or negative wake threshold
with 1.00 mV, 2.25 mV, 4.5 mV and
9 mV programmable options
Accuracy of V(WAKE)
V(WAKE_TCO)
Temperature drift of V(WAKE)
accuracy
t(WAKE)
Time from application of current and
wake of bq20z95
mV
0.5
%/°C
1
10
ms
POWER-ON RESET
VIT–
Negative-going voltage input
Voltage at REG25 pin
1.70
1.80
1.90
V
Vhys
Hysteresis
VIT+ – VIT–
50
150
250
mV
tRST
RESET active low time
Active low time after power up or watchdog reset
100
250
560
µs
250
500
1000
ms
WATCHDOG TIMER
tWDTINT
Watchdog start up detect time
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
tWDWT
TEST CONDITIONS
Watchdog detect time
MIN
TYP
MAX
UNIT
50
100
150
µs
2.41
2.5
2.59
V
2.5V LDO; I(REG33OUT) = 0 mA; TA = 25°C (unless otherwise noted)
V(REG25)
Regulator output voltage
4.5 < VCC or BAT < 25 V;
I(REG25OUT) ≤ 16 mA;
TA = –40°C to 100°C
ΔV(REG25TEMP)
Regulator output change with
temperature
I(REG25OUT) = 2 mA;
TA = –40°C to 100°C
ΔV(REG25LINE)
Line regulation
5.4 < VCC or BAT < 25 V;
I(REG25OUT) = 2 mA
ΔV(REG25LOAD)
Load Regulation
I(REG25MAX)
Current Limit
±0.2
%
3
10
0.2 mA ≤ I(REG25OUT) ≤ 2 mA
7
25
0.2 mA ≤ I(REG25OUT) ≤ 16 mA
25
50
5
40
75
mA
3
3.3
3.6
V
Drawing current until
REG25 = 2 V to 0 V
mV
mV
3.3V LDO; I(REG25OUT) = 0 mA; TA = 25°C (unless otherwise noted)
V(REG33)
Regulator output voltage
4.5 < VCC or BAT < 25 V;
I(REG33OUT) ≤ 25 mA;
TA = –40°C to 100°C
ΔV(REG33TEMP)
Regulator output change with
temperature
I(REG33OUT) = 2 mA;
TA = –40°C to 100°C
ΔV(REG33LINE)
Line regulation
5.4 < VCC or BAT < 25 V;
I(REG33OUT) = 2 mA
ΔV(REG33LOAD)
Load Regulation
I(REG33MAX)
Current Limit
±0.2
3
%
10
0.2 mA ≤ I(REG33OUT) ≤ 2 mA
7
17
0.2mA ≤ I(REG33OUT) ≤ 25 mA
40
100
100
145
Drawing current until REG33 = 3 V
25
Short REG33 to VSS, REG33 = 0 V
12
65
mV
mV
mA
THERMISTOR DRIVE
V(TOUT)
RDS(on)
Output voltage
I(TOUT) = 0 mA; TA = 25°C
TOUT pass element resistance
I(TOUT) = 1 mA; RDS(on) = (V(REG25) – V(TOUT))/1 mA; TA =
–40°C to 100°C
V(REG25)
V
50
100
Ω
VCELL+ HIGH VOLTAGE TRANSLATION
V(VCELL+OUT)
V(VCELL+REF)
Translation output
VC(n) – VC(n+1) = 0 V;
TA = –40°C to 100°C
0.950
0.975
1
VC(n) – VC(n+1) = 4.5 V;
TA = –40°C to 100°C
0.275
0.3
0.375
internal AFE reference voltage;
TA = –40°C to 100°C
0.965
0.975
0.985
V(PACK)/1
8
1.02 ×
V(PACK)/1
8
V(BAT)/18
1.02 ×
V(BAT)/18
V(VCELL+PACK)
Voltage at PACK pin;
TA = –40°C to 100°C
0.98 ×
V(PACK)/1
8
V(VCELL+BAT)
Voltage at BAT pin;
TA = –40°C to 100°C
0.98 ×
V(BAT)/18
CMMR
Common mode rejection ratio
K
Cell scale factor
VCELL+
40
V
dB
K= {VCELL+ output (VC5=0 V; VC4=4.5 V) – VCELL+
output (VC5=0 V; VC4=0 V)}/4.5
0.147
0.150
0.153
K= {VCELL+ output (VC2=13.5V; VC1=18 V) – VCELL+
output
(VC5=13.5 V; VC1=13.5 V)}/4.5
0.147
0.150
0.153
I(VCELL+OUT)
Drive Current to VCELL+ capacitor
VC(n) – VC(n+1) = 0V; VCELL+ = 0 V;
TA = –40°C to 100°C
12
18
V(VCELL+O)
CELL offset error
CELL output (VC2 = VC1 = 18 V) – CELL output (VC2 =
VC1 = 0 V)
–18
–1
18
mV
IVCnL
VC(n) pin leakage current
VC1, VC2, VC3, VC4, VC5 = 3 V
–1
0.01
1
μA
RDS(on) for internal FET switch at
VDS = 2 V; TA = 25°C
200
400
600
Ω
μA
CELL BALANCING
RBAL
6
Internal cell balancing FET
resistance
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)
V(OL)
V(SCC)
V(SCD)
OL detection threshold voltage
accuracy
SCC detection threshold voltage
accuracy
SCD detection threshold voltage
accuracy
tda
Delay time accuracy
tpd
Protection circuit propagation delay
VOL = 25 mV (min)
15
25
35
VOL = 100 mV; RSNS = 0, 1
90
100
110
VOL = 205 mV (max)
185
205
225
V(SCC) = 50 mV (min)
30
50
70
V(SCC) = 200 mV; RSNS = 0, 1
180
200
220
V(SCC) = 475 mV (max)
428
475
523
V(SCD) = –50 mV (min)
–30
–50
–70
V(SCD) = –200 mV; RSNS = 0, 1
–180
–200
–220
V(SCD) = –475 mV (max)
–428
–475
–523
mV
mV
mV
±15.25
μs
50
μs
FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)
V(DSGON)
DSG pin output on voltage
V(DSGON) = V(DSG) – V(PACK); V(GS) = 10 MΩ; DSG and
CHG on;
TA = –40°C to 100°C
8
12
16
V
V(CHGON)
CHG pin output on voltage
V(CHGON) = V(CHG) – V(BAT); V(GS) = 10 MΩ; DSG and
CHG on;
TA = –40°C to 100°C
8
12
16
V
V(DSGOFF)
DSG pin output off voltage
V(DSGOFF) = V(DSG) – V(PACK)
0.2
V
V(CHGOFF)
CHG pin output off voltage
V(CHGOFF) = V(CHG) – V(BAT)
0.2
V
tr
Rise time
tf
Fall time
V(ZVCHG)
ZVCHG clamp voltage
CL= 4700 pF; V(PACK) ≤ DSG ≤ V(PACK) + 4V
400
1000
CL= 4700 pF; V(BAT) ≤ CHG ≤ V(BAT) + 4V
400
1000
CL= 4700pF; V(PACK) + V(DSGON) ≤ DSG ≤ V(PACK) + 1V
40
200
CL= 4700 pF; V(BAT) + V(CHGON) ≤ CHG ≤ V(BAT) + 1 V
40
200
BAT = 4.5 V
3.3
3.5
3.7
ALERT
60
100
200
RESET
1
3
6
μs
μs
V
LOGIC; TA = –40°C to 100°C (unless otherwise noted)
R(PULLUP)
VOL
Internal pullup resistance
Logic low output voltage level
ALERT
0.2
RESET; V(BAT) = 7V; V(REG25) = 1.5 V; I (RESET) = 200 μA
0.4
GPOD; I(GPOD) = 50 μA
0.6
kΩ
V
LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT
VIH
High-level input voltage
VIL
Low-level input voltage
2.0
VOH
Output voltage high (1)
IL = –0.5 mA
VOL
Low-level output voltage
PRES, PFIN, ALERT, IL = 7 mA;
CI
V
0.8
V
VREG25–0
.5
V
0.4
Input capacitance
V
5
I(SAFE)
SAFE source currents
SAFE active, SAFE = V(REG25) –0.6 V
Ilkg(SAFE)
SAFE leakage current
SAFE inactive
Ilkg
Input leakage current
pF
–3
mA
–0.2
0.2
µA
1
µA
ADC (2)
Input voltage range
TS1, TS2, using Internal Vref
–0.2
Conversion time
Resolution (no missing codes)
16
Effective resolution
14
Integral nonlinearity
(1)
(2)
(3)
1
V
31.5
ms
bits
15
bits
±0.03
%FSR (3)
RC[0:7] bus
Unless otherwise specified, the specification limits are valid at all measurement speed modes.
Full-scale reference
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ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) =
14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Offset error (4)
Offset error drift (4)
TA = 25°C to 85°C
Full-scale error (5)
Full-scale error drift
TYP
MAX
140
250
µV
2.5
18
μV/°C
±0.1%
±0.7%
50
Effective input resistance (6)
UNIT
PPM/°C
8
MΩ
COULOMB COUNTER
Input voltage range
–0.20
Conversion time
Single conversion
Effective resolution
Single conversion
Integral nonlinearity
Offset error
(7)
0.20
ms
15
bits
–0.1 V to 0.20 V
±0.007
–0.20 V to –0.1 V
±0.007
TA = 25°C to 85°C
±0.034
0.4
(9)
µV
2.45
µV/°C
±0.35%
Full-scale error drift
150
Effective input resistance
%FSR
10
Offset error drift
Full-scale error (8)
V
250
(10)
TA = 25°C to 85°C
PPM/°C
2.5
MΩ
INTERNAL TEMPERATURE SENSOR
V(TEMP)
Temperature sensor voltage (11)
–2.0
mV/°C
VOLTAGE REFERENCE
Output voltage
1.215
Output voltage drift
1.225
1.230
65
V
PPM/°C
HIGH FREQUENCY OSCILLATOR
f(OSC)
Operating frequency
f(EIO)
Frequency error
t(SXO)
Start-up time (14)
4.194
(12) (13)
TA = 20°C to 70°C
MHz
–3%
0.25%
3%
–2%
0.25%
2%
2.5
5
ms
LOW FREQUENCY OSCILLATOR
f(LOSC)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Operating frequency
f(LEIO)
Frequency error (13)
t(LSXO)
Start-up time (14)
32.768
(15)
TA = 20°C to 70°C
kHz
–2.5%
0.25%
2.5%
–1.5%
0.25%
1.5%
500
µs
Post-calibration performance and no I/O changes during conversion with SRN as the ground reference
Uncalibrated performance. This gain error can be eliminated with external calibration.
The A/D input is a switched-capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
Post-calibration performance
Reference voltage for the coulomb counter is typically Vref/3.969 at V(REG25) = 2.5 V, TA = 25°C.
Uncalibrated performance. This gain error can be eliminated with external calibration.
The CC input is a switched capacitor input. Since the input is switched, the effective input resistance is a measure of the average
resistance.
–53.7 LSB/°C
The frequency error is measured from 4.194 MHz.
The frequency drift is included and measured from the trimmed frequency at V(REG25) = 2.5V, TA = 25°C.
The startup time is defined as the time it takes for the oscillator output frequency to be ±3%.
The frequency error is measured from 32.768 kHz.
DATA FLASH CHARACTERISTICS (Over Recommended Operating Temperature and Supply
Voltage)
Typical Values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
8
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DATA FLASH CHARACTERISTICS (Over Recommended Operating Temperature and Supply
Voltage) (continued)
Typical Values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Data retention
Flash programming write-cycles
t(ROWPROG)
Row programming time
TYP
MAX
10
20k
See
UNIT
Years
Cycles
(1)
2
ms
t(MASSERASE) Mass-erase time
200
ms
t(PAGEERASE) Page-erase time
20
ms
I(DDPROG)
Flash-write supply current
5
10
mA
I(DDERASE)
Flash-erase supply current
5
10
mA
V(RBI) > V(RBI)MIN, VREG25 < VIT–,
TA = 85°C
1000
2500
V(RBI) > V(RBI)MIN, VREG25 < VIT–,
TA = 25°C
90
220
RAM BACKUP
I(RB)
RB data-retention input current
RB data-retention input voltage (1)
V(RB)
(1)
nA
1.7
V
Specified by design. Not production tested.
SMBUS TIMING CHARACTERISTICS
TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
f(SMB)
SMBus operating frequency
SLAVE mode, SMBC 50% duty cycle
f(MAS)
SMBus master clock frequency
MASTER mode, No clock low slave extend
t(BUF)
Bus free time between start and stop
(see Figure 1)
t(HD:STA)
Hold time after (repeated) start (see
Figure 1)
t(SU:STA)
Repeated start setup time (see Figure 1)
t(SU:STO)
Stop setup time (see Figure 1)
t(HD:DAT)
t(SU:DAT)
t(TIMEOUT)
t(LOW)
Data hold time (see Figure 1)
Error signal/detect (see Figure 1)
MAX
UNIT
100
kHz
51.2
kHz
4.7
µs
4
µs
4.7
µs
4
µs
0
ns
300
250
See
(1)
Clock low period (see Figure 1)
25
ns
35
4.7
µs
µs
See
(2)
50
µs
See
(3)
25
µs
Cumulative clock low master extend time
(see Figure 1)
See
(4)
10
µs
tf
Clock/data fall time
See
(5)
300
ns
tr
Clock/data rise time
See
(6)
1000
ns
t(HIGH)
t(LOW:MEXT)
(3)
(4)
(5)
(6)
TRANSMIT mode
Data setup time (see Figure 1)
Clock high period (see Figure 1)
t(LOW:SEXT) Cumulative clock low slave extend time
(1)
(2)
RECEIVE mode
TYP
10
4
The bq20z95 times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z95 that is in
progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tf = 0.9VDD to (VILMAX – 0.15)
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TLOW
SCLK
www.ti.com
TR
THD:STA
TF
THIGH
THD:DAT
THD:STA
TSU:STA
TSU:STO
TSU:DAT
SDATA
TBUF
P
S
S
P
Start
Stop
TLOW:SEXT
SCLK ACK†
SCLK ACK†
TLOW:MEXT
TLOW:MEXT
TLOW:MEXT
SCLK
SDATA
A.
SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram
10
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FEATURE SET
Primary (1st Level) Safety Features
The bq20z95 supports a wide range of battery and system protection features that can easily be configured. The
primary safety features include:
•
•
•
•
•
Cell over/undervoltage protection
Charge and discharge overcurrent
Short circuit
Charge and discharge overtemperature
AFE watchdog
Secondary (2nd Level) Safety Features
The secondary safety features of the bq20z95 can be used to indicate more serious faults via the SAFE (pin 7).
This pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. The secondary safety protection features include:
•
•
•
•
•
•
Safety overvoltage
Safety overcurrent in Charge and Discharge
Safety overtemperature in Charge and Discharge
Charge FET and 0-V Charge FET fault
Discharge FET fault
AFE communication fault
Charge Control Features
The bq20z95 charge control features include:
•
•
•
•
•
•
Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
Determines the chemical state of charge of each battery cell using Impedance Track and can reduce the
charge difference of the battery cells in fully charged state of the battery pack gradually using cell balancing
algorithm during charging. This prevents fully charged cells from overcharging and causing excessive
degradation and also increases the usable pack energy by preventing premature charge termination
Supports pre-charging/zero-volt charging
Support fast charging
Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range
Reports charging fault and also indicate charge status via charge and discharge alarms.
Gas Gauging
The bq20z95 uses the Impedance Track technology to measure and calculate the available charge in battery
cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full charge
discharge learning cycle required.
See Theory and Implementation of Impedance Track Battery Fuel-Gauging Algorithm application note (SLUA364)
for further details.
Authentication
The bq20z95 supports authentication by the host using SHA-1.
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Power Modes
The bq20z95 supports three power modes to reduce power consumption:
•
•
•
In NORMAL mode, the bq20z95 performs measurements, calculations, protection decisions and data updates
in 1-s intervals. Between these intervals, the bq20z95 is in a reduced power stage.
In SLEEP mode, the bq20z95 performs measurements, calculations, protection decisions, and data updates
in adjustable time intervals. Between these intervals, the bq20z95 is in a reduced power stage. The bq20z95
has a wake function that enables exit from SLEEP mode when current flow or failure is detected.
In SHUTDOWN mode the bq20z95 is completely disabled.
CONFIGURATION
Oscillator Function
The bq20z95 fully integrates the system oscillators. Therefore, the bq20z95 requires no external components for
this feature.
System Present Operation
The bq20z95 checks the PRES pin periodically (1s). If PRES input is pulled to ground by external system, the
bq20z95 detects this as system present.
BATTERY PARAMETER MEASUREMENTS
The bq20z95 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a
second delta-sigma ADC for individual cell and battery voltage and temperature measurement.
Charge and Discharge Counting
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from –0.25 V to 0.25 V. The bq20z95 detects charge activity when VSR = V(SRP) – V(SRN)is positive and
discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq20z95 continuously integrates the signal over
time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.
Voltage
The bq20z95 updates the individual series cell voltages at 1-s intervals. The internal ADC of the bq20z95
measures the voltage, and scales and calibrates it appropriately. This data is also used to calculate the
impedance of the cell for the Impedance Track gas-gauging.
Current
The bq20z95 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current
using a 5-mΩ to 20-mΩ typ. sense resistor.
Auto Calibration
The bq20z95 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The bq20z95 performs auto-calibration when the SMBus lines stay
low continuously for a minimum of 5 s.
Temperature
The bq20z95 has an internal temperature sensor and two external temperature sensor inputs TS1 and TS2 used
in conjunction with two identical NTC thermistors (default are Semitec 103AT) to sense the battery environmental
temperature. The bq20z95 can be configured to use internal or up to two external temperature sensors.
12
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COMMUNICATIONS
The bq20z95 uses SMBus v1.1 with MASTER mode and package error checking (PEC) options per the SBS
specification.
SMBus On and Off State
The bq20z95 detects an SMBus off state when SMBC and SMBD are logic-low for ≥ 2 seconds. Clearing this
state requires either SMBC or SMBD to transition high. Within 1 ms, the communication bus is available.
SBS Commands
Table 2. SBS COMMANDS
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min
Value
Max
Value
Default
Value
0x00
R/W
ManufacturerAccess
hex
2
0x0000
0xffff
—
0x01
R/W
RemainingCapacityAlarm
unsigned int
2
0
65535
—
mAh or
10 mWh
0x02
R/W
RemainingTimeAlarm
unsigned int
2
0
65535
—
min
0x03
R/W
BatteryMode
hex
2
0x0000
0xffff
—
0x04
R/W
AtRate
signed int
2
–32768
32767
—
mA or 10
mW
0x05
R
AtRateTimeToFull
unsigned int
2
0
65535
—
min
0x06
R
AtRateTimeToEmpty
unsigned int
2
0
65535
—
min
0x07
R
AtRateOK
unsigned int
2
0
65535
—
0x08
R
Temperature
unsigned int
2
0
65535
—
0.1°K
0x09
R
Voltage
unsigned int
2
0
20000
—
mV
0x0a
R
Current
signed int
2
–32768
32767
—
mA
0x0b
R
AverageCurrent
signed int
2
–32768
32767
—
mA
Unit
0x0c
R
MaxError
unsigned int
1
0
100
—
%
0x0d
R
RelativeStateOfCharge
unsigned int
1
0
100
—
%
0x0e
R
AbsoluteStateOfCharge
unsigned int
1
0
100
—
%
0x0f
R/W
RemainingCapacity
unsigned int
2
0
65535
—
mAh or
10 mWh
0x10
R
FullChargeCapacity
unsigned int
2
0
65535
—
mAh or
10 mWh
0x11
R
RunTimeToEmpty
unsigned int
2
0
65535
—
min
0x12
R
AverageTimeToEmpty
unsigned int
2
0
65535
—
min
0x13
R
AverageTimeToFull
unsigned int
2
0
65535
—
min
0x14
R
ChargingCurrent
unsigned int
2
0
65535
—
mA
0x15
R
ChargingVoltage
unsigned int
2
0
65535
—
mV
0x16
R
BatteryStatus
unsigned int
2
0x0000
0xffff
—
0x17
R/W
CycleCount
unsigned int
2
0
65535
—
0x18
R/W
DesignCapacity
unsigned int
2
0
65535
—
mAh or
10 mWh
0x19
R/W
DesignVoltage
unsigned int
2
7000
16000
14400
mV
0x1a
R/W
SpecificationInfo
unsigned int
2
0x0000
0xffff
0x0031
0x1b
R/W
ManufactureDate
unsigned int
2
0
65535
0
0x1c
R/W
SerialNumber
hex
2
0x0000
0xffff
0x0001
0x20
R/W
ManufacturerName
String
11+1
—
—
Texas
Instruments
ASCII
0x21
R/W
DeviceName
String
7+1
—
—
bq20z95
ASCII
0x22
R/W
DeviceChemistry
String
4+1
—
—
LION
ASCII
0x23
R
ManufacturerData
String
14+1
—
—
—
ASCII
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Table 2. SBS COMMANDS (continued)
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min
Value
Max
Value
Default
Value
Unit
0x2f
R/W
Authenticate
String
20+1
—
—
—
ASCII
0x3c
R
CellVoltage4
unsigned int
2
0
65535
—
mV
0x3d
R
CellVoltage3
unsigned int
2
0
65535
—
mV
0x3e
R
CellVoltage2
unsigned int
2
0
65535
—
mV
0x3f
R
CellVoltage1
unsigned int
2
0
65535
—
mV
Table 3. EXTENDED SBS COMMANDS
SBS
Cmd
Mode
Name
Format
Size in
Bytes
Min Value
Max Value
Default
Value
Unit
ASCII
0x45
R
AFEData
String
11+1
—
—
—
0x46
R/W
FETControl
hex
1
0x00
0xff
—
0x4f
R
StateOfHealth
unsigned int
1
0
100
—
0x51
R
SafetyStatus
hex
2
0x0000
0xffff
—
0x53
R
PFStatus
hex
2
0x0000
0xffff
—
0x54
R
OperationStatus
hex
2
0x0000
0xffff
—
0x55
R
ChargingStatus
hex
2
0x0000
0xffff
—
0x57
R
ResetData
hex
2
0x0000
0xffff
—
0x5a
R
PackVoltage
unsigned int
2
0
65535
—
mV
0x5d
R
AverageVoltage
unsigned int
2
0
65535
—
mV
0x60
R/W
UnSealKey
hex
4
0x00000000
0xffffffff
—
0x61
R/W
FullAccessKey
hex
4
0x00000000
0xffffffff
—
0x62
R/W
PFKey
hex
4
0x00000000
0xffffffff
—
0x63
R/W
AuthenKey3
hex
4
0x00000000
0xffffffff
—
0x64
R/W
AuthenKey2
hex
4
0x00000000
0xffffffff
—
0x65
R/W
AuthenKey1
hex
4
0x00000000
0xffffffff
—
0x66
R/W
AuthenKey0
hex
4
0x00000000
0xffffffff
—
0x70
R/W
ManufacturerInfo
String
31+1
—
—
—
0x71
R/W
SenseResistor
unsigned int
2
0
65535
—
0x77
R/W
DataFlashSubClassID
hex
2
0x0000
0xffff
—
0x78
R/W
DataFlashSubClassPage1
hex
32
—
—
—
0x79
R/W
DataFlashSubClassPage2
hex
32
—
—
—
0x7a
R/W
DataFlashSubClassPage3
hex
32
—
—
—
0x7b
R/W
DataFlashSubClassPage4
hex
32
—
—
—
0x7c
R/W
DataFlashSubClassPage5
hex
32
—
—
—
0x7d
R/W
DataFlashSubClassPage6
hex
32
—
—
—
0x7e
R/W
DataFlashSubClassPage7
hex
32
—
—
—
0x7f
R/W
DataFlashSubClassPage8
hex
32
—
—
—
14
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μΩ
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Application Schematic
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15
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ20Z95DBT
NRND
TSSOP
DBT
44
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
20Z95DBT
BQ20Z95DBTG4
NRND
TSSOP
DBT
44
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
20Z95DBT
BQ20Z95DBTR
NRND
TSSOP
DBT
44
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
20Z95DBT
BQ20Z95DBTRG4
NRND
TSSOP
DBT
44
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2014
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ20Z95DBTR
Package Package Pins
Type Drawing
TSSOP
DBT
44
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
6.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
11.7
1.6
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ20Z95DBTR
TSSOP
DBT
44
2000
367.0
367.0
45.0
Pack Materials-Page 2
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