ICST MK2771-16 Vcxo and set-top clock source Datasheet

I C R O C LOC K
MK2771-16
VCXO and Set-Top Clock Source
Description
Features
The MK2771-16 is a low cost, low jitter, high
performance VCXO and clock synthesizer
designed for set-top boxes. The on-chip Voltage
Controlled Crystal Oscillator accepts a 0 to 3V
input voltage to cause the output clocks to vary by
±100 ppm. Using ICS/MicroClock’s patented
VCXO and analog Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive
13.5 MHz crystal input to produce multiple
output clocks including a selectable processor
clock, a selectable audio clock, two
communications clocks, a 13.5 MHz clock, and
three 27 MHz clocks. All clocks are frequency
locked to the 27.00MHz output (and to each
other) with zero ppm error, so any output can be
used as the VCXO output.
• Packaged in 28 pin SSOP (QSOP)
• On-chip patented VCXO with pull range
of 200ppm (minimum)
• VCXO tuning voltage of 0 to 3V
• Processor frequency include 16.66, 20, 25, 32, 40,
and 50 MHz
• Audio clocks support 32 kHz, 44.1 kHz, 48 kHz
and 96 kHz sampling rates
• Zero ppm synthesis error in all clocks (all exactly
track 27MHz VCXO)
• Uses an inexpensive 13.5 MHz crystal
• Full CMOS output swings with 25mA output
drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 5V operating voltage with 3.3V capable I/O
VDD5
Block Diagram
GND
VDDIO
3
AS2:0
2
PS1, PS0
2
CS1, CS0
PLL
Clock
Synthesis
Circuitry
VIN
13.5 MHz
pullable
crystal
X1
X2
Voltage
Controlled
Crystal
Oscillator
Output
Buffer
ACLK
Output
Buffer
PCLK
Output
Buffer
CCLK1
Output
Buffer
CCLK2
Output
Buffers
x2
PLL
÷2
Output
Buffer
3
27.000 MHz
13.500 MHz
1
Revision 102099
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
MDS 2771-16 C
I C R O C LOC K
Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PS0
X2
GND
X1
VDD5
VIN
VDDIO
VDD5
CS1
GND
GND
PCLK
CCLK2
ACLK
Audio Clock (MHz)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AS1
AS0
CS0
27M
GND
27M
VDD5
AS2
GND
GND
27M
CCLK1
PS1
13.5M
VDD5=5V±10%
VDDIO=3.3V±10%
VIN=0 to 3.0V (3.3V OK)
Number
1
2
3, 10, 11
4
5, 8, 22
6
7
9
12
13
14
15
16
17
18, 23, 25
19, 20, 24
21
26
27
28
MK2771-16
VCXO and Set-Top Clock Source
Name
PS0
X2
GND
X1
VDD5
VIN
VDDIO
CS1
PCLK
CCLK2
ACLK
13.5M
PS1
CCLK1
27M
GND
AS2
CS0
AS0
AS1
Type
I
XO
P
XI
P
I
P
I
O
O
O
O
TI
O
O
P
I
I
I
I
AS2 AS1 AS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ACLK
8.192
11.2896
12.288
5.6448
18.432
16.9344
49.152
24.576
0 = connect directly to GND
M = leave unconnected (floating)
1 = connect directly to VDDIO
Communications Clocks (MHz)
CS1 CS0 CCLK1
0
0
Low
0
1
Low
1
0
11.0592
1
1
11.0592
CCLK2
33.333
24.576
18.432
3.6864
Processor Clock (MHz)
PS1 PS0
0
0
0
1
M 0
M 1
1
0
1
1
PCLK
50
16.667
25
32
40
20
Description
Processor Clock Select 0. Selects PCLK frequency. See table above. Internal pull-up.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Connect to ground.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Connect to +5V.
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
Connect to +3.3V or +5V. Amplitude of inputs and outputs will match this.
Communications clock select pin 1 . Selects CCLK 1 and 2 per table above. Internal pull-up.
Processor Clock output. Determined by status of PS1, PS0.
Communications Clock output 2 determined by status of CS1,CS0 per table above.
Audio Clock Output. Determined by status of AS2:0 per table above.
13.50 MHz VCXO clock output.
Processor Clock Select 1. Selects PCLK frequency. See table above. Self-biased to M.
Communications Clock output 1 determined by status of CS1, CS0 per table above.
27.00 MHz VCXO clock output.
Connect to ground.
Audio Clock Select 2. Selects ACLK on pin 14 per table above. Internal pull-up.
Communications clocks select pin 0. Selects CCLK1 and 2 per table above. Internal pull-up.
Audio Clock Select 0. Selects ACLK on pin 14. See table above. Internal pull-up.
Audio Clock Select 1. Selects ACLK on pin 14. See table above. Internal pull-up.
Key: I = Input; TI = Tri-level input; O = output; P = power supply connection; XI, XO = crystal connections
2
Revision 102099
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
MDS 2771-16 C
MK2771-16
VCXO and Set-Top Clock Source
I C R O C LOC K
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
7
VDD+0.5
70
260
150
V
V
°C
°C
°C
5.25
5.25
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
pF
ppm
V
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Referenced to GND
Referenced to GND
-0.5
0
Max of 10 seconds
-65
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
Operating Voltage, VDDIO
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH (except PS1)
Input Low Voltage, VIL (except PS1)
Input High Voltage, VIH, PS1 only
Input Low Voltage, VIL, PS1 only
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD5
Operating Supply Current, IDDIO
Short Circuit Current
Input Capacitance
Frequency synthesis error
VIN, VCXO control voltage
for all inputs/outputs
4.75
3.00
3.5
2.5
2.5
1.5
2
0.8
VDD-0.5
0.5
IOH=-25mA
IOL=25mA
IOH=-8mA
No Load, note 2
No Load, VDDIO=3.3V
Each output
2.4
0.4
VDD-0.4
42
19
±100
7
All clocks
0
3
0
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Maximum Absolute Jitter, short term
27 MHz output pullability, note 3
Notes:
13.500000
0.8 to 2.0V
2.0 to 0.8V
At 1.4V
0V ≤ VIN ≤ 3V
1.5
1.5
60
40
±100
300
±140
MHz
ns
ns
%
ps
ppm
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest MHz.
3. With a pullable crystal that conforms to ICS’ specifications:
Correlation (load) capacitance
C0/C1
ESR
Initial Accuracy
Aging and Temp stability
Operating Temperature
14 pF
240 maximum
25 Ω maximum
±20 ppm
±50 ppm
0 to 70°C
3
Revision 102099
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
MDS 2771-16 C
MK2771-16
VCXO and Set-Top Clock Source
I C R O C LOC K
External Components
The MK2771-16 requires a minimum number of external components for proper operation. Use a low inductance ground
plane, connect all GNDs to this. Connect 0.01µF decoupling caps on pins 5, 7, 8 and 22 directly to the ground plane, as
close to the MK2771-16 as possible. A series termination resistor of 33Ω may be used for each clock output.The 13.500
MHz crystal must be connected as close to the chip as possible. The crystal should be a parallel mode, pullable, with load
capacitance of 14pF. Consult ICS/MicroClock full specifications. Please obey Application Note MAN05 for pullable
crystal layout info except for the following: the MK2771-16 introduces a GND pin (pin #3) between the pullable crystal
pins. This ground should be brought in straight from the right side underneath the device.
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
28 pin SSOP
E
Symbol
A
A1
B
C
D
E
e
H
L
H
D
A1
e
Millimeters
Min
Max
1.35
1.75
0.102
0.254
0.203
0.305
0.191
0.254
9.804 10.008
3.810
3.988
0.635 BSC
5.791
6.198
0.406
1.270
A
C
B
Inches
Min
Max
0.053 0.069
0.004 0.010
0.008 0.012
0.007 0.010
0.386 0.394
0.150 0.157
.025 BSC
0.228 0.244
0.016 0.050
L
Ordering Information
Part/Order Number
MK2771-16R
MK2771-16RTR
Marking
MK2771-16R
MK2771-16R
Shipping packaging
tubes
tape and reel
Package
Temperature
28 pin SSOP (QSOP)
0-70 °C
28 pin SSOP (QSOP)
0-70 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any
ICS product for use in life support devices or critical medical instruments.
4
Revision 102099
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
MDS 2771-16 C
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