CY23FP12 200 MHz Field Programmable Zero Delay Buffer Features Functional Description ■ Fully field-programmable ❐ Input and output dividers ❐ Inverting/noninverting outputs ❐ Phase-locked loop (PLL) or fanout buffer configuration ■ 10 MHz to 200 MHz operating range The CY23FP12 is a high performance fully field-programmable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection. These parameters are critical for reference clock distribution in systems using high performance ASICs and microprocessors. ■ Split 2.5 V or 3.3 V outputs ■ Two LVCMOS reference inputs ■ Twelve low skew outputs ❐ 35 ps typical output-to-output skew (same frequency) ■ 110 ps typical cycle-cycle jitter (same frequency) ■ Three-stateable outputs ■ Less than 50 μA shutdown current ■ Spread aware ■ 28-pin SSOP ■ 3.3 V operation ■ Industrial temperature available The CY23FP12 is fully programmable through volume or prototype programmers, enabling the user to define an application-specific Zero Delay Buffer with customized input and output dividers, feedback topology (internal/external), output inversions, and output drive strengths. For additional flexibility, the user can mix and match multiple functions listed in Table 2, and assign a particular function set to any one of the four possible S1-S2 control bit combinations. This feature enables the implementation of four distinct personalities, selectable with S1-S2 bits, on a single programmed silicon. The CY23FP12 also features a proprietary auto power down circuit that shuts down the device in case of a REF failure, resulting in less than 50 μA of current draw. The CY23FP12 provides 12 outputs grouped in two banks with separate power supply pins which can be connected independently to either a 2.5 V or a 3.3 V rail. Selectable reference input is a fault tolerance feature which enables glitch-free switch over to a secondary clock source when REFSEL is asserted/deasserted. Logic Block Diagram VDDA VDDC CLKA0 Lock Detect CLKA1 CLKA2 CLKA3 REFSEL CLKA4 REF1 REF2 FBK ÷M ÷N 100 to 400MHz PLL ÷1 ÷2 CLKA5 VSSA ÷3 VDDB ÷4 CLKB0 ÷X CLKB1 CLKB2 CLKB3 Test Logic S[2:1] CLKB4 Function Selection CLKB5 VSSC Cypress Semiconductor Corporation Document #: 38-07246 Rev. *G VSSB • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 18, 2011 [+] Feedback CY23FP12 Contents Pin Configuration ............................................................. 3 Pin Description ................................................................. 3 Field Programming the CY23FP12 ............................. 6 CyberClocks™ Software .............................................. 6 CY3672-USB Development Kit ................................... 6 CY23FP12 Frequency Calculation .................................. 6 Absolute Maximum Conditions ....................................... 7 Operating Conditions ....................................................... 7 DC Electrical Specifications ............................................ 7 Switching Characteristics ................................................ 8 Switching Waveforms ...................................................... 9 Test Circuits .................................................................... 10 Ordering Information ...................................................... 11 Ordering Code Definition ........................................... 11 Document #: 38-07246 Rev. *G Package Drawing and Dimension ................................. 12 Acronyms ....................................................................... 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC Solutions ......................................................... 15 Page 2 of 15 [+] Feedback CY23FP12 Pin Configuration Figure 1. 28-Pin SSOP Top View REF2 REF1 1 28 2 27 CLKB0 CLKB1 3 26 4 25 VSSB CLKB2 5 24 6 23 CLKB3 VDDB VSSB CLKB4 CLKB5 VDDB VDDC S2 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 REFSEL FBK CLKA0 CLKA1 VSSA CLKA2 CLKA3 VDDA VSSA CLKA4 CLKA5 VDDA VSSC S1 Pin Description Pin No. Name I/O Type Description 1 REF2 I LVTTL/LVCMOS Input reference frequency, 5 V-tolerant input. 2 REF1 I LVTTL/LVCMOS Input reference frequency, 5 V-tolerant input. 3 CLKB0 O LVTTL Clock output, Bank B. 4 CLKB1 O LVTTL Clock output, Bank B. 5 VSSB PWR POWER Ground for Bank B. 6 CLKB2 O LVTTL Clock output, Bank B. 7 CLKB3 O LVTTL Clock output, Bank B. 8 VDDB PWR POWER 2.5 V or 3.3 V supply, Bank B. 9 VSSB PWR POWER Ground for Bank B. 10 CLKB4 O LVTTL Clock output, Bank B. 11 CLKB5 O LVTTL Clock output, Bank B. 12 VDDB PWR POWER 2.5 V or 3.3 V supply, Bank B. 13 VDDC PWR POWER 3.3 V core supply. 14 S2 I LVTTL Select input. 15 S1 I LVTTL Select input. 16 VSSC PWR POWER Ground for core. 17 VDDA PWR POWER 2.5 V or 3.3 V supply, Bank A. 18 CLKA5 O LVTTL Clock output, Bank A. 19 CLKA4 O LVTTL Clock output, Bank A. 20 VSSA PWR POWER Ground for Bank A. 21 VDDA PWR POWER 2.5 V or 3.3 V supply Bank A. 22 CLKA3 O LVTTL Clock output, Bank A. 23 CLKA2 O LVTTL Clock output, Bank A. 24 VSSA PWR POWER Ground for Bank A. 25 CLKA1 O LVTTL Clock output, Bank A. 26 CLKA0 O LVTTL CLock output, Bank A. 27 FBK I LVTTL PLL feedback input. 28 REFSEL I LVTTL Reference select input. When REFSEL = 0, REF1 is selected. When REFSEL = 1, REF2 is selected. Document #: 38-07246 Rev. *G Page 3 of 15 [+] Feedback CY23FP12 Figure 2. Basic PLL Block Diagram CLKB5 /1,/2,/3,/4, /x,/2x CLKB4 /1,/2,/3,/4, /x,/2x REF /M /1,/2,/3,/4, /x,/2x PLL FBK /N /1,/2,/3,/4, /x,/2x CLKB3 CLKB2 Output CLKB1 Function CLKB0 Select CLKA5 Matrix CLKA4 /1,/2,/3,/4, /x,/2x CLKA3 /1,/2,/3,/4, /x,/2x CLKA1 CLKA2 CLKA0 The following table lists independent functions that can be programmed with a volume or prototype programmer on the “default” silicon. Table 1. Programmable Functions Configuration Description Default DC Drive Bank A Programs the drive strength of Bank A outputs. The user can select one out of two possible +16 mA drive strength settings that produce output DC currents in the range of ±16 mA to ±20 mA. DC Drive Bank B Programs the drive strength of Bank B outputs. The user can select one out of two possible +16 mA drive strength settings that produce output DC currents in the range of ±16 mA to ±20 mA. Output Enable for Bank B Enables/Disables CLKB[5:0] outputs. Each of the six outputs can be disabled individually Enable clocks if not used, to minimize electromagnetic interference (EMI) and switching noise. Output Enable for Bank A Enables/Disables CLKA[5:0] outputs. Each of the six outputs can be disabled individually Enable clocks if not used, to minimize EMI and switching noise. Inv CLKA0 Generates an inverted clock on the CLKA0 output. When this option is programmed, CLKA0 and CLKA1 will become complimentary pairs. Non-invert Inv CLKA2 Generates an inverted clock on the CLKA2 output. When this option is programmed, CLKA2 and CLKA3 will become complimentary pairs. Non-invert Inv CLKA4 Generates an inverted clock on the CLKA4 output. When this option is programmed, CLKA4 and CLKA5 will become complimentary pairs. Non-invert Inv CLKB0 Generates an inverted clock on the CLKB0 output. When this option is programmed, CLKB0 and CLKB1 will become complimentary pairs. Non-invert Inv CLKB2 Generates an inverted clock on the CLKB2 output. When this option is programmed, CLKB2 and CLKB3 will become complimentary pairs. Non-invert Inv CLKB4 Generates an inverted clock on the CLKB4 output. When this option is programmed, CLKB4 and CLKB5 will become complimentary pairs. Non-invert Document #: 38-07246 Rev. *G Page 4 of 15 [+] Feedback CY23FP12 Table 1. Programmable Functions Configuration Description Default Pull-down Enable Enables/Disables internal pulldowns on all outputs Fbk Pull-down Enable Enables/Disables internal pulldowns on the feedback path (applicable to both internal and Enable external feedback topologies) Enable Fbk Sel Selects between the internal and the external feedback topologies External Table 2 lists independent functions that can be assigned to each of the four S1 and S2 combinations. When a particular S1 and S2 combination is selected, the device assumes the configuration (which is essentially a set of functions given in Table 2) that has been preassigned to that particular combination. Table 2. Programmable Functions for S1/S2 Combinations Function Description Default Output Enable CLKB[5:4] Enables/Disables CLKB[5:4] output pair See Table 4 on page 6 Output Enable CLKB[3:2] Enables/Disables CLKB[3:2] output pair See Table 4 on page 6 Output Enable CLKB[1:0] Enables/Disables CLKB[1:0] output pair See Table 4 on page 6 Output Enable CLKA[5:4] Enables/Disables CLKA[5:4] output pair See Table 4 on page 6 Output Enable CLKA[3:2] Enables/Disables CLKA[3:2] output pair See Table 4 on page 6 Output Enable CLKA[1:0] Enables/Disables CLKA[1:0] output pair See Table 4 on page 6 Auto Power-down Enable Enables/Disables the auto power down circuit, which monitors the reference clock rising Enable edges and shuts down the device in case of a reference “failure.” This failure is triggered by a drift in reference frequency below a set limit. This auto power down circuit is disabled internally when one or more of the outputs are configured to be driven directly from the reference clock. PLL Power-down Shuts down the PLL when the device is configured as a non-PLL fanout buffer. M[7:0] Assigns an eight-bit value to reference divider –M. The divider can be any integer value 2 from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz. N[7:0] Assigns an eight-bit value to feedback divider –N. The divider can be any integer value from 1 to 256; however, the PLL input frequency cannot be lower than 10 MHz. X[6:0] Assigns a seven-bit value to output divider –X. The divider can be any integer value from 1 5 to 130. Divide by 1,2,3, and 4 are preprogrammed on the device and can be activated by the appropriate output mux setting. Divider Source Selects between the PLL output and the reference clock as the source clock for the output See Table 4 on dividers. page 6 CLKA54 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKA5 and CLKA4 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKA32 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKA3 and CLKA2 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKA10 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKA1 and CLKA0 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKB54 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKB5 and CLKB4 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKB32 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKB3 and CLKB2 pair. Please refer to Table 3 on page 6 for a list of divider values. CLKB10 Source Independently selects one out of the eight possible output dividers that will connect to the Divide by 2 CLKB1 and CLKB0 pair. Please refer to Table 3 on page 6 for a list of divider values. Document #: 38-07246 Rev. *G PLL Enabled 2 Page 5 of 15 [+] Feedback CY23FP12 Table 3 is a list of output dividers that are independently selected to connect to each output pair. In the default (unprogrammed) state of the device, S1 and S2 pins will function as indicated in Table 4. Table 3. Output Dividers CyberClocks™ Software CyberClocks is an easy-to-use software application that allows the user to custom-configure the CY23FP12. Users can specify the REF frequency, PLL frequency, output frequencies and/or post-dividers, and different functional options. CyberClocks outputs an industry standard JEDEC file used for programming the CY23FP12. CLKA/B Source Output Connects To 0 [000] REF 1 [001] Divide by 1 CyberClocks can be downloaded free of charge from the Cypress website at www.cypress.com. 2 [010] Divide by 2 CY3672-USB Development Kit 3 [011] Divide by 3 4 [100] Divide by 4 The Cypress CY3672-USB Development Kit, in combination with the CY3692 Socket Adapter, is used to program samples and small prototype quantities of the CY23FP12. This portable programmer connects to a PC via a USB interface. 5 [101] Divide by X 6 [110] Divide by 2X[1] 7 [111] TEST mode [LOCK signal][2] Table 4. S1/S2 Default Functionality S2 S1 CLKA[5:0] CLKB[5:0] Divider Source 0 0 Three-state Three-state PLL 0 1 Driven Three-state PLL 1 0 Driven Driven Reference 1 1 Driven Driven PLL Field Programming the CY23FP12 The CY23FP12 must be programmed in a device programmer prior to being installed in a circuit. The CY23FP12 is based on flash technology, so it can be reprogrammed up to 100 times. This enables fast and easy design changes and product updates, and eliminates any issues with old and out-of-date inventory. Samples and small prototype quantities can be programmed on the CY3672-USB programmer. Cypress’s value-added distribution partners and third-party programming systems from BP Microsystems, HiLo Systems, and others are available for large production quantities. CY23FP12 Frequency Calculation The CY23FP12 is an extremely flexible clock buffer with up to twelve individual outputs, generated from an integrated PLL. Four variables are used to determine the final output frequency. These are the input Reference Frequency, the M and N dividers, and the post divider. The basic PLL block diagram is shown in Figure 2 on page 4. Each of the six clock output pairs has many post divider options available to it. There are six post divider options: /1, /2, /3, /4, /X, and /2X. X is a programmable value between 5 and 130, and 2X is twice that value. The post divider options can be applied to the calculated PLL frequency or to the REF directly. The feedback is connected either internally to CLKA0 or externally to any output. A programmable divider, M, is inserted between the reference input, REF, and the phase detector. The divider M can be any integer 1 to 256. The PLL input frequency cannot be lower than 10 MHz or higher than 200 MHz. A programmable divider, N, is inserted between the feedback input, FBK, and the phase detector. The divider N can be any integer 1 to 256. The PLL input frequency cannot be lower than 10 MHz or higher than 200 MHz. The output can be calculated as follows: FREF / M = FFBK / N. FPLL = (FREF * N * post divider) / M. FOUT = FPLL / post divider. In addition to above divider options, the following option bypasses the PLL and passes the REF directly to the output. FOUT = FREF. Notes 1. Outputs will be rising edge aligned only to those outputs using this same device setting. 2. When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is set to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode. If CLKA0 is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode. Document #: 38-07246 Rev. *G Page 6 of 15 [+] Feedback CY23FP12 Absolute Maximum Conditions Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Parameter Description Condition Min Max Unit VDD Supply voltage Non-functional –0.5 7 VDC VIN Input voltage REF Relative to VCC –0.5 VDD + 0.5 VDC VIN Input voltage except REF Relative to VCC –0.5 VDD + 0.5 VDC LUI Latch-up immunity Functional TS Temperature, storage Non-functional TJ Junction temperature ØJc Dissipation, Junction to case Functional 34 °C/W ØJa Dissipation, Junction to ambient Functional 86 °C/W ESDh ESD protection (Human body model) MSL Moisture sensitivity level GATES Total functional gate count Assembled Die UL–94 Flammability rating At 1/8 in. FIT Failure in time Manufacturing test 300 mA –65 125 °C – 125 °C 2000 V MSL – 1 class 21375 each V–0 class 10 ppm Operating Conditions Parameter Description VDDC Core supply voltage VDDA, VDDB Bank A, Bank B supply voltage TA Test Conditions Temperature, operating ambient Min Max Unit 3.135 3.465 V 3.135 3.465 V 2.375 2.625 V °C Commercial temperature Industrial temperature tPU Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0 70 –40 85 0.05 500 ms DC Electrical Specifications Parameter Description VIL Input LOW voltage[3] voltage[3] Test Conditions VIH Input HIGH IIL Input LOW current[3] VIN = 0 V IIH Input HIGH current[3] VIN = VDD VOL Output LOW voltage[4] VDDA/VDDB = 3.3 V, IOL = 16 mA (standard drive) VDDA/VDDB = 3.3 V, IOL = 20 mA (high drive) VDDA/VDDB = 2.5 V, IOL = 16 mA (high drive) VOH Output HIGH voltage[4] VDDA/VDDB = 3.3 V, IOH = –16 mA (standard drive) VDDA/VDDB = 3.3 V, IOH = –20 mA (high drive) VDDA/VDDB = 2.5 V, IOH = –16 mA (high drive) IDDS Power-down supply current REF = 0 MHz Min Typ Max Unit – – 0.3 × VDD V 0.7 × VDD – – V – – 50 μA – – 50 μA – – 0.5 V VDD – 0.5 – – V – 12 50 μA Notes 3. Applies to both REF Clock and FBK. 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. Document #: 38-07246 Rev. *G Page 7 of 15 [+] Feedback CY23FP12 DC Electrical Specifications Parameter IDD Description Supply current Test Conditions Min Typ Max Unit VDDA = VDDB = 2.5 V, Unloaded outputs at 166 MHz – VDDA = VDDB = 2.5 V, Loaded outputs at 166 MHz, CL = 15 pF – 40 65 mA 65 100 VDDA = VDDB = 3.3 V, Unloaded outputs at 166 MHz – 50 80 VDDA = VDDB = 3.3 V, Loaded outputs at166 MHz, CL = 15 pF – 100 120 Switching Characteristics [5] Parameter fREF Description Reference frequency Test Conditions [6] Min Typ Max Unit MHz Commercial temperature 10 – 200 Industrial temperature 10 – 166.7 ERREF Reference edge rate 1 – – V/ns DCREF Reference duty cycle 25 – 75 % MHz fOUT DCOUT t3 t4 Output frequency[7] Output duty cycle[5] Rise time[5] Fall time[5] CL = 15 pF, Commercial temperature 10 – 200 CL = 15 pF, Industrial temperature 10 – 166.7 CL = 30 pF, Commercial temperature 10 – 100 CL = 30 pF, Industrial temperature 10 – 83.3 VDDA/B = 3.3 V, measured at VDD/2 45 50 55 VDDA/B = 2.5 V, measured at VDD/2 40 50 60 VDDA/B = 3.3 V, 0.8 V to 2.0 V, CL = 30 pF (standard drive and high drive) – – 1.6 VDDA/B = 3.3 V, 0.8 V,10 V to 2.0 V, CL = 15 pF (standard drive and high drive) – – 0.8 VDDA/B = 2.5 V, 0.6 V to 1.8 V, CL = 30 pF (high drive only) – – 2.0 VDDA/B = 2.5 V, 0.6 V to 1.8 V, CL = 15 pF (high drive only) – – 1.0 VDDA/B = 3.3 V, 0.8 V to 2.0 V, CL = 30 pF (standard drive and high drive) – – 1.6 VDDA/B = 3.3 V, 0.8 V to 2.0 V, CL = 15 pF (standard drive and high drive) – – 0.8 VDDA/B = 2.5 V, 0.6 V to 1.8 V, CL = 30 pF (high drive only) – – 1.6 VDDA/B = 2.5 V, 0.6 V to 1.8 V, CL = 15 pF (high drive only) – – 0.8 % ns ns Notes 5. All parameters are specified with loaded outputs. 6. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10MHz. With auto power-down disabled and PLL power-down enabled, the reference frequency can be as low as DC level. 7. When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the output frequency can be lower than 10MHz. With auto power-down disabled and PLL power-down enabled, the output frequency can be as low as DC level. Document #: 38-07246 Rev. *G Page 8 of 15 [+] Feedback CY23FP12 Switching Characteristics [5] Parameter TTB Description budget,[8,9] Total timing Bank A and B same frequency Test Conditions Outputs at 200 MHz, tracking skew not included Total timing budget, Bank A and B different frequency t5 Min Typ Max Unit – – 650 ps – – 850 Output to output skew[5] All outputs equally loaded – 35[10] 200 Bank to bank skew Same frequency – – 200 Bank to bank skew Different frequency – – 400 Bank to bank skew Different voltage, same frequency ps – – 400 t6 Input to output skew (static Measured at VDD/2, REF to FBK phase offset)[5] – 0 250 ps t7 Device-to-device skew[5] – 0 500 ps ps tJ Cycle-to-cycle (Peak) jitter[5] Measured at VDD/2 [11] Banks A and B at same frequency – 110 200 Cycle-to-cycle jitter[5] (Peak) Banks A and B at different frequencies – – 400 tTSK Tracking skew Input reference clock at < 50-KHz modulation with ±3.75% spread – – 200 ps tLOCK PLL lock time[5] Stable power supply, valid clock at REF – – 1.0 ms tLD Inserted loop delay Max loop delay for PLL Lock (stable frequency) – – 7 ns Max loop delay to meet Tracking Skew Spec – – 4 ns Switching Waveforms Figure 3. Duty Cycle Timing Figure 4. All Outputs Rise/Fall Time Notes 8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 9. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency. 10. Same frequency, 15pF load, high drive. 11. Same frequency, 15pF load, low drive. Document #: 38-07246 Rev. *G Page 9 of 15 [+] Feedback CY23FP12 Figure 5. Output-Output Skew Figure 6. Input-Output Propagation Delay Figure 7. Device-Device Skew Test Circuits Document #: 38-07246 Rev. *G Page 10 of 15 [+] Feedback CY23FP12 Ordering Information Ordering Code Pb-free CY23FP12OXC CY23FP12OXCT CY23FP12OXI CY23FP12OXIT Programmer CY3672-USB CY3692 Package Type 28-pin SSOP 28-pin SSOP – Tape and Reel 28-pin SSOP 28-pin SSOP – Tape and Reel Operating Range Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Programmer with USB Interface CY23FP12 Socket Adapter for CY3672-USB Programmer (Labeled CY3672 ADP006) Ordering Code Definition CY23FP12 OX X (T) Package type: T = tape and reel, blank = tube Temperature code: C = Commercial, I = Industrial Package: 28-pin SSOP, Pb-free Device number Document #: 38-07246 Rev. *G Page 11 of 15 [+] Feedback CY23FP12 Package Drawing and Dimension Figure 8. 28-Pin (5.3 mm) Shrunk Small Outline Package 51-85079 *D Document #: 38-07246 Rev. *G Page 12 of 15 [+] Feedback CY23FP12 Acronyms Acronym Document Conventions Description DCXO digitally controlled crystal oscillator ESD electrostatic discharge PLL phase locked loop RMS root mean square SSOP shrunk small outline package XTAL crystal Document #: 38-07246 Rev. *G Units of Measure Symbol Unit of Measure °C degree Celsius µA micro amperes mA milli amperes ms milli seconds MHz Mega Hertz ns nano seconds pF pico Farad ps pico seconds V Volts Page 13 of 15 [+] Feedback CY23FP12 Document History Page Document Title: CY23FP12 200 MHz Field Programmable Zero Delay Buffer Document Number: 38-07246 Revision ECN Submission Date Orig. of Change ** 115158 07/03/02 HWT *A 121880 12/14/02 RBI Power-up requirements added to Absolute Maximum Ratings information *B 124523 03/19/03 RGL Final data sheet Changed title to “200 MHz Field Programmable Zero Delay Buffer” *C 126938 06/16/03 RGL Interchanged REF2 in the Pin Configuration diagram Replaced all divide by 2 default value to divide by 2 in Table 2 Fixed the formula in the Frequency Calculation section *D 129364 09/10/03 RGL Changed the CyClocksRT trademark to CyberClocks Added Note 2 in the TEST mode in Table 3 Added TLD specifications in the Switching Characteristics table *E 299718 See ECN RGL Added lead-free devices Added typical values *F 2865396 01/25/2010 KVM Updated template. Added captions to tables 1-4. Added Operating Conditions table. Various edits to text. Removed “FTG” from text about the CY3672 programmer. Specified separate commercial and industrial max values for fREF Removed part numbers CY23FP12OC, CY23FP12OCT, CY23FP12OI and CY23FP12OIT. Changed part number CY3672 to CY3672-USB. Updated package drawing. *G 3146083 01/18/11 BASH Modified VIN max vaue from 7 to VDD + 0.5 in “Absolute Maximum Conditions” on page 8. Added Acronyms, Document Conventions, and Ordering Code Definition. Document #: 38-07246 Rev. *G Description of Change New datasheet Page 14 of 15 [+] Feedback CY23FP12 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07246 Rev. *G Revised January 18, 2011 Page 15 of 15 2 CyberClocks™ is a trademark and CyClocks is a registered trademark of Cypress Semiconductor Corporation. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback