MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Some of contents are subject to change without notice. The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S40ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems. FEATURES - Single 3.3v±0.3v power supply - Clock frequency 125MHz /100MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/Full Page (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Burst Write / Single Write (programmable) - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A7 - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch Max. Frequency CLK Access Time M5M4V64S40ATP-8A 125MHz 6ns M5M4V64S40ATP-8 100MHz 6ns M5M4V64S40ATP-10 100MHz 8ns Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 Vdd CLK CKE /CS /RAS /CAS /WE DQ0-15 DQML/U A0-11 BA0,1 Vdd VddQ Vss VssQ MITSUBISHI ELECTRIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 400mil 54pin TSOP(II) PIN CONFIGURATION (TOP VIEW) DESCRIPTION 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC (Vref) DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss : Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output 1 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM DQ0-15 BLOCK DIAGRAM I/O Buffer Memory Array Memory Array Memory Array Memory Array Bank #0 Bank #1 Bank #2 Bank #3 Mode Register Control Circuitry Address Buffer A0-11 BA0,1 Control Signal Buffer Clock Buffer CLK /CS /RAS /CAS /WE DQM CKE Type Designation Code This rule is applied to only Synchronous DRAM family. M 5M 4 V 64 S 4 0 A TP - 8 Access Item Package Type TP: TSOP(II) Process Generation Function 0: Random Column, 1: 2N-rule Organization 2n 2: x4, 3: x8, 4: x16 Synchronous DRAM Density 64:64M bits Interface S: SSTL, V:LVTTL Memory Style (DRAM) Use, Recommended Operating Conditions, etc Mitsubishi Main Designation MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM PIN FUNCTION CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. /CS Input Chip Select: When /CS is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. A0-11 Input A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-7 . A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. BA0,1 Input Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. DQ0-15 Input / Output Data In and Data out are referenced to the rising edge of CLK. Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the current cycle is masked. When DQMU/L is high in burst read, Dout is disabled at the next but one cycle. DQMU/L Input Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only. MITSUBISHI ELECTRIC 3 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM BASIC FUNCTIONS The M5M4V64S40ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. CLK /CS Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Refresh Option @refresh command A10 Precharge Option @precharge or read/write command define basic commands Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge, READA). Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (autoprecharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read / write operation. When A10 =H at this command, both banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically. MITSUBISHI ELECTRIC 4 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM COMMAND TRUTH TABLE COMMAND MNEMONIC CKE n-1 CKE n /CS Deselect DESEL H X H X No Operation NOP H X L Row Address Entry & Bank Activate ACT H X Single Bank Precharge PRE H Precharge All Banks PREA Column Address Entry & Write /RAS /CAS /WE BA0,1 A11 A10 A0-9 X X X X X X H H H X X X X L L H H V V V V X L L H L V X L X H X L L H L X X H X WRITE H X L H L L V X L V Column Address Entry & Write with AutoPrecharge WRITEA H X L H L L V X H V Column Address Entry & Read READ H X L H L H V X L V Column Address Entry & Read with AutoPrecharge READA H X L H L H V X H V Auto-Refresh REFA H H L L L H X X X X Self-Refresh Entry REFS H L L L L H X X X X Self-Refresh Exit REFSX L H H X X X X X X X L H L H H H X X X X Burst Terminate TBST H X L H H L X X X X Mode Register Set MRS H X L L L L L L L V*1 H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM FUNCTION TRUTH TABLE Current State /CS /RAS /CAS /WE IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA Auto-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST NOP L H L H BA, CA, A10 READ / READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A10 WRITE / WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA ACT Bank Active / ILLEGAL*2 L L H L BA, A10 PRE / PREA Precharge / Precharge All L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST Terminate Burst ROW ACTIVE READ L H L H Address BA, CA, A10 Command Action READ / WRITE ILLEGAL*2 Bank Active, Latch RA NOP*4 Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MITSUBISHI ELECTRIC Bank Active / ILLEGAL*2 Terminate Burst, Precharge 6 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM FUNCTION TRUTH TABLE(continued) Current State /CS /RAS /CAS /WE WRITE H X X X L H H L H H L READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE H L Command Action X DESEL NOP (Continue Burst to END) H X NOP NOP (Continue Burst to END) L BA TBST Terminate Burst H Address BA, CA, A10 Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge*3 WRITE / WRITEA Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST ILLEGAL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L BA TBST ILLEGAL L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Bank Active / ILLEGAL*2 Terminate Burst, Precharge READ / READA ILLEGAL WRITE / WRITEA ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 READ / READA ILLEGAL WRITE / WRITEA MITSUBISHI ELECTRIC ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 7 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM FUNCTION TRUTH TABLE(continued) Current State /CS /RAS /CAS /WE PRE CHARGING H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L BA TBST ILLEGAL*2 L H L X BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE / PREA L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Row Active after tRCD) L H H H X NOP NOP (Row Active after tRCD) L H H L BA TBST ILLEGAL*2 L H L X BA, CA, A10 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP L H H H X NOP NOP L H H L BA TBST ILLEGAL*2 L H L X BA, CA, A10 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE / PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING WRITE RECOVERING Address Command Action READ / WRITE ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) READ / WRITE ILLEGAL*2 READ / WRITE ILLEGAL*2 MITSUBISHI ELECTRIC 8 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM FUNCTION TRUTH TABLE(continued) Current State /CS /RAS /CAS /WE REFRESHING H X X X X DESEL NOP (Idle after tRC) L H H H X NOP NOP (Idle after tRC) L H H L BA TBST ILLEGAL L H L X BA, CA, A10 L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Idle after tRSC) L H H H X NOP NOP (Idle after tRSC) L H H L BA TBST ILLEGAL L H L X BA, CA, A10 L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE / PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL MODE REGISTER SETTING Address Command Action READ / WRITE ILLEGAL READ / WRITE ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. MITSUBISHI ELECTRIC 9 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM FUNCTION TRUTH TABLE for CKE Current State SELFREFRESH*1 POWER DOWN ALL BANKS IDLE*2 ANY STATE other than listed above CKE n-1 CKE n /CS H X X X L H H L H L /RAS /CAS /WE Add Action X X X INVALID X X X X Exit Self-Refresh (Idle after tRC) L H H H X Exit Self-Refresh (Idle after tRC) H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) H X X X X X X INVALID L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Self-Refresh) H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State =Power Down H H X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle*3 L H X X X X X Exit CLK Suspend at Next Cycle*3 L L X X X X X Maintain CLK Suspend ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. MITSUBISHI ELECTRIC 10 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM SIMPLIFIED STATE DIAGRAM SELF REFRESH REFS REFSX MRS MODE REGISTER SET REFA IDLE AUTO REFRESH CKEL CKEH CLK SUSPEND ACT POWER DOWN CKEL CKEH TBST (for Full Page) WRITE WRITE SUSPEND READ WRITEA CKEL TBST (for Full Page) ROW ACTIVE READA READ WRITE WRITE CKEL READ CKEH CKEH WRITEA READA WRITEA READA CKEL WRITEA SUSPEND CKEL PRE WRITEA CKEH POWER APPLIED READ SUSPEND POWER ON PRE PRE READA PRE CKEH READA SUSPEND PRE CHARGE Automatic Sequence Command Sequence MITSUBISHI ELECTRIC 11 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER CLK Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are inÅ@ idle state. After tRSC from a MRS command, the SDRAM is ready for new command. /CS /RAS /CAS /WE V BA0,1 A11-A0 BA0 BA1 A11 A10 A9 0 0 0 LATENCY MODE CL 000 001 010 011 100 101 110 111 WRITE MODE 0 1 0 A8 WM 0 A7 A6 0 /CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT A5 A4 A3 LTMODE A2 A1 A0 BT BL BURST LENGTH BL BT= 0 BT= 1 000 001 010 011 100 101 110 111 1 2 4 8 R R R FP 1 2 4 8 R R R R 0 SEQUENTIAL INTERLEAVED 1 R: Reserved for Future Use FP: Full Page BURST TYPE MITSUBISHI ELECTRIC 12 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM CLK Command Read Write Y Y Address Q0 DQ CL= 3 BL= 4 /CAS Latency Q1 Q2 Q3 D0 Burst Length D1 D2 D3 Burst Length Burst Type Initial Address BL Column Addressing A2 A1 A0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 Sequential Interleaved 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 1 0 1 0 2 - - 1 MITSUBISHI ELECTRIC 13 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM [ /CAS LATENCY ] /CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the speed of CLK determines which CL should be used. First output data is available after CL cycles from READ command. /CAS Latency Timing(BL=4) CLK ACT Command READ tRCD X Address Y CL=2 DQ Q0 CL=3 DQ Q1 Q2 Q3 Q0 Q1 Q2 CL=2 Q3 CL=3 [ BURST LENGTH ] The burst length, BL, determines the number of consecutive writes or reads that will be automatically performed after the initial write or read command. For BL=1,2,4,8, the output data is tristated (Hi-Z) after the last read. For BL=FP (Full Page), the TBST (Burst Terminate) command must be used to stop the output of data. Burst Length Timing( CL=2 ) tRCD CLK Command ACT READ Address X Y DQ Q0 DQ Q0 Q1 DQ Q0 Q1 Q2 Q3 DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 BL=1 BL=2 BL=4 BL=8 Q8 M5M4V64S20A : m=1023 M5M4V64S30A : m=511 M5M4V64S40A : m=255 MITSUBISHI ELECTRIC Qm Q0 Q1 BL=FP Full Page counter rolls over and continues to count. 14 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM OPERATIONAL DESCRIPTION BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A11-0. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC, although the number of banks which are active concurrently is not limited. PRECHARGE The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued. Bank Activation and Precharge All (BL=4, CL=3) CLK 2 ACT command / tRCmin tRCmin Command ACT ACT READ tRRD A0-9 PRE ACT tRAS Xa Xb Y 0 tRP Xb tRCD A10 Xa Xb A11 Xa Xb BA0,1 00 DQ 01 1 Xb Xb 00 01 Qa0 Qa1 Qa2 Qa3 Precharge all READ After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A7-0(X16), and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. MITSUBISHI ELECTRIC 15 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Multi Bank Interleaving READ (BL=4, CL=3) CLK Command ACT A0-9 Xa Y Xb Y A10 Xa 0 Xb 0 0 A11 Xa 10 00 Qa1 Qa2 READ ACT READ PRE tRCD BA0,1 Xb 00 00 10 DQ Qa0 /CAS latency Qa3 Qb0 Qb1 Qb2 Burst Length READ with Auto-Precharge (BL=4, CL=3) CLK BL + tRP Command ACT READ A0-9 Xa Y Xa A10 Xa 1 Xa A11 Xa tRCD BA0,1 00 ACT BL tRP Xa 00 00 Qa0 DQ Qa1 Qa2 Qa3 Internal precharge start READ Auto-Precharge Timing (BL=4) CLK Command ACT READ BL CL=3 DQ CL=2 DQ Qa0 Qa0 Qa1 Qa2 Qa1 Qa2 Qa3 Qa3 Internal Precharge Start Timing MITSUBISHI ELECTRIC 16 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A7-0 (x 16), and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing. The Mode Register can be programmed for burst read and single write. In this mode the write data is only clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data burst length os unaffected while in this mode Multi Bank Interleaving WRITE (BL=4) CLK Command ACT Write ACT tRCD Write PRE PRE 0 0 0 0 10 00 10 Db0 Db1 tRCD A0-9 Xa Y Xb Y A10 Xa 0 Xb 0 A11 Xa BA0,1 00 Xb DQ 00 10 Da0 Da1 Da2 Da3 Db2 Db3 WRITE with Auto-Precharge (BL=4) CLK Command ACT Write ACT tRCD tWR tRP A0-9 Xa Y Xa A10 Xa 1 Xa A11 Xa BA0,1 00 DQ Xa 00 Da0 00 Da1 Da2 Da3 Internal precharge starts MITSUBISHI ELECTRIC 17 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM [ BURST WRITE ] A burst write operation is enabled by setting A9=0. A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1,2,4,8, and full-page, like burst read operations. tRCD CLK Command Address ACT X WRITE Y DQ Q0 DQ Q0 Q1 DQ Q0 Q1 Q2 Q3 DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 BL=1 BL=2 BL=4 BL=8 Q8 Q9 M5M4V64S20A : m=1023 M5M4V64S30A : m=511 M5M4V64S40A : m=255 Q10 Qm Q0 Q1 BL=FP Full Page counter rolls over and continues to count. [ SINGLE WRITE ] A single write operation is enabled by setting A9=1. In a single write operation, data is only written to the column address specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0.) CLK Command ACT WRITE tRCD Address DQ X Y Q0 MITSUBISHI ELECTRIC 18 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read Interrupted by Read (BL=4, CL=3) CLK Command READ READ READ READ A0-9 Yi Yj Yk Yl A10 0 0 0 0 00 00 10 01 A11 BA0,1 Qai0 Qaj0 DQ Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 [ Read Interrupted by Write ] Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3) CLK READ Write A0-9 Yi Yj A10 0 0 00 00 Command A11 BA0,1 DQM Q D Qai0 Daj0 Daj1 Daj2 Daj3 DQM control Write control MITSUBISHI ELECTRIC 19 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM [ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. Read Interrupted by Precharge (BL=4) CLK Command READ PRE DQ Command READ Q0 Q1 Q0 Q1 Q2 PRE CL=3 DQ Command READ PRE Q0 DQ Command READ Q0 DQ Command CL=2 READ DQ Q1 Q2 PRE Q0 DQ Command PRE Q1 READ PRE Q0 MITSUBISHI ELECTRIC 20 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM [ Read Interrupted by Burst Terminate ] Similar to a precharge, the burst terminate command, TBST, can interrupt the burst read operation and disable the data output. The READ to TBST interval is a minimum of one CLK. TBST is mainly used to interrupt FP bursts. The figures below show examples, of how the output data is terminated with TBST. Read Interrupted by Burst Terminate(BL=4) CLK Command READ TBST DQ CL=3 Command Q0 READ Q0 Command READ TBST Q0 READ DQ Q1 Q2 Q3 TBST DQ Command Q2 Q0 DQ CL=2 Q1 Q3 READ TBST DQ Command Q2 TBST DQ Command Q1 Q0 Q1 Q2 READ TBST Q0 MITSUBISHI ELECTRIC 21 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=4) CLK Command Write Write Write Write A0-9 Yi Yj Yk Yl A10 0 0 0 0 BA0,1 00 00 10 00 DQ Dai0 Daj0 A11 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=3) CLK Command Write READ Write READ A0-9 Yi Yj Yk Yl A10 0 0 0 0 00 00 10 00 A11 BA0,1 DQM DQ Dai0 Qaj0 Qaj1 Dbk0 Dbk1 MITSUBISHI ELECTRIC Qal0 22 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank . Random column access is allowed. Write recovery time (tWR) is required from the last data to PRE command. Write Interrupted by Precharge (BL=4) CLK Command Write PRE tWR A0-9 Yi A10 0 ACT tRP Xb 0 Xb Xb A11 BA0,1 00 00 00 DQM Dai0 DQ Dai1 Dai2 [ Write Interrupted by Burst Terminate ] A burst terminate command TBST can be used to terminate a burst write operation. In this case, the write recovery time is not required and the bank remains active (Please see the waveforms below). The WRITE to TBST minimum interval is one CLK. Write Interrupted by Burst Terminate(BL=4) CLK Command WRITE A0-9 Yi A10 0 BA 0 TBST DQMU/DQML (DQM) DQ Dai0 Dai1 Dai2 MITSUBISHI ELECTRIC 23 SDRAM (Rev.1.3) Mar'98 MITSUBISHI LSIs M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command. Auto-Refresh CLK /CS NOP or DESELECT /RAS /CAS /WE CKE minimum tRC A0-11 BA0,1 Auto Refresh on All Banks Auto Refresh on All Banks MITSUBISHI ELECTRIC 24 SDRAM (Rev.1.3) Mar'98 MITSUBISHI LSIs M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh CLK Stable CLK NOP /CS /RAS /CAS /WE CKE tSRX new command X A0-11 00 BA0,1 Self Refresh Entry Self Refresh Exit MITSUBISHI ELECTRIC minimum tRC +1 CLOCK for recovery 25 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. ext.CLK CKE int.CLK Power Down by CKE CLK Standby Power Down CKE Command PRE NOP NOP NOP NOP Active Power Down CKE Command NOP NOP NOP ACT NOP NOP NOP NOP NOP NOP NOP DQ Suspend by CKE CLK CKE Command DQ Write D0 READ D1 D2 D3 MITSUBISHI ELECTRIC Q0 Q1 Q2 Q3 26 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM DQM CONTROL DQMU/L is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQMU/L masks input data word by word. DQMU/L to write mask latency is 0. During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2. DQM Function CLK Command Write READ DQMU/L DQ D0 D2 D3 masked by DQMU/L=H MITSUBISHI ELECTRIC Q0 Q1 Q3 disabled by DQMU/L=H 27 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V VddQ Supply Voltage for Output with respect to VssQ -0.5 ~ 4.6 V VI Input Voltage with respect to Vss -0.5 ~ Vdd+0.5 V VO Output Voltage with respect to VssQ -0.5 ~ VddQ+0.5 V IO Output Current 50 mA Pd Power Dissipation 1000 mW Topr Operating Temperature 0 ~ 70 °C Tstg Storage Temperature -65 ~ 150 °C Ta = 25 °C RECOMMENDED OPERATING CONDITIONS (Ta=0 ~ 70°C, unless otherwise noted) Limits Symbol Parameter Unit Min. Typ. Max. Vdd Supply Voltage 3.0 3.3 3.6 V Vss Supply Voltage 0 0 0 V VddQ Supply Voltage for Output 3.0 3.3 3.6 V VssQ Supply Voltage for Output 0 0 0 V VIH High-Level Input Voltage all inputs 2.0 Vdd+0.3 V VIL Low-Level Input Voltage all inputs -0.3 0.8 V Note:* VIH (max) = Vdd+2.0V AC for pulse width<=3ns acceptable. VIL(min) = -2V AC for pulse width<=3ns acceptable. CAPACITANCE (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Symbol Parameter Test Condition min. max. Unit CI(A) Input Capacitance, address pin VI=Vss 2.5 5 pF CI(C) Input Capacitance, control pin f=1MHz 2.5 5 pF CI(K) Input Capacitance, CLK pin Vi=25mVrms 2.5 4 pF CI/O Input Capacitance, I/O pin 4 6.5 pF MITSUBISHI ELECTRIC 28 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, Output Open, unless otherwise noted) Limits (max) Symbol Parameter Test Conditions Unit -8A -8 -10 Icc1s operating current, single bank tRC=min, tCLK=min, BL=1, CL=3 115 115 90 mA Icc1d operating current, dual bank tRC=90ns, tCLK=min, BL=1, CL=3 140 125 125 mA Icc2h standby current, CKE=H all banks idle, tCLK=min 25 22 22 mA Icc2l standby current, CKE=L all banks idle, tCLK=min 2 2 2 mA Icc3h active standby current, CKE=H all banks active, tCLK=min 55 55 45 mA Icc3l active standby current, CKE=L all banks active, tCLK=min 5 5 2 mA Icc4 burst current all banks active, tCLK=min, BL=4, CL=3 140 125 125 mA Icc5 auto-refresh current tRC=min, tCLK=min 150 150 115 mA 1 1 1 mA Icc6 self-refresh current CKE <0.2v 0.5 0.5 mA -8A,-8,-10 -8L,-10L AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Limits Symbol Parameter Test Conditions Unit Min. VOH (DC) High-Level Output Voltage (DC) IOH=-2mA VOL (DC) Low-Level Output Voltage (DC) IOL= 2mA Off-state Output Current Q floating VO=0 ~ VddQ Input Current VIH = 0 ~ VddQ+0.3V IOZ II MITSUBISHI ELECTRIC Max. 2.4 V 0.4 V -5 5 µA -5 5 µA 29 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM AC TIMING REQUIREMENTS (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V Limits Symbol Parameter -8A Min. tCLK -8 Max. Unit -10 Min. Max. Min. note Max. CL=2 12 15 15 ns CL=3 8 10 10 ns CLK cycle time tCH CLK High pulse width 3 3 4 ns 1 tCL CLK Low pulse width 3 3 4 ns 1 tT Transition time of CLK 1 tIS Input Setup time (all inputs) 2 2 3 ns 1 tIH Input Hold time (all inputs) 1 1 1 ns 1 tRC Row Cycle time 72 70 90 ns tRCD Row to Column Delay 20 20 30 ns tRAS Row Active time 48 tRP Row Precharge time 20 20 30 ns tWR Write Recovery time 10 10 10 ns tRRD Act to Act Delay time 16 20 20 ns tCCD Col to Col Delay time 8 10 10 ns tRSC Mode Register Set Cycle time 16 20 20 ns tSRX Self Refresh Exit time 8 10 10 ns tREF Refresh Interval time Note:1 2 10 100K 1 10 50 1 100K 64 64 60 10 100K 64 ns ns 2 ms The timing requirements are assumed tT=1ns. If tT is longer than 1ns, (tT-1)ns should be added to the parameter. 2 ACT commands are allowed within tRC. CLK 1.4V Signal 1.4V MITSUBISHI ELECTRIC Any AC timing is referenced to the input signal crossing through 1.4V. 30 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM SWITCHING CHARACTERISTICS (Ta=0 ~ 70°C, Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise notedsee note3) Limits Symbol Parameter -8A Min. tAC -8 Max. Min. -10 Max. Min. Unit Max. CL=2 8 9 9 ns CL=3 6 6 8 ns Access time from CLK tOH Output Hold time from CLK 2.5 3 3 ns tOLZ Delay time, output low impedance from CLK 0 0 0 ns tOHZ Delay time, output high impedance from CLK 2.5 Note:3 6 3 6 3 8 ns If tr(clock rising time) is longer than 1ns, (tT/2-0.5)ns should be added to the parameter. Output Load Condition VTT=1.4V CLK 1.4V 50Ω VREF =1.4V DQ 1.4V VOUT 50pF Output Timing Measurement Reference Point CLK 1.4V DQ 1.4V tAC tOH tOHZ MITSUBISHI ELECTRIC 31 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Burst Write (single bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE tWR CKE DQMU/L A0-7 X Y A10 X X A8,9,11 X X BA0,1 0 0 D0 DQ ACT#0 X 0 D0 WRITE#0 D0 0 D0 Y 0 D0 PRE#0 ACT#0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 32 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Burst Write (multi bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE tWR tWR CKE DQMU/L A0-7 X X A10 X A8,9,11 BA0,1 Y X X X X X X X X X 0 1 0 D0 DQ ACT#0 Y D0 WRITE#0 ACT#1 D0 D0 1 0 D1 D1 0 D1 PRE#0 WRITE#1 D1 1 2 Y 0 D0 ACT#0 D0 D0 D0 ACT#2 WRITE#0 PRE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 33 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Burst Read (single bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQMU/L DQM read latency =2 A0-7 X A10 X X A8,9,11 X X BA0,1 0 Y X 0 0 0 Y 0 CL=3 Q0 DQ ACT#0 READ#0 Q0 Q0 PRE#0 Q0 Q0 ACT#0 Q0 READ#0 READ to PRE ≥BL allows full data out Italic parameter indicates minimum case MITSUBISHI ELECTRIC 34 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Burst Read (multiple bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD tRAS tRP /RAS tRCD tRCD /CAS /WE CKE DQMU/L DQM read latency =2 A0-7 X X A10 X A8,9,11 BA0,1 Y Y X X X X X X X X X 0 1 0 1 CL=3 ACT#0 READ#0 ACT#1 0 1 2 Q1 Q1 Q1 0 CL=3 Q0 DQ 0 Y Q0 Q0 Q0 PRE#0 READ#1 Q1 ACT#0 PRE#1 Q0 READ#0 ACT#2 Italic parameter indicates minimum case 35 MITSUBISHI ELECTRIC MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Burst Write (multi bank) with Auto-Precharge @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL-1+ tWR + tRP BL-1+ tWR + tRP /WE CKE DQMU/L A0-7 X X A10 X X X X A8,9,11 X X X X BA0,1 0 1 Y 0 D0 DQ ACT#0 ACT#1 Y X 1 D0 D0 WRITE#0 with AutoPrecharge D0 D1 D1 D1 Y X 0 0 1 D1 D0 D0 ACT#0 WRITE#1 with AutoPrecharge Y 1 D0 WRITE#0 ACT#1 D0 D1 WRITE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 36 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK tRC /CS tRRD tRRD /RAS tRCD tRCD tRCD /CAS BL+tRP BL+tRP /WE CKE DQMU/L DQM read latency =2 A0-7 X X Y Y A10 X X X X A8,9,11 X X X X BA0,1 0 1 0 1 CL=3 ACT#0 ACT#1 Y 0 0 CL=3 Q0 DQ X READ#0 with Auto-Precharge Q0 Q0 X Y 1 1 CL=3 Q0 Q1 Q1 ACT#0 READ#1 with Auto-Precharge Q1 Q1 Q0 Q0 READ#0 ACT#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 37 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Page Mode Burst Write (multi bank) @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU/L A0-7 X X A10 X X A8,9,11 X X BA0,1 0 1 Y Y Y Y 0 0 1 0 D0 DQ ACT#0 D0 WRITE#0 ACT#1 D0 D0 D0 D0 D0 D0 D1 D1 WRITE#0 D1 D1 D0 D0 D0 WRITE#0 WRITE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 38 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Page Mode Burst Read (multi bank) @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU/L DQM read latency=2 A0-7 X X A10 X X A8,9,11 X X 0 1 BA0,1 Y Y Y Y 0 0 1 0 CL=3 CL=3 Q0 DQ ACT#0 READ#0 ACT#1 Q0 Q0 Q0 CL=3 Q0 Q0 Q0 READ#0 Q0 Q1 Q1 Q1 Q1 READ#0 READ#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 39 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Write Interrupted by Write / Read @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD tCCD /CAS /WE CKE DQMU/L A0-7 X X A10 X X A8,9,11 X X BA0,1 0 1 Y Y Y Y Y 0 0 0 1 0 CL=3 DQ D0 D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0 ACT#0 WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1 Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 40 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Read Interrupted by Read / Write @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU/L DQM read latency=2 A0-7 X X A10 X X A8,9,11 X X 0 1 BA0,1 DQ ACT#0 Y Y Y Y Y Y 0 0 0 1 0 0 Q0 Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q0 D0 D0 READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 41 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Write Interrupted by Precharge @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU/L A0-7 X X A10 X X X A8,9,11 X X X 0 1 BA0,1 DQ Y Y 0 D0 D0 ACT#0 WRITE#0 ACT#1 D0 D0 X 1 0 D1 D1 1 1 1 D1 PRE#0 WRITE#1 PRE#1 Burst Write is not interrupted by Precharge of the other bank. Y ACT#1 D1 D1 WRITE#1 Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 42 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Read Interrupted by Precharge @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRRD tRP /RAS tRCD tRCD /CAS /WE CKE DQMU/L DQM read latency=2 A0-7 X X A10 X X X A8,9,11 X X X 0 1 BA0,1 Y Y 0 Q0 DQ ACT#0 READ#0 ACT#1 X 1 0 1 Q0 Q0 Q0 1 Q1 PRE#0 READ#1 PRE#1 Burst Read is not interrupted by Precharge of the other bank. Y 1 Q1 ACT#1 READ#1 Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 43 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Mode Register Setting 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRSC tRC /RAS tRCD /CAS /WE CKE DQMU/L M A0-7 X A10 X A8,9,11 X BA0,1 0 0 Y 0 D0 DQ Auto-Ref (last of 8 cycles) Mode Register Setting ACT#0 D0 D0 D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 44 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Auto-Refresh @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS tRC /RAS tRCD /CAS /WE CKE DQMU/L A0-7 X A10 X A8,9,11 X BA0,1 0 Y 0 D0 DQ D0 D0 Auto-Refresh ACT#0 Before Auto-Refresh, all banks must be idle state. After tRC from Auto-Refresh, all banks are idle state. D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 45 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Self-Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK CLK can be stopped tRC /CS /RAS /CAS /WE tSRX CKE CKE must be low to maintain Self-Refresh DQMU/L A0-7 X A10 X A8,9,11 X BA0,1 0 DQ Self-Refresh Entry Self-Refresh Exit Before Self-Refresh Entry, all banks must be idle state. ACT#0 After tRC from Self-Refresh Exit, all banks are idle state. Italic parameter indicates minimum case MITSUBISHI ELECTRIC 46 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM DQM Write Mask @BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQMU/L A0-7 X A10 X A8,9,11 X BA0,1 0 Y Y Y 0 0 0 masked D0 DQ ACT#0 D0 WRITE#0 D0 D0 masked D0 WRITE#0 D0 D0 WRITE#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 47 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM DQM Read Mask @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE DQM read latency=2 DQMU/L A0-7 X A10 X A8,9,11 X BA0,1 0 Y Y Y 0 0 0 masked Q0 DQ ACT#0 READ#0 Q0 Q0 Q0 masked Q0 READ#0 Q0 Q0 READ#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 48 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Power Down 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS /CAS /WE Standby Power Down Active Power Down CKE CKE latency=1 DQMU/L A0-7 X A10 X A8,9,11 X BA0,1 0 DQ Precharge All ACT#0 Italic parameter indicates minimum case MITSUBISHI ELECTRIC 49 MITSUBISHI LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM CLK Suspend @BL=4 CL=3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=1 CKE latency=1 DQMU/L A0-7 X A10 X A8,9,11 X BA0,1 0 Y Y 0 0 D0 DQ ACT#0 D0 D0 D0 Q0 WRITE#0 READ#0 CLK suspended Q0 Q0 Q0 CLK suspended Italic parameter indicates minimum case MITSUBISHI ELECTRIC 50 SDRAM (Rev.1.3) Mar'98 MITSUBISHI LSIs M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. 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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein A8,9,11for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. MITSUBISHI ELECTRIC 51