IRF IR2166PBF Pfc & ballast control ic Datasheet

Data Sheet No. PD60198 revE
IR2166(S) & (PbF)
PFC & BALLAST CONTROL IC
Features
• Programmable dead time
• Internal ignition ramp
• Internal fault counter
• DC bus under-voltage reset
• Shutdown pin with hysteresis
• Internal 15.6V zener clamp diode on Vcc
• Micropower startup (150µA)
• Latch immunity and ESD protection
• 16-Lead PDIP also available LEAD-FREE
• PFC, Ballast control and half-bridge driver in one IC
• Critical conduction mode boost type PFC
• No PFC current sense resistor required
• Programmable preheat frequency
• Programmable preheat time
• Programmable run frequency
• Programmable over-current protection
• Programmable end-of-life protection
Description
Packages
The IR2166 is a fully integrated, fully protected 600V ballast control IC designed to
drive all types of fluorescent lamps. PFC circuitry operates in critical conduction mode
and provides for high PF, low THD and DC Bus regulation. The IR2166 features include programmable preheat and run frequencies, programmable preheat time, programmable dead-time, programmable over-current protection, and programmable endof-life protection. Comprehensive protection features such as protection from failure of
a lamp to strike, filament failures, end-of-life protection, DC bus undervoltage reset as
well as an automatic restart function, have been included in the design. The IR2166 is
available in both 16-lead PDIP and 16-lead (narrow body) SOIC packages.
16-Lead SOIC
(narrow body)
16-Lead
PDIP
also available
LEAD-FREE
IR2166 Application Diagram
D BUS
+ Rectified AC Line
R BUS
R SUPPLY
C VDC
16
1
CPH
RT
RT
3
RPH
4
CT
RPH
CT
5
CCOMP
DZCOMP
COMP
7
6
R1
8
VCC
D BOOT
14
COM
12
CVCC1
C SNUB
D CP1
R5
CVCC2
R GLS
LO
11
CS
R2
SD/EOL
D1
R3
M2
CRES
R6
D CP2
R7
10
PFC
M3
C BOOT
13
ZX
7
VB
+
C PH
C BLOCK LRES
15
2
+
M1
VS
IR2166
C BUS
R GHS
HO
VBUS
R VDC
9
R GPFC
R4
RCS
C SD1
C CS
C SD2
D2
D3
C EOL
R8
- Rectified AC Line
*Please note that this data sheet contains advanced information that could change before the product is released to production.
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1
IR2166 & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
VB
High side floating supply voltage
-0.3
625
VS
High side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VLO
Low side output voltage
-0.3
VCC + 0.3
VPFC
PFC gate driver output voltage
-0.3
VCC + 0.3
IOMAX
Maximum allowable output current (HO, LO, PFC)
due to external power transistor miller effect
-500
500
V BUS
mA
VBUS pin voltage
-0.3
VCC + 0.3
VCT
CT pin voltage
-0.3
VCC + 0.3
I CPH
CPH pin current
-5
5
I RPH
RPH pin current
-5
5
V RPH
RPH pin voltage
-0.3
VCC + 0.3
V
mA
IRT
RT pin current
-5
5
RT pin voltage
-0.3
VCC + 0.3
VCS
Current sense pin voltage
-0.3
5.5
I CS
Current sense pin current
-5
5
Shutdown pin current
-5
5
I CC
Supply current (Note 1)
-20
20
IZX
PFC inductor current, zero crossing detection input current
-5
5
PFC error compensation current
-5
5
ICOMP
dV/dt
PD
RthJA
-50
50
Package power dissipation @ TA ≤ +25°C
Allowable offset voltage slew rate
(16-Pin PDIP)
—
1.80
PD = (TJMAX-TA)/RthJA
(16-Pin SOIC)
—
1.40
(16-Pin PDIP)
—
70
(16-Pin SOIC)
—
86
Thermal resistance, junction to ambient
TJ
Junction temperature
-55
150
TS
Storage temperature
-55
150
TL
Lead temperature (soldering, 10 seconds)
—
300
Note 1:
V
mA
VRT
ISD/EOL
2
V
V
mA
V/ns
W
o
C/W
o
C
This IC contains a zener clamp structure between the chip VCC and COM which has a nominal breakdown
voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source
greater than the VCLAMP specified in the Electrical Characteristics section.
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IR2166 & (PbF)
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol
Definition
VBS
High side floating supply voltage
VS
Min.
Max.
VCC - 0.7
V CLAMP
Steady state high side floating supply offset voltage
-1
600
V CLAMP
V CC
Supply voltage
V CCUV+
I CC
Supply current
Note 2
CT
CT lead capacitance
ISD/EOL
220
-1
End-of-life lead current
V
10
mA
—
pF
1
I CS
Current sense lead current
-1
1
IZX
Zero crossing detection pin current
-1
1
TJ
Junction temperature
-25
125
Note 2:
Units
mA
o
C
Enough current should be supplied into the VCC lead to keep the internal 15.6V zener clamp diode on this lead
regulating its voltage, VCLAMP.
Electrical Characteristics
VCC = VBS = VBIAS = 14V +/- 0.25V, VBUS = Open, RT = 39.0kΩ, RPH = 100kΩ, CT = 470 pF, VCPH = 0.0V, VSD = 0.0V,
VCOMP = 0.0V, VCS = 0.0V, CLO = CHO = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition
Min.
Typ.
Max.
10.0
11.5
12.5
Units Test Conditions
Supply Characteristics
VCCUV+
VCC supply undervoltage positive going
threshold
VCCUVVUVHYS
IQCCUV
IQCC
VCC supply undervoltage negative going
threshold
VCC supply undervoltage lockout hysteresis
UVLO mode quiescent current
Quiescent VCC supply current
VCLAMP
VCC zener clamp voltage
VCC rising from 0V
8.5
9.5
10.7
V
1.5
145
—
2.0
170
2.3
3.0
290
4.0
µA
mA
14.3
15.6
17
V
-1
5
—
0
30
2.5
5
70
—
µA
—
—
50
µA
VCC falling from 14V
VCC = 8V
CT connected toCOM
VCC =14V
ICC = 10mA
Floating Supply Characteristics
IQBS0
IQBS1
VBSMIN
ILK
Quiescent VBS supply current
Quiescent VBS supply current
Minimum required VBS voltage for proper
HO functionality
Offset supply leakage current
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VHO = VS (CT = 0V)
VHO = VB (CT = 14V)
V
VB = VS = 600V
3
IR2166 & (PbF)
Electrical Characteristics cont.
VCC = VBS = VBIAS = 14V +/- 0.25V, VBUS = Open, RT = 39.0kΩ, RPH = 100kΩ, CT = 470 pF, VCPH = 0.0V, VSD = 0.0V,
VCOMP = 0.0V, VCS = 0.0V, CLO = CHO = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition
Min.
Typ.
Max.
5
35
55
-62
-30
-12
10.5
13.5
Units
Test Conditions
PFC Error Amplifier Characteristics
ICOMP
Error amplifier output current sourcing
SOURCE
ICOMP
Error amplifier output current sinking
SINK
VCOMPOH Error amplifier output voltage swing
(high state)
VCOMPOL Error amplifier output voltage swing
(low state)
µA
14.5
V
VCPH = 14V
VBUS = 3.5V
VCPH = 14V
VBUS = 4.5V
VBUS = 3.0V
VBUS = 5.0V
—
0.25
4
Overvoltage comparator threshold
Overvoltage comparator hysterisis
3.8
150
4.3
300
4.7
400
V
mV
VBUS internal reference voltage
3.7
4.0
4.2
V
1.1
75
6.3
1.65
300
7.5
2
800
9.1
V
mV
V
90
400
824
µS
ZX = 0V, VCOMP> =2V
39
73
—
6.8
1.8
—
0.7
0.7
42
78
50
8.4
4.6
0
1.0
1.0
50
84
—
10.7
5.6
—
1.5
1.5
kHz
Run mode
Preheat mode
2.6
—
3.2
0
—
—
0.1
0
PFC DC Bus Regulation
VBUSOV
VBUSOV
HYS
VVBUS
REG
VCOMP = 4.0V
VCOMP = 4V
VCOMP = 4V
PFC Zero Current Detector
VZX
ZX pin comparator threshold voltage
VZXhys
ZX pin comparator hysterisis
VZXclamp ZX pin clamp voltage (high state)
VCOMP = 4V
VCOMP = 4V
IZX = 5mA
PFC Watch-dog
tWD
Watch-dog pulse interval
Ballast Control Oscillator Characteristics
f osc
d
VCT+
VCTVCTFLT
tDLO
tDHO
Oscillator frequency
Oscillator duty cycle
Upper CT ramp voltage threshold
Lower CT ramp voltage threshold
Fault-mode CT lead voltage
LO output deadtime
HO output deadtime
%
V
VCC = 14V
SD > 5.0V or CS >1.3V
usec
CT = 470pF
4.6
—
µA
mV
SD > 5.0V or CS >1.3V
—
—
µA
mV
SD > 5.0V or CS >1.3V
Ballast Control Preheat Characteristics
ICPH
CPH pin charging current
VCPHFLT Fault-mode CPH pin voltage
VCPH=5V,CT=0V, VBUS=0V
RPH Characteristics
I RPHLK
Open circuit RPH pin leakage current
VRPHFLT Fault-mode RPH pin voltage
4
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IR2166 & (PbF)
Electrical Characteristics cont.
VCC = VBS = VBIAS = 14V +/- 0.25V, VBUS = Open, RT = 39.0kΩ, RPH = 100kΩ, CT = 470 pF, VCPH = 0.0V, VSD = 0.0V,
VCOMP = 0.0V VCS = 0.0V, CLO = CHO = 1000pF, TA = 25oC unless otherwise specified.
Symbol Definition
Min.
Typ.
Max.
Units
—
—
0.1
0
—
—
µA
mV
VSDTH+
Rising shutdown pin reset threshold voltage 4.5
V SDHYS Shutdown pin 5.0V threshold hysteresis
100
VSDEOL+ Rising shutdown pin end-of-life threshold volt.
2.4
VSDEOL- Falling shutdown pin end-of-life threshold volt. 0.7
VCSTH+Over-current sense threshold voltage
0.91
25
#FAULT- Number of sequential over-current fault
cycles before IC shuts down
VBUSUV- The VBUS threshold below which the IC
2.6
shuts down
V CPH
CPH pin end-of-life enable threshold
10.3
5.2
150
3.0
1.0
1.2
75
5.6
350
3.6
1.6
1.3
90
V
mV
3.0
3.3
Test Conditions
RT Characteristics
I RTLK
VRTFLT
Open circuit RT pin leakage current
Fault-mode RT pin voltage
CT = 10V
SD > 5.0V or CS >1.3V
Protection Circuitry Characteristics
V
Cycles
VCPH>12V
V CPH>7.5V
VCPH>7.5V, CYCLES
CS > 1.3V
V
12
13.2
Gate Driver Output Characteristics (HO, LO and PFC pins)
VOL
VOH
tr
tf
I0+
I0-
Low-level output voltage
High-level output voltage
—
—
0
0
100
100
Turn-on rise time
Turn-off fall time
HO, LO, PFC source current
HO, LO, PFC sink current
—
—
—
—
110
55
300
400
210
160
—
—
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mV
Io = 0
VBIAS - Vo, Io = 0
nsec
CHO = CLO = CPFC
= 1nF
mA
5
IR2166 & (PbF)
Block Diagram
Vcc 13
S1
RT 3
R
Soft
Start
S2
R
40K
Driver
Logic
Comp
1
CT 5
VTH
RDT
3.0K
R
T
Q
R
Q
HighSide
Driver
14
VB
16
HO
15
VS
11
LO
10
CS
9
SD/EOL
8
PFC
S3
S4
Fault
Logic
S6
R
RPH
4
Fault
Counter
R
LowSide
Driver
Schmitt
1
3uA
CPH 2
COM 12
S
Q
R1
R2 Q
Comp
3
1.3V
3V
UnderVoltage
Detect
2.0V
1.0M
1V
CPH>12V
CPH>12V
VBUS 1
Over-Voltage
Protection
Gain
4.0V
OTA1
7.6V
5.2V
VCC
4.3V
COMP 6
Under-Voltage
Reset
3.0V
S
Q
R
Q
VCC
S
S
Q
R
Q
Q
Watch
Dog
Timer
R1
R2 Q
ZX 7
1.0V
7.6V
6
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IR2166 & (PbF)
State Diagram
Power Turned On
UVLO Mode
1/ -Bridge
2
Off
IQCC ≅ 400µA
CPH = 0V
CT = 0V (Oscillator Off)
VCC > 11.5V (UV+)
and
SD/EOL < 5.0V
SD/EOL > 5.0V
(Lamp Removal)
or
VCC < 9.5V (UV-)
(Power Turned Off)
PREHEAT Mode
FAULT Mode
Fault Latch Set
1/ -Bridge Off
2
IQCC ≅ 180µA
CPH = 0V
VCC = 15.6V
CT = 0V (Oscillator Off)
VCC < 9.5V
(VCC Fault or Power Down)
or
SD/EOL > 5.0V
(Lamp Fault or Lamp Removal)
1
CS > 1.3V for 25
cycles
/2-Bridge oscillating @ fPH
RPH // RT
CPH Charging @ ICPH = 5 µA
PFC Enabled (High Gain)
CS Enabled
Fault Counter Enabled
CPH > (VCC - 4V)
(End of PREHEAT Mode)
CS > 1.3V for 25 cycles
(Failure to Strike Lamp)
Ignition Ramp
Mode
RPH>Open
fPH ramps to fRUN
CPH charging
CS > 1.3V
(Lamp Fault)
or
SD/EOL<1.0V or SD/EOL>3.0V
(End-of-Life)
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CPH > (VCC - 2V)
RUN Mode
RPH = Open
1/2-Bridge Oscillating @fRUN
EOL Thresholds Enabled
PFC = Low Gain Mode
VBUS UV Threshold Enabled
Fault Counter Disabled
VBUS<3.0V
Discharge
VCC
to UVLO-
7
IR2166 & (PbF)
Lead Assignments & Definitions
VBUS
HO
1
16
CPH
VS
2
15
3
14
VB
RPH
4
CT
5
COMP
7
6
IR2166
RT
8
RT
4
RPH
CT
7
COM
8
9
PFC
SD/EOL
10
LO
11
10
9
3
COMP
ZX
SD/EOL
8
CPH
6
12
PFC
VBUS
2
VCC
CS
7
1
5
13
ZX
Pin # Symbol
Description
DC Bus Sensing Input
Preheat Timing Capacitor
Minimum Frequency Timing Resistor
Preheat Frequency Timing Resistor
Oscillator Timing Capacitor
PFC Error Amplifier Compensation
CS
PFC Zero-Crossing Detection
PFC Gate Driver Output
Shut-Down/End of Life Sensing Circuit
Current Sensing Input
11
LO
Low-Side Gate Driver Output
12
COM
IC Power & Signal Ground
13
VCC
VB
Logic & Low-Side Gate Driver Supply
High-Side Gate Driver Floating Supply
14
15
VS
High Voltage Floating Return
16
HO
High-Side Gate Driver Output
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IR2166 & (PbF)
BALLAST TIMING DIAGRAMS
NORMAL OPERATION
VCC
15.6V
UVLO+
UVLO-
VCC
7.5V
CPH
frun
FREQ
fph
HO
LO
CS
Over-Current Threshold
1.3V
PH
IGN
UVLO
RUN
UVLO
RT
RT
RT
RPH
RPH
RPH
CT
CT
CT
HO
HO
HO
LO
LO
LO
CS
CS
CS
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9
IR2166 & (PbF)
BALLAST TIMING
DIAGRAMS
FAULT CONDITION
VCC
15.6V
UVLO+
UVLO-
VCC
7.5V
CPH
f run
FREQ
fp
h
SD
HO
LO
CS
1.3V
PH
IGN
SD > 5.1V
IGN
10
PH
FAULT
UVLO
RUN
RT
RT
RT
RPH
RPH
RPH
CT
CT
CT
HO
HO
HO
LO
LO
LO
CS
CS
CS
UVLO
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IR2166 & (PbF)
14
1600
12
UVLO+
1400
10
UVLO-
1200
1000
CT (pF)
VCC (V)
8
6
800
600
4
400
2
200
0
-25
0
25
50
75
100
0
125
0
0.5
1
Temperature (°C)
Graph 1. VCCUV+, VCCUV- vs TEMP
2
2.5
3
Graph 2. CT vs Dead Time
1000000
9
8
CT+
6
100000
Frequency (KHz)
7
CT (V)
1.5
DeadTime(µS)
CT-
5
4
3
10000
2
1
0
1000
-25
0
25
50
75
100
Temperature (°C)
Graph 3: CT+, CT- vs TEMP
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125
5
25
45
65
85
RT(K Ω)
Graph 4: Frequency vs RT
11
IR2166 & (PbF)
8
3.5
7
3
2.5
6
2
ICPH (mA)
ICC (mA)
5
4
3
1.5
1
0.5
0
2
-0.5
1
-1
-1.5
0
40
80
120
160
0
200
3
6
50
2.5
40
2
ZX Threshold & HYS.(V)
ILK ( A)
12
15
Graph 6: ICPH vs VCPH
Graph 5: ICC vs Frequency
30
20
10
ZX+
1.5
ZX1
HYS
0.5
0
0
-25
0
25
50
75
Temperature (°C)
Graph 7. ILK vs TEMP
12
9
VCPH (V)
FREQUENCY (KHz)
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Graph 8: ZX+, ZX- vs TEMP
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IR2166 & (PbF)
325
9
8.5
IZX(ZXInput Bias) ( A)
315
8
305
7.5
295
7
285
6.5
275
6
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph 9: IZX (ZX Input Bias) vs TEMP
Graph 10: VZX (ZX Clamp Voltage) vs TEMP
5
5
4.5
4.5
VBUS+
4
4
3.5
3.5
3
VBUS-
3
-25
0
25
50
75
100
125
Temperature (°C)
Graph 11: VBUS Sense Thresh vs TEMP
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-25
0
25
50
75
100
125
Temperature (°C)
Graph 12: VBUS+, VBUS- vs TEMP
13
IR2166 & (PbF)
63
150
Trise
61
100
FREQ(KHz)
PFC Trise, Tfall (nS)
125
Tfall
75
59
57
50
55
25
0
53
-25
0
25
50
75
100
125
-25
0
Temperature (°C)
25
50
75
100
125
Temperature (°C)
Graph 14: Frequency vs TEMP
Graph 13: PFC Trise, Tfall vs TEMP
2.5
200
175
150
t RISE, t FALL (nS)
tDEAD (
S)
2.3
t DEAD HO
2.1
1.9
t DEAD LO
125
t RISE
100
75
50
1.7
t FALL
25
1.5
0
-25
0
25
50
75
100
125
Temperature (°C)
Graph 15: tDEAD HO, tDEAD LO vs TEMP
14
-25
0
25
50
75
100
125
Temperature (°C)
Graph 16: tRISE, tFALL vs TEMP
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50
5
40
4
CS Threshold (V)
# CS Pulses
IR2166 & (PbF)
30
20
3
2
1
10
0
0
-25
0
25
50
75
100
-25
125
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph 17: CS Pulses vs TEMP
Graph 18: CS Threshold vs TEMP
3.5
6
EOL+
3
5.5
VSD/EOL (V)
V SD/EOL (V)
2.5
2
1.5
EOL-
1
SD+
5
SD-
4.5
0.5
0
4
-25
0
25
50
75
100
Tem perature (°C)
Graph 19: EOL+,EOL- vs TEMP
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125
-25
0
25
50
75
100
125
Tem perature (°C)
Graph 20: SD+, SD- vs TEMP
15
IR2166 & (PbF)
3
2.5
14
2
13
IQCC (mA)
VCPH(EOL/RUN) Threshold (V)
15
12
1.5
1
11
0.5
10
0
-25
0
25
50
75
100
125
8
9
10
Temperature (°C)
13
Graph 22: I QCC vs V CC UVLO Hysteresis
16
90
14
80
70
12
60
10
IQBS ( A)
VCOMP (V)
12
V CC (V)
Graph 21: VCPH (EOL/RUN) Threshold vs TEMP
8
6
50
40
30
20
4
10
2
0
-10
0
0
5
10
15
PFC ON TIME (µS)
Graph 23: VCOMP vs PFC ON TIME
16
11
20
0
3
6
9
12
15
V BS (V )
Graph 24: IQBS(1) vs VCC vs Temp
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IR2166 & (PbF)
20
20
-25
-25
16
25
16
75
125
75
12
IQCC (mA)
IQCC (mA)
25
125
8
4
12
8
4
0
0
0
5
10
15
20
15
15.5
16.5
V CC (V)
VCC (V)
Graph 25. IQCC vs VCC vs Temp
Graph 26. IQCC vs V CC vs Temp
Internal Zener Diode Curve
0.3
2.5
-2 5
-25
0.25
2
25
25
75
75
0.2
IQCC (mA)
16
125
1.5
125
0.15
1
0.1
0.5
0.05
0
0
0
3
6
9
12
VCC (V)
Graph 27. IQCC vs VCC vs Temp
Micropower Startup Mode
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15
10
10.5
11
11.5
12
12.5
13
V C C (V )
Graph 28: IQCC vs VCC vs Temp VCCUV+
17
IR2166 & (PbF)
3
-25
2.5
25
75
IQCC ( A)
2
125
1.5
1
0.5
0
8.5
9
9.5
10
10.5
V CC (V)
Graph 29: IQCC vs VCC vs Temp VCCUV-
18
www.irf.com
IR2166 & (PbF)
I. Ballast Section
Functional Description
VC1
CVCC
DISCHARGE
Under-voltage Lock-Out Mode (UVLO)
The under-voltage lock-out mode (UVLO) is
defined as the state the IC is in when VCC is
below the turn-on threshold of the IC. To identify
the different modes of the IC, refer to the State
Diagram shown on page 7 of this document. The
IR2166 undervoltage lock-out is designed to
maintain an ultra low supply current of less than
400uA, and to guarantee the IC is fully functional
before the high and low side output drivers are
activated. Figure 1 shows an efficient supply
voltage using the start-up current of the IR2166
together with a charge pump from the ballast
output stage (RSUPPLY, CVCC, DCP1 and DCP2).
VBUS(+)
R SUPPLY
D BOOT
16
15
14
IR2166
13
12
11
HO
M1
VS
Half-Bridge
Output
VB
VCC
COM
C BOOT
C SNUB
C VCC
LO
M2
D CP1
RCS
D CP2
VBUS(-)
Figure 1, Start-up and supply circuitry.
The start-up capacitor (CVCC) is charged by
current through supply resistor (RSUPPLY)
minus the start-up current drawn by the IC. This
resistor is chosen to set the line input voltage
turn-on threshold for the ballast . Once the
capacitor voltage on VCC reaches the start-up
threshold, and the SD pin is below 5.0 volts, the
IC turns on and HO and LO begin to oscillate.
The capacitor begins to discharge due to the
increase in IC operating current (Figure 2).
www.irf.com
INTERNAL VCC
ZENER CLAMP VOLTAGE
VUVLO+
VHYST
VUVLO-
DISCHARGE
TIME
CHARGE PUMP
OUTPUT
RSUPPLY & CVCC
TIME
CONSTANT
t
Figure 2, Supply capacitor (CVCC) voltage.
During the discharge cycle, the rectified current
from the charge pump charges the capacitor above
the IC turnoff threshold. The charge pump and
the internal 15.6V zener clamp of the IC take over
as the supply voltage. The start-up capacitor and
snubber capacitor must be selected such that
enough supply current is available over all ballast
operating conditions. A bootstrap diode (DBOOT)
and supply capacitor (CBOOT) comprise the
supply voltage for the high side driver circuitry.
To guarantee that the high-side supply is charged
up before the first pulse on pin HO, the first pulse
from the output drivers comes from the LO pin.
During under-voltage lockout mode, the highand low-side driver outputs HO and LO are both
low, pin CT is connected internally to COM to
disable the oscillator, and pin CPH is connected
internally to COM for resetting the preheat time.
Preheat Mode (PH)
The preheat mode is defined as the state the IC
is in when the lamp filaments are being heated to
their correct emission temperature. This is
necessary for maximizing lamp life and reducing
the required ignition voltage. The IR2166 enters
preheat mode when VCC exceeds the UVLO
positive-going threshold. HO and LO begin to
19
IR2166 & (PbF)
oscillate at the preheat frequency with 50% duty
cycle and with a dead-time which is set by the
value of the external timing capacitor, CT, and
internal deadtime resistor, RDT. Pin CPH is
disconnected from COM and an internal 3µA
current source (Figure 3)
V BUS (+)
RT
S4
RPH
HalfBridge
Driver
4
R PH
CT
16
OSC.
3
RT
15
HO
M1
VS
HalfBridge
Output
ILOAD
5
CT
11
LO
M2
3uA
CPH
2
RCS
C CPH
12
IR2166
COM
Load
Return
V BUS (-)
VCC is the dead-time (both off) of the output
gate drivers, HO and LO. The selected value of
CT together with RDT therefore program the
desired dead-time (see Design Equations, page
26, Equations 1 and 2). Once CT discharges
below 1/3 VCC, MOSFET S3 is turned off,
disconnecting RDT from COM, and MOSFET
S1 is turned on, connecting RT and RPH again
to VCC. The frequency remains at the preheat
frequency until the voltage on pin CPH exceeds
10V and the IC enters Ignition Mode. During the
preheat mode, the over-current protection
together with the fault counter are enabled. The
peak ignition current must not exceed the
maximum allowable current ratings of the output
stage MOSFETs. Should this voltage exceed the
internal threshold of 1.3V, the internal FAULT
Counter begins counting the sequential overcurrent faults (See Timing Diagram). If the
number of over-current faults exceed 25, the IC
will enter FAULT mode and gate driver outputs
HO, LO and PFC will be latched low.
Figure 3, Preheat circuitry.
charges the external preheat timing capacitor
on CPH linearly. The over-current protection on
pin CS is disabled during preheat. The preheat
frequency is determined by the parallel
combination of resistors RT and RPH, together
with timing capacitor CT. CT charges and
discharges between 1/3 and 3/5 of VCC (see
Timing Diagram, page 9). CT is charged
exponentially through the parallel combination
of RT and RPH connected internally to VCC
through MOSFET S1. The charge time of CT
from 1/3 to 3/5 VCC is the on-time of the
respective output gate driver, HO or LO. Once
CT exceeds 3/5 VCC, MOSFET S1 is turned
off, disconnecting RT and RPH from VCC. CT is
then discharged exponentially through an
internal resistor, RDT, through MOSFET S3 to
COM. The discharge time of CT from 3/5 to 1/3
20
V BUS (+)
VCC
13
S1
RT
RT
HO
M1
HalfBridge
Output
S4
RPH
4
R PH
CT
16
OSC
3
Fault
Logic
5
CT
HalfBridge
Driver
15
VS
I LOAD
11
LO
M2
S3
CS
1.3V
10
3uA
CPH
R1
Comp 4
CCS
2
CCPH
12
IR2166
RCS
COM
Load
Return
V BUS (-)
Figure 4, Ignition circuitry.
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IR2166 & (PbF)
Ignition Mode (IGN)
The ignition mode is defined as the state the IC
is in when a high voltage is being established
across the lamp necessary for igniting the lamp.
The IR2166 enters ignition mode when the
voltage on pin CPH exceeds 10V.
Pin CPH is connected internally to the gate of a
P-channel MOSFET (S4) (see Figure 4) that
connects pin RPH with pin RT. As pin CPH
exceeds 10V, the gate-to-source voltage of
MOSFET S4 begins to fall below the turn-on
threshold of S4. As pin CPH continues to ramp
towards VCC, switch S4 turns off slowly. This
results in resistor RPH being disconnected
smoothly from resistor RT, which causes the
operating frequency to ramp smoothly from the
preheat frequency, through the ignition frequency,
to the final run frequency. The over-current
threshold on pin CS will protect the ballast
against a non-strike or open-filament lamp fault
condition. The voltage on pin CS is defined by
the lower half-bridge MOSFET current flowing
through the external current sensing resistor
RCS. The resistor RCS therefore programs the
maximum allowable peak ignition current (and
therefore peak ignition voltage) of the ballast
output stage. If the number of over current pulses
exceed 25, the IC will enter fault mode and gate
driver outputs HO, LO and PFC will be latched
low.
Run Mode (RUN)
Once the lamp has successfully ignited, the
ballast enters run mode. The run mode is defined
as the state the IC is in when the lamp arc is
established and the lamp is being driven to a
given power level. The run mode oscillating
frequency is determined by the timing resistor
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RT and timing capacitor CT (see Design
Equations, page 26, Equations 3 and 4). Should
hard-switching occur at the half-bridge at any
time due to an open-filament or lamp removal,
the voltage across the current sensing resistor,
RCS, will exceed the internal threshold of 1.3 volts
and the IC will enter FAULT mode and gate driver
outputs HO, LO and PFC will be latched low.
DC Bus Under-voltage Reset
Should the DC bus decrease too low during a
brownout line condition or overload condition,
the resonant output stage to the lamp can shift
near or below resonance. This can produce
hard-switching at the half-bridge which can
damage the half-bridge switches or, the DC bus
can decrease too far and the lamp can
extinguish. To protect against this, the VBUS pin
includes a 3.0V under-voltage threshold. Should
the voltage at the VBUS pin decrease below 3.0V,
VCC will be discharged to the UVLO- threshold
and all gate driver outputs will be latched low.
For proper ballast design, the designer should
design the PFC section such that the DC bus
does not drop until the AC line input voltage falls
below the rated input voltage of the ballast (See
PFC section). When correctly designed, the
voltage measured at the VBUS pin will decrease
below the internal 3.0V threshold and the ballast
will turn off cleanly. The pull-up resistor to VCC
(RSUPPLY) will then turn the ballast on again
with the AC input line voltage increasing to the
minimum specified value causing VCC to exceed
UVLO+.
RSUPPLY should be set to turn the ballast on at
the minimum specified ballast input voltage. The
PFC should then be designed such that the DC
bus decreases at an input line voltage that is
21
IR2166 & (PbF)
lower than the minimum specified ballast input
voltage. This hysteresis will result in clean turnon and turnoff of the ballast.
CS and EOL Fault Mode (FAULT)
Should the voltage at the SD/EOL pin exceed 3V
or decrease below 1V during RUN mode, the IC
enters fault mode and all gate driver outputs, HO,
LO and PFC, are latched off in the 'low' state.
CPH is discharged to COM for resetting the
preheat time, and CT is discharged to COM for
disabling the oscillator. To exit fault mode, VCC
must be recycled back below the UVLO negativegoing turn-off threshold, or, the shutdown pin, SD,
must be pulled above 5.2 volts. Either of these
will force the IC to enter UVLO mode (see State
Diagram, page 7). Once VCC is above the turnon threshold and SD is below 5.0 volts, the IC
will begin oscillating again in the preheat mode.
The current sense function will force the IC to
enter FAULT mode only after the voltage at the
current sense pin has been pulsed about 25 times
with a voltage greater than 1.3 volts during preheat
and ignition modes only. These over-currents must
occur during the on-time of LO. During run mode,
a single pulse on the CS pin above 1.3V will force
the IC to enter FAULT mode.
25 Pulses
LO
II. PFC Section Functional Description
In most electronic ballasts it is necessary to
have the circuit act as a pure resistive load to
the AC input line voltage. The degree to which
the circuit matches a pure resistor is measured
by the phase shift between the input voltage
and input current and how well the shape of the
input current waveform matches the shape of
the sinusoidal input voltage. The cosine of the
phase angle between the input voltage and input
current is defined as the power factor (PF), and
how well the shape of the input current waveform
matches the shape of the input voltage is
determined by the total harmonic distortion
(THD). A power factor of 1.0 (maximum)
corresponds to zero phase shift and a THD of
0% represents a pure sinewave (no distortion).
For this reason it is desirable to have a high PF
and a low THD. To achieve this, the IR2166
includes an active power factor correction (PFC)
circuit which, for an AC line input voltage,
produces an AC line input current. The control
method implemented in the IR2166 is for a boosttype converter (Figure 6) running in criticalconduction mode (CCM). This means that during
each switching cycle of the PFC MOSFET, the
circuit waits until the inductor current discharges
to zero before turning the PFC MOSFET on again.
The PFC MOSFET is turned on and off at a
much higher frequency (>10KHz) than the line
input frequency (50 to 60Hz).
LPFC
(+)
CS
DPFC
DC Bus
2.0V
+
MPFC
Run Mode
Fault Mode
Figure 5: FAULT counter during preheat and ignition
22
CBUS
(-)
Figure 6: Boost-type PFC circuit
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IR2166 & (PbF)
When the switch MPFC is turned on, the inductor
LPFC is connected between the rectified line
input (+) and (-) causing the current in LPFC to
charge up linearly. When MPFC is turned off,
LPFC is connected between the rectified line
input (+) and the DC bus capacitor CBUS
(through diode DPFC) and the stored current in
LPFC flows into CBUS. As MPFC is turned on
and off at a high-frequency, the voltage on CBUS
charges up to a specified voltage. The feedback
loop of the IR2166 regulates this voltage to a
fixed value by continuously monitoring the DC
voltage and adjusting the on-time of MPFC
accordingly. For an increasing DC bus the ontime is decreased, and for a decreasing DC bus
the on-time is increased. This negative feedback
control is performed with a slow loop speed and
a low loop gain such that the average inductor
current smoothly follows the low-frequency line
input voltage for high power factor and low THD.
The on-time of MPFC therefore appears to be
fixed (with an additional modulation to be
discussed later) over several cycles of the line
voltage. With a fixed on-time, and an off-time
determined by the inductor current discharging
to zero, the result is a system where the
switching frequency is free-running and
constantly changing from a high frequency near
the zero crossing of the AC input line voltage,
to a lower frequency at the peaks (Figure 7).
www.irf.com
V, I
t
Figure 7: Sinusoidal line input voltage (solid line), triangular
PFC Inductor current and smoothed sinusoidal line input
current (dashed line) over one half-cycle of the line input
voltage.
When the line input voltage is low (near the zero
crossing), the inductor current will charge up to
a small amount and the discharge time will be
fast resulting in a high switching frequency.
When the input line voltage is high (near the
peak), the inductor current will charge up to a
higher amount and the discharge time will be
longer giving a lower switching frequency. The
triangular PFC inductor current is then smoothed
by the EMI filter to produce a sinusoidal line
input current.
The PFC control circuit of the IR2166 (Figure 8)
only requires four control pins: VBUS, COMP,
ZX and PFC. The VBUS pin is for sensing the
DC bus voltage (via an external resistor voltage
divider), the COMP pin programs the on-time of
MPFC and the speed of the feedback loop, the
ZX pin detects when the inductor current
discharges to zero (via a secondary winding
from the PFC inductor), and the PFC pin is the
low-side gate driver output for MPFC.
23
IR2166 & (PbF)
LPFC
(+)
Fault Mode Signal
Run Mode Signal
DFPC
VBUS 1
GAIN
4.0V
VCC
COMP4
OTA1
4.3V
M1
RZX
COMP
Discharge
VCC to
UVLO-
ZX
PFC
Control
CBUS
PFC
3.0V
C1
S
Q
R
Q
PFC
WATCH
DOG
TIMER
COMP2
VBUS
8
RS3
COMP5
COMP 6
RVBUS1
M2
RS4
S Q
R1
R2 Q
RPFC
MPFC
COMP3
ZX 7
7.6V
2.0V
COM
DCOMP CCOMP
RVBUS
Figure 9: IR2166 detailed PFC control circuit
(-)
Figure 8:IR2166 simplified PFC control circuit
The VBUS pin is regulated against a fixed
internal 4V reference voltage for regulating the
DC bus voltage (Figure 9). The feedback loop
is performed by an operational transconductance
amplifier (OTA) that sinks or sources a current
to the external capacitor at the COMP pin. The
resulting voltage on the COMP pin sets the
threshold for the charging of the internal timing
capacitor (C1) and therefore programs the ontime of MPFC. During preheat and ignition
modes of the ballast section, the gain of the
OTA is set to a high level to raise the DC bus
level quickly. When the voltage on the VBUS pin
exceeds 3V, the gain is set to a low level to
reduce overshoot. When the voltage on the VBUS
pin exceeds 4V, the gain is set to a high level
again to minimize the transient on the DC bus
which can occur during ignition. During run
mode, the gain is then decreased to a lower
level necessary for achieving high power factor
and low THD.
24
The off-time of MPFC is determined by the time
it takes the LPFC current to discharge to zero.
This zero current level is detected by a
secondary winding on LPFC which is connected
to the ZX pin. A positive-going edge exceeding
the internal 2V threshold signals the beginning
of the off-time. A negative-going edge on the
ZX pin falling below 1.7V will occur when the
LPFC current discharges to zero which signals
the end of the off-time and MPFC is turned on
again (Figure 10). The cycle repeats itself
indefinitely until the PFC section is disabled due
to a fault detected by the ballast section (Fault
Mode), an over-voltage or under-voltage
condition on the DC bus, or, the negative
transition of ZX pin voltage does not occur.
Should the negative edge on the ZX pin not occur,
MPFC will remain off until the watch-dog timer
forces a turn-on of MPFC for an on-time duration
programmed by the voltage on the COMP pin.
The watch-dog pulses occur every 400µs
indefinitely until a correct positive- and negativegoing signal is detected on the ZX pin and normal
PFC operation is resumed.
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IR2166 & (PbF)
ILPFC
0
modulation circuit has been added to the PFC
control. This circuit dynamically increases the
on-time of MPFC as the line input voltage nears
the zero-crossings (Figure 11). This causes the
peak LPFC current, and therefore the smoothed
line input current, to increase slightly higher near
the zero-crossings of the line input voltage. This
reduces the amount of cross-over distortion in
the line input current which reduces the THD
and higher harmonics to low levels.
PFC
pin
0
ILPFC
0
ZX
pin
PFC
pin
0
0
near peak region of
rectified AC line
Figure 10: LPFC current, PFC pin and ZX pin timing
diagram.
near zero-crossing region
of rectified AC line
Figure 11: On-time modulation near the zero-crossings.
On-time Modulation
Over-voltage Protection (OVP)
A fixed on-time of MPFC over an entire cycle of
the line input voltage produces a peak inductor
current which naturally follows the sinusoidal
shape of the line input voltage. The smoothed
averaged line input current is in phase with the
line input voltage for high power factor but the
total harmonic distortion (THD), as well as the
individual higher harmonics, of the current can
still be too high. This is mostly due to crossover distortion of the line current near the zerocrossings of the line input voltage. To achieve
low harmonics which are acceptable to
international standard organizations and general
market requirements, an additional on-time
Should over-voltage occur on the DC bus
causing the VBUS pin to exceed the internal 4.3V
threshold, the PFC output is disabled (set to a
logic 'low'). When the DC bus decreases again
causing the VBUS pin to decrease below the
internal 4V threshold, a watch-dog pulse is forced
on the PFC pin and normal PFC operation is
resumed.
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Under-voltage Reset (UVR)
When the line input voltage is decreased,
interrupted or a brown-out condition occurs, the
PFC feedback loop causes the on-time of MPFC
25
IR2166 & (PbF)
to increase in order to keep the DC bus constant.
Should the on-time increase too far, the resulting
peak currents in LPFC can exceed the saturation
current limit of LPFC. LPFC will then saturate
and very high peak currents and di/dt levels will
occur. To prevent this, the maximum on-time is
limited by limiting the maximum voltage on the
COMP pin with an external zener diode DCOMP
(Figure 8). As the line input voltage decreases,
the COMP pin voltage and therefore the on-time
will eventually limit. The PFC can no longer
supply enough current to keep the DC bus fixed
for the given load power and the DC bus will
begin to drop. Decreasing the line input voltage
further will cause the VBUS pin to eventually
decrease below the internal 3V threshold (Figure
9). When this occurs, VCC is discharged
internally to UVLO-, the IR2166 enters UVLO
mode and both the PFC and ballast sections
are disabled (see State Diagram). The start-up
supply resistor to VCC, together with the micropower start-up current of the IR2166, determine
the line input turn-on voltage. This should be
set such that the ballast turns on at a line voltage
level above the under-voltage turn-off level. It
is the correct selection of the value of the supply
resistor to VCC and the zener diode on the
COMP pin that correctly program the on and off
line input voltage thresholds for the ballast. With
these thresholds correctly set, the ballast will
turn off due to the 3V under-voltage threshold
on the VBUS pin, and on again at a higher line
input voltage (hysterisis) due to the supply
resistor to VCC. This hysterisis will result in a
proper reset of the ballast without flickering of
the lamp, bouncing of the DC bus or re-ignition
of the lamp when the DC bus is too low.
PFC Over-Current Protection (optional)
In case of fast on/off interruptions of the mains input
voltage or during normal lamp ignition, the DC bus
voltage level can decrease below the instantaneous
rectified line voltage. Should this occur, the PFC
inductor current and PFC MOSFET current can
increase to high levels causing the PFC inductor to
saturate and/or the PFC MOSFET to become
damaged. During fast on/off interruptions of the input
mains voltage, the DC bus can drop during the time
when the mains voltage is interrupted (off). Since
VCC is still above UVLO-, the IC will continue to
operate and will increase the COMP pin voltage to
increase the PFC MOSFET on-time due to the
dropping of the DC bus. When the mains voltage
returns again quickly, (before VCC reaches UVLO), the on-time of the PFC MOSFET is too long for
the given mains voltage level resulting in high PFC
inductor and MOSFET currents that can saturate
the inductor and/or damage the PFC MOSFET
(Figure 12).
Figure 12, High PFC inductor current during fast mains
on/off (upper trace: DC Bus, 100V/div; middle trace:
AC line input voltage, 100V/div; lower trace: PFC
inductor current 1A/div).
26
www.irf.com
IR2166 & (PbF)
During lamp ignition, the DC bus can drop below
the rectified AC line voltage causing current to
conduct directly from the output of the rectifier,
through the PFC inductor and diode, to the DC
bus capacitor. This results in a low-frequency offset
of current in the PFC inductor. Since the zerocrossing detection circuit only detects the highfrequency zero-crossing of the inductor current,
the PFC MOSFET will turn on again each cycle
before the inductor current has reached zero. This
causes the PFC to work in a continuous conduction
mode and the sum of the low-frequency and highfrequency components of current can saturate the
PFC inductor and/or damage the PFC MOSFET.
restart the PFC as normal (Figure 14). The current
sensing resistor value should be selected such
that the over-current protection does not false trip
during normal operation over the entire line voltage
range and load range. A current-sensing resistor
value, for example, of 1.0 W will set the overcurrent protection threshold to about 5 A peak.
To protect against these conditions, a current
sense resistor (RS) can be inserted between the
source on the PFC MOSFET and ground, and a
diode (D4) connected from the top of this currentsensing resistor to the VBUS pin (Figure 13).
Rectified
AC line
HO
VBUS
1
16
2
15
VS
CPH
RT
VB
3
4
D4
CT
5
1N4148
RS
1Ω
14
IR2166
RPH
VCC
13
COM
12
Device
Ground
LO
COMP
7
6
11
7
10
8
9
CS
ZX
SD/EOL
PFC
High
Current
Ground
13, External over-current protection circuit
Should high currents occur, the voltage across
the current-sensing resistor (RS) will exceed the
4.3V over-voltage protection threshold at the VBUS
pin and the PFC MOSFET will turn off safely
limiting the current. The watch-dog timer will then
www.irf.com
Figure 14, PFC inductor current limited using overcurrent protection circuit (upper trace: DC Bus,
100V/div; middle trace: AC line input voltage, 100V/
div; lower trace: PFC inductor current 1A/div).
The effect that these line and load conditions have
on the performance of the ballast depends on the
saturation level of the PFC inductor, the selection
of the PFC MOSFET, the DC bus capacitor value,
the maximum on-time limit set by DZCOMP, and,
how fast VCC decreases below UVLO- when the
DC bus drops during ignition (the 3V reset on the
VBUS pin does not become active until RUN mode).
For these reasons, the ballast designer should
perform these mains interrupt and ignition tests
carefully to determine the robustness of their final
design and to decide if this additional over-current
protection circuit is necessary.
27
IR2166 & (PbF)
Ballast Design Equations
Step 3: Program Preheat Frequency
Note: The results from the following design
equations can differ slightly from experimental
measurements due to IC tolerances, component
tolerances, and oscillator over- and undershoot
due to internal comparator response time.
The preheat frequency is programmed with
timing resistors RT and RPH, and timing
capacitor CT. The timing resistors are
connected in parallel internally for the duration
of the preheat time. The preheat frequency is
therefore given as:
Step 1: Program Dead-time
The dead-time between the gate driver outputs
HO and LO is programmed with timing capacitor
CT and an internal dead-time resistor RDT. The
dead-time is the discharge time of capacitor CT
from 3/5VCC to 1/3VCC and is given as:
t DT = CT ⋅1475 [Seconds]
f PH =
or
(1)
R PH
or
CT =
t DT
1475
[Farads]
1
 0.51 ⋅ RT ⋅ R PH

2 ⋅ CT ⋅ 
+ 1475 [Hertz] (5)
R
R
+
T
PH




1

− 2892  ⋅ RT
 1.02 ⋅ C T ⋅ f PH

=


1
RT − 
− 2892 
C
f
⋅
⋅
1
.
02
T
PH


[Ohms] (6)
(2)
Step 4: Program Preheat Time
Step 2: Program Run Frequency
The final run frequency is programmed with
timing resistor RT and timing capacitor CT. The
charge time of capacitor CT from 1/3VCC to
3/5VCC determines the on-time of HO and LO
gate driver outputs. The run frequency is
therefore given as:
f RUN
The preheat time is defined by the time it takes
for the capacitor on pin CPH to charge up to
10 volts. An internal current source of 3uA flows
out of pin CPH. The preheat time is therefore
given as:
t PH = CPH ⋅ 3.33e6
[Seconds] (7)
or
1
=
2 ⋅ C T (0.51 ⋅ RT + 1475)
[Hertz] (3)
1
− 2892
1.02 ⋅ C T ⋅ f RUN
[Ohms] (4)
C PH = t PH ⋅ 0 . 3 e − 6
[Farads] (8)
or
RT =
28
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IR2166 & (PbF)
Step 5: Program Maximum Ignition Current
The maximum ignition current is programmed
with the external resistor RCS and an internal
threshold of 1.3 volts. This threshold determines
the over-current limit of the ballast, which can
be exceeded when the frequency ramps down
towards resonance during ignition and the lamp
does not ignite. The maximum ignition current
is given as:
I IGN =
1 .3
RCS
[Amps Peak] (9)
RCS =
1. 3
I IGN
[Ohms] (10)
or
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29
IR2166 & (PbF)
P F C D e s ig n E q u a tio n s
S te p 1 : C a lc u la te P F C in d u c to r v a lu e :
L PFC =
(VBUS − 2 ⋅ VAC MIN ) ⋅ VAC
2 ⋅ f MIN ⋅ POUT ⋅ VBUS
2
MIN
⋅η
[H e n rie s] (1 )
w h e re ,
f MIN
=
=
=
=
POUT
=
VBUS
VAC MIN
η
D C b u s v o lta g e
M in im u m rm s A C in p u t v o lta g e
P F C e ffic ie n c y (ty p ic a lly 0 .9 5 )
M in im u m P F C s w itc h in g fre q u e n c y a t m in im u m A C in p u t v o lta g e
B a lla s t o u tp u t p o w e r
S te p 2 : C a lc u la te p e a k P F C in d u c to r c u rre n t:
i PK =
2 ⋅ 2 ⋅ POUT
VAC MIN ⋅ η
[A m p s P e a k ]
N o te : T h e P F C in d u c to r m u s t n o t s a tu ra te a t
i PK
(2 )
o v e r th e s p e c ifie d b a lla s t o p e ra tin g te m p e ra tu re ra n g e .
P ro p e r c o re s iz in g a n d a ir-g a p p in g s h o u ld b e c o n s id e re d in th e in d u c to r d e s ig n .
S te p 3 : C a lc u la te m a x im u m o n -tim e :
t ON MAX =
2 ⋅ POUT ⋅ L PFC
2
VAC MIN
⋅η
[S e c o n d s]
(3 )
[V o lts]
(4 )
S te p 4 : C a lc u la te m a x im u m C O M P v o lta g e :
V COMP
MAX
=
t ON MAX
0 .9 E − 6
S te p 5 : S e le c t z e n e r d io d e D C O M P v a lu e :
D COMP z e n e r v o lta g e ≈ V COMP
MAX
[V o lts] (5 )
S te p 6 : C a lc u la te re s is to r R S U P P L Y v a lu e :
R SUPPLY
30
=
VAC
MIN
PK
IQCCUV
+ 10
[O h m s] (6 )
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IR2166 & (PbF)
Case outline
16 Lead PDIP
16 Lead SOIC (narrow body)
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01-6015
01-3065 00 (MS-001A)
01-6018
01-3064 00 (MS-012AC)
31
IR2166 & (PbF)
LEADFREE PART MARKING INFORMATION
Part number
Date code
IRxxxxxx
YWW?
Pin 1
Identifier
?
P
MARKING CODE
Lead Free Released
Non-Lead Free
Released
IR logo
?XXXX
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
ORDER INFORMATION
Basic Part (Non-Lead Free)
16-Lead PDIP IR2166 order IR2166
16-Lead SOIC IR2166S order IR2166S
Leadfree Part
16-Lead PDIP IR2166 order IR2166PbF
16-Lead SOIC IR2166S not yet available
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 1/12/2005
32
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