H CAT24WC128 EE GEN FR ALO 128K-Bit I2C Serial CMOS EEPROM LE FEATURES ■ 1MHz I2C Bus Compatible* A D F R E ETM ■ Write Protect Feature – Entire Array Protected When WP at VIH ■ 1.8 to 6 Volt Operation ■ Low Power CMOS Technology ■ 100,000 Program/Erase Cycles ■ 64-Byte Page Write Buffer ■ 100 Year Data Retention ■ Self-Timed Write Cycle with Auto-Clear ■ 8-Pin DIP, 8-Pin SOIC or 14-pin TSSOP ■ Commercial, Industrial and Automotive ■ "Green" Package Options Available Temperature Ranges DESCRIPTION The CAT24WC128 is a 128K-bit Serial CMOS E2PROM internally organized as 16384 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The CAT24WC128 features a 64-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP, 8-pin SOIC or 14-pin TSSOP packages. BLOCK DIAGRAM PIN CONFIGURATION DIP Package (P, L) NC NC NC VSS 1 2 3 4 8 7 6 5 VCC WP TSSOP Package (U14, Y14) SCL VCC 1 14 NC SDA NC WP 13 2 NC NC 12 3 NC SOIC Package (J, W, K, X) NC 1 8 VCC NC 2 3 4 7 6 5 WP SCL SDA NC VSS NC NC VSS 4 5 6 7 11 10 9 NC NC SCL 8 SDA EXTERNAL LOAD SENSE AMPS SHIFT REGISTERS DOUT ACK VCC WORD ADDRESS BUFFERS VSS COLUMN DECODERS 512 START/STOP LOGIC SDA XDEC 256 EEPROM 256X512 CONTROL LOGIC WP PIN FUNCTIONS Pin Name Function SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC +1.8V to +6V Power Supply VSS Ground DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL STATE COUNTERS SCL * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1038, Rev. E CAT24WC128 ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (Ta = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND TDR Parameter (3) Units Reference Test Method 100,000 Cycles/Byte MIL-STD-883, Test Method 1033 Data Retention 100 Years MIL-STD-883, Test Method 1008 ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 Latch-up 100 mA Endurance (3) VZAP Min. (3) ILTH(3)(4) Max. JEDEC Standard 17 D.C. OPERATING CHARACTERISTICS VCC = +1.8V to +6.0V, unless otherwise specified. Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 Power Supply Current - Read 1 mA fSCL = 100 KHz VCC=5V ICC2 Power Supply Current - Write 3 mA fSCL = 100 KHz VCC=5V ISB(5) Standby Current 1 µA VIN = GND or VCC VCC=5V ILI Input Leakage Current 3 µA VIN = GND to VCC ILO Output Leakage Current 3 µA VOUT = GND to VCC VIL Input Low Voltage –1 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low Voltage (VCC = +3.0V) 0.4 V IOL = 3.0 mA VOL2 Output Low Voltage (VCC = +1.8V) 0.5 V IOL = 1.5 mA CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V Symbol Test Max. Units Conditions CI/O(3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V CIN(3) Input Capacitance (SCL, WP) 6 pF VIN = 0V Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. (5) Maximum standby current (ISB ) = 10µA for the Automotive and Extended Automotive temperature range. Doc. No. 1038, Rev. E 2 CAT24WC128 A.C. CHARACTERISTICS VCC = +1.8V to +6V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V Min. Max. Min. 100 Max. Min. Units 1000 kHz 0.55 µs FSCL Clock Frequency tAA SCL Low to SDA Data Out and ACK Out 0.1 tBUF(1) Time the Bus Must be Free Before a New Transmission Can Start 4.7 1.2 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tLOW Clock Low Period 4.7 1.2 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.0 0.6 0.25 µs tHD:DAT Data In Hold Time 0 0 0 ns tSU:DAT Data In Setup Time 100 100 100 ns tR(1) SDA and SCL Rise Time 1.0 0.3 0.3 µs tF(1) SDA and SCL Fall Time 300 300 100 ns tSU:STO Stop Condition Setup Time 4.7 0.6 0.25 µs tDH Data Out Hold Time 100 50 50 ns tWR Write Cycle Time 3.5 10 400 Max. 0.05 0.9 0.05 10 10 ms Power-Up Timing (1)(2) Symbol Parameter Max. Units tPUR Power-Up to Read Operation 1 ms tPUW Power-Up to Write Operation 1 ms Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. FUNCTIONAL DESCRIPTION The CAT24WC128 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC128 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. 3 Doc. No. 1038, Rev. E CAT24WC128 PIN DESCRIPTIONS I2C BUS PROTOCOL SCL: Serial Clock The serial clock input clocks all data transferred into or out of the device. The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. SDA: Serial Data/Address The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. WP: Write Protect This input, when tied to GND, allows write operations to the entire memory. When this pin is tied to Vcc, the entire memory is write protected. When left floating, memory is unprotected. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24WC128 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Figure 1. Bus Timing tF tHIGH tLOW tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 2. Write Cycle Timing SCL SDA 8TH BIT BYTE n ACK tWR STOP CONDITION START CONDITION Figure 3. Start/Stop Timing SDA SCL START BIT Doc. No. 1038, Rev. E STOP BIT 4 ADDRESS CAT24WC128 DEVICE ADDRESSING knowledge, the CAT24WC128 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The seven most significant bits of the 8-bit slave address are fixed as 1010XXX (Fig. 5), where X can be a 0 or 1. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24WC128. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24WC128 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. After the Master sends a START condition and the slave address byte, the CAT24WC128 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24WC128 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. Page Write The CAT24WC128 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. The CAT24WC128 writes up to 64 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 63 additional bytes. After each byte has been transmitted, CAT24WC128 will respond with an When the CAT24WC128 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acFigure 4. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 5. Slave Address Bits 1 0 1 0 A2 X A1 X A0 X R/W X is Don't Care, can be a '0' or a '1'. 5 Doc. No. 1038, Rev. E CAT24WC128 protected and becomes read only. The CAT24WC128 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. acknowledge, and internally increment the six low order address bits by one. The high order bits remain unchanged. If the Master transmits more than 64 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. READ OPERATIONS When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24WC128 in a single write cycle. The READ operation for the CAT24WC128 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24WC128 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24WC128 is still busy with the write operation, no ACK will be returned. If CAT24WC128 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Immediate/Current Address Read The CAT24WC128’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E=16383), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24WC128 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. WRITE PROTECTION Selective/Random Read The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the entire memory array is Selective/Random READ operations allow the Master device to select at random any memory location for a Figure 6. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S S T O P DATA P ** A C K A C K A C K A C K *=Don't Care Bit Figure 7. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15–A8 A7–A0 S DATA DATA n+63 P ** A C K A C K A C K *=Don't Care Bit Doc. No. 1038, Rev. E DATA n S T O P 6 A C K A C K A C K A C K CAT24WC128 READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After CAT24WC128 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24WC128 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. data. The CAT24WC128 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from CAT24WC128 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24WC128 address bits so that the entire memory array can be read during one operation. If more than E (where E=16383) bytes are read out, the counter will ‘wrap around’ and continue to clock out data bytes. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24WC128 sends the initial 8bit byte requested, the Master will respond with an acknowledge which tells the device it requires more Figure 8. Immediate Address Read Timing S T A R T BUS ACTIVITY: MASTER SDA LINE SLAVE ADDRESS S T O P DATA S P N O A C K A C K 8 SCL SDA 9 8TH BIT DATA OUT NO ACK STOP 24WC128 F10 Figure 9. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS A15–A8 A7–A0 ** S A C K SLAVE ADDRESS S T O P DATA S A C K A C K P A C K N O A C K *=Don't Care Bit 7 Doc. No. 1038, Rev. E CAT24WC128 Figure 10. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K ORDERING INFORMATION Prefix Device # CAT 24WC128 Optional Company ID Product Number Suffix K -1.8 I Temperature Range Blank = Commercial (0° - 70°C) I = Industrial (-40° - 85°C) A = Automotive (-40° - 105°C)* Rev A(2) TE13 Tape & Reel Die Revision Package P: PDIP K: SOIC (EIAJ) J: SOIC (JEDEC) U14: 14 pin TSSOP L: PDIP (Lead free, Halogen free) X: SOIC (EIAJ, Lead free, Halogen free) W: SOIC (JEDEC, Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Operating Voltage Blank: 2.5V - 6.0V 1.8: 1.8V - 6.0V * -40° to +125°C is available upon request Notes: (1) The device used in the above example is a 24WC128KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWA). For additional information, please contact your Catalyst sales office. Doc. No. 1038, Rev. E 8 REVISION HISTORY Date 04/18/04 Revision Comments B Delete data sheet designation Update Features Update Pin Configuration Update Ordering Information 07/23/04 C Add die revision to Ordering Information 08/05/04 D Update DC Operating Characteristics & notes 03/11/05 E Update Ordering Information Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1038 E 03/11/05