Honeywell HLX6256KSH 32k x 8 static ram low power soi Datasheet

Military & Space Products
32K x 8 STATIC RAM—Low Power SOI
HLX6256
FEATURES
RADIATION
OTHER
• Fabricated with RICMOS™ IV Silicon on Insulator (SOI)
0.55 µm Low Power Process
• Read/Write Cycle Times
≤ 17 ns (Typical)
≤ 25 ns (-55 to 125°C)
• Total Dose Hardness through 1x106 rad(SiO2)
• Typical Operating Power <10 mW/MHz
• Neutron Hardness through 1x1014 cm-2
• Asynchronous Operation
• Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
• JEDEC Standard Low Voltage
CMOS Compatible I/O
• Dose Rate Survivability through 1x1011 rad(Si)/s
• Single 3.3 V ± 0.3V Power Supply
• Soft Error Rate of <1x10-10 upsets/bit-day
• Latchup Free
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 word x 8-bit static random access
memory with industry-standard functionality. It is fabricated with Honeywell’s radiation hardened technology,
and is designed for use in low voltage systems operating in
radiation environments. The RAM operates over the full
military temperature range and requires only a single 3.3 V
± 0.3V power supply. The RAM is compatible with JEDEC
standard low voltage CMOS I/O. Power consumption is
typically less than 10 mW/MHz in operation, and less than
2 mW when de-selected. The RAM read operation is fully
asynchronous, with an associated typical access time of 14
ns at 3.3 V.
Honeywell’s enhanced SOI RICMOS™ IV (Radiation Insensitive CMOS) technology is radiation hardened through the
use of advanced and proprietary design, layout and process hardening techniques. The RICMOS™ IV low power
process is a SIMOX CMOS technology with a 150 Å gate
oxide and a minimum drawn feature size of 0.7 µm (0.55 µm
effective gate length—Leff). Additional features include
tungsten via plugs, Honeywell’s proprietary SHARP planarization process and a lightly doped drain (LDD) structure for improved short channel reliability. A 7 transistor
(7T) memory cell is used for superior single event upset
hardening, while three layer metal power bussing and the
low collection volume SIMOX substrate provide improved
dose rate hardening.
• Packaging Options
- 28-Lead Flat Pack (0.500 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- Various Multi-Chip Module (MCM) Configurations
HLX6256
FUNCTIONAL DIAGRAM
A:0-8,12-13
32,768 x 8
Memory
Array
•
•
•
Row
Decoder
11
CE
NCS
•
•
•
8
Column Decoder
Data Input/Output
NWE
WE • CS • CE
NOE
NWE • CS • CE • OE
(0 = high Z)
A:9-11, 14
8
Signal
DQ:0-7
1 = enabled
#
Signal
All controls must be
enabled for a signal to
pass. (#: number of
buffers, default = 1)
4
SIGNAL DEFINITIONS
A: 0-14
Address input pins which select a particular eight-bit word within the memory array.
DQ: 0-7
Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write
operation.
NCS
Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS
forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and
disables all input buffers except CE. If this signal is not used it must be connected to VSS.
NWE
Negative write enable, when at a low level activates a write operation and holds the data output drivers in a
high impedance state. When at a high level NWE allows normal read operation.
NOE
Negative output enable, when at a high level holds the data output drivers in a high impedance state. When
at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must
be connected to VSS.
CE*
Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a
precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers
except the NCS input buffer. If this signal is not used it must be connected to VDD.
TRUTH TABLE
NCS
CE*
NWE
NOE
MODE
DQ
L
H
H
L
Read
Data Out
L
H
L
X
Write
Data In
H
X
XX
XX
Deselected
High Z
X
L
XX
XX
Disabled
High Z
*Not Available in 28-Lead DIP or 28-Lead Flat Pack
2
Notes:
X: VI=VIH or VIL
XX: VSS≤VI≤VDD
NOE=H: High Z output state maintained for
NCS=X, CE=X, NWE=X
HLX6256
RADIATION CHARACTERISTICS
Total Ionizing Radiation Dose
The SRAM will meet any functional or electrical specification after exposure to a radiation pulse of up to the transient
dose rate survivability specification, when applied under
recommended operating conditions. Note that the current
conducted during the pulse by the RAM inputs, outputs and
power supply may significantly exceed the normal operating levels. The application design must accommodate
these effects.
The SRAM will meet all stated functional and electrical
specifications over the entire operating temperature range
after the specified total ionizing radiation dose. All electrical
and timing performance parameters will remain within
specifications after rebound at VDD = 3.6 V and T =125°C
extrapolated to ten years of operation. Total dose hardness
is assured by wafer level testing of process monitor transistors and RAM product using 10 keV X-ray and Co60
radiation sources. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a
dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma
rays (Cobalt 60 source) to ensure that wafer level X-ray
testing is consistent with standard military radiation test
environments.
Neutron Radiation
The SRAM will meet any functional or timing specification
after exposure to the specified neutron fluence under
recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV.
Transient Pulse Ionizing Radiation
Soft Error Rate
The SRAM is capable of writing, reading, and retaining
stored data during and after exposure to a transient
ionizing radiation pulse up to the transient dose rate upset
specification, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation
(timing degradation during transient pulse radiation (timing degradation during transient pulse radiation is ≤10%),
it is suggested that stiffening capacitance be placed on or
near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through
or valid stored data requirements, typical circuit board
mounted de-coupling capacitors are recommended.
The SRAM is immune to single event upsets (SEU’s) to the
specified soft error rate (SER), under recommended operating conditions. This hardness level is defined by the
Adams 10% worst case cosmic ray environment for geosynchronous orbits.
Latchup
The SRAM will not latch up due to any of the above
radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SIMOX
substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any
potential SCR latchup structures. Sufficient transistor
body tie connections to the p- and n-channel substrates
are made to ensure no source/drain snapback occurs.
RADIATION HARDNESS RATINGS (1)
Parameter
Units
Limits (2)
Total Dose
≥1x106
rad(SiO2)
Transient Dose Rate Upset (3)
≥1x109
rad(Si)/s
Transient Dose Rate Survivability (3)
≥1x1011
rad(Si)/s
-10
Soft Error Rate (SER)
<1x10
Neutron Fluence
≥1x1014
upsets/bit-day
N/cm2
(1) Device will not latch up due to any of the specified radiation exposure conditions.
(2) Operating conditions (unless otherwise specified): VDD=3.0 V to 3.6 V, TA=-55°C to 125°C.
(3) Not guaranteed with 28–Lead DIP.
3
Test Conditions
TA=25°C
Pulse width ≤1 µs
Pulse width ≤50 ns, X-ray,
VDD=4.0 V, TA=25°C
TA=125°C, Adams 10%
worst case environment
1 MeV equivalent energy,
Unbiased, TA=25°C
HLX6256
ABSOLUTE MAXIMUM RATINGS (1)
Rating
Symbol
Parameter
Min
Max
Units
VDD
Positive Supply Voltage (2)
-0.5
6.5
V
VPIN
Voltage on Any Pin (2)
-0.5
VDD+0.5
V
TSTORE
Storage Temperature (Zero Bias)
-65
150
°C
TSOLDER
Soldering Temperature • Time
270•5
°C•s
PD
Total Package Power Dissipation (3)
2.0
W
IOUT
DC or Average Output Current
2.0
mA
VPROT
ESD Input Protection Voltage (4)
ΘJC
Thermal Resistance (Jct-to-Case)
TJ
Junction Temperature
2000
V
28 FP/36 FP
2
28 DIP
10
°C/W
°C
175
(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not
implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.
(2) Voltage referenced to VSS.
(3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification.
(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.
RECOMMENDED OPERATING CONDITIONS
Description
Parameter
Symbol
Min
Typ
Max
Units
VDD
Supply Voltage (referenced to VSS)
3.0
3.3
3.6
V
TA
Ambient Temperature
-55
25
125
°C
VPIN
Voltage on Any Pin (referenced to VSS)
-0.3
VDD+0.3
V
CAPACITANCE (1)
Symbol
Parameter
Typical
(1)
Worst Case
Min
Max
Units
Test Conditions
CI
Input Capacitance
7
pF
VI=VDD or VSS, f=1 MHz
CO
Output Capacitance
9
pF
VIO=VDD or VSS, f=1 MHz
(1) This parameter is tested during initial design characterization only.
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
VDR
Data Retention Voltage
IDR
Data Retention Current
Typical
(1)
Worst Case (2)
Units
Min
1.65
300
(1) Typical operating conditions: TA= 25°C, pre-radiation.
(2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C.
4
Test Conditions
Max
V
NCS=VDR
VI=VDR or VSS
µA
NCS=VDD=VDR
VI=VDR or VSS
HLX6256
DC ELECTRICAL CHARACTERISTICS
Symbol
Typical Worst Case (2)
Units
(1)
Min
Max
Parameter
Test Conditions
1.0
mA
IDDSBMF Standby Supply Current - Deselected
1.0
mA
IDDOPW
Dynamic Supply Current, Selected (Write)
3.0
mA
IDDOPR
Dynamic Supply Current, Selected (Read)
3.0
mA
VIH=VDD IO=0
VIL=VSS Inputs Stable
NCS=VDD, IO=0,
f=40 MHz
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS
II
Input Leakage Current
-1
+1
µA
VSS≤VI≤VDD
IOZ
Output Leakage Current
-1
+1
µA
VSS≤VIO≤VDD
Output=high Z
VIL
Low-Level Input Voltage
-0.3
VIH
High-Level Input Voltage
VOL
Low-Level Output Voltage
VOH
High-Level Output Voltage
IDDSB1
Static Supply Current
0.3xVDD
0.7xVDD VDD+.3
0.4
2.7
V
V
March Pattern
VDD = 3.0V
V
V
March Pattern
VDD = 3.6V
V
VDD = 3.0V, IOL = 8 mA
V
VDD = 3.0V, IOH = -4 mA
(1) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=3.0 V to 3.6 V, TA=-55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
2.2 V
+
-
Vref1
Valid high
output
249Ω
DUT
output
Vref2
+
-
Valid low
output
CL >50 pF*
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
5
HLX6256
READ CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
Typical
(2)
-55 to 125°C
Min
Units
Max
TAVAVR
Address Read Cycle Time
25
ns
TAVQV
Address Access Time
TAXQX
Address Change to Output Invalid Time
TSLQV
Chip Select Access Time
TSLQX
Chip Select Output Enable Time
TSHQZ
Chip Select Output Disable Time
14
ns
TEHQV
Chip Enable Access Time (4)
25
ns
TEHQX
Chip Enable Output Enable Time (4)
TELQZ
Chip Enable Output Disable Time (4)
TGLQV
Output Enable Access Time
TGLQX
Output Enable Output Enable Time
TGHQZ
Output Enable Output Disable Time
25
3
ns
ns
25
5
ns
ns
5
ns
14
ns
9
ns
0
ns
12.6
ns
(1) Test conditions: input switching levels,VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the
Tester AC Timing Characteristics table, capacitive output loading CL>50 pF, or equivalent capacitive output loading CL=5 pF for TSHQZ, TELQZ
TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical).
(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, post total dose at 25°C.
(4) Chip Enable (CE) pin not available on 28-lead FP or DIP.
TAVAVR
ADDRESS
TAVQV
TAXQX
TSLQV
NCS
TSLQX
DATA OUT
TSHQZ
HIGH
IMPEDANCE
DATA VALID
TEHQX
TEHQV
CE
TELQZ
TGLQX
TGLQV
TGHQZ
NOE
(NWE = high)
6
HLX6256
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
-55 to 125°C
Typical
(2)
Min
Units
Max
TAVAVW Write Cycle Time (4)
25
ns
TWLWH
Write Enable Write Pulse Width
20
ns
TSLWH
Chip Select to End of Write Time
20
ns
TDVWH
Data Valid to End of Write Time
15
ns
TAVWH
Address Valid to End of Write Time
20
ns
TWHDX
Data Hold Time after End of Write Time
0
ns
TAVWL
Address Valid Setup to Start of Write Time
0
ns
TWHAX
Address Valid Hold after End of Write Time
0
ns
TWLQZ
Write Enable to Output Disable Time
TWHQX
Write Disable to Output Enable Time
5
ns
TWHWL
Write Disable to Write Enable Pulse Width (5)
5
ns
TEHWH
Chip Enable to End of Write Time (6)
20
ns
12.6
ns
(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the
Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125°C, post total dose at 25°C.
(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested.
(6) Chip Enable (CE) pin not available on 28-lead FP or DIP.
TAVAVW
ADDRESS
TAVWH
TWHAX
TAVWL
TWHWL
TWLWH
NWE
TWLQZ
DATA OUT
TWHQX
HIGH
IMPEDANCE
TDVWH
DATA IN
DATA VALID
TSLWH
NCS
TEHWH
CE
7
TWHDX
HLX6256
DYNAMIC ELECTRICAL CHARACTERISTICS
Read Cycle
Write Cycle
The RAM is asynchronous in operation, allowing the read
cycle to be controlled by address, chip select (NCS), or chip
enable (CE) (refer to Read Cycle timing diagram). To
perform a valid read operation, both chip select and output
enable (NOE) must be low and chip enable and write enable
(NWE) must be high. The output drivers can be controlled
independently by the NOE signal. Consecutive read cycles
can be executed with NCS held continuously low, and with
CE held continuously high, and toggling the addresses.
The write operation is synchronous with respect to the
address bits, and control is governed by write enable
(NWE), chip select (NCS), or chip enable (CE) edge
transitions (refer to Write Cycle timing diagrams). To perform a write operation, both NWE and NCS must be low,
and CE must be high. Consecutive write cycles can be
performed with NWE or NCS held continuously low, or CE
held continuously high. At least one of the control signals
must transition to the opposite state between consecutive
write operations.
For an address activated read cycle, NCS and CE must be
valid prior to or coincident with the activating address edge
transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs
will become valid TAVQV time following the latest occurring
address edge transition. The minimum address activated
read cycle time is TAVAV. When the RAM is operated at the
minimum address activated read cycle time, the data outputs
will remain valid on the RAM I/O until TAXQX time following
the next sequential address transition.
The write mode can be controlled via three different control
signals: NWE, NCS, and CE. All three modes of control are
similar, except the NCS and CE controlled modes actually
disable the RAM during the write recovery pulse. Both CE
and NCS fully disable the RAM decode logic and input
buffers for power savings. Only the NWE controlled mode
is shown in the table and diagram on the previous page for
simplicity; however, each mode of control provides the
same write cycle timing characteristics. Thus, some of the
parameter names referenced below are not shown in the
write cycle table or diagram, but indicate which control pin
is in control as it switches high or low.
To control a read cycle with NCS, all addresses and CE
must be valid prior to or coincident with the enabling NCS
edge transition. Address or CE edge transitions can occur
later than the specified setup times to NCS; however, the
valid data access time will be delayed. Any address edge
transition, which occurs during the time when NCS is low,
will initiate a new read access, and data outputs will not
become valid until TAVQV time following the address edge
transition. Data outputs will enter a high impedance state
TSHQZ time following a disabling NCS edge transition.
To write data into the RAM, NWE and NCS must be held low
and CE must be held high for at least TWLWH/TSLSH/
TEHEL time. Any amount of edge skew between the
signals can be tolerated, and any one of the control signals
can initiate or terminate the write operation. For consecutive write operations, write pulses must be separated by the
minimum specified TWHWL/TSHSL/TELEH time. Address
inputs must be valid at least TAVWL/TAVSL/TAVEH time
before the enabling NWE/NCS/CE edge transition, and
must remain valid during the entire write time. A valid data
overlap of write pulse width time of TDVWH/TDVSH/TDVEL,
and an address valid to end of write time of TAVWH/
TAVSH/TAVEL also must be provided for during the write
operation. Hold times for address inputs and data inputs
with respect to the disabling NWE/NCS/CE edge transition
must be a minimum of TWHAX/TSHAX/TELAX time and
TWHDX/TSHDX/TELDX time, respectively. The minimum
write cycle time is TAVAV.
To control a read cycle with CE, all addresses and NCS
must be valid prior to or coincident with the enabling CE
edge transition. Address or NCS edge transitions can
occur later than the specified setup times to CE; however,
the valid data access time will be delayed. Any address
edge transition which occurs during the time when CE is
high will initiate a new read access, and data outputs will
not become valid until TAVQV time following the address
edge transition. Data outputs will enter a high impedance
state TELQZ time following a disabling CE edge transition.
8
HLX6256
TESTER AC TIMING CHARACTERISTICS
3V
Input
Levels*
VDD/2
0V
VDD/2
Output
Sense
Levels
VDD-0.4V
High Z
0.4 V
2.7 V
High Z
1.7 V
High Z = 2.2V
* Input rise and fall times <1 ns/V
QUALITY AND RADIATION HARDNESS
ASSURANCE
ing the need to create detailed specifications and offer
benefits of improved quality and cost savings through
standardization.
Honeywell maintains a high level of product integrity through
process control, utilizing statistical process control, a complete “Total Quality Assurance System,” a computer data
base process performance tracking system and a radiation-hardness assurance strategy.
RELIABILITY
The radiation hardness assurance strategy starts with a
technology that is resistant to the effects of radiation.
Radiation hardness is assured on every wafer by irradiating
test structures as well as SRAM product, and then monitoring key parameters which are sensitive to ionizing radiation. Conventional MIL-STD-883 TM 5005 Group E testing,
which includes total dose exposure with Cobalt 60, may
also be performed as required. This Total Quality approach
ensures our customers of a reliable product by engineering
in reliability, starting with process development and continuing through product qualification and screening.
Honeywell understands the Stringent reliability requirements for space and defense systems and has extensive
experience in reliability testing on programs of this nature.
This experience is derived from comprehensive testing of
VLSI processes. Reliability attributes of the RICMOSTM
process were characterized by testing specially designed
irradiated and non-irradiated test structures from which
specific failure mechanisms were evaluated. These specific
mechanisms included, but were not limited to, hot carriers,
electromigration and time dependent dielectric breakdown.
This data was then used to make changes to the design
models and process to ensure more reliable products.
SCREENING LEVELS
In addition, the reliability of the RICMOSTM process and
product in a military environment was monitored by testing
irradiated and non-irradiated circuits in accelerated dynamic life test conditions. Packages are qualified for product use after undergoing Groups B & D testing as outlined
in MIL-STD-883, TM 5005, Class S. The product is qualified by following a screening and testing flow to meet the
customer’s requirements. Quality conformance testing is
performed as an option on all production lots to ensure the
ongoing reliability of the product.
Honeywell offers several levels of device screening to meet
your system needs. “Engineering Devices” are available
with limited performance and screening for breadboarding
and/or evaluation testing. Hi-Rel Level B and S devices
undergo additional screening per the requirements of MILSTD-883. As a QML supplier, Honeywell also offers QML
Class Q and V devices per MIL-PRF-38535 and are available per the applicable Standard Microcircuit Drawing
(SMD). QML devices offer ease of procurement by eliminat9
HLX6256
PACKAGING
The 32K x 8 SRAM is offered in a custom 36-lead flat pack
(FP), 28-Lead FP, or standard 28-lead DIP. Each package
is constructed of multilayer ceramic (Al2O3) and features
internal power and ground planes. The 36-lead FP also
features a non-conductive ceramic tie bar on the lead
frame. The tie bar allows electrical testing of the device,
while preserving the lead integrity during shipping and
handling, up to the point of lead forming and insertion.
Ceramic chip capacitors can be mounted to the package by
the user to maximize supply noise decoupling and increase
board packing density. These capacitors attach directly to
the internal package power and ground planes. This design
minimizes resistance and inductance of the bond wire and
package. All NC (no connect) pins should be connected
to VSS to prevent charge build up in the radiation
environment.
28-LEAD DIP & FP PINOUT
36-LEAD FP PINOUT
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
2
3
27
26
4
5
25
24
6
7
Top
View
8
9
VDD
NWE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
23
22
21
20
10
11
19
18
12
13
14
17
16
15
VSS
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
NC
VDD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Top
View
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VSS
VDD
NWE
CE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
VSS
28-LEAD FLAT PACK (22018131-001)
E
All dimensions in inches
Index
1
1
b
(width)
e
BOTTOM
VIEW
D
F
TOP
VIEW
(pitch)
S
U
L
W
Capacitor
Pads
X
Y
Q
G
A
Kovar
Lid [4]
E2
Ceramic
Body
C
[1]
[2]
[3]
[4]
Lead
Alloy 42 [3]
A
b
C
D
e
E
E2
E3
F
G
L
Q
S
U
W
X
Y
0.105 ± 0.015
0.017 ± 0.002
0.003 to 0.006
0.720 ± 0.008
0.050 ± 0.005 [1]
0.500 ± 0.007
0.380 ± 0.008
0.060 ref
0.650 ± 0.005 [2]
0.035 ± 0.004
0.295 min [3]
0.026 to 0.045
0.045 ± 0.010
0.130 ref
0.050 ref
0.075 ref
0.010 ref
BSC – Basic lead spacing between centers
Where lead is brazed to package
Parts delivered with leads unformed
Lid connected to VSS
E3
28-LEAD DIP
For 28-Lead DIP description, see MIL-STD-1835, Type CDIP2-T28, Config. C, Dimensions D-10
10
HLX6256
36-LEAD FLAT PACK (22018131-001)
E
22018131-001
1
b
(width)
D
G
Top
View
e
(pitch)
L
L
Ceramic
Body
A
J
I
NonConductive
Tie-Bar
Kovar
Lid [3]
0.004
C
VDD
M
N
X
Optional
Capacitors
VSS
VDD
All dimensions are in inches [1]
VSS
F
S
Y
1
1
A
b
C
D
E
e
F
G
H
I
J
L
O
W
DYNAMIC BURN-IN DIAGRAM*
STATIC BURN-IN DIAGRAM*
F16
F7
F6
F5
F4
F3
F2
F8
F13
F14
F1
F1
F1
VSS
R
R
R
R
R
R
R
R
R
R
R
R
R
2
3
4
5
6
7
8
9
10
11
12
13
14
32K x 8 SRAM
VDD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VDD
NWE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
26
25
24
23
22
21
20
19
18
17
16
15
VDD
VDD
28
27
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0.008 ± 0.003
0.050 ± 0.010
0.090 ref
0.015 ref
0.075 ref
0.113 ± 0.010
0.050 ref
0.030 ref
0.080 ref
0.005 ref
0.450 ref
0.400 ref
U
R
1
M
N
O
P
R
S
T
U
V
W
X
Y
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
V
T
P
0.095 ± 0.014
0.008 ± 0.002
0.005 to 0.0075
0.650 ± 0.010
0.630 ± 0.007
0.025 ± 0.002 [2]
0.425 ± 0.005 [2]
0.525 ± 0.005
0.135 ± 0.005
0.030 ± 0.005
0.080 typ.
0.285 ± 0.015
F0
F15
F12
F11
F10
F17
F9
F17
F1
F1
F1
F1
F1
R
R
R
R
R
R
R
R
R
R
R
R
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
32K x 8 SRAM
H
VDD
NWE
A13
A8
A9
A11
NOE
A10
NCS
DQ7
DQ6
DQ5
DQ4
DQ3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R
R
R
R
R
R
R
R
R
R
R
R
R
R
VDD = 3.6V min., R ≤ 10 KΩ
Ambient Temperature ≥ 125 °C
VDD = 3.9V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS
Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave
Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
*36-lead Flat Pack burn-in diagram has similar connections and is available on request.
11
HLX6256
ORDERING INFORMATION (1)
H
LX
6256
S
N
H
SCREEN LEVEL
V=QML Class V
Q=QML Class Q
PACKAGE DESIGNATION
S=Level S
N=28-Lead FP
B=Level B
TOTAL DOSE
R=28-Lead DIP
E=Engineering Device (2)
HARDNESS
X=36-Lead FP
R=1x105 rad(SiO2)
K=Known Good Die
F=3x105 rad(SiO2)
- = Bare die (No Package)
H=1x106 rad(SiO2)
N=No Level Guaranteed
PART NUMBER
PROCESS
LX=Low Power SOI
SOURCE
H=HONEYWELL
(1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information.
(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.
Contact Factory with other needs.
To learn more about Honeywell Solid State Electronics Center,
visit our web site at http://www.ssec.honeywell.com
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
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