ASM2P3805AH June 2005 rev 0.2 3.3V CMOS Buffer Clock Driver Functional Description Features Advanced CMOS Technology The ASM2P3805AH is a 3.3V, non-inverting clock driver Guaranteed low skew < 500pS (max.) built using advanced CMOS technology. The device Very low duty cycle distortion < 1.0nS (max) consists of two banks of drivers, each with a 1:5 fanout and Very low CMOS power levels its own output enable control. The device has a "heartbeat" TTL compatible inputs and outputs monitor for diagnostics and PLL driving. The MON output is Inputs can be driven from 3.3V or 5V components identical to all other outputs and complies with the output Two independent output banks with 3-state control specifications in this document. The ASM2P3805AH offers 1:5 fanout per bank low capacitance inputs. "Heartbeat" monitor output VCC = 3.3V ± 0.3V The ASM2P3805AH is designed for high speed clock Available in SSOP, SOIC and QSOP Packages distribution where signal quality and skew are critical. The ASM2P3805AH also allows single point-to-point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. Block Diagram Pin Diagram OEA INA INB 5 5 OA1 – OA5 OB1 – OB5 OEB MON VCCA 1 OA1 2 OA2 3 OA3 4 GNDA 5 OA4 6 OA5 7 GNDQ 8 OEA INA 20 VCCB 19 OB1 18 OB2 17 OB3 16 GNDB 15 OB4 14 OB5 13 MON 9 12 OEB 10 11 INB A S M 2 3 8 0 5 A H Alliance Semiconductor 2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com Notice: The information in this document is subject to change without notice. ASM2P3805AH June 2005 rev 0.2 Pin Description Pin # Pin Names 9,12 ¯¯ B OE ¯¯ A, OE 10,11 INA, INB Clock Inputs 2,3,4,6,7 OA1-OA5 Clock Outputs 19,18,17,15,14 OB1-OB5 Clock Outputs 1 VCCA Power supply for Bank A 20 VCCB Power supply for Bank B 5 GNDA Ground for Bank A 16 GNDB Ground for Bank B 8 GNDQ Ground 13 MON Monitor Output Description 3-State Output Enable Inputs (Active LOW) Function Table Inputs Outputs OE ¯¯ A, OE ¯¯ B INA, INB OAn, OBn MON L L L L L H H H H L Z L H H Z H Note: H = HIGH; L = LOW; Z = High-Impedance Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter1 Conditions Typ Max Unit CIN Input Capacitance VIN= 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF Note: 1 This parameter is measured at characterization but not tested. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 2 of 13 ASM2P3805AH June 2005 rev 0.2 Absolute Maximum Ratings1 Symbol Description VTERM2 VTERM3 VTERM4 Max Unit Terminal Voltage with Respect to GND -0.5 to +4.6 V Terminal Voltage with Respect to GND -0.5 to +7 V Terminal Voltage with Respect to GND -0.5 to VCC+0.5 V IOUT DC Output Current -60 to +60 mA TSTG Storage Temperature -65 to +150 °C TJ Junction Temperature 150 °C Ts Max. Soldering Temperature (10 sec) 260 °C 2 KV TDV Static Discharge Voltage (As per JEDEC STD 22- A114-B) Note: 1 These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 2. VCC terminals. 3. Input terminals. 4. Outputs and I/O terminals. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 3 of 13 ASM2P3805AH June 2005 rev 0.2 DC Electrical Characteristics over Operating Range Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0°C to +70°C, VCC = 3.3V ± 0.3V; Industrial: TA = -40 0°C to +85°C, VCC = 3.3V ± 0.3V Symbol VIH Test Conditions1 Min Typ2 Max 2 - 5.5 2 - VCC+ 0.5 -0.5 - 0.8 VI = 5.5V - - ±1 Input HIGH Current (I/O pins) VI = VCC - - ±1 Input LOW Current (Input pins) VI = GND - - ±1 Input LOW Current (I/O pins) VI = GND - - ±1 High Impedance Output Current VCC= Max. (3-State Output Pins) VO = VCC - - ±1 VO = GND - - ±1 Parameter Input HIGH Level (Input pins) Guaranteed Logic HIGH Level Input HIGH Level (I/O pins) VIL IIH IIL IOZH IOZL Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level Input HIGH Current (Input pins) VCC= Max. VCC= Max. Unit V V µA µA VIK Clamp Diode Voltage VCC= Min., IIN = -18mA - -0.7 -1.2 V IODH Output HIGH Current VCC= 3.3V, VIN = VIH or 3 VIL, VO = 1.5V -36 -60 -110 mA IODL Output LOW Current VCC= 3.3V, VIN = VIH or 3 VIL, VO = 1.5V 50 90 200 mA VOH Output HIGH Voltage VCC= Min. VIN = VIH or VIL VCC–0.2 - - IOH= -8mA 2.45 3 - IOL= 0.1mA - - 0.2 IOL= 16mA - 0.2 0.4 IOL= 24mA - 0.3 0.5 - - ±1 µA -60 -135 -240 mA VOL IOFF VCC= Min. VIN = VIH or VIL Output LOW Voltage Input Power Off Leakage 4 IOH= -0.1mA VCC= 0V, VIN = 4.5V 3 V V IOS Short Circuit Current VCC= Max., VO = GND VH Input Hysteresis - - 150 - mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC= Max. VIN = GND or VCC - 0.1 10 µA Notes:1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC - 0.6V at rated current. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 4 of 13 ASM2P3805AH June 2005 rev 0.2 Power Supply Characteristics Symbol Parameter Test Conditions1 ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC= Max. VIN = VCC –0.6V ICCD Dynamic Power Supply Current 4 3 VCC= Max. Outputs Open OE ¯¯ A = OE ¯¯ B= GND Per Output Toggling 50% Duty Cycle VIN= VCC VIN= GND VIN= VCC VCC= Max. VIN= GND Outputs Open fO= 25MHz 50% Duty Cycle OE ¯¯ A = OE ¯¯ B= VCC VIN= VCC-0.6V Mon. Output Toggling VIN= GND IC Total Power Supply Current Min Typ2 Max Unit - 10 30 µA - 0.035 0.06 mA/ MHz - 0.9 1.6 - 0.9 1.6 6 mA VCC= Max. Outputs Open fO= 50MHz 50% Duty Cycle OEA = OEB= GND Eleven Outputs Toggling VIN= VCC VIN= GND - 20 33 VIN= VCC-0.6V VIN= GND - 20 33 5 5 Notes: 1. For conditions shown as Max or Min, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25°C ambient. 3. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 5 of 13 ASM2P3805AH June 2005 rev 0.2 Switching Characteristics Over Operating Range – Commercial3,4 Symbol Conditions1 Parameter ASM2P3805A ASM2P3805AH Unit Min Max Min2 Max 1.5 5.8 1.5 5 nS Output Rise Time (0.8V to 2.0V) - 2 - 2 nS Output Fall Time (2.0V to 0.8V) - 2 - 2 nS tSK(O) Output skew: skew between outputs of all banks of same package (inputs tied together) - 0.5 - 0.5 nS tSK(P) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) - 1 - 1 nS tSK(T) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade - 1.5 - 1.2 nS tPZL tPZH Output Enable Time OE ¯¯ A to OAn, OE ¯¯ B to OBn 1.5 6.5 1.5 6 nS tPLZ tPHZ Output Disable Time OE ¯¯ A to OAn, OE ¯¯ B to OBn 1.5 5.5 1.5 5 nS tPLH tPHL tR tF 2 Propagation Delay INA to OAn, INB to OBn CL= 50pF RL= 500Ω Switching Characteristics Over Operating Range – Industrial3,4 Symbol tPLH tPHL Conditions1 Parameter Propagation Delay INA to OAn, INB to OBn ASM2P3805A 2 ASM2P3805AH Unit Min Max Min2 Max 1.5 5.8 1.5 5.2 nS tR Output Rise Time (0.8V to 2.0V) - 2 - 2 nS tF Output Fall Time (2.0V to 0.8V) - 2 - 2 nS tSK(O) Output skew: skew between outputs of all banks of same package (inputs tied together) - 0.6 - 0.6 nS tSK(P) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) - 1 - 1 nS tSK(T) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade - 1.5 - 1.2 nS tPZL tPZH Output Enable Time OE ¯¯ A to OAn, OE ¯¯ B to OBn 1.5 6.5 1.5 6 nS tPLZ tPHZ Output Disable Time OE ¯¯ A to OAn, OE ¯¯ B to OBn 1.5 5.5 1.5 5 nS CL= 50pF RL= 500Ω Note: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 6 of 13 ASM2P3805AH June 2005 rev 0.2 Test Circuits and Waveforms Switch Position Test Switch Disable Low Enable Low 6V Disable High Enable High GND Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 7 of 13 ASM2P3805AH June 2005 rev 0.2 Package Information 20-lead SSOP ( 150 mil ) Package Dimensions Symbol Inches Min Max Millimeters Min Max A 0.053 0.069 1.346 1.753 A1 0.004 0.010 0.102 0.254 A2 …. 0.059 …. 1.499 D 0.337 0.344 8.560 8.738 c 0.007 0.012 0.178 0.274 E 0.228 0.244 5.791 6.198 E1 0.150 0.157 3.810 3.988 L 0.016 0.035 0.406 0.890 L1 0.010 BASIC 0.254 BASIC b 0.203 0.325 0.008 0.014 R1 0.003 …. 0.08 ….. a 0° 8° 0° 8° e 0.025 BASIC 0.635 BASIC 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 8 of 13 ASM2P3805AH June 2005 rev 0.2 20-lead QSOP Package Symbol Dimensions Inches Millimeters Min Max Min Max A 0.060 0.068 1.52 1.73 A1 0.004 0.008 0.10 0.20 b 0.009 0.012 0.23 0.30 c 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99 e 0.025 BSC 0.64 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 S 0.056 0.060 1.42 1.52 a 0° 8° 0° 8° 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 9 of 13 ASM2P3805AH June 2005 rev 0.2 20L SOIC Package (300 mil) Dimensions Symbol Inches Min Max Millimeters Min Max A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 A2 0.088 0.094 2.25 2.40 D 0.496 0.512 12.60 13.00 L 0.016 0.050 0.40 1.27 E1 0.291 0.299 7.40 7.60 R1 0.003 …. 0.08 ….. b 0.013 0.022 0.33 0.56 c 0.009 0.015 0.23 0.38 E 0.394 0.419 10.00 10.65 e a 0.050 BSC 0° 1.27 BSC 8° 0° 8° 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 10 of 13 ASM2P3805AH June 2005 rev 0.2 Ordering Information Part Number Marking Package Type Temperature ASM2P3805AHG-20-AR 2P3805AHG 20-Pin SSOP, TAPE & REEL, Green Commercial ASM2P3805AHG-20-AT 2P3805AHG 20-Pin SSOP, TUBE, Green Commercial ASM2P3805AHG-20-DR 2P3805AHG 20-Pin QSOP, TAPE & REEL, Green Commercial ASM2P3805AHG-20-DT 2P3805AHG 20-Pin QSOP, TUBE, Green Commercial ASM2P3805AHG-20-SR 2P3805AHG 20-Pin SOIC, TAPE & REEL, Green Commercial ASM2P3805AHG-20-ST 2P3805AHG 20-Pin SOIC, TUBE, Green Commercial ASM2I3805AHG-20-AR 2I3805AHG 20-Pin SSOP, TAPE & REEL, Green ASM2I3805AHG-20-AT 2I3805AHG 20-Pin SSOP, TUBE, Green Industrial Industrial ASM2I3805AHG-20-DR 2I3805AHG 20-Pin QSOP, TAPE & REEL, Green Industrial ASM2I3805AHG-20-DT 2I3805AHG 20-Pin QSOP, TUBE, Green Industrial ASM2I3805AHG-20-SR 2I3805AHG 20-Pin SOIC, TAPE & REEL, Green Industrial ASM2I3805AHG-20-ST 2I3805AHG 20-Pin SOIC, TUBE, Green Industrial ASM2P3805AG-20-AR 2P3805AG 20-Pin SSOP, TAPE & REEL, Green Commercial ASM2P3805AG-20-AT 2P3805AG 20-Pin SSOP, TUBE, Green Commercial ASM2P3805AG-20-DR 2P3805AG 20-Pin QSOP, TAPE & REEL, Green Commercial ASM2P3805AG-20-DT 2P3805AG 20-Pin QSOP, TUBE, Green Commercial ASM2P3805AG-20-SR 2P3805AG 20-Pin SOIC, TAPE & REEL, Green Commercial ASM2P3805AG-20-ST 2P3805AG 20-Pin SOIC, TUBE, Green Commercial ASM2I3805AG-20-AR 2I3805AG 20-Pin SSOP, TAPE & REEL, Green ASM2I3805AG-20-AT 2I3805AG 20-Pin SSOP, TUBE, Green Industrial Industrial ASM2I3805AG-20-DR 2I3805AG 20-Pin QSOP, TAPE & REEL, Green Industrial ASM2I3805AG-20-DT 2I3805AG 20-Pin QSOP, TUBE, Green Industrial ASM2I3805AG-20-SR 2I3805AG 20-Pin SOIC, TAPE & REEL, Green Industrial ASM2I3805AG-20-ST 2I3805AG 20-Pin SOIC, TUBE, Green Industrial 3.3V CMOS Buffer Clock Driver 11 of 13 Notice: The information in this document is subject to change without notice. ASM2P3805AH June 2005 rev 0.2 Device Ordering Information A S M 2 P 3 8 0 5 A H G - 2 0 - D R R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 12 of 13 ASM2P3805AH June 2005 rev 0.2 Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright © Alliance Semiconductor All Rights Reserved Part Number: ASM2P3805AH Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 © Copyright 2003 Alliance Semiconductor Corporation. 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Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3V CMOS Buffer Clock Driver Notice: The information in this document is subject to change without notice. 13 of 13